ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_STM/TARGET_STM32F2/can_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2016 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "can_api.h"
group-onsemi 0:098463de4c5d 17
group-onsemi 0:098463de4c5d 18 #if DEVICE_CAN
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 #include "cmsis.h"
group-onsemi 0:098463de4c5d 21 #include "pinmap.h"
group-onsemi 0:098463de4c5d 22 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 23 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 24 #include <math.h>
group-onsemi 0:098463de4c5d 25 #include <string.h>
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 #define CAN_NUM 2
group-onsemi 0:098463de4c5d 28 static CAN_HandleTypeDef CanHandle;
group-onsemi 0:098463de4c5d 29 static uint32_t can_irq_ids[CAN_NUM] = {0};
group-onsemi 0:098463de4c5d 30 static can_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 void can_init(can_t *obj, PinName rd, PinName td)
group-onsemi 0:098463de4c5d 33 {
group-onsemi 0:098463de4c5d 34 uint32_t filter_number;
group-onsemi 0:098463de4c5d 35 CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
group-onsemi 0:098463de4c5d 36 CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
group-onsemi 0:098463de4c5d 37 obj->can = (CANName)pinmap_merge(can_rd, can_td);
group-onsemi 0:098463de4c5d 38 MBED_ASSERT((int)obj->can != NC);
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 if (obj->can == CAN_1) {
group-onsemi 0:098463de4c5d 41 __HAL_RCC_CAN1_CLK_ENABLE();
group-onsemi 0:098463de4c5d 42 obj->index = 0;
group-onsemi 0:098463de4c5d 43 } else {
group-onsemi 0:098463de4c5d 44 __HAL_RCC_CAN2_CLK_ENABLE();
group-onsemi 0:098463de4c5d 45 obj->index = 1;
group-onsemi 0:098463de4c5d 46 }
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 // Configure the CAN pins
group-onsemi 0:098463de4c5d 49 pinmap_pinout(rd, PinMap_CAN_RD);
group-onsemi 0:098463de4c5d 50 pinmap_pinout(td, PinMap_CAN_TD);
group-onsemi 0:098463de4c5d 51 if (rd != NC) {
group-onsemi 0:098463de4c5d 52 pin_mode(rd, PullUp);
group-onsemi 0:098463de4c5d 53 }
group-onsemi 0:098463de4c5d 54 if (td != NC) {
group-onsemi 0:098463de4c5d 55 pin_mode(td, PullUp);
group-onsemi 0:098463de4c5d 56 }
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 CanHandle.Instance = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 CanHandle.Init.TTCM = DISABLE;
group-onsemi 0:098463de4c5d 61 CanHandle.Init.ABOM = DISABLE;
group-onsemi 0:098463de4c5d 62 CanHandle.Init.AWUM = DISABLE;
group-onsemi 0:098463de4c5d 63 CanHandle.Init.NART = DISABLE;
group-onsemi 0:098463de4c5d 64 CanHandle.Init.RFLM = DISABLE;
group-onsemi 0:098463de4c5d 65 CanHandle.Init.TXFP = DISABLE;
group-onsemi 0:098463de4c5d 66 CanHandle.Init.Mode = CAN_MODE_NORMAL;
group-onsemi 0:098463de4c5d 67 CanHandle.Init.SJW = CAN_SJW_1TQ;
group-onsemi 0:098463de4c5d 68 CanHandle.Init.BS1 = CAN_BS1_6TQ;
group-onsemi 0:098463de4c5d 69 CanHandle.Init.BS2 = CAN_BS2_8TQ;
group-onsemi 0:098463de4c5d 70 CanHandle.Init.Prescaler = 2;
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 if (HAL_CAN_Init(&CanHandle) != HAL_OK) {
group-onsemi 0:098463de4c5d 73 error("Cannot initialize CAN");
group-onsemi 0:098463de4c5d 74 }
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 filter_number = (obj->can == CAN_1) ? 0 : 14;
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 // Set initial CAN frequency to 100kb/s
group-onsemi 0:098463de4c5d 79 can_frequency(obj, 100000);
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 can_filter(obj, 0, 0, CANStandard, filter_number);
group-onsemi 0:098463de4c5d 82 }
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 85 {
group-onsemi 0:098463de4c5d 86 irq_handler = handler;
group-onsemi 0:098463de4c5d 87 can_irq_ids[obj->index] = id;
group-onsemi 0:098463de4c5d 88 }
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 void can_irq_free(can_t *obj)
group-onsemi 0:098463de4c5d 91 {
group-onsemi 0:098463de4c5d 92 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
group-onsemi 0:098463de4c5d 95 CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
group-onsemi 0:098463de4c5d 96 can_irq_ids[obj->can] = 0;
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 void can_free(can_t *obj)
group-onsemi 0:098463de4c5d 100 {
group-onsemi 0:098463de4c5d 101 // Reset CAN and disable clock
group-onsemi 0:098463de4c5d 102 if (obj->can == CAN_1) {
group-onsemi 0:098463de4c5d 103 __HAL_RCC_CAN1_FORCE_RESET();
group-onsemi 0:098463de4c5d 104 __HAL_RCC_CAN1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 105 __HAL_RCC_CAN1_CLK_DISABLE();
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 if (obj->can == CAN_2) {
group-onsemi 0:098463de4c5d 109 __HAL_RCC_CAN2_FORCE_RESET();
group-onsemi 0:098463de4c5d 110 __HAL_RCC_CAN2_RELEASE_RESET();
group-onsemi 0:098463de4c5d 111 __HAL_RCC_CAN2_CLK_DISABLE();
group-onsemi 0:098463de4c5d 112 }
group-onsemi 0:098463de4c5d 113 }
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 // The following table is used to program bit_timing. It is an adjustment of the sample
group-onsemi 0:098463de4c5d 116 // point by synchronizing on the start-bit edge and resynchronizing on the following edges.
group-onsemi 0:098463de4c5d 117 // This table has the sampling points as close to 75% as possible (most commonly used).
group-onsemi 0:098463de4c5d 118 // The first value is TSEG1, the second TSEG2.
group-onsemi 0:098463de4c5d 119 static const int timing_pts[23][2] = {
group-onsemi 0:098463de4c5d 120 {0x0, 0x0}, // 2, 50%
group-onsemi 0:098463de4c5d 121 {0x1, 0x0}, // 3, 67%
group-onsemi 0:098463de4c5d 122 {0x2, 0x0}, // 4, 75%
group-onsemi 0:098463de4c5d 123 {0x3, 0x0}, // 5, 80%
group-onsemi 0:098463de4c5d 124 {0x3, 0x1}, // 6, 67%
group-onsemi 0:098463de4c5d 125 {0x4, 0x1}, // 7, 71%
group-onsemi 0:098463de4c5d 126 {0x5, 0x1}, // 8, 75%
group-onsemi 0:098463de4c5d 127 {0x6, 0x1}, // 9, 78%
group-onsemi 0:098463de4c5d 128 {0x6, 0x2}, // 10, 70%
group-onsemi 0:098463de4c5d 129 {0x7, 0x2}, // 11, 73%
group-onsemi 0:098463de4c5d 130 {0x8, 0x2}, // 12, 75%
group-onsemi 0:098463de4c5d 131 {0x9, 0x2}, // 13, 77%
group-onsemi 0:098463de4c5d 132 {0x9, 0x3}, // 14, 71%
group-onsemi 0:098463de4c5d 133 {0xA, 0x3}, // 15, 73%
group-onsemi 0:098463de4c5d 134 {0xB, 0x3}, // 16, 75%
group-onsemi 0:098463de4c5d 135 {0xC, 0x3}, // 17, 76%
group-onsemi 0:098463de4c5d 136 {0xD, 0x3}, // 18, 78%
group-onsemi 0:098463de4c5d 137 {0xD, 0x4}, // 19, 74%
group-onsemi 0:098463de4c5d 138 {0xE, 0x4}, // 20, 75%
group-onsemi 0:098463de4c5d 139 {0xF, 0x4}, // 21, 76%
group-onsemi 0:098463de4c5d 140 {0xF, 0x5}, // 22, 73%
group-onsemi 0:098463de4c5d 141 {0xF, 0x6}, // 23, 70%
group-onsemi 0:098463de4c5d 142 {0xF, 0x7}, // 24, 67%
group-onsemi 0:098463de4c5d 143 };
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw)
group-onsemi 0:098463de4c5d 146 {
group-onsemi 0:098463de4c5d 147 uint32_t btr;
group-onsemi 0:098463de4c5d 148 uint16_t brp = 0;
group-onsemi 0:098463de4c5d 149 uint32_t calcbit;
group-onsemi 0:098463de4c5d 150 uint32_t bitwidth;
group-onsemi 0:098463de4c5d 151 int hit = 0;
group-onsemi 0:098463de4c5d 152 int bits;
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 bitwidth = (pclk / cclk);
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 brp = bitwidth / 0x18;
group-onsemi 0:098463de4c5d 157 while ((!hit) && (brp < bitwidth / 4)) {
group-onsemi 0:098463de4c5d 158 brp++;
group-onsemi 0:098463de4c5d 159 for (bits = 22; bits > 0; bits--) {
group-onsemi 0:098463de4c5d 160 calcbit = (bits + 3) * (brp + 1);
group-onsemi 0:098463de4c5d 161 if (calcbit == bitwidth) {
group-onsemi 0:098463de4c5d 162 hit = 1;
group-onsemi 0:098463de4c5d 163 break;
group-onsemi 0:098463de4c5d 164 }
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166 }
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 if (hit) {
group-onsemi 0:098463de4c5d 169 btr = ((timing_pts[bits][1] << 20) & 0x00700000)
group-onsemi 0:098463de4c5d 170 | ((timing_pts[bits][0] << 16) & 0x000F0000)
group-onsemi 0:098463de4c5d 171 | ((psjw << 24) & 0x0000C000)
group-onsemi 0:098463de4c5d 172 | ((brp << 0) & 0x000003FF);
group-onsemi 0:098463de4c5d 173 } else {
group-onsemi 0:098463de4c5d 174 btr = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 175 }
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 return btr;
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 }
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 int can_frequency(can_t *obj, int f)
group-onsemi 0:098463de4c5d 182 {
group-onsemi 0:098463de4c5d 183 int pclk = HAL_RCC_GetPCLK1Freq();
group-onsemi 0:098463de4c5d 184 int btr = can_speed(pclk, (unsigned int)f, 1);
group-onsemi 0:098463de4c5d 185 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 if (btr > 0) {
group-onsemi 0:098463de4c5d 188 can->MCR |= CAN_MCR_INRQ ;
group-onsemi 0:098463de4c5d 189 while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
group-onsemi 0:098463de4c5d 190 }
group-onsemi 0:098463de4c5d 191 can->BTR = btr;
group-onsemi 0:098463de4c5d 192 can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
group-onsemi 0:098463de4c5d 193 while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
group-onsemi 0:098463de4c5d 194 }
group-onsemi 0:098463de4c5d 195 return 1;
group-onsemi 0:098463de4c5d 196 } else {
group-onsemi 0:098463de4c5d 197 return 0;
group-onsemi 0:098463de4c5d 198 }
group-onsemi 0:098463de4c5d 199 }
group-onsemi 0:098463de4c5d 200
group-onsemi 0:098463de4c5d 201 int can_write(can_t *obj, CAN_Message msg, int cc)
group-onsemi 0:098463de4c5d 202 {
group-onsemi 0:098463de4c5d 203 uint32_t transmitmailbox = 5;
group-onsemi 0:098463de4c5d 204 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 /* Select one empty transmit mailbox */
group-onsemi 0:098463de4c5d 207 if ((can->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
group-onsemi 0:098463de4c5d 208 transmitmailbox = 0;
group-onsemi 0:098463de4c5d 209 } else if ((can->TSR & CAN_TSR_TME1) == CAN_TSR_TME1) {
group-onsemi 0:098463de4c5d 210 transmitmailbox = 1;
group-onsemi 0:098463de4c5d 211 } else if ((can->TSR & CAN_TSR_TME2) == CAN_TSR_TME2) {
group-onsemi 0:098463de4c5d 212 transmitmailbox = 2;
group-onsemi 0:098463de4c5d 213 } else {
group-onsemi 0:098463de4c5d 214 transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
group-onsemi 0:098463de4c5d 215 }
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) {
group-onsemi 0:098463de4c5d 218 can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
group-onsemi 0:098463de4c5d 219 if (!(msg.format)) {
group-onsemi 0:098463de4c5d 220 can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | msg.type);
group-onsemi 0:098463de4c5d 221 } else {
group-onsemi 0:098463de4c5d 222 can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | msg.type);
group-onsemi 0:098463de4c5d 223 }
group-onsemi 0:098463de4c5d 224
group-onsemi 0:098463de4c5d 225 /* Set up the DLC */
group-onsemi 0:098463de4c5d 226 can->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
group-onsemi 0:098463de4c5d 227 can->sTxMailBox[transmitmailbox].TDTR |= (msg.len & (uint8_t)0x0000000F);
group-onsemi 0:098463de4c5d 228
group-onsemi 0:098463de4c5d 229 /* Set up the data field */
group-onsemi 0:098463de4c5d 230 can->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)msg.data[3] << 24) |
group-onsemi 0:098463de4c5d 231 ((uint32_t)msg.data[2] << 16) |
group-onsemi 0:098463de4c5d 232 ((uint32_t)msg.data[1] << 8) |
group-onsemi 0:098463de4c5d 233 ((uint32_t)msg.data[0]));
group-onsemi 0:098463de4c5d 234 can->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)msg.data[7] << 24) |
group-onsemi 0:098463de4c5d 235 ((uint32_t)msg.data[6] << 16) |
group-onsemi 0:098463de4c5d 236 ((uint32_t)msg.data[5] << 8) |
group-onsemi 0:098463de4c5d 237 ((uint32_t)msg.data[4]));
group-onsemi 0:098463de4c5d 238 /* Request transmission */
group-onsemi 0:098463de4c5d 239 can->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
group-onsemi 0:098463de4c5d 240 }
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 return 1;
group-onsemi 0:098463de4c5d 243 }
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 int can_read(can_t *obj, CAN_Message *msg, int handle)
group-onsemi 0:098463de4c5d 246 {
group-onsemi 0:098463de4c5d 247 //handle is the FIFO number
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 // check FPM0 which holds the pending message count in FIFO 0
group-onsemi 0:098463de4c5d 252 // if no message is pending, return 0
group-onsemi 0:098463de4c5d 253 if ((can->RF0R & CAN_RF0R_FMP0) == 0) {
group-onsemi 0:098463de4c5d 254 return 0;
group-onsemi 0:098463de4c5d 255 }
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 /* Get the Id */
group-onsemi 0:098463de4c5d 258 msg->format = (CANFormat)((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR);
group-onsemi 0:098463de4c5d 259 if (!msg->format) {
group-onsemi 0:098463de4c5d 260 msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[handle].RIR >> 21);
group-onsemi 0:098463de4c5d 261 } else {
group-onsemi 0:098463de4c5d 262 msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[handle].RIR >> 3);
group-onsemi 0:098463de4c5d 263 }
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 msg->type = (CANType)((uint8_t)0x02 & can->sFIFOMailBox[handle].RIR);
group-onsemi 0:098463de4c5d 266 /* Get the DLC */
group-onsemi 0:098463de4c5d 267 msg->len = (uint8_t)0x0F & can->sFIFOMailBox[handle].RDTR;
group-onsemi 0:098463de4c5d 268 // /* Get the FMI */
group-onsemi 0:098463de4c5d 269 // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDTR >> 8);
group-onsemi 0:098463de4c5d 270 /* Get the data field */
group-onsemi 0:098463de4c5d 271 msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDLR;
group-onsemi 0:098463de4c5d 272 msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 8);
group-onsemi 0:098463de4c5d 273 msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 16);
group-onsemi 0:098463de4c5d 274 msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 24);
group-onsemi 0:098463de4c5d 275 msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDHR;
group-onsemi 0:098463de4c5d 276 msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 8);
group-onsemi 0:098463de4c5d 277 msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 16);
group-onsemi 0:098463de4c5d 278 msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 24);
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 /* Release the FIFO */
group-onsemi 0:098463de4c5d 281 if (handle == CAN_FIFO0) {
group-onsemi 0:098463de4c5d 282 /* Release FIFO0 */
group-onsemi 0:098463de4c5d 283 can->RF0R |= CAN_RF0R_RFOM0;
group-onsemi 0:098463de4c5d 284 } else { /* FIFONumber == CAN_FIFO1 */
group-onsemi 0:098463de4c5d 285 /* Release FIFO1 */
group-onsemi 0:098463de4c5d 286 can->RF1R |= CAN_RF1R_RFOM1;
group-onsemi 0:098463de4c5d 287 }
group-onsemi 0:098463de4c5d 288
group-onsemi 0:098463de4c5d 289 return 1;
group-onsemi 0:098463de4c5d 290 }
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 void can_reset(can_t *obj)
group-onsemi 0:098463de4c5d 293 {
group-onsemi 0:098463de4c5d 294 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 295
group-onsemi 0:098463de4c5d 296 can->MCR |= CAN_MCR_RESET;
group-onsemi 0:098463de4c5d 297 can->ESR = 0x0;
group-onsemi 0:098463de4c5d 298 }
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300 unsigned char can_rderror(can_t *obj)
group-onsemi 0:098463de4c5d 301 {
group-onsemi 0:098463de4c5d 302 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 303 return (can->ESR >> 24) & 0xFF;
group-onsemi 0:098463de4c5d 304 }
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 unsigned char can_tderror(can_t *obj)
group-onsemi 0:098463de4c5d 307 {
group-onsemi 0:098463de4c5d 308 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 309 return (can->ESR >> 16) & 0xFF;
group-onsemi 0:098463de4c5d 310 }
group-onsemi 0:098463de4c5d 311
group-onsemi 0:098463de4c5d 312 void can_monitor(can_t *obj, int silent)
group-onsemi 0:098463de4c5d 313 {
group-onsemi 0:098463de4c5d 314 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 can->MCR |= CAN_MCR_INRQ ;
group-onsemi 0:098463de4c5d 317 while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319 if (silent) {
group-onsemi 0:098463de4c5d 320 can->BTR |= ((uint32_t)1 << 31);
group-onsemi 0:098463de4c5d 321 } else {
group-onsemi 0:098463de4c5d 322 can->BTR &= ~((uint32_t)1 << 31);
group-onsemi 0:098463de4c5d 323 }
group-onsemi 0:098463de4c5d 324 can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
group-onsemi 0:098463de4c5d 325 while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
group-onsemi 0:098463de4c5d 326 }
group-onsemi 0:098463de4c5d 327 }
group-onsemi 0:098463de4c5d 328
group-onsemi 0:098463de4c5d 329 int can_mode(can_t *obj, CanMode mode)
group-onsemi 0:098463de4c5d 330 {
group-onsemi 0:098463de4c5d 331 int success = 0;
group-onsemi 0:098463de4c5d 332 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 333 can->MCR |= CAN_MCR_INRQ ;
group-onsemi 0:098463de4c5d 334 while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
group-onsemi 0:098463de4c5d 335 }
group-onsemi 0:098463de4c5d 336 switch (mode) {
group-onsemi 0:098463de4c5d 337 case MODE_NORMAL:
group-onsemi 0:098463de4c5d 338 can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
group-onsemi 0:098463de4c5d 339 success = 1;
group-onsemi 0:098463de4c5d 340 break;
group-onsemi 0:098463de4c5d 341 case MODE_SILENT:
group-onsemi 0:098463de4c5d 342 can->BTR |= CAN_BTR_SILM;
group-onsemi 0:098463de4c5d 343 can->BTR &= ~CAN_BTR_LBKM;
group-onsemi 0:098463de4c5d 344 success = 1;
group-onsemi 0:098463de4c5d 345 break;
group-onsemi 0:098463de4c5d 346 case MODE_TEST_GLOBAL:
group-onsemi 0:098463de4c5d 347 case MODE_TEST_LOCAL:
group-onsemi 0:098463de4c5d 348 can->BTR |= CAN_BTR_LBKM;
group-onsemi 0:098463de4c5d 349 can->BTR &= ~CAN_BTR_SILM;
group-onsemi 0:098463de4c5d 350 success = 1;
group-onsemi 0:098463de4c5d 351 break;
group-onsemi 0:098463de4c5d 352 case MODE_TEST_SILENT:
group-onsemi 0:098463de4c5d 353 can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
group-onsemi 0:098463de4c5d 354 success = 1;
group-onsemi 0:098463de4c5d 355 break;
group-onsemi 0:098463de4c5d 356 default:
group-onsemi 0:098463de4c5d 357 success = 0;
group-onsemi 0:098463de4c5d 358 break;
group-onsemi 0:098463de4c5d 359 }
group-onsemi 0:098463de4c5d 360 can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
group-onsemi 0:098463de4c5d 361 while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
group-onsemi 0:098463de4c5d 362 }
group-onsemi 0:098463de4c5d 363 return success;
group-onsemi 0:098463de4c5d 364 }
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
group-onsemi 0:098463de4c5d 367 {
group-onsemi 0:098463de4c5d 368 CanHandle.Instance = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 369 CAN_FilterConfTypeDef sFilterConfig;
group-onsemi 0:098463de4c5d 370
group-onsemi 0:098463de4c5d 371 sFilterConfig.FilterNumber = handle;
group-onsemi 0:098463de4c5d 372 sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
group-onsemi 0:098463de4c5d 373 sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
group-onsemi 0:098463de4c5d 374 sFilterConfig.FilterIdHigh = (uint8_t)(id >> 8);
group-onsemi 0:098463de4c5d 375 sFilterConfig.FilterIdLow = (uint8_t) id;
group-onsemi 0:098463de4c5d 376 sFilterConfig.FilterMaskIdHigh = (uint8_t)(mask >> 8);
group-onsemi 0:098463de4c5d 377 sFilterConfig.FilterMaskIdLow = (uint8_t) mask;
group-onsemi 0:098463de4c5d 378 sFilterConfig.FilterFIFOAssignment = 0;
group-onsemi 0:098463de4c5d 379 sFilterConfig.FilterActivation = ENABLE;
group-onsemi 0:098463de4c5d 380 sFilterConfig.BankNumber = 14 + handle;
group-onsemi 0:098463de4c5d 381
group-onsemi 0:098463de4c5d 382 HAL_CAN_ConfigFilter(&CanHandle, &sFilterConfig);
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 return 0;
group-onsemi 0:098463de4c5d 385 }
group-onsemi 0:098463de4c5d 386
group-onsemi 0:098463de4c5d 387 static void can_irq(CANName name, int id)
group-onsemi 0:098463de4c5d 388 {
group-onsemi 0:098463de4c5d 389 uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
group-onsemi 0:098463de4c5d 390 CanHandle.Instance = (CAN_TypeDef *)name;
group-onsemi 0:098463de4c5d 391
group-onsemi 0:098463de4c5d 392 if (__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
group-onsemi 0:098463de4c5d 393 tmp1 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_0);
group-onsemi 0:098463de4c5d 394 tmp2 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_1);
group-onsemi 0:098463de4c5d 395 tmp3 = __HAL_CAN_TRANSMIT_STATUS(&CanHandle, CAN_TXMAILBOX_2);
group-onsemi 0:098463de4c5d 396 if (tmp1 || tmp2 || tmp3) {
group-onsemi 0:098463de4c5d 397 irq_handler(can_irq_ids[id], IRQ_TX);
group-onsemi 0:098463de4c5d 398 }
group-onsemi 0:098463de4c5d 399 }
group-onsemi 0:098463de4c5d 400
group-onsemi 0:098463de4c5d 401 tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
group-onsemi 0:098463de4c5d 402 tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 if ((tmp1 != 0) && tmp2) {
group-onsemi 0:098463de4c5d 405 irq_handler(can_irq_ids[id], IRQ_RX);
group-onsemi 0:098463de4c5d 406 }
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV);
group-onsemi 0:098463de4c5d 409 tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_EPV);
group-onsemi 0:098463de4c5d 410 tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
group-onsemi 0:098463de4c5d 411
group-onsemi 0:098463de4c5d 412 if (tmp1 && tmp2 && tmp3) {
group-onsemi 0:098463de4c5d 413 irq_handler(can_irq_ids[id], IRQ_PASSIVE);
group-onsemi 0:098463de4c5d 414 }
group-onsemi 0:098463de4c5d 415
group-onsemi 0:098463de4c5d 416 tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_BOF);
group-onsemi 0:098463de4c5d 417 tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_BOF);
group-onsemi 0:098463de4c5d 418 tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
group-onsemi 0:098463de4c5d 419 if (tmp1 && tmp2 && tmp3) {
group-onsemi 0:098463de4c5d 420 irq_handler(can_irq_ids[id], IRQ_BUS);
group-onsemi 0:098463de4c5d 421 }
group-onsemi 0:098463de4c5d 422
group-onsemi 0:098463de4c5d 423 tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR);
group-onsemi 0:098463de4c5d 424 if (tmp1 && tmp2 && tmp3) {
group-onsemi 0:098463de4c5d 425 irq_handler(can_irq_ids[id], IRQ_ERROR);
group-onsemi 0:098463de4c5d 426 }
group-onsemi 0:098463de4c5d 427 }
group-onsemi 0:098463de4c5d 428
group-onsemi 0:098463de4c5d 429 void CAN1_RX0_IRQHandler(void)
group-onsemi 0:098463de4c5d 430 {
group-onsemi 0:098463de4c5d 431 can_irq(CAN_1, 0);
group-onsemi 0:098463de4c5d 432 }
group-onsemi 0:098463de4c5d 433
group-onsemi 0:098463de4c5d 434 void CAN1_TX_IRQHandler(void)
group-onsemi 0:098463de4c5d 435 {
group-onsemi 0:098463de4c5d 436 can_irq(CAN_1, 0);
group-onsemi 0:098463de4c5d 437 }
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 void CAN1_SCE_IRQHandler(void)
group-onsemi 0:098463de4c5d 440 {
group-onsemi 0:098463de4c5d 441 can_irq(CAN_1, 0);
group-onsemi 0:098463de4c5d 442 }
group-onsemi 0:098463de4c5d 443
group-onsemi 0:098463de4c5d 444 void CAN2_RX0_IRQHandler(void)
group-onsemi 0:098463de4c5d 445 {
group-onsemi 0:098463de4c5d 446 can_irq(CAN_2, 1);
group-onsemi 0:098463de4c5d 447 }
group-onsemi 0:098463de4c5d 448
group-onsemi 0:098463de4c5d 449 void CAN2_TX_IRQHandler(void)
group-onsemi 0:098463de4c5d 450 {
group-onsemi 0:098463de4c5d 451 can_irq(CAN_2, 1);
group-onsemi 0:098463de4c5d 452 }
group-onsemi 0:098463de4c5d 453
group-onsemi 0:098463de4c5d 454 void CAN2_SCE_IRQHandler(void)
group-onsemi 0:098463de4c5d 455 {
group-onsemi 0:098463de4c5d 456 can_irq(CAN_2, 1);
group-onsemi 0:098463de4c5d 457 }
group-onsemi 0:098463de4c5d 458
group-onsemi 0:098463de4c5d 459 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
group-onsemi 0:098463de4c5d 460 {
group-onsemi 0:098463de4c5d 461
group-onsemi 0:098463de4c5d 462 CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
group-onsemi 0:098463de4c5d 463 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 464 uint32_t vector = 0;
group-onsemi 0:098463de4c5d 465 uint32_t ier;
group-onsemi 0:098463de4c5d 466
group-onsemi 0:098463de4c5d 467 if (obj->can == CAN_1) {
group-onsemi 0:098463de4c5d 468 switch (type) {
group-onsemi 0:098463de4c5d 469 case IRQ_RX:
group-onsemi 0:098463de4c5d 470 ier = CAN_IT_FMP0;
group-onsemi 0:098463de4c5d 471 irq_n = CAN1_RX0_IRQn;
group-onsemi 0:098463de4c5d 472 vector = (uint32_t)&CAN1_RX0_IRQHandler;
group-onsemi 0:098463de4c5d 473 break;
group-onsemi 0:098463de4c5d 474 case IRQ_TX:
group-onsemi 0:098463de4c5d 475 ier = CAN_IT_TME;
group-onsemi 0:098463de4c5d 476 irq_n = CAN1_TX_IRQn;
group-onsemi 0:098463de4c5d 477 vector = (uint32_t)&CAN1_TX_IRQHandler;
group-onsemi 0:098463de4c5d 478 break;
group-onsemi 0:098463de4c5d 479 case IRQ_ERROR:
group-onsemi 0:098463de4c5d 480 ier = CAN_IT_ERR;
group-onsemi 0:098463de4c5d 481 irq_n = CAN1_SCE_IRQn;
group-onsemi 0:098463de4c5d 482 vector = (uint32_t)&CAN1_SCE_IRQHandler;
group-onsemi 0:098463de4c5d 483 break;
group-onsemi 0:098463de4c5d 484 case IRQ_PASSIVE:
group-onsemi 0:098463de4c5d 485 ier = CAN_IT_EPV;
group-onsemi 0:098463de4c5d 486 irq_n = CAN1_SCE_IRQn;
group-onsemi 0:098463de4c5d 487 vector = (uint32_t)&CAN1_SCE_IRQHandler;
group-onsemi 0:098463de4c5d 488 break;
group-onsemi 0:098463de4c5d 489 case IRQ_BUS:
group-onsemi 0:098463de4c5d 490 ier = CAN_IT_BOF;
group-onsemi 0:098463de4c5d 491 irq_n = CAN1_SCE_IRQn;
group-onsemi 0:098463de4c5d 492 vector = (uint32_t)&CAN1_SCE_IRQHandler;
group-onsemi 0:098463de4c5d 493 break;
group-onsemi 0:098463de4c5d 494 default:
group-onsemi 0:098463de4c5d 495 return;
group-onsemi 0:098463de4c5d 496 }
group-onsemi 0:098463de4c5d 497 } else {
group-onsemi 0:098463de4c5d 498 switch (type) {
group-onsemi 0:098463de4c5d 499 case IRQ_RX:
group-onsemi 0:098463de4c5d 500 ier = CAN_IT_FMP0;
group-onsemi 0:098463de4c5d 501 irq_n = CAN2_RX0_IRQn;
group-onsemi 0:098463de4c5d 502 vector = (uint32_t)&CAN2_RX0_IRQHandler;
group-onsemi 0:098463de4c5d 503 break;
group-onsemi 0:098463de4c5d 504 case IRQ_TX:
group-onsemi 0:098463de4c5d 505 ier = CAN_IT_TME;
group-onsemi 0:098463de4c5d 506 irq_n = CAN2_TX_IRQn;
group-onsemi 0:098463de4c5d 507 vector = (uint32_t)&CAN2_TX_IRQHandler;
group-onsemi 0:098463de4c5d 508 break;
group-onsemi 0:098463de4c5d 509 case IRQ_ERROR:
group-onsemi 0:098463de4c5d 510 ier = CAN_IT_ERR;
group-onsemi 0:098463de4c5d 511 irq_n = CAN2_SCE_IRQn;
group-onsemi 0:098463de4c5d 512 vector = (uint32_t)&CAN2_SCE_IRQHandler;
group-onsemi 0:098463de4c5d 513 break;
group-onsemi 0:098463de4c5d 514 case IRQ_PASSIVE:
group-onsemi 0:098463de4c5d 515 ier = CAN_IT_EPV;
group-onsemi 0:098463de4c5d 516 irq_n = CAN2_SCE_IRQn;
group-onsemi 0:098463de4c5d 517 vector = (uint32_t)&CAN2_SCE_IRQHandler;
group-onsemi 0:098463de4c5d 518 break;
group-onsemi 0:098463de4c5d 519 case IRQ_BUS:
group-onsemi 0:098463de4c5d 520 ier = CAN_IT_BOF;
group-onsemi 0:098463de4c5d 521 irq_n = CAN2_SCE_IRQn;
group-onsemi 0:098463de4c5d 522 vector = (uint32_t)&CAN2_SCE_IRQHandler;
group-onsemi 0:098463de4c5d 523 break;
group-onsemi 0:098463de4c5d 524 default:
group-onsemi 0:098463de4c5d 525 return;
group-onsemi 0:098463de4c5d 526 }
group-onsemi 0:098463de4c5d 527 }
group-onsemi 0:098463de4c5d 528
group-onsemi 0:098463de4c5d 529 if (enable) {
group-onsemi 0:098463de4c5d 530 can->IER |= ier;
group-onsemi 0:098463de4c5d 531 } else {
group-onsemi 0:098463de4c5d 532 can->IER &= ~ier;
group-onsemi 0:098463de4c5d 533 }
group-onsemi 0:098463de4c5d 534
group-onsemi 0:098463de4c5d 535 NVIC_SetVector(irq_n, vector);
group-onsemi 0:098463de4c5d 536 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 537 }
group-onsemi 0:098463de4c5d 538
group-onsemi 0:098463de4c5d 539 #endif // DEVICE_CAN
group-onsemi 0:098463de4c5d 540