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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC11U6X/device/LPC11U6x.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1
group-onsemi 0:098463de4c5d 2 /****************************************************************************************************//**
group-onsemi 0:098463de4c5d 3 * @file LPC11U6x.h
group-onsemi 0:098463de4c5d 4 *
group-onsemi 0:098463de4c5d 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
group-onsemi 0:098463de4c5d 6 * LPC11U6x from .
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * @version V0.4
group-onsemi 0:098463de4c5d 9 * @date 22. October 2013
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * @note Generated with SVDConv V2.81a
group-onsemi 0:098463de4c5d 12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * modified by Keil
group-onsemi 0:098463de4c5d 15 *******************************************************************************************************/
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 /** @addtogroup (null)
group-onsemi 0:098463de4c5d 20 * @{
group-onsemi 0:098463de4c5d 21 */
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 /** @addtogroup LPC11U6x
group-onsemi 0:098463de4c5d 24 * @{
group-onsemi 0:098463de4c5d 25 */
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 #ifndef LPC11U6X_H
group-onsemi 0:098463de4c5d 28 #define LPC11U6X_H
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 31 extern "C" {
group-onsemi 0:098463de4c5d 32 #endif
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 /* ------------------------- Interrupt Number Definition ------------------------ */
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 typedef enum {
group-onsemi 0:098463de4c5d 38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
group-onsemi 0:098463de4c5d 39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
group-onsemi 0:098463de4c5d 40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
group-onsemi 0:098463de4c5d 41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
group-onsemi 0:098463de4c5d 49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
group-onsemi 0:098463de4c5d 50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
group-onsemi 0:098463de4c5d 51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
group-onsemi 0:098463de4c5d 52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
group-onsemi 0:098463de4c5d 53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
group-onsemi 0:098463de4c5d 54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
group-onsemi 0:098463de4c5d 55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
group-onsemi 0:098463de4c5d 56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
group-onsemi 0:098463de4c5d 57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
group-onsemi 0:098463de4c5d 58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
group-onsemi 0:098463de4c5d 59 GINT0_IRQn = 8, /*!< 8 GINT0 */
group-onsemi 0:098463de4c5d 60 GINT1_IRQn = 9, /*!< 9 GINT1 */
group-onsemi 0:098463de4c5d 61 I2C1_IRQn = 10, /*!< 10 I2C1 */
group-onsemi 0:098463de4c5d 62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
group-onsemi 0:098463de4c5d 63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
group-onsemi 0:098463de4c5d 64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
group-onsemi 0:098463de4c5d 65 SSP1_IRQn = 14, /*!< 14 SSP1 */
group-onsemi 0:098463de4c5d 66 I2C0_IRQn = 15, /*!< 15 I2C0 */
group-onsemi 0:098463de4c5d 67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
group-onsemi 0:098463de4c5d 68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
group-onsemi 0:098463de4c5d 69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
group-onsemi 0:098463de4c5d 70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
group-onsemi 0:098463de4c5d 71 SSP0_IRQn = 20, /*!< 20 SSP0 */
group-onsemi 0:098463de4c5d 72 USART0_IRQn = 21, /*!< 21 USART0 */
group-onsemi 0:098463de4c5d 73 USB_IRQn = 22, /*!< 22 USB */
group-onsemi 0:098463de4c5d 74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
group-onsemi 0:098463de4c5d 75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
group-onsemi 0:098463de4c5d 76 RTC_IRQn = 25, /*!< 25 RTC */
group-onsemi 0:098463de4c5d 77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
group-onsemi 0:098463de4c5d 78 FLASH_IRQn = 27, /*!< 27 FLASH */
group-onsemi 0:098463de4c5d 79 DMA_IRQn = 28, /*!< 28 DMA */
group-onsemi 0:098463de4c5d 80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
group-onsemi 0:098463de4c5d 81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
group-onsemi 0:098463de4c5d 82 } IRQn_Type;
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 /** @addtogroup Configuration_of_CMSIS
group-onsemi 0:098463de4c5d 86 * @{
group-onsemi 0:098463de4c5d 87 */
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 /* ================================================================================ */
group-onsemi 0:098463de4c5d 91 /* ================ Processor and Core Peripheral Section ================ */
group-onsemi 0:098463de4c5d 92 /* ================================================================================ */
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
group-onsemi 0:098463de4c5d 95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
group-onsemi 0:098463de4c5d 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
group-onsemi 0:098463de4c5d 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
group-onsemi 0:098463de4c5d 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
group-onsemi 0:098463de4c5d 99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
group-onsemi 0:098463de4c5d 100 /** @} */ /* End of group Configuration_of_CMSIS */
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
group-onsemi 0:098463de4c5d 103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 /* ================================================================================ */
group-onsemi 0:098463de4c5d 107 /* ================ Device Specific Peripheral Section ================ */
group-onsemi 0:098463de4c5d 108 /* ================================================================================ */
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /** @addtogroup Device_Peripheral_Registers
group-onsemi 0:098463de4c5d 112 * @{
group-onsemi 0:098463de4c5d 113 */
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 /* ------------------- Start of section using anonymous unions ------------------ */
group-onsemi 0:098463de4c5d 117 #if defined(__CC_ARM)
group-onsemi 0:098463de4c5d 118 #pragma push
group-onsemi 0:098463de4c5d 119 #pragma anon_unions
group-onsemi 0:098463de4c5d 120 #elif defined(__ICCARM__)
group-onsemi 0:098463de4c5d 121 #pragma language=extended
group-onsemi 0:098463de4c5d 122 #elif defined(__GNUC__)
group-onsemi 0:098463de4c5d 123 /* anonymous unions are enabled by default */
group-onsemi 0:098463de4c5d 124 #elif defined(__TMS470__)
group-onsemi 0:098463de4c5d 125 /* anonymous unions are enabled by default */
group-onsemi 0:098463de4c5d 126 #elif defined(__TASKING__)
group-onsemi 0:098463de4c5d 127 #pragma warning 586
group-onsemi 0:098463de4c5d 128 #else
group-onsemi 0:098463de4c5d 129 #warning Not supported compiler type
group-onsemi 0:098463de4c5d 130 #endif
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133
group-onsemi 0:098463de4c5d 134 /* ================================================================================ */
group-onsemi 0:098463de4c5d 135 /* ================ I2C0 ================ */
group-onsemi 0:098463de4c5d 136 /* ================================================================================ */
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 /**
group-onsemi 0:098463de4c5d 140 * @brief I2C-bus controller (I2C0)
group-onsemi 0:098463de4c5d 141 */
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 typedef struct { /*!< I2C0 Structure */
group-onsemi 0:098463de4c5d 144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
group-onsemi 0:098463de4c5d 145 this register, the corresponding bit in the I2C control register
group-onsemi 0:098463de4c5d 146 is set. Writing a zero has no effect on the corresponding bit
group-onsemi 0:098463de4c5d 147 in the I2C control register. */
group-onsemi 0:098463de4c5d 148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
group-onsemi 0:098463de4c5d 149 detailed status codes that allow software to determine the next
group-onsemi 0:098463de4c5d 150 action needed. */
group-onsemi 0:098463de4c5d 151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
group-onsemi 0:098463de4c5d 152 to be transmitted is written to this register. During master
group-onsemi 0:098463de4c5d 153 or slave receive mode, data that has been received may be read
group-onsemi 0:098463de4c5d 154 from this register. */
group-onsemi 0:098463de4c5d 155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
group-onsemi 0:098463de4c5d 156 for operation of the I2C interface in slave mode, and is not
group-onsemi 0:098463de4c5d 157 used in master mode. The least significant bit determines whether
group-onsemi 0:098463de4c5d 158 a slave responds to the General Call address. */
group-onsemi 0:098463de4c5d 159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
group-onsemi 0:098463de4c5d 160 time of the I2C clock. */
group-onsemi 0:098463de4c5d 161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
group-onsemi 0:098463de4c5d 162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
group-onsemi 0:098463de4c5d 163 clock frequency generated by an I2C master and certain times
group-onsemi 0:098463de4c5d 164 used in slave mode. */
group-onsemi 0:098463de4c5d 165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
group-onsemi 0:098463de4c5d 166 this register, the corresponding bit in the I2C control register
group-onsemi 0:098463de4c5d 167 is cleared. Writing a zero has no effect on the corresponding
group-onsemi 0:098463de4c5d 168 bit in the I2C control register. */
group-onsemi 0:098463de4c5d 169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
group-onsemi 0:098463de4c5d 170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
group-onsemi 0:098463de4c5d 171 for operation of the I2C interface in slave mode, and is not
group-onsemi 0:098463de4c5d 172 used in master mode. The least significant bit determines whether
group-onsemi 0:098463de4c5d 173 a slave responds to the General Call address. */
group-onsemi 0:098463de4c5d 174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
group-onsemi 0:098463de4c5d 175 for operation of the I2C interface in slave mode, and is not
group-onsemi 0:098463de4c5d 176 used in master mode. The least significant bit determines whether
group-onsemi 0:098463de4c5d 177 a slave responds to the General Call address. */
group-onsemi 0:098463de4c5d 178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
group-onsemi 0:098463de4c5d 179 for operation of the I2C interface in slave mode, and is not
group-onsemi 0:098463de4c5d 180 used in master mode. The least significant bit determines whether
group-onsemi 0:098463de4c5d 181 a slave responds to the General Call address. */
group-onsemi 0:098463de4c5d 182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
group-onsemi 0:098463de4c5d 183 shift register will be transferred to the DATA_BUFFER automatically
group-onsemi 0:098463de4c5d 184 after every nine bits (8 bits of data plus ACK or NACK) has
group-onsemi 0:098463de4c5d 185 been received on the bus. */
group-onsemi 0:098463de4c5d 186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
group-onsemi 0:098463de4c5d 187 with I2ADR0 to determine an address match. The mask register
group-onsemi 0:098463de4c5d 188 has no effect when comparing to the General Call address (0000000). */
group-onsemi 0:098463de4c5d 189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
group-onsemi 0:098463de4c5d 190 with I2ADR0 to determine an address match. The mask register
group-onsemi 0:098463de4c5d 191 has no effect when comparing to the General Call address (0000000). */
group-onsemi 0:098463de4c5d 192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
group-onsemi 0:098463de4c5d 193 with I2ADR0 to determine an address match. The mask register
group-onsemi 0:098463de4c5d 194 has no effect when comparing to the General Call address (0000000). */
group-onsemi 0:098463de4c5d 195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
group-onsemi 0:098463de4c5d 196 with I2ADR0 to determine an address match. The mask register
group-onsemi 0:098463de4c5d 197 has no effect when comparing to the General Call address (0000000). */
group-onsemi 0:098463de4c5d 198 } LPC_I2C0_Type;
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200
group-onsemi 0:098463de4c5d 201 /* ================================================================================ */
group-onsemi 0:098463de4c5d 202 /* ================ WWDT ================ */
group-onsemi 0:098463de4c5d 203 /* ================================================================================ */
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 /**
group-onsemi 0:098463de4c5d 207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
group-onsemi 0:098463de4c5d 208 */
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 typedef struct { /*!< WWDT Structure */
group-onsemi 0:098463de4c5d 211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
group-onsemi 0:098463de4c5d 212 and status of the Watchdog Timer. */
group-onsemi 0:098463de4c5d 213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
group-onsemi 0:098463de4c5d 214 the time-out value. */
group-onsemi 0:098463de4c5d 215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
group-onsemi 0:098463de4c5d 216 to this register reloads the Watchdog timer with the value contained
group-onsemi 0:098463de4c5d 217 in WDTC. */
group-onsemi 0:098463de4c5d 218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
group-onsemi 0:098463de4c5d 219 the current value of the Watchdog timer. */
group-onsemi 0:098463de4c5d 220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
group-onsemi 0:098463de4c5d 221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
group-onsemi 0:098463de4c5d 222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
group-onsemi 0:098463de4c5d 223 } LPC_WWDT_Type;
group-onsemi 0:098463de4c5d 224
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 /* ================================================================================ */
group-onsemi 0:098463de4c5d 227 /* ================ USART0 ================ */
group-onsemi 0:098463de4c5d 228 /* ================================================================================ */
group-onsemi 0:098463de4c5d 229
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 /**
group-onsemi 0:098463de4c5d 232 * @brief USART0 (USART0)
group-onsemi 0:098463de4c5d 233 */
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 typedef struct { /*!< USART0 Structure */
group-onsemi 0:098463de4c5d 236
group-onsemi 0:098463de4c5d 237 union {
group-onsemi 0:098463de4c5d 238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
group-onsemi 0:098463de4c5d 239 value. The full divisor is used to generate a baud rate from
group-onsemi 0:098463de4c5d 240 the fractional rate divider. (DLAB=1) */
group-onsemi 0:098463de4c5d 241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
group-onsemi 0:098463de4c5d 242 is written here. (DLAB=0) */
group-onsemi 0:098463de4c5d 243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
group-onsemi 0:098463de4c5d 244 to be read. (DLAB=0) */
group-onsemi 0:098463de4c5d 245 };
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 union {
group-onsemi 0:098463de4c5d 248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
group-onsemi 0:098463de4c5d 249 bits for the 7 potential USART interrupts. (DLAB=0) */
group-onsemi 0:098463de4c5d 250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
group-onsemi 0:098463de4c5d 251 value. The full divisor is used to generate a baud rate from
group-onsemi 0:098463de4c5d 252 the fractional rate divider. (DLAB=1) */
group-onsemi 0:098463de4c5d 253 };
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255 union {
group-onsemi 0:098463de4c5d 256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
group-onsemi 0:098463de4c5d 257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
group-onsemi 0:098463de4c5d 258 };
group-onsemi 0:098463de4c5d 259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
group-onsemi 0:098463de4c5d 260 and break generation. */
group-onsemi 0:098463de4c5d 261 __IO uint32_t MCR; /*!< Modem Control Register. */
group-onsemi 0:098463de4c5d 262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
group-onsemi 0:098463de4c5d 263 status, including line errors. */
group-onsemi 0:098463de4c5d 264 __I uint32_t MSR; /*!< Modem Status Register. */
group-onsemi 0:098463de4c5d 265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
group-onsemi 0:098463de4c5d 266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
group-onsemi 0:098463de4c5d 267 feature. */
group-onsemi 0:098463de4c5d 268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
group-onsemi 0:098463de4c5d 269 control) mode. */
group-onsemi 0:098463de4c5d 270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
group-onsemi 0:098463de4c5d 271 baud rate divider. */
group-onsemi 0:098463de4c5d 272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
group-onsemi 0:098463de4c5d 273 each bit time. */
group-onsemi 0:098463de4c5d 274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
group-onsemi 0:098463de4c5d 275 with software flow control. */
group-onsemi 0:098463de4c5d 276 __I uint32_t RESERVED0[3];
group-onsemi 0:098463de4c5d 277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
group-onsemi 0:098463de4c5d 278 __I uint32_t RESERVED1;
group-onsemi 0:098463de4c5d 279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
group-onsemi 0:098463de4c5d 280 the Smart Card Interface feature. */
group-onsemi 0:098463de4c5d 281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
group-onsemi 0:098463de4c5d 282 aspects of RS-485/EIA-485 modes. */
group-onsemi 0:098463de4c5d 283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
group-onsemi 0:098463de4c5d 284 for RS-485/EIA-485 mode. */
group-onsemi 0:098463de4c5d 285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
group-onsemi 0:098463de4c5d 286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
group-onsemi 0:098463de4c5d 287 } LPC_USART0_Type;
group-onsemi 0:098463de4c5d 288
group-onsemi 0:098463de4c5d 289
group-onsemi 0:098463de4c5d 290 /* ================================================================================ */
group-onsemi 0:098463de4c5d 291 /* ================ CT16B0 ================ */
group-onsemi 0:098463de4c5d 292 /* ================================================================================ */
group-onsemi 0:098463de4c5d 293
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 /**
group-onsemi 0:098463de4c5d 296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
group-onsemi 0:098463de4c5d 297 */
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 typedef struct { /*!< CT16B0 Structure */
group-onsemi 0:098463de4c5d 300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
group-onsemi 0:098463de4c5d 301 The IR can be read to identify which of eight possible interrupt
group-onsemi 0:098463de4c5d 302 sources are pending. */
group-onsemi 0:098463de4c5d 303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
group-onsemi 0:098463de4c5d 304 Counter functions. The Timer Counter can be disabled or reset
group-onsemi 0:098463de4c5d 305 through the TCR. */
group-onsemi 0:098463de4c5d 306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
group-onsemi 0:098463de4c5d 307 of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
group-onsemi 0:098463de4c5d 309 to this value, the next clock increments the TC and clears the
group-onsemi 0:098463de4c5d 310 PC. */
group-onsemi 0:098463de4c5d 311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
group-onsemi 0:098463de4c5d 312 to the value stored in PR. When the value in PR is reached,
group-onsemi 0:098463de4c5d 313 the TC is incremented and the PC is cleared. The PC is observable
group-onsemi 0:098463de4c5d 314 and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
group-onsemi 0:098463de4c5d 316 is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 318 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 319 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 321 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 322 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 324 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 325 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 327 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 328 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
group-onsemi 0:098463de4c5d 330 capture inputs are used to load the Capture Registers and whether
group-onsemi 0:098463de4c5d 331 or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
group-onsemi 0:098463de4c5d 333 is an event on the CAP input. */
group-onsemi 0:098463de4c5d 334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
group-onsemi 0:098463de4c5d 335 is an event on the CAP input. */
group-onsemi 0:098463de4c5d 336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
group-onsemi 0:098463de4c5d 337 is an event on the CAP input. */
group-onsemi 0:098463de4c5d 338 __I uint32_t RESERVED0;
group-onsemi 0:098463de4c5d 339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
group-onsemi 0:098463de4c5d 340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
group-onsemi 0:098463de4c5d 341 __I uint32_t RESERVED1[12];
group-onsemi 0:098463de4c5d 342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
group-onsemi 0:098463de4c5d 343 mode, and in Counter mode selects the signal and edge(s) for
group-onsemi 0:098463de4c5d 344 counting. */
group-onsemi 0:098463de4c5d 345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
group-onsemi 0:098463de4c5d 346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
group-onsemi 0:098463de4c5d 347 } LPC_CT16B0_Type;
group-onsemi 0:098463de4c5d 348
group-onsemi 0:098463de4c5d 349
group-onsemi 0:098463de4c5d 350 /* ================================================================================ */
group-onsemi 0:098463de4c5d 351 /* ================ CT32B0 ================ */
group-onsemi 0:098463de4c5d 352 /* ================================================================================ */
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354
group-onsemi 0:098463de4c5d 355 /**
group-onsemi 0:098463de4c5d 356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
group-onsemi 0:098463de4c5d 357 */
group-onsemi 0:098463de4c5d 358
group-onsemi 0:098463de4c5d 359 typedef struct { /*!< CT32B0 Structure */
group-onsemi 0:098463de4c5d 360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
group-onsemi 0:098463de4c5d 361 The IR can be read to identify which of eight possible interrupt
group-onsemi 0:098463de4c5d 362 sources are pending. */
group-onsemi 0:098463de4c5d 363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
group-onsemi 0:098463de4c5d 364 Counter functions. The Timer Counter can be disabled or reset
group-onsemi 0:098463de4c5d 365 through the TCR. */
group-onsemi 0:098463de4c5d 366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
group-onsemi 0:098463de4c5d 367 of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
group-onsemi 0:098463de4c5d 369 to this value, the next clock increments the TC and clears the
group-onsemi 0:098463de4c5d 370 PC. */
group-onsemi 0:098463de4c5d 371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
group-onsemi 0:098463de4c5d 372 to the value stored in PR. When the value in PR is reached,
group-onsemi 0:098463de4c5d 373 the TC is incremented and the PC is cleared. The PC is observable
group-onsemi 0:098463de4c5d 374 and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
group-onsemi 0:098463de4c5d 376 is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 378 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 379 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 381 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 382 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 384 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 385 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
group-onsemi 0:098463de4c5d 387 TC, stop both the TC and PC, and/or generate an interrupt every
group-onsemi 0:098463de4c5d 388 time MR0 matches the TC. */
group-onsemi 0:098463de4c5d 389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
group-onsemi 0:098463de4c5d 390 capture inputs are used to load the Capture Registers and whether
group-onsemi 0:098463de4c5d 391 or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
group-onsemi 0:098463de4c5d 393 is an event on the CAP input. */
group-onsemi 0:098463de4c5d 394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
group-onsemi 0:098463de4c5d 395 is an event on the CAP input. */
group-onsemi 0:098463de4c5d 396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
group-onsemi 0:098463de4c5d 397 is an event on the CAP input. */
group-onsemi 0:098463de4c5d 398 __I uint32_t RESERVED0;
group-onsemi 0:098463de4c5d 399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
group-onsemi 0:098463de4c5d 400 and the external match pins CT32Bn_MAT[3:0]. */
group-onsemi 0:098463de4c5d 401 __I uint32_t RESERVED1[12];
group-onsemi 0:098463de4c5d 402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
group-onsemi 0:098463de4c5d 403 mode, and in Counter mode selects the signal and edge(s) for
group-onsemi 0:098463de4c5d 404 counting. */
group-onsemi 0:098463de4c5d 405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
group-onsemi 0:098463de4c5d 406 match pins CT32Bn_MAT[3:0]. */
group-onsemi 0:098463de4c5d 407 } LPC_CT32B0_Type;
group-onsemi 0:098463de4c5d 408
group-onsemi 0:098463de4c5d 409
group-onsemi 0:098463de4c5d 410 /* ================================================================================ */
group-onsemi 0:098463de4c5d 411 /* ================ ADC ================ */
group-onsemi 0:098463de4c5d 412 /* ================================================================================ */
group-onsemi 0:098463de4c5d 413
group-onsemi 0:098463de4c5d 414
group-onsemi 0:098463de4c5d 415 /**
group-onsemi 0:098463de4c5d 416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
group-onsemi 0:098463de4c5d 417 */
group-onsemi 0:098463de4c5d 418
group-onsemi 0:098463de4c5d 419 typedef struct { /*!< ADC Structure */
group-onsemi 0:098463de4c5d 420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
group-onsemi 0:098463de4c5d 421 bits for each sequence and the A/D power-down bit. */
group-onsemi 0:098463de4c5d 422 __I uint32_t RESERVED0;
group-onsemi 0:098463de4c5d 423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
group-onsemi 0:098463de4c5d 424 and channel selection for conversion sequence-A. Also specifies
group-onsemi 0:098463de4c5d 425 interrupt mode for sequence-A. */
group-onsemi 0:098463de4c5d 426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
group-onsemi 0:098463de4c5d 427 and channel selection for conversion sequence-B. Also specifies
group-onsemi 0:098463de4c5d 428 interrupt mode for sequence-B. */
group-onsemi 0:098463de4c5d 429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
group-onsemi 0:098463de4c5d 430 the result of the most recent A/D conversion performed under
group-onsemi 0:098463de4c5d 431 sequence-A */
group-onsemi 0:098463de4c5d 432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
group-onsemi 0:098463de4c5d 433 the result of the most recent A/D conversion performed under
group-onsemi 0:098463de4c5d 434 sequence-B */
group-onsemi 0:098463de4c5d 435 __I uint32_t RESERVED1[2];
group-onsemi 0:098463de4c5d 436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
group-onsemi 0:098463de4c5d 437 of the most recent conversion completed on channel 0. */
group-onsemi 0:098463de4c5d 438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
group-onsemi 0:098463de4c5d 439 level for automatic threshold comparison for any channels linked
group-onsemi 0:098463de4c5d 440 to threshold pair 0. */
group-onsemi 0:098463de4c5d 441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
group-onsemi 0:098463de4c5d 442 level for automatic threshold comparison for any channels linked
group-onsemi 0:098463de4c5d 443 to threshold pair 1. */
group-onsemi 0:098463de4c5d 444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
group-onsemi 0:098463de4c5d 445 level for automatic threshold comparison for any channels linked
group-onsemi 0:098463de4c5d 446 to threshold pair 0. */
group-onsemi 0:098463de4c5d 447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
group-onsemi 0:098463de4c5d 448 level for automatic threshold comparison for any channels linked
group-onsemi 0:098463de4c5d 449 to threshold pair 1. */
group-onsemi 0:098463de4c5d 450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
group-onsemi 0:098463de4c5d 451 threshold compare registers are to be used for each channel */
group-onsemi 0:098463de4c5d 452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
group-onsemi 0:098463de4c5d 453 bits that enable the sequence-A, sequence-B, threshold compare
group-onsemi 0:098463de4c5d 454 and data overrun interrupts to be generated. */
group-onsemi 0:098463de4c5d 455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
group-onsemi 0:098463de4c5d 456 and the individual component overrun and threshold-compare flags.
group-onsemi 0:098463de4c5d 457 (The overrun bits replicate information stored in the result
group-onsemi 0:098463de4c5d 458 registers). */
group-onsemi 0:098463de4c5d 459 __IO uint32_t TRM; /*!< ADC trim register. */
group-onsemi 0:098463de4c5d 460 } LPC_ADC_Type;
group-onsemi 0:098463de4c5d 461
group-onsemi 0:098463de4c5d 462
group-onsemi 0:098463de4c5d 463 /* ================================================================================ */
group-onsemi 0:098463de4c5d 464 /* ================ RTC ================ */
group-onsemi 0:098463de4c5d 465 /* ================================================================================ */
group-onsemi 0:098463de4c5d 466
group-onsemi 0:098463de4c5d 467
group-onsemi 0:098463de4c5d 468 /**
group-onsemi 0:098463de4c5d 469 * @brief Real-Time Clock (RTC) (RTC)
group-onsemi 0:098463de4c5d 470 */
group-onsemi 0:098463de4c5d 471
group-onsemi 0:098463de4c5d 472 typedef struct { /*!< RTC Structure */
group-onsemi 0:098463de4c5d 473 __IO uint32_t CTRL; /*!< RTC control register */
group-onsemi 0:098463de4c5d 474 __IO uint32_t MATCH; /*!< RTC match register */
group-onsemi 0:098463de4c5d 475 __IO uint32_t COUNT; /*!< RTC counter register */
group-onsemi 0:098463de4c5d 476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
group-onsemi 0:098463de4c5d 477 } LPC_RTC_Type;
group-onsemi 0:098463de4c5d 478
group-onsemi 0:098463de4c5d 479
group-onsemi 0:098463de4c5d 480 /* ================================================================================ */
group-onsemi 0:098463de4c5d 481 /* ================ DMATRIGMUX ================ */
group-onsemi 0:098463de4c5d 482 /* ================================================================================ */
group-onsemi 0:098463de4c5d 483
group-onsemi 0:098463de4c5d 484
group-onsemi 0:098463de4c5d 485 /**
group-onsemi 0:098463de4c5d 486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
group-onsemi 0:098463de4c5d 487 */
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 typedef struct { /*!< DMATRIGMUX Structure */
group-onsemi 0:098463de4c5d 490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
group-onsemi 0:098463de4c5d 491 } LPC_DMATRIGMUX_Type;
group-onsemi 0:098463de4c5d 492
group-onsemi 0:098463de4c5d 493
group-onsemi 0:098463de4c5d 494 /* ================================================================================ */
group-onsemi 0:098463de4c5d 495 /* ================ PMU ================ */
group-onsemi 0:098463de4c5d 496 /* ================================================================================ */
group-onsemi 0:098463de4c5d 497
group-onsemi 0:098463de4c5d 498
group-onsemi 0:098463de4c5d 499 /**
group-onsemi 0:098463de4c5d 500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
group-onsemi 0:098463de4c5d 501 */
group-onsemi 0:098463de4c5d 502
group-onsemi 0:098463de4c5d 503 typedef struct { /*!< PMU Structure */
group-onsemi 0:098463de4c5d 504 __IO uint32_t PCON; /*!< Power control register */
group-onsemi 0:098463de4c5d 505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
group-onsemi 0:098463de4c5d 506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
group-onsemi 0:098463de4c5d 507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
group-onsemi 0:098463de4c5d 508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
group-onsemi 0:098463de4c5d 509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
group-onsemi 0:098463de4c5d 510 } LPC_PMU_Type;
group-onsemi 0:098463de4c5d 511
group-onsemi 0:098463de4c5d 512
group-onsemi 0:098463de4c5d 513 /* ================================================================================ */
group-onsemi 0:098463de4c5d 514 /* ================ FLASHCTRL ================ */
group-onsemi 0:098463de4c5d 515 /* ================================================================================ */
group-onsemi 0:098463de4c5d 516
group-onsemi 0:098463de4c5d 517
group-onsemi 0:098463de4c5d 518 /**
group-onsemi 0:098463de4c5d 519 * @brief Flash controller (FLASHCTRL)
group-onsemi 0:098463de4c5d 520 */
group-onsemi 0:098463de4c5d 521
group-onsemi 0:098463de4c5d 522 typedef struct { /*!< FLASHCTRL Structure */
group-onsemi 0:098463de4c5d 523 __I uint32_t RESERVED0[4];
group-onsemi 0:098463de4c5d 524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
group-onsemi 0:098463de4c5d 525 __I uint32_t RESERVED1[3];
group-onsemi 0:098463de4c5d 526 __IO uint32_t FMSSTART; /*!< Signature start address register */
group-onsemi 0:098463de4c5d 527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
group-onsemi 0:098463de4c5d 528 __I uint32_t RESERVED2;
group-onsemi 0:098463de4c5d 529 __I uint32_t FMSW0; /*!< Signature Word */
group-onsemi 0:098463de4c5d 530 } LPC_FLASHCTRL_Type;
group-onsemi 0:098463de4c5d 531
group-onsemi 0:098463de4c5d 532
group-onsemi 0:098463de4c5d 533 /* ================================================================================ */
group-onsemi 0:098463de4c5d 534 /* ================ SSP0 ================ */
group-onsemi 0:098463de4c5d 535 /* ================================================================================ */
group-onsemi 0:098463de4c5d 536
group-onsemi 0:098463de4c5d 537
group-onsemi 0:098463de4c5d 538 /**
group-onsemi 0:098463de4c5d 539 * @brief SSP/SPI (SSP0)
group-onsemi 0:098463de4c5d 540 */
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 typedef struct { /*!< SSP0 Structure */
group-onsemi 0:098463de4c5d 543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
group-onsemi 0:098463de4c5d 544 and data size. */
group-onsemi 0:098463de4c5d 545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
group-onsemi 0:098463de4c5d 546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
group-onsemi 0:098463de4c5d 547 the receive FIFO. */
group-onsemi 0:098463de4c5d 548 __I uint32_t SR; /*!< Status Register */
group-onsemi 0:098463de4c5d 549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
group-onsemi 0:098463de4c5d 550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
group-onsemi 0:098463de4c5d 551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
group-onsemi 0:098463de4c5d 552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
group-onsemi 0:098463de4c5d 553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
group-onsemi 0:098463de4c5d 554 } LPC_SSP0_Type;
group-onsemi 0:098463de4c5d 555
group-onsemi 0:098463de4c5d 556
group-onsemi 0:098463de4c5d 557 /* ================================================================================ */
group-onsemi 0:098463de4c5d 558 /* ================ IOCON ================ */
group-onsemi 0:098463de4c5d 559 /* ================================================================================ */
group-onsemi 0:098463de4c5d 560
group-onsemi 0:098463de4c5d 561
group-onsemi 0:098463de4c5d 562 /**
group-onsemi 0:098463de4c5d 563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
group-onsemi 0:098463de4c5d 564 */
group-onsemi 0:098463de4c5d 565
group-onsemi 0:098463de4c5d 566 typedef struct { /*!< IOCON Structure */
group-onsemi 0:098463de4c5d 567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
group-onsemi 0:098463de4c5d 591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
group-onsemi 0:098463de4c5d 623 __I uint32_t RESERVED0[4];
group-onsemi 0:098463de4c5d 624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 626 __I uint32_t RESERVED1;
group-onsemi 0:098463de4c5d 627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
group-onsemi 0:098463de4c5d 649 } LPC_IOCON_Type;
group-onsemi 0:098463de4c5d 650
group-onsemi 0:098463de4c5d 651
group-onsemi 0:098463de4c5d 652 /* ================================================================================ */
group-onsemi 0:098463de4c5d 653 /* ================ SYSCON ================ */
group-onsemi 0:098463de4c5d 654 /* ================================================================================ */
group-onsemi 0:098463de4c5d 655
group-onsemi 0:098463de4c5d 656
group-onsemi 0:098463de4c5d 657 /**
group-onsemi 0:098463de4c5d 658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
group-onsemi 0:098463de4c5d 659 */
group-onsemi 0:098463de4c5d 660
group-onsemi 0:098463de4c5d 661 typedef struct { /*!< SYSCON Structure */
group-onsemi 0:098463de4c5d 662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
group-onsemi 0:098463de4c5d 663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
group-onsemi 0:098463de4c5d 664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
group-onsemi 0:098463de4c5d 665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
group-onsemi 0:098463de4c5d 666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
group-onsemi 0:098463de4c5d 667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
group-onsemi 0:098463de4c5d 668 __I uint32_t RESERVED0;
group-onsemi 0:098463de4c5d 669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
group-onsemi 0:098463de4c5d 670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
group-onsemi 0:098463de4c5d 671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
group-onsemi 0:098463de4c5d 672 __I uint32_t RESERVED1[2];
group-onsemi 0:098463de4c5d 673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
group-onsemi 0:098463de4c5d 674 __I uint32_t RESERVED2[3];
group-onsemi 0:098463de4c5d 675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
group-onsemi 0:098463de4c5d 676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
group-onsemi 0:098463de4c5d 677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
group-onsemi 0:098463de4c5d 678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
group-onsemi 0:098463de4c5d 679 __I uint32_t RESERVED3[8];
group-onsemi 0:098463de4c5d 680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
group-onsemi 0:098463de4c5d 681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
group-onsemi 0:098463de4c5d 682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
group-onsemi 0:098463de4c5d 683 __I uint32_t RESERVED4;
group-onsemi 0:098463de4c5d 684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
group-onsemi 0:098463de4c5d 685 __I uint32_t RESERVED5[4];
group-onsemi 0:098463de4c5d 686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
group-onsemi 0:098463de4c5d 687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
group-onsemi 0:098463de4c5d 688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
group-onsemi 0:098463de4c5d 689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
group-onsemi 0:098463de4c5d 690 of USART1 to USART4 */
group-onsemi 0:098463de4c5d 691 __I uint32_t RESERVED6[7];
group-onsemi 0:098463de4c5d 692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
group-onsemi 0:098463de4c5d 693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
group-onsemi 0:098463de4c5d 694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
group-onsemi 0:098463de4c5d 695 __I uint32_t RESERVED7[5];
group-onsemi 0:098463de4c5d 696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
group-onsemi 0:098463de4c5d 697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
group-onsemi 0:098463de4c5d 698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
group-onsemi 0:098463de4c5d 699 __I uint32_t RESERVED8;
group-onsemi 0:098463de4c5d 700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
group-onsemi 0:098463de4c5d 701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
group-onsemi 0:098463de4c5d 702 __I uint32_t RESERVED9;
group-onsemi 0:098463de4c5d 703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
group-onsemi 0:098463de4c5d 704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
group-onsemi 0:098463de4c5d 705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
group-onsemi 0:098463de4c5d 706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
group-onsemi 0:098463de4c5d 707 __I uint32_t RESERVED10[10];
group-onsemi 0:098463de4c5d 708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 709 filter */
group-onsemi 0:098463de4c5d 710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 711 filter */
group-onsemi 0:098463de4c5d 712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 713 filter */
group-onsemi 0:098463de4c5d 714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 715 filter */
group-onsemi 0:098463de4c5d 716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 717 filter */
group-onsemi 0:098463de4c5d 718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 719 filter */
group-onsemi 0:098463de4c5d 720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
group-onsemi 0:098463de4c5d 721 filter */
group-onsemi 0:098463de4c5d 722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
group-onsemi 0:098463de4c5d 723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
group-onsemi 0:098463de4c5d 724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
group-onsemi 0:098463de4c5d 725 __I uint32_t RESERVED11[5];
group-onsemi 0:098463de4c5d 726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
group-onsemi 0:098463de4c5d 727 __IO uint32_t NMISRC; /*!< NMI Source Control */
group-onsemi 0:098463de4c5d 728 union {
group-onsemi 0:098463de4c5d 729 __IO uint32_t PINTSEL[8];
group-onsemi 0:098463de4c5d 730 struct {
group-onsemi 0:098463de4c5d 731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
group-onsemi 0:098463de4c5d 739 };
group-onsemi 0:098463de4c5d 740 };
group-onsemi 0:098463de4c5d 741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
group-onsemi 0:098463de4c5d 742 __I uint32_t USBCLKST; /*!< USB clock status */
group-onsemi 0:098463de4c5d 743 __I uint32_t RESERVED12[25];
group-onsemi 0:098463de4c5d 744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
group-onsemi 0:098463de4c5d 745 __I uint32_t RESERVED13[3];
group-onsemi 0:098463de4c5d 746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
group-onsemi 0:098463de4c5d 747 __I uint32_t RESERVED14[6];
group-onsemi 0:098463de4c5d 748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
group-onsemi 0:098463de4c5d 749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
group-onsemi 0:098463de4c5d 750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
group-onsemi 0:098463de4c5d 751 __I uint32_t RESERVED15[110];
group-onsemi 0:098463de4c5d 752 __I uint32_t DEVICE_ID; /*!< Device ID */
group-onsemi 0:098463de4c5d 753 } LPC_SYSCON_Type;
group-onsemi 0:098463de4c5d 754
group-onsemi 0:098463de4c5d 755
group-onsemi 0:098463de4c5d 756 /* ================================================================================ */
group-onsemi 0:098463de4c5d 757 /* ================ USART4 ================ */
group-onsemi 0:098463de4c5d 758 /* ================================================================================ */
group-onsemi 0:098463de4c5d 759
group-onsemi 0:098463de4c5d 760
group-onsemi 0:098463de4c5d 761 /**
group-onsemi 0:098463de4c5d 762 * @brief USART4 (USART4)
group-onsemi 0:098463de4c5d 763 */
group-onsemi 0:098463de4c5d 764
group-onsemi 0:098463de4c5d 765 typedef struct { /*!< USART4 Structure */
group-onsemi 0:098463de4c5d 766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
group-onsemi 0:098463de4c5d 767 that typically are not changed during operation. */
group-onsemi 0:098463de4c5d 768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
group-onsemi 0:098463de4c5d 769 likely to change during operation. */
group-onsemi 0:098463de4c5d 770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
group-onsemi 0:098463de4c5d 771 here. Writing ones clears some bits in the register. Some bits
group-onsemi 0:098463de4c5d 772 can be cleared by writing a 1 to them. */
group-onsemi 0:098463de4c5d 773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
group-onsemi 0:098463de4c5d 774 interrupt enable bit for each potential USART interrupt. A complete
group-onsemi 0:098463de4c5d 775 value may be read from this register. Writing a 1 to any implemented
group-onsemi 0:098463de4c5d 776 bit position causes that bit to be set. */
group-onsemi 0:098463de4c5d 777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
group-onsemi 0:098463de4c5d 778 of bits in the INTENSET register. Writing a 1 to any implemented
group-onsemi 0:098463de4c5d 779 bit position causes the corresponding bit to be cleared. */
group-onsemi 0:098463de4c5d 780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
group-onsemi 0:098463de4c5d 781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
group-onsemi 0:098463de4c5d 782 received with the current USART receive status. Allows DMA or
group-onsemi 0:098463de4c5d 783 software to recover incoming data and status together. */
group-onsemi 0:098463de4c5d 784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
group-onsemi 0:098463de4c5d 785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
group-onsemi 0:098463de4c5d 786 value. */
group-onsemi 0:098463de4c5d 787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
group-onsemi 0:098463de4c5d 788 enabled. */
group-onsemi 0:098463de4c5d 789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
group-onsemi 0:098463de4c5d 790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
group-onsemi 0:098463de4c5d 791 } LPC_USART4_Type;
group-onsemi 0:098463de4c5d 792
group-onsemi 0:098463de4c5d 793
group-onsemi 0:098463de4c5d 794 /* ================================================================================ */
group-onsemi 0:098463de4c5d 795 /* ================ GINT0 ================ */
group-onsemi 0:098463de4c5d 796 /* ================================================================================ */
group-onsemi 0:098463de4c5d 797
group-onsemi 0:098463de4c5d 798
group-onsemi 0:098463de4c5d 799 /**
group-onsemi 0:098463de4c5d 800 * @brief GPIO group interrupt 0 (GINT0)
group-onsemi 0:098463de4c5d 801 */
group-onsemi 0:098463de4c5d 802
group-onsemi 0:098463de4c5d 803 typedef struct { /*!< GINT0 Structure */
group-onsemi 0:098463de4c5d 804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
group-onsemi 0:098463de4c5d 805 __I uint32_t RESERVED0[7];
group-onsemi 0:098463de4c5d 806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
group-onsemi 0:098463de4c5d 807 __I uint32_t RESERVED1[5];
group-onsemi 0:098463de4c5d 808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
group-onsemi 0:098463de4c5d 809 } LPC_GINT0_Type;
group-onsemi 0:098463de4c5d 810
group-onsemi 0:098463de4c5d 811
group-onsemi 0:098463de4c5d 812 /* ================================================================================ */
group-onsemi 0:098463de4c5d 813 /* ================ USB ================ */
group-onsemi 0:098463de4c5d 814 /* ================================================================================ */
group-onsemi 0:098463de4c5d 815
group-onsemi 0:098463de4c5d 816
group-onsemi 0:098463de4c5d 817 /**
group-onsemi 0:098463de4c5d 818 * @brief USB device controller (USB)
group-onsemi 0:098463de4c5d 819 */
group-onsemi 0:098463de4c5d 820
group-onsemi 0:098463de4c5d 821 typedef struct { /*!< USB Structure */
group-onsemi 0:098463de4c5d 822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
group-onsemi 0:098463de4c5d 823 __IO uint32_t INFO; /*!< USB Info register */
group-onsemi 0:098463de4c5d 824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
group-onsemi 0:098463de4c5d 825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
group-onsemi 0:098463de4c5d 826 __IO uint32_t LPM; /*!< Link Power Management register */
group-onsemi 0:098463de4c5d 827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
group-onsemi 0:098463de4c5d 828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
group-onsemi 0:098463de4c5d 829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
group-onsemi 0:098463de4c5d 830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
group-onsemi 0:098463de4c5d 831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
group-onsemi 0:098463de4c5d 832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
group-onsemi 0:098463de4c5d 833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
group-onsemi 0:098463de4c5d 834 __I uint32_t RESERVED0;
group-onsemi 0:098463de4c5d 835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
group-onsemi 0:098463de4c5d 836 } LPC_USB_Type;
group-onsemi 0:098463de4c5d 837
group-onsemi 0:098463de4c5d 838
group-onsemi 0:098463de4c5d 839 /* ================================================================================ */
group-onsemi 0:098463de4c5d 840 /* ================ CRC ================ */
group-onsemi 0:098463de4c5d 841 /* ================================================================================ */
group-onsemi 0:098463de4c5d 842
group-onsemi 0:098463de4c5d 843
group-onsemi 0:098463de4c5d 844 /**
group-onsemi 0:098463de4c5d 845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
group-onsemi 0:098463de4c5d 846 */
group-onsemi 0:098463de4c5d 847
group-onsemi 0:098463de4c5d 848 typedef struct { /*!< CRC Structure */
group-onsemi 0:098463de4c5d 849 __IO uint32_t MODE; /*!< CRC mode register */
group-onsemi 0:098463de4c5d 850 __IO uint32_t SEED; /*!< CRC seed register */
group-onsemi 0:098463de4c5d 851
group-onsemi 0:098463de4c5d 852 union {
group-onsemi 0:098463de4c5d 853 __O uint32_t WR_DATA; /*!< CRC data register */
group-onsemi 0:098463de4c5d 854 __I uint32_t SUM; /*!< CRC checksum register */
group-onsemi 0:098463de4c5d 855 };
group-onsemi 0:098463de4c5d 856 } LPC_CRC_Type;
group-onsemi 0:098463de4c5d 857
group-onsemi 0:098463de4c5d 858
group-onsemi 0:098463de4c5d 859 /* ================================================================================ */
group-onsemi 0:098463de4c5d 860 /* ================ DMA ================ */
group-onsemi 0:098463de4c5d 861 /* ================================================================================ */
group-onsemi 0:098463de4c5d 862
group-onsemi 0:098463de4c5d 863
group-onsemi 0:098463de4c5d 864 /**
group-onsemi 0:098463de4c5d 865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
group-onsemi 0:098463de4c5d 866 */
group-onsemi 0:098463de4c5d 867
group-onsemi 0:098463de4c5d 868 typedef struct { /*!< DMA Structure */
group-onsemi 0:098463de4c5d 869 __IO uint32_t CTRL; /*!< DMA control. */
group-onsemi 0:098463de4c5d 870 __I uint32_t INTSTAT; /*!< Interrupt status. */
group-onsemi 0:098463de4c5d 871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
group-onsemi 0:098463de4c5d 872 __I uint32_t RESERVED0[5];
group-onsemi 0:098463de4c5d 873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
group-onsemi 0:098463de4c5d 874 __I uint32_t RESERVED1;
group-onsemi 0:098463de4c5d 875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
group-onsemi 0:098463de4c5d 876 __I uint32_t RESERVED2;
group-onsemi 0:098463de4c5d 877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
group-onsemi 0:098463de4c5d 878 __I uint32_t RESERVED3;
group-onsemi 0:098463de4c5d 879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
group-onsemi 0:098463de4c5d 880 __I uint32_t RESERVED4;
group-onsemi 0:098463de4c5d 881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
group-onsemi 0:098463de4c5d 882 __I uint32_t RESERVED5;
group-onsemi 0:098463de4c5d 883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
group-onsemi 0:098463de4c5d 884 __I uint32_t RESERVED6;
group-onsemi 0:098463de4c5d 885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
group-onsemi 0:098463de4c5d 886 __I uint32_t RESERVED7;
group-onsemi 0:098463de4c5d 887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
group-onsemi 0:098463de4c5d 888 __I uint32_t RESERVED8;
group-onsemi 0:098463de4c5d 889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
group-onsemi 0:098463de4c5d 890 __I uint32_t RESERVED9;
group-onsemi 0:098463de4c5d 891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
group-onsemi 0:098463de4c5d 892 __I uint32_t RESERVED10;
group-onsemi 0:098463de4c5d 893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
group-onsemi 0:098463de4c5d 894 __I uint32_t RESERVED11;
group-onsemi 0:098463de4c5d 895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
group-onsemi 0:098463de4c5d 896 __I uint32_t RESERVED12[225];
group-onsemi 0:098463de4c5d 897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 900 __I uint32_t RESERVED13;
group-onsemi 0:098463de4c5d 901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 904 __I uint32_t RESERVED14;
group-onsemi 0:098463de4c5d 905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 908 __I uint32_t RESERVED15;
group-onsemi 0:098463de4c5d 909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 912 __I uint32_t RESERVED16;
group-onsemi 0:098463de4c5d 913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 916 __I uint32_t RESERVED17;
group-onsemi 0:098463de4c5d 917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 920 __I uint32_t RESERVED18;
group-onsemi 0:098463de4c5d 921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 924 __I uint32_t RESERVED19;
group-onsemi 0:098463de4c5d 925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 928 __I uint32_t RESERVED20;
group-onsemi 0:098463de4c5d 929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 932 __I uint32_t RESERVED21;
group-onsemi 0:098463de4c5d 933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 936 __I uint32_t RESERVED22;
group-onsemi 0:098463de4c5d 937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 940 __I uint32_t RESERVED23;
group-onsemi 0:098463de4c5d 941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 944 __I uint32_t RESERVED24;
group-onsemi 0:098463de4c5d 945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 948 __I uint32_t RESERVED25;
group-onsemi 0:098463de4c5d 949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 952 __I uint32_t RESERVED26;
group-onsemi 0:098463de4c5d 953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 956 __I uint32_t RESERVED27;
group-onsemi 0:098463de4c5d 957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
group-onsemi 0:098463de4c5d 959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
group-onsemi 0:098463de4c5d 960 } LPC_DMA_Type;
group-onsemi 0:098463de4c5d 961
group-onsemi 0:098463de4c5d 962
group-onsemi 0:098463de4c5d 963 /* ================================================================================ */
group-onsemi 0:098463de4c5d 964 /* ================ SCT0 ================ */
group-onsemi 0:098463de4c5d 965 /* ================================================================================ */
group-onsemi 0:098463de4c5d 966
group-onsemi 0:098463de4c5d 967
group-onsemi 0:098463de4c5d 968 /**
group-onsemi 0:098463de4c5d 969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
group-onsemi 0:098463de4c5d 970 */
group-onsemi 0:098463de4c5d 971
group-onsemi 0:098463de4c5d 972 typedef struct { /*!< SCT0 Structure */
group-onsemi 0:098463de4c5d 973 __IO uint32_t CONFIG; /*!< SCT configuration register */
group-onsemi 0:098463de4c5d 974 __IO uint32_t CTRL; /*!< SCT control register */
group-onsemi 0:098463de4c5d 975 __IO uint32_t LIMIT; /*!< SCT limit register */
group-onsemi 0:098463de4c5d 976 __IO uint32_t HALT; /*!< SCT halt condition register */
group-onsemi 0:098463de4c5d 977 __IO uint32_t STOP; /*!< SCT stop condition register */
group-onsemi 0:098463de4c5d 978 __IO uint32_t START; /*!< SCT start condition register */
group-onsemi 0:098463de4c5d 979 __I uint32_t RESERVED0[10];
group-onsemi 0:098463de4c5d 980 __IO uint32_t COUNT; /*!< SCT counter register */
group-onsemi 0:098463de4c5d 981 __IO uint32_t STATE; /*!< SCT state register */
group-onsemi 0:098463de4c5d 982 __I uint32_t INPUT; /*!< SCT input register */
group-onsemi 0:098463de4c5d 983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
group-onsemi 0:098463de4c5d 984 __IO uint32_t OUTPUT; /*!< SCT output register */
group-onsemi 0:098463de4c5d 985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
group-onsemi 0:098463de4c5d 986 __IO uint32_t RES; /*!< SCT conflict resolution register */
group-onsemi 0:098463de4c5d 987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
group-onsemi 0:098463de4c5d 988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
group-onsemi 0:098463de4c5d 989 __I uint32_t RESERVED1[35];
group-onsemi 0:098463de4c5d 990 __IO uint32_t EVEN; /*!< SCT event enable register */
group-onsemi 0:098463de4c5d 991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
group-onsemi 0:098463de4c5d 992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
group-onsemi 0:098463de4c5d 993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
group-onsemi 0:098463de4c5d 994
group-onsemi 0:098463de4c5d 995 union {
group-onsemi 0:098463de4c5d 996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
group-onsemi 0:098463de4c5d 997 = 1 */
group-onsemi 0:098463de4c5d 998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
group-onsemi 0:098463de4c5d 999 REGMODE4 = 0 */
group-onsemi 0:098463de4c5d 1000 };
group-onsemi 0:098463de4c5d 1001
group-onsemi 0:098463de4c5d 1002 union {
group-onsemi 0:098463de4c5d 1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
group-onsemi 0:098463de4c5d 1004 = 1 */
group-onsemi 0:098463de4c5d 1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
group-onsemi 0:098463de4c5d 1006 REGMODE4 = 0 */
group-onsemi 0:098463de4c5d 1007 };
group-onsemi 0:098463de4c5d 1008
group-onsemi 0:098463de4c5d 1009 union {
group-onsemi 0:098463de4c5d 1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
group-onsemi 0:098463de4c5d 1011 REGMODE4 = 0 */
group-onsemi 0:098463de4c5d 1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
group-onsemi 0:098463de4c5d 1013 = 1 */
group-onsemi 0:098463de4c5d 1014 };
group-onsemi 0:098463de4c5d 1015
group-onsemi 0:098463de4c5d 1016 union {
group-onsemi 0:098463de4c5d 1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
group-onsemi 0:098463de4c5d 1018 = 1 */
group-onsemi 0:098463de4c5d 1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
group-onsemi 0:098463de4c5d 1020 REGMODE4 = 0 */
group-onsemi 0:098463de4c5d 1021 };
group-onsemi 0:098463de4c5d 1022
group-onsemi 0:098463de4c5d 1023 union {
group-onsemi 0:098463de4c5d 1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
group-onsemi 0:098463de4c5d 1025 = 1 */
group-onsemi 0:098463de4c5d 1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
group-onsemi 0:098463de4c5d 1027 REGMODE4 = 0 */
group-onsemi 0:098463de4c5d 1028 };
group-onsemi 0:098463de4c5d 1029 __I uint32_t RESERVED2[59];
group-onsemi 0:098463de4c5d 1030
group-onsemi 0:098463de4c5d 1031 union {
group-onsemi 0:098463de4c5d 1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
group-onsemi 0:098463de4c5d 1033 = 1 */
group-onsemi 0:098463de4c5d 1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
group-onsemi 0:098463de4c5d 1035 = 0 */
group-onsemi 0:098463de4c5d 1036 };
group-onsemi 0:098463de4c5d 1037
group-onsemi 0:098463de4c5d 1038 union {
group-onsemi 0:098463de4c5d 1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
group-onsemi 0:098463de4c5d 1040 = 0 */
group-onsemi 0:098463de4c5d 1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
group-onsemi 0:098463de4c5d 1042 = 1 */
group-onsemi 0:098463de4c5d 1043 };
group-onsemi 0:098463de4c5d 1044
group-onsemi 0:098463de4c5d 1045 union {
group-onsemi 0:098463de4c5d 1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
group-onsemi 0:098463de4c5d 1047 = 0 */
group-onsemi 0:098463de4c5d 1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
group-onsemi 0:098463de4c5d 1049 = 1 */
group-onsemi 0:098463de4c5d 1050 };
group-onsemi 0:098463de4c5d 1051
group-onsemi 0:098463de4c5d 1052 union {
group-onsemi 0:098463de4c5d 1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
group-onsemi 0:098463de4c5d 1054 = 1 */
group-onsemi 0:098463de4c5d 1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
group-onsemi 0:098463de4c5d 1056 = 0 */
group-onsemi 0:098463de4c5d 1057 };
group-onsemi 0:098463de4c5d 1058
group-onsemi 0:098463de4c5d 1059 union {
group-onsemi 0:098463de4c5d 1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
group-onsemi 0:098463de4c5d 1061 = 1 */
group-onsemi 0:098463de4c5d 1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
group-onsemi 0:098463de4c5d 1063 = 0 */
group-onsemi 0:098463de4c5d 1064 };
group-onsemi 0:098463de4c5d 1065 __I uint32_t RESERVED3[59];
group-onsemi 0:098463de4c5d 1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
group-onsemi 0:098463de4c5d 1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
group-onsemi 0:098463de4c5d 1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
group-onsemi 0:098463de4c5d 1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
group-onsemi 0:098463de4c5d 1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
group-onsemi 0:098463de4c5d 1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
group-onsemi 0:098463de4c5d 1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
group-onsemi 0:098463de4c5d 1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
group-onsemi 0:098463de4c5d 1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
group-onsemi 0:098463de4c5d 1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
group-onsemi 0:098463de4c5d 1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
group-onsemi 0:098463de4c5d 1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
group-onsemi 0:098463de4c5d 1078 __I uint32_t RESERVED4[116];
group-onsemi 0:098463de4c5d 1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
group-onsemi 0:098463de4c5d 1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
group-onsemi 0:098463de4c5d 1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
group-onsemi 0:098463de4c5d 1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
group-onsemi 0:098463de4c5d 1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
group-onsemi 0:098463de4c5d 1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
group-onsemi 0:098463de4c5d 1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
group-onsemi 0:098463de4c5d 1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
group-onsemi 0:098463de4c5d 1087 } LPC_SCT0_Type;
group-onsemi 0:098463de4c5d 1088
group-onsemi 0:098463de4c5d 1089
group-onsemi 0:098463de4c5d 1090 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1091 /* ================ GPIO_PORT ================ */
group-onsemi 0:098463de4c5d 1092 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1093
group-onsemi 0:098463de4c5d 1094
group-onsemi 0:098463de4c5d 1095 /**
group-onsemi 0:098463de4c5d 1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
group-onsemi 0:098463de4c5d 1097 */
group-onsemi 0:098463de4c5d 1098
group-onsemi 0:098463de4c5d 1099 typedef struct { /*!< GPIO_PORT Structure */
group-onsemi 0:098463de4c5d 1100 __IO uint8_t B[88]; /*!< Byte pin registers */
group-onsemi 0:098463de4c5d 1101 __I uint32_t RESERVED0[42];
group-onsemi 0:098463de4c5d 1102 __IO uint32_t W[88]; /*!< Word pin registers */
group-onsemi 0:098463de4c5d 1103 __I uint32_t RESERVED1[1896];
group-onsemi 0:098463de4c5d 1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
group-onsemi 0:098463de4c5d 1105 __I uint32_t RESERVED2[29];
group-onsemi 0:098463de4c5d 1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
group-onsemi 0:098463de4c5d 1107 __I uint32_t RESERVED3[29];
group-onsemi 0:098463de4c5d 1108 __IO uint32_t PIN[3]; /*!< Port pin register */
group-onsemi 0:098463de4c5d 1109 __I uint32_t RESERVED4[29];
group-onsemi 0:098463de4c5d 1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
group-onsemi 0:098463de4c5d 1111 __I uint32_t RESERVED5[29];
group-onsemi 0:098463de4c5d 1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
group-onsemi 0:098463de4c5d 1113 __I uint32_t RESERVED6[29];
group-onsemi 0:098463de4c5d 1114 __O uint32_t CLR[3]; /*!< Clear port */
group-onsemi 0:098463de4c5d 1115 __I uint32_t RESERVED7[29];
group-onsemi 0:098463de4c5d 1116 __O uint32_t NOT[3]; /*!< Toggle port */
group-onsemi 0:098463de4c5d 1117 } LPC_GPIO_PORT_Type;
group-onsemi 0:098463de4c5d 1118
group-onsemi 0:098463de4c5d 1119
group-onsemi 0:098463de4c5d 1120 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1121 /* ================ PINT ================ */
group-onsemi 0:098463de4c5d 1122 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1123
group-onsemi 0:098463de4c5d 1124
group-onsemi 0:098463de4c5d 1125 /**
group-onsemi 0:098463de4c5d 1126 * @brief Pin interruptand pattern match (PINT) (PINT)
group-onsemi 0:098463de4c5d 1127 */
group-onsemi 0:098463de4c5d 1128
group-onsemi 0:098463de4c5d 1129 typedef struct { /*!< PINT Structure */
group-onsemi 0:098463de4c5d 1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
group-onsemi 0:098463de4c5d 1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
group-onsemi 0:098463de4c5d 1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
group-onsemi 0:098463de4c5d 1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
group-onsemi 0:098463de4c5d 1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
group-onsemi 0:098463de4c5d 1135 register */
group-onsemi 0:098463de4c5d 1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
group-onsemi 0:098463de4c5d 1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
group-onsemi 0:098463de4c5d 1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
group-onsemi 0:098463de4c5d 1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
group-onsemi 0:098463de4c5d 1140 __IO uint32_t IST; /*!< Pin interrupt status register */
group-onsemi 0:098463de4c5d 1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
group-onsemi 0:098463de4c5d 1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
group-onsemi 0:098463de4c5d 1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
group-onsemi 0:098463de4c5d 1144 } LPC_PINT_Type;
group-onsemi 0:098463de4c5d 1145
group-onsemi 0:098463de4c5d 1146
group-onsemi 0:098463de4c5d 1147 /* -------------------- End of section using anonymous unions ------------------- */
group-onsemi 0:098463de4c5d 1148 #if defined(__CC_ARM)
group-onsemi 0:098463de4c5d 1149 #pragma pop
group-onsemi 0:098463de4c5d 1150 #elif defined(__ICCARM__)
group-onsemi 0:098463de4c5d 1151 /* leave anonymous unions enabled */
group-onsemi 0:098463de4c5d 1152 #elif defined(__GNUC__)
group-onsemi 0:098463de4c5d 1153 /* anonymous unions are enabled by default */
group-onsemi 0:098463de4c5d 1154 #elif defined(__TMS470__)
group-onsemi 0:098463de4c5d 1155 /* anonymous unions are enabled by default */
group-onsemi 0:098463de4c5d 1156 #elif defined(__TASKING__)
group-onsemi 0:098463de4c5d 1157 #pragma warning restore
group-onsemi 0:098463de4c5d 1158 #else
group-onsemi 0:098463de4c5d 1159 #warning Not supported compiler type
group-onsemi 0:098463de4c5d 1160 #endif
group-onsemi 0:098463de4c5d 1161
group-onsemi 0:098463de4c5d 1162
group-onsemi 0:098463de4c5d 1163
group-onsemi 0:098463de4c5d 1164
group-onsemi 0:098463de4c5d 1165 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1166 /* ================ Peripheral memory map ================ */
group-onsemi 0:098463de4c5d 1167 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1168
group-onsemi 0:098463de4c5d 1169 #define LPC_I2C0_BASE 0x40000000UL
group-onsemi 0:098463de4c5d 1170 #define LPC_WWDT_BASE 0x40004000UL
group-onsemi 0:098463de4c5d 1171 #define LPC_USART0_BASE 0x40008000UL
group-onsemi 0:098463de4c5d 1172 #define LPC_CT16B0_BASE 0x4000C000UL
group-onsemi 0:098463de4c5d 1173 #define LPC_CT16B1_BASE 0x40010000UL
group-onsemi 0:098463de4c5d 1174 #define LPC_CT32B0_BASE 0x40014000UL
group-onsemi 0:098463de4c5d 1175 #define LPC_CT32B1_BASE 0x40018000UL
group-onsemi 0:098463de4c5d 1176 #define LPC_ADC_BASE 0x4001C000UL
group-onsemi 0:098463de4c5d 1177 #define LPC_I2C1_BASE 0x40020000UL
group-onsemi 0:098463de4c5d 1178 #define LPC_RTC_BASE 0x40024000UL
group-onsemi 0:098463de4c5d 1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
group-onsemi 0:098463de4c5d 1180 #define LPC_PMU_BASE 0x40038000UL
group-onsemi 0:098463de4c5d 1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
group-onsemi 0:098463de4c5d 1182 #define LPC_SSP0_BASE 0x40040000UL
group-onsemi 0:098463de4c5d 1183 #define LPC_IOCON_BASE 0x40044000UL
group-onsemi 0:098463de4c5d 1184 #define LPC_SYSCON_BASE 0x40048000UL
group-onsemi 0:098463de4c5d 1185 #define LPC_USART4_BASE 0x4004C000UL
group-onsemi 0:098463de4c5d 1186 #define LPC_SSP1_BASE 0x40058000UL
group-onsemi 0:098463de4c5d 1187 #define LPC_GINT0_BASE 0x4005C000UL
group-onsemi 0:098463de4c5d 1188 #define LPC_GINT1_BASE 0x40060000UL
group-onsemi 0:098463de4c5d 1189 #define LPC_USART1_BASE 0x4006C000UL
group-onsemi 0:098463de4c5d 1190 #define LPC_USART2_BASE 0x40070000UL
group-onsemi 0:098463de4c5d 1191 #define LPC_USART3_BASE 0x40074000UL
group-onsemi 0:098463de4c5d 1192 #define LPC_USB_BASE 0x40080000UL
group-onsemi 0:098463de4c5d 1193 #define LPC_CRC_BASE 0x50000000UL
group-onsemi 0:098463de4c5d 1194 #define LPC_DMA_BASE 0x50004000UL
group-onsemi 0:098463de4c5d 1195 #define LPC_SCT0_BASE 0x5000C000UL
group-onsemi 0:098463de4c5d 1196 #define LPC_SCT1_BASE 0x5000E000UL
group-onsemi 0:098463de4c5d 1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
group-onsemi 0:098463de4c5d 1198 #define LPC_PINT_BASE 0xA0004000UL
group-onsemi 0:098463de4c5d 1199
group-onsemi 0:098463de4c5d 1200
group-onsemi 0:098463de4c5d 1201 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1202 /* ================ Peripheral declaration ================ */
group-onsemi 0:098463de4c5d 1203 /* ================================================================================ */
group-onsemi 0:098463de4c5d 1204
group-onsemi 0:098463de4c5d 1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
group-onsemi 0:098463de4c5d 1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
group-onsemi 0:098463de4c5d 1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
group-onsemi 0:098463de4c5d 1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
group-onsemi 0:098463de4c5d 1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
group-onsemi 0:098463de4c5d 1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
group-onsemi 0:098463de4c5d 1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
group-onsemi 0:098463de4c5d 1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
group-onsemi 0:098463de4c5d 1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
group-onsemi 0:098463de4c5d 1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
group-onsemi 0:098463de4c5d 1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
group-onsemi 0:098463de4c5d 1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
group-onsemi 0:098463de4c5d 1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
group-onsemi 0:098463de4c5d 1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
group-onsemi 0:098463de4c5d 1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
group-onsemi 0:098463de4c5d 1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
group-onsemi 0:098463de4c5d 1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
group-onsemi 0:098463de4c5d 1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
group-onsemi 0:098463de4c5d 1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
group-onsemi 0:098463de4c5d 1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
group-onsemi 0:098463de4c5d 1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
group-onsemi 0:098463de4c5d 1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
group-onsemi 0:098463de4c5d 1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
group-onsemi 0:098463de4c5d 1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
group-onsemi 0:098463de4c5d 1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
group-onsemi 0:098463de4c5d 1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
group-onsemi 0:098463de4c5d 1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
group-onsemi 0:098463de4c5d 1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
group-onsemi 0:098463de4c5d 1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
group-onsemi 0:098463de4c5d 1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
group-onsemi 0:098463de4c5d 1235
group-onsemi 0:098463de4c5d 1236
group-onsemi 0:098463de4c5d 1237 /** @} */ /* End of group Device_Peripheral_Registers */
group-onsemi 0:098463de4c5d 1238 /** @} */ /* End of group LPC11U6x */
group-onsemi 0:098463de4c5d 1239 /** @} */ /* End of group (null) */
group-onsemi 0:098463de4c5d 1240
group-onsemi 0:098463de4c5d 1241 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 1242 }
group-onsemi 0:098463de4c5d 1243 #endif
group-onsemi 0:098463de4c5d 1244
group-onsemi 0:098463de4c5d 1245
group-onsemi 0:098463de4c5d 1246 #endif /* LPC11U6x_H */
group-onsemi 0:098463de4c5d 1247