ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2015-2016 Nuvoton
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #include "us_ticker_api.h"
group-onsemi 0:098463de4c5d 18 #include "sleep_api.h"
group-onsemi 0:098463de4c5d 19 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 20 #include "nu_modutil.h"
group-onsemi 0:098463de4c5d 21 #include "nu_miscutil.h"
group-onsemi 0:098463de4c5d 22 #include "critical.h"
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 // us_ticker tick = us = timestamp
group-onsemi 0:098463de4c5d 25 #define US_PER_TICK 1
group-onsemi 0:098463de4c5d 26 #define US_PER_SEC (1000 * 1000)
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 #define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
group-onsemi 0:098463de4c5d 29 #define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
group-onsemi 0:098463de4c5d 30 #define TMR1LORES_CLK_PER_SEC (__LIRC)
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 #define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
group-onsemi 0:098463de4c5d 33 #define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
group-onsemi 0:098463de4c5d 34 #define US_PER_TMR1LORES_CLK (US_PER_SEC / TMR1LORES_CLK_PER_SEC)
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 #define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
group-onsemi 0:098463de4c5d 37 #define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 // Determine to use lo-res/hi-res timer according to CD period
group-onsemi 0:098463de4c5d 41 #define US_TMR_SEP_CD 1000
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 static void tmr0_vec(void);
group-onsemi 0:098463de4c5d 44 static void tmr1_vec(void);
group-onsemi 0:098463de4c5d 45 static void us_ticker_arm_cd(void);
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 static int us_ticker_inited = 0;
group-onsemi 0:098463de4c5d 48 static volatile uint32_t counter_major = 0;
group-onsemi 0:098463de4c5d 49 static volatile uint32_t pd_comp_us = 0; // Power-down compenstaion for normal counter
group-onsemi 0:098463de4c5d 50 static volatile uint32_t cd_major_minor_us = 0;
group-onsemi 0:098463de4c5d 51 static volatile uint32_t cd_minor_us = 0;
group-onsemi 0:098463de4c5d 52 static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
group-onsemi 0:098463de4c5d 53
group-onsemi 0:098463de4c5d 54 // NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
group-onsemi 0:098463de4c5d 55 // NOTE: Choose clock source of timer:
group-onsemi 0:098463de4c5d 56 // 1. HIRC: Be the most accurate but might cause unknown HardFault.
group-onsemi 0:098463de4c5d 57 // 2. HXT: Less accurate and cannot pass mbed-drivers test.
group-onsemi 0:098463de4c5d 58 // 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
group-onsemi 0:098463de4c5d 59 // NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
group-onsemi 0:098463de4c5d 60 static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
group-onsemi 0:098463de4c5d 61 static const struct nu_modinit_s timer1lores_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
group-onsemi 0:098463de4c5d 62 static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 #define TMR_CMP_MIN 2
group-onsemi 0:098463de4c5d 65 #define TMR_CMP_MAX 0xFFFFFFu
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 void us_ticker_init(void)
group-onsemi 0:098463de4c5d 68 {
group-onsemi 0:098463de4c5d 69 if (us_ticker_inited) {
group-onsemi 0:098463de4c5d 70 return;
group-onsemi 0:098463de4c5d 71 }
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 counter_major = 0;
group-onsemi 0:098463de4c5d 74 pd_comp_us = 0;
group-onsemi 0:098463de4c5d 75 cd_major_minor_us = 0;
group-onsemi 0:098463de4c5d 76 cd_minor_us = 0;
group-onsemi 0:098463de4c5d 77 cd_hires_tmr_armed = 0;
group-onsemi 0:098463de4c5d 78 us_ticker_inited = 1;
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 // Reset IP
group-onsemi 0:098463de4c5d 81 SYS_ResetModule(timer0hires_modinit.rsetidx);
group-onsemi 0:098463de4c5d 82 SYS_ResetModule(timer1lores_modinit.rsetidx);
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 // Select IP clock source
group-onsemi 0:098463de4c5d 85 CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
group-onsemi 0:098463de4c5d 86 CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
group-onsemi 0:098463de4c5d 87 // Enable IP clock
group-onsemi 0:098463de4c5d 88 CLK_EnableModuleClock(timer0hires_modinit.clkidx);
group-onsemi 0:098463de4c5d 89 CLK_EnableModuleClock(timer1lores_modinit.clkidx);
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 // Timer for normal counter
group-onsemi 0:098463de4c5d 92 uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
group-onsemi 0:098463de4c5d 93 uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
group-onsemi 0:098463de4c5d 94 MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
group-onsemi 0:098463de4c5d 95 MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
group-onsemi 0:098463de4c5d 96 uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
group-onsemi 0:098463de4c5d 97 MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
group-onsemi 0:098463de4c5d 98 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
group-onsemi 0:098463de4c5d 99 ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
group-onsemi 0:098463de4c5d 100 ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
group-onsemi 0:098463de4c5d 103 NVIC_SetVector(timer1lores_modinit.irq_n, (uint32_t) timer1lores_modinit.var);
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 NVIC_EnableIRQ(timer0hires_modinit.irq_n);
group-onsemi 0:098463de4c5d 106 NVIC_EnableIRQ(timer1lores_modinit.irq_n);
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
group-onsemi 0:098463de4c5d 109 TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
group-onsemi 0:098463de4c5d 110 }
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 uint32_t us_ticker_read()
group-onsemi 0:098463de4c5d 113 {
group-onsemi 0:098463de4c5d 114 if (! us_ticker_inited) {
group-onsemi 0:098463de4c5d 115 us_ticker_init();
group-onsemi 0:098463de4c5d 116 }
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 do {
group-onsemi 0:098463de4c5d 121 uint32_t major_minor_us;
group-onsemi 0:098463de4c5d 122 uint32_t minor_us;
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
group-onsemi 0:098463de4c5d 125 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
group-onsemi 0:098463de4c5d 126 do {
group-onsemi 0:098463de4c5d 127 core_util_critical_section_enter();
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 // NOTE: Order of reading minor_us/carry here is significant.
group-onsemi 0:098463de4c5d 130 minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
group-onsemi 0:098463de4c5d 131 uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
group-onsemi 0:098463de4c5d 132 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
group-onsemi 0:098463de4c5d 133 if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
group-onsemi 0:098463de4c5d 134 major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
group-onsemi 0:098463de4c5d 135 }
group-onsemi 0:098463de4c5d 136 else {
group-onsemi 0:098463de4c5d 137 major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
group-onsemi 0:098463de4c5d 138 }
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 core_util_critical_section_exit();
group-onsemi 0:098463de4c5d 141 }
group-onsemi 0:098463de4c5d 142 while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 // Add power-down compensation
group-onsemi 0:098463de4c5d 145 return (major_minor_us + pd_comp_us) / US_PER_TICK;
group-onsemi 0:098463de4c5d 146 }
group-onsemi 0:098463de4c5d 147 while (0);
group-onsemi 0:098463de4c5d 148 }
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 void us_ticker_disable_interrupt(void)
group-onsemi 0:098463de4c5d 151 {
group-onsemi 0:098463de4c5d 152 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
group-onsemi 0:098463de4c5d 153 }
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 void us_ticker_clear_interrupt(void)
group-onsemi 0:098463de4c5d 156 {
group-onsemi 0:098463de4c5d 157 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
group-onsemi 0:098463de4c5d 158 }
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 void us_ticker_set_interrupt(timestamp_t timestamp)
group-onsemi 0:098463de4c5d 161 {
group-onsemi 0:098463de4c5d 162 TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
group-onsemi 0:098463de4c5d 163 cd_hires_tmr_armed = 0;
group-onsemi 0:098463de4c5d 164
group-onsemi 0:098463de4c5d 165 int delta = (int) (timestamp - us_ticker_read());
group-onsemi 0:098463de4c5d 166 if (delta > 0) {
group-onsemi 0:098463de4c5d 167 cd_major_minor_us = delta * US_PER_TICK;
group-onsemi 0:098463de4c5d 168 us_ticker_arm_cd();
group-onsemi 0:098463de4c5d 169 }
group-onsemi 0:098463de4c5d 170 else {
group-onsemi 0:098463de4c5d 171 cd_major_minor_us = cd_minor_us = 0;
group-onsemi 0:098463de4c5d 172 /**
group-onsemi 0:098463de4c5d 173 * This event was in the past. Set the interrupt as pending, but don't process it here.
group-onsemi 0:098463de4c5d 174 * This prevents a recurive loop under heavy load which can lead to a stack overflow.
group-onsemi 0:098463de4c5d 175 */
group-onsemi 0:098463de4c5d 176 NVIC_SetPendingIRQ(timer1lores_modinit.irq_n);
group-onsemi 0:098463de4c5d 177 }
group-onsemi 0:098463de4c5d 178 }
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 void us_ticker_prepare_sleep(struct sleep_s *obj)
group-onsemi 0:098463de4c5d 181 {
group-onsemi 0:098463de4c5d 182 // Reject power-down if hi-res timer (HIRC/HXT) is now armed for CD counter.
group-onsemi 0:098463de4c5d 183 if (obj->powerdown) {
group-onsemi 0:098463de4c5d 184 obj->powerdown = ! cd_hires_tmr_armed;
group-onsemi 0:098463de4c5d 185 }
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 core_util_critical_section_enter();
group-onsemi 0:098463de4c5d 188
group-onsemi 0:098463de4c5d 189 if (obj->powerdown) {
group-onsemi 0:098463de4c5d 190 // NOTE: On entering power-down mode, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
group-onsemi 0:098463de4c5d 191 // To not be inconsistent due to above, always disable clock source of normal counter, and then re-enable it and make compensation on wakeup from power-down.
group-onsemi 0:098463de4c5d 192 CLK_DisableModuleClock(timer0hires_modinit.clkidx);
group-onsemi 0:098463de4c5d 193 }
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 core_util_critical_section_exit();
group-onsemi 0:098463de4c5d 196 }
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 void us_ticker_wakeup_from_sleep(struct sleep_s *obj)
group-onsemi 0:098463de4c5d 199 {
group-onsemi 0:098463de4c5d 200 core_util_critical_section_enter();
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 if (obj->powerdown) {
group-onsemi 0:098463de4c5d 203 // Calculate power-down compensation
group-onsemi 0:098463de4c5d 204 pd_comp_us += obj->period_us;
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 CLK_EnableModuleClock(timer0hires_modinit.clkidx);
group-onsemi 0:098463de4c5d 207 }
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 core_util_critical_section_exit();
group-onsemi 0:098463de4c5d 210 }
group-onsemi 0:098463de4c5d 211
group-onsemi 0:098463de4c5d 212 static void tmr0_vec(void)
group-onsemi 0:098463de4c5d 213 {
group-onsemi 0:098463de4c5d 214 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
group-onsemi 0:098463de4c5d 215 counter_major ++;
group-onsemi 0:098463de4c5d 216 }
group-onsemi 0:098463de4c5d 217
group-onsemi 0:098463de4c5d 218 static void tmr1_vec(void)
group-onsemi 0:098463de4c5d 219 {
group-onsemi 0:098463de4c5d 220 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
group-onsemi 0:098463de4c5d 221 cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
group-onsemi 0:098463de4c5d 222 cd_hires_tmr_armed = 0;
group-onsemi 0:098463de4c5d 223 if (cd_major_minor_us == 0) {
group-onsemi 0:098463de4c5d 224 // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
group-onsemi 0:098463de4c5d 225 us_ticker_irq_handler();
group-onsemi 0:098463de4c5d 226 }
group-onsemi 0:098463de4c5d 227 else {
group-onsemi 0:098463de4c5d 228 us_ticker_arm_cd();
group-onsemi 0:098463de4c5d 229 }
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 static void us_ticker_arm_cd(void)
group-onsemi 0:098463de4c5d 233 {
group-onsemi 0:098463de4c5d 234 TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
group-onsemi 0:098463de4c5d 235 uint32_t tmr1_clk_per_sec;
group-onsemi 0:098463de4c5d 236 uint32_t us_per_tmr1_clk;
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 /**
group-onsemi 0:098463de4c5d 239 * Reserve US_TMR_SEP_CD-plus alarm period for hi-res timer
group-onsemi 0:098463de4c5d 240 * 1. period >= US_TMR_SEP_CD * 2. Divide into two rounds:
group-onsemi 0:098463de4c5d 241 * US_TMR_SEP_CD * n (lo-res timer)
group-onsemi 0:098463de4c5d 242 * US_TMR_SEP_CD + period % US_TMR_SEP_CD (hi-res timer)
group-onsemi 0:098463de4c5d 243 * 2. period < US_TMR_SEP_CD * 2. Just one round:
group-onsemi 0:098463de4c5d 244 * period (hi-res timer)
group-onsemi 0:098463de4c5d 245 */
group-onsemi 0:098463de4c5d 246 if (cd_major_minor_us >= US_TMR_SEP_CD * 2) {
group-onsemi 0:098463de4c5d 247 cd_minor_us = cd_major_minor_us - cd_major_minor_us % US_TMR_SEP_CD - US_TMR_SEP_CD;
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
group-onsemi 0:098463de4c5d 250 tmr1_clk_per_sec = TMR1LORES_CLK_PER_SEC;
group-onsemi 0:098463de4c5d 251 us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
group-onsemi 0:098463de4c5d 252
group-onsemi 0:098463de4c5d 253 cd_hires_tmr_armed = 0;
group-onsemi 0:098463de4c5d 254 }
group-onsemi 0:098463de4c5d 255 else {
group-onsemi 0:098463de4c5d 256 cd_minor_us = cd_major_minor_us;
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
group-onsemi 0:098463de4c5d 259 tmr1_clk_per_sec = TMR1HIRES_CLK_PER_SEC;
group-onsemi 0:098463de4c5d 260 us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
group-onsemi 0:098463de4c5d 261
group-onsemi 0:098463de4c5d 262 cd_hires_tmr_armed = 1;
group-onsemi 0:098463de4c5d 263 }
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
group-onsemi 0:098463de4c5d 266 timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
group-onsemi 0:098463de4c5d 267 // One-shot mode, Clock = 1 MHz
group-onsemi 0:098463de4c5d 268 uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
group-onsemi 0:098463de4c5d 269 uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_per_sec - 1;
group-onsemi 0:098463de4c5d 270 MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
group-onsemi 0:098463de4c5d 271 MBED_ASSERT((clk_timer1 % tmr1_clk_per_sec) == 0);
group-onsemi 0:098463de4c5d 272 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
group-onsemi 0:098463de4c5d 273 timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
group-onsemi 0:098463de4c5d 274 timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 uint32_t cmp_timer1 = cd_minor_us / us_per_tmr1_clk;
group-onsemi 0:098463de4c5d 277 cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
group-onsemi 0:098463de4c5d 278 timer1_base->CMP = cmp_timer1;
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 TIMER_EnableInt(timer1_base);
group-onsemi 0:098463de4c5d 281 TIMER_Start(timer1_base);
group-onsemi 0:098463de4c5d 282 }