ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32610/sleep.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "sleep_api.h"
group-onsemi 0:098463de4c5d 35 #include "cmsis.h"
group-onsemi 0:098463de4c5d 36 #include "pwrman_regs.h"
group-onsemi 0:098463de4c5d 37 #include "pwrseq_regs.h"
group-onsemi 0:098463de4c5d 38 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 39 #include "rtc_regs.h"
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 // Normal wait mode
group-onsemi 0:098463de4c5d 44 void sleep(void)
group-onsemi 0:098463de4c5d 45 {
group-onsemi 0:098463de4c5d 46 // Normal sleep mode for ARM core
group-onsemi 0:098463de4c5d 47 SCB->SCR = 0;
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 __DSB();
group-onsemi 0:098463de4c5d 50 __WFI();
group-onsemi 0:098463de4c5d 51 }
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 // Work-around for issue of clearing power sequencer I/O flag
group-onsemi 0:098463de4c5d 54 static void clearAllGPIOWUD(void)
group-onsemi 0:098463de4c5d 55 {
group-onsemi 0:098463de4c5d 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
group-onsemi 0:098463de4c5d 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 // I/O must be a wakeup detect to clear
group-onsemi 0:098463de4c5d 60 MXC_IOMAN->wud_req0 = 0xffffffff;
group-onsemi 0:098463de4c5d 61 MXC_IOMAN->wud_req1 = 0xffffffff;
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 // Clear all WUDs
group-onsemi 0:098463de4c5d 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
group-onsemi 0:098463de4c5d 65 MXC_PWRMAN->wud_pulse0 = 1;
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 // Restore WUD requests
group-onsemi 0:098463de4c5d 68 MXC_IOMAN->wud_req0 = wud_req0;
group-onsemi 0:098463de4c5d 69 MXC_IOMAN->wud_req1 = wud_req1;
group-onsemi 0:098463de4c5d 70 }
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 // Low-power stop mode
group-onsemi 0:098463de4c5d 73 void deepsleep(void)
group-onsemi 0:098463de4c5d 74 {
group-onsemi 0:098463de4c5d 75 __disable_irq();
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
group-onsemi 0:098463de4c5d 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 // Prepare for LP1
group-onsemi 0:098463de4c5d 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
group-onsemi 0:098463de4c5d 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
group-onsemi 0:098463de4c5d 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
group-onsemi 0:098463de4c5d 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
group-onsemi 0:098463de4c5d 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
group-onsemi 0:098463de4c5d 86 } else {
group-onsemi 0:098463de4c5d 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
group-onsemi 0:098463de4c5d 88 }
group-onsemi 0:098463de4c5d 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
group-onsemi 0:098463de4c5d 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
group-onsemi 0:098463de4c5d 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
group-onsemi 0:098463de4c5d 92 MXC_PWRSEQ->reg0 = reg0;
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 // Deep sleep for ARM core
group-onsemi 0:098463de4c5d 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 // clear latches for wakeup detect
group-onsemi 0:098463de4c5d 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
group-onsemi 0:098463de4c5d 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
group-onsemi 0:098463de4c5d 102 // attempt work-around for I/O flag clearing issue
group-onsemi 0:098463de4c5d 103 clearAllGPIOWUD();
group-onsemi 0:098463de4c5d 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
group-onsemi 0:098463de4c5d 105 }
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 // Wait for pending RTC transaction
group-onsemi 0:098463de4c5d 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 // Ensure that the event register is clear
group-onsemi 0:098463de4c5d 111 __SEV(); // set event
group-onsemi 0:098463de4c5d 112 __WFE(); // clear event
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 // Enter LP1
group-onsemi 0:098463de4c5d 115 __WFE();
group-onsemi 0:098463de4c5d 116 // Woke up from LP1
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 // The RTC timer does not update until the next tick
group-onsemi 0:098463de4c5d 119 uint32_t temp = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 120 while (MXC_RTCTMR->timer == temp);
group-onsemi 0:098463de4c5d 121
group-onsemi 0:098463de4c5d 122 __enable_irq();
group-onsemi 0:098463de4c5d 123 }