ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32610/device/max32610.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MAX32610_H_
group-onsemi 0:098463de4c5d 35 #define _MAX32610_H_
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #include <stdint.h>
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39 typedef enum IRQn_Type {
group-onsemi 0:098463de4c5d 40 NonMaskableInt_IRQn = -14,
group-onsemi 0:098463de4c5d 41 HardFault_IRQn = -13,
group-onsemi 0:098463de4c5d 42 MemoryManagement_IRQn = -12,
group-onsemi 0:098463de4c5d 43 BusFault_IRQn = -11,
group-onsemi 0:098463de4c5d 44 UsageFault_IRQn = -10,
group-onsemi 0:098463de4c5d 45 SVCall_IRQn = -5,
group-onsemi 0:098463de4c5d 46 DebugMonitor_IRQn = -4,
group-onsemi 0:098463de4c5d 47 PendSV_IRQn = -2,
group-onsemi 0:098463de4c5d 48 SysTick_IRQn = -1,
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 /* Externals interrupts */
group-onsemi 0:098463de4c5d 51 UART0_IRQn = 0, /* 16:01 UART0 */
group-onsemi 0:098463de4c5d 52 UART1_IRQn, /* 17: 2 UART1 */
group-onsemi 0:098463de4c5d 53 I2CM0_IRQn, /* 18: 3 I2C Master 0 */
group-onsemi 0:098463de4c5d 54 I2CS_IRQn, /* 19: 4 I2C Slave */
group-onsemi 0:098463de4c5d 55 USB_IRQn, /* 20: 5 USB */
group-onsemi 0:098463de4c5d 56 PMU_IRQn, /* 21: 6 DMA */
group-onsemi 0:098463de4c5d 57 AFE_IRQn, /* 22: 7 AFE */
group-onsemi 0:098463de4c5d 58 MAA_IRQn, /* 23: 8 MAA */
group-onsemi 0:098463de4c5d 59 AES_IRQn, /* 24: 9 AES */
group-onsemi 0:098463de4c5d 60 SPI0_IRQn, /* 25:10 SPI0 */
group-onsemi 0:098463de4c5d 61 SPI1_IRQn, /* 26:11 SPI1 */
group-onsemi 0:098463de4c5d 62 SPI2_IRQn, /* 27:12 SPI2 */
group-onsemi 0:098463de4c5d 63 TMR0_IRQn, /* 28:13 Timer32-0 */
group-onsemi 0:098463de4c5d 64 TMR1_IRQn, /* 29:14 Timer32-1 */
group-onsemi 0:098463de4c5d 65 TMR2_IRQn, /* 30:15 Timer32-1 */
group-onsemi 0:098463de4c5d 66 TMR3_IRQn, /* 31:16 Timer32-2 */
group-onsemi 0:098463de4c5d 67 RSVD0_IRQn, /* 32:17 RSVD */
group-onsemi 0:098463de4c5d 68 RSVD1_IRQn, /* 33:18 RSVD */
group-onsemi 0:098463de4c5d 69 DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
group-onsemi 0:098463de4c5d 70 DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
group-onsemi 0:098463de4c5d 71 DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
group-onsemi 0:098463de4c5d 72 DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
group-onsemi 0:098463de4c5d 73 ADC_IRQn, /* 38:23 ADC */
group-onsemi 0:098463de4c5d 74 FLC_IRQn, /* 39:24 Flash Controller */
group-onsemi 0:098463de4c5d 75 PWRMAN_IRQn, /* 40:25 PWRMAN */
group-onsemi 0:098463de4c5d 76 CLKMAN_IRQn, /* 41:26 CLKMAN */
group-onsemi 0:098463de4c5d 77 RTC0_IRQn, /* 42:27 RTC INT0 */
group-onsemi 0:098463de4c5d 78 RTC1_IRQn, /* 43:28 RTC INT1 */
group-onsemi 0:098463de4c5d 79 RTC2_IRQn, /* 44:29 RTC INT2 */
group-onsemi 0:098463de4c5d 80 RTC3_IRQn, /* 45:30 RTC INT3 */
group-onsemi 0:098463de4c5d 81 WDT0_IRQn, /* 46:31 WATCHDOG0 */
group-onsemi 0:098463de4c5d 82 WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
group-onsemi 0:098463de4c5d 83 WDT1_IRQn, /* 48:33 WATCHDOG1 */
group-onsemi 0:098463de4c5d 84 WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
group-onsemi 0:098463de4c5d 85 GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
group-onsemi 0:098463de4c5d 86 GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
group-onsemi 0:098463de4c5d 87 GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
group-onsemi 0:098463de4c5d 88 GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
group-onsemi 0:098463de4c5d 89 GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
group-onsemi 0:098463de4c5d 90 GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
group-onsemi 0:098463de4c5d 91 GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
group-onsemi 0:098463de4c5d 92 GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
group-onsemi 0:098463de4c5d 93 TMR16_0_IRQn, /* 58:43 Timer16-s0 */
group-onsemi 0:098463de4c5d 94 TMR16_1_IRQn, /* 59:44 Timer16-s1 */
group-onsemi 0:098463de4c5d 95 TMR16_2_IRQn, /* 60:45 Timer16-s2 */
group-onsemi 0:098463de4c5d 96 TMR16_3_IRQn, /* 61:46 Timer16-s3 */
group-onsemi 0:098463de4c5d 97 I2CM1_IRQn, /* 62:47 I2C Master 1 */
group-onsemi 0:098463de4c5d 98 MXC_IRQ_EXT_COUNT,
group-onsemi 0:098463de4c5d 99 } IRQn_Type;
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 /* ================================================================================ */
group-onsemi 0:098463de4c5d 104 /* ================ Processor and Core Peripheral Section ================ */
group-onsemi 0:098463de4c5d 105 /* ================================================================================ */
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 #include <core_cm3.h> /* Processor and core peripherals */
group-onsemi 0:098463de4c5d 110 #include "system_max32610.h" /* System Header */
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 /* ================================================================================ */
group-onsemi 0:098463de4c5d 113 /* ================== Device Specific Memory Section ================== */
group-onsemi 0:098463de4c5d 114 /* ================================================================================ */
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 #define MXC_FLASH_MEM_BASE 0x00000000UL
group-onsemi 0:098463de4c5d 117 #define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB
group-onsemi 0:098463de4c5d 118 #define MXC_FLASH_MEM_SIZE 0x00040000UL
group-onsemi 0:098463de4c5d 119 #define MXC_SYS_MEM_BASE 0x20000000UL
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 /* ================================================================================ */
group-onsemi 0:098463de4c5d 122 /* ================ Device Specific Peripheral Section ================ */
group-onsemi 0:098463de4c5d 123 /* ================================================================================ */
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 /*******************************************************************************/
group-onsemi 0:098463de4c5d 126 /* General Purpose I/O Ports (GPIO) */
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 #define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
group-onsemi 0:098463de4c5d 129 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
group-onsemi 0:098463de4c5d 130 #define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 #define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn)
group-onsemi 0:098463de4c5d 133
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 /*******************************************************************************/
group-onsemi 0:098463de4c5d 136 /* Pulse Train Generation */
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 #define MXC_CFG_PT_INSTANCES (13)
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 #define MXC_BASE_PTG ((uint32_t)0x40001000UL)
group-onsemi 0:098463de4c5d 141 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
group-onsemi 0:098463de4c5d 142 #define MXC_BASE_PT ((uint32_t)0x40001008UL)
group-onsemi 0:098463de4c5d 143 #define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
group-onsemi 0:098463de4c5d 144 #define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
group-onsemi 0:098463de4c5d 145 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
group-onsemi 0:098463de4c5d 146 #define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
group-onsemi 0:098463de4c5d 147 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
group-onsemi 0:098463de4c5d 148 #define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
group-onsemi 0:098463de4c5d 149 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
group-onsemi 0:098463de4c5d 150 #define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
group-onsemi 0:098463de4c5d 151 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
group-onsemi 0:098463de4c5d 152 #define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
group-onsemi 0:098463de4c5d 153 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
group-onsemi 0:098463de4c5d 154 #define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
group-onsemi 0:098463de4c5d 155 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
group-onsemi 0:098463de4c5d 156 #define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
group-onsemi 0:098463de4c5d 157 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
group-onsemi 0:098463de4c5d 158 #define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
group-onsemi 0:098463de4c5d 159 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 /* PT12, PT13, PT14 are not used */
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 /*******************************************************************************/
group-onsemi 0:098463de4c5d 164 /* CRC-16/CRC-32 Engine */
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 #define MXC_BASE_CRC ((uint32_t)0x40010000UL)
group-onsemi 0:098463de4c5d 167 #define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 #define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
group-onsemi 0:098463de4c5d 170 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 /*******************************************************************************/
group-onsemi 0:098463de4c5d 173 /* Trust Protection Unit (TPU) */
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 #define MXC_BASE_TPU ((uint32_t)0x40011000UL)
group-onsemi 0:098463de4c5d 176 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 #define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
group-onsemi 0:098463de4c5d 179 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 /*******************************************************************************/
group-onsemi 0:098463de4c5d 182 /* AES Cryptographic Engine */
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 #define MXC_BASE_AES ((uint32_t)0x40011400UL)
group-onsemi 0:098463de4c5d 185 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 #define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
group-onsemi 0:098463de4c5d 188 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 /*******************************************************************************/
group-onsemi 0:098463de4c5d 192 /* MAA Cryptographic Engine */
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 #define MXC_BASE_MAA ((uint32_t)0x40011800UL)
group-onsemi 0:098463de4c5d 195 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
group-onsemi 0:098463de4c5d 196
group-onsemi 0:098463de4c5d 197 #define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
group-onsemi 0:098463de4c5d 198 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200 /*******************************************************************************/
group-onsemi 0:098463de4c5d 201 /* 32-Bit PWM Timer/Counter */
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 #define MXC_CFG_TMR_INSTANCES (4)
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 #define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
group-onsemi 0:098463de4c5d 206 #define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
group-onsemi 0:098463de4c5d 207 #define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 #define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
group-onsemi 0:098463de4c5d 210 #define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
group-onsemi 0:098463de4c5d 211 #define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 #define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
group-onsemi 0:098463de4c5d 214 #define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
group-onsemi 0:098463de4c5d 215 #define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 #define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
group-onsemi 0:098463de4c5d 218 #define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
group-onsemi 0:098463de4c5d 219 #define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221
group-onsemi 0:098463de4c5d 222 #define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
group-onsemi 0:098463de4c5d 223 (i) == 1 ? TMR1_IRQn : \
group-onsemi 0:098463de4c5d 224 (i) == 2 ? TMR2_IRQn : \
group-onsemi 0:098463de4c5d 225 (i) == 3 ? TMR3_IRQn : 0)
group-onsemi 0:098463de4c5d 226
group-onsemi 0:098463de4c5d 227 #define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
group-onsemi 0:098463de4c5d 228 (i) == 1 ? TMR1_IRQn : \
group-onsemi 0:098463de4c5d 229 (i) == 2 ? TMR2_IRQn : \
group-onsemi 0:098463de4c5d 230 (i) == 3 ? TMR3_IRQn : \
group-onsemi 0:098463de4c5d 231 (i) == 4 ? TMR16_0_IRQn : \
group-onsemi 0:098463de4c5d 232 (i) == 5 ? TMR16_1_IRQn : \
group-onsemi 0:098463de4c5d 233 (i) == 6 ? TMR16_2_IRQn : \
group-onsemi 0:098463de4c5d 234 (i) == 7 ? TMR16_3_IRQn : 0)
group-onsemi 0:098463de4c5d 235
group-onsemi 0:098463de4c5d 236 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
group-onsemi 0:098463de4c5d 237 (i) == 1 ? MXC_BASE_TMR1 : \
group-onsemi 0:098463de4c5d 238 (i) == 2 ? MXC_BASE_TMR2 : \
group-onsemi 0:098463de4c5d 239 (i) == 3 ? MXC_BASE_TMR3 : 0)
group-onsemi 0:098463de4c5d 240
group-onsemi 0:098463de4c5d 241 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
group-onsemi 0:098463de4c5d 242 (i) == 1 ? MXC_TMR1 : \
group-onsemi 0:098463de4c5d 243 (i) == 2 ? MXC_TMR2 : \
group-onsemi 0:098463de4c5d 244 (i) == 3 ? MXC_TMR3 : 0)
group-onsemi 0:098463de4c5d 245 /*******************************************************************************/
group-onsemi 0:098463de4c5d 246 /* Watchdog Timer */
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 #define MXC_CFG_WDT_INSTANCES (2)
group-onsemi 0:098463de4c5d 249
group-onsemi 0:098463de4c5d 250 #define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
group-onsemi 0:098463de4c5d 251 #define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
group-onsemi 0:098463de4c5d 252 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 #define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
group-onsemi 0:098463de4c5d 255 #define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
group-onsemi 0:098463de4c5d 256 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 #define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
group-onsemi 0:098463de4c5d 259 (i) == 1 ? WDT1_IRQn : 0)
group-onsemi 0:098463de4c5d 260
group-onsemi 0:098463de4c5d 261 #define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
group-onsemi 0:098463de4c5d 262 (i) == 1 ? WDT1_P_IRQn : 0)
group-onsemi 0:098463de4c5d 263
group-onsemi 0:098463de4c5d 264 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
group-onsemi 0:098463de4c5d 265 (i) == 1 ? MXC_BASE_WDT1 : 0)
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
group-onsemi 0:098463de4c5d 268 (i) == 1 ? MXC_WDT1 : 0)
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 /*******************************************************************************/
group-onsemi 0:098463de4c5d 271 /* SPI Interface */
group-onsemi 0:098463de4c5d 272
group-onsemi 0:098463de4c5d 273 #define MXC_CFG_SPI_INSTANCES (3)
group-onsemi 0:098463de4c5d 274 #define MXC_CFG_SPI_FIFO_DEPTH (16)
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 #define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
group-onsemi 0:098463de4c5d 277 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
group-onsemi 0:098463de4c5d 278
group-onsemi 0:098463de4c5d 279 #define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL)
group-onsemi 0:098463de4c5d 280 #define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
group-onsemi 0:098463de4c5d 281 #define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL)
group-onsemi 0:098463de4c5d 282 #define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
group-onsemi 0:098463de4c5d 283
group-onsemi 0:098463de4c5d 284 #define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
group-onsemi 0:098463de4c5d 285 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 #define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL)
group-onsemi 0:098463de4c5d 288 #define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
group-onsemi 0:098463de4c5d 289 #define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL)
group-onsemi 0:098463de4c5d 290 #define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 #define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
group-onsemi 0:098463de4c5d 293 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 #define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL)
group-onsemi 0:098463de4c5d 296 #define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
group-onsemi 0:098463de4c5d 297 #define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL)
group-onsemi 0:098463de4c5d 298 #define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300
group-onsemi 0:098463de4c5d 301 #define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
group-onsemi 0:098463de4c5d 302 (i) == 1 ? SPI1_IRQn : \
group-onsemi 0:098463de4c5d 303 (i) == 2 ? SPI2_IRQn : 0)
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
group-onsemi 0:098463de4c5d 306 (i) == 1 ? MXC_BASE_SPI1 : \
group-onsemi 0:098463de4c5d 307 (i) == 2 ? MXC_BASE_SPI2 : 0)
group-onsemi 0:098463de4c5d 308
group-onsemi 0:098463de4c5d 309 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
group-onsemi 0:098463de4c5d 310 (i) == 1 ? MXC_SPI1 : \
group-onsemi 0:098463de4c5d 311 (i) == 2 ? MXC_SPI2 : 0)
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 #define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \
group-onsemi 0:098463de4c5d 314 (i) == 1 ? MXC_SPI1_RXFIFO : \
group-onsemi 0:098463de4c5d 315 (i) == 2 ? MXC_SPI2_RXFIFO : 0)
group-onsemi 0:098463de4c5d 316
group-onsemi 0:098463de4c5d 317 #define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \
group-onsemi 0:098463de4c5d 318 (i) == 1 ? MXC_SPI1_TXFIFO : \
group-onsemi 0:098463de4c5d 319 (i) == 2 ? MXC_SPI2_TXFIFO : 0)
group-onsemi 0:098463de4c5d 320
group-onsemi 0:098463de4c5d 321 #define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
group-onsemi 0:098463de4c5d 322 #define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12)
group-onsemi 0:098463de4c5d 323
group-onsemi 0:098463de4c5d 324
group-onsemi 0:098463de4c5d 325 /*******************************************************************************/
group-onsemi 0:098463de4c5d 326 /* UART Interface */
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 #define MXC_CFG_UART_INSTANCES (2)
group-onsemi 0:098463de4c5d 329
group-onsemi 0:098463de4c5d 330 #define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
group-onsemi 0:098463de4c5d 331 #define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
group-onsemi 0:098463de4c5d 332 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
group-onsemi 0:098463de4c5d 333
group-onsemi 0:098463de4c5d 334 #define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
group-onsemi 0:098463de4c5d 335 #define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
group-onsemi 0:098463de4c5d 336 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
group-onsemi 0:098463de4c5d 337
group-onsemi 0:098463de4c5d 338
group-onsemi 0:098463de4c5d 339 #define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
group-onsemi 0:098463de4c5d 340 (i) == 1 ? UART1_IRQn : 0)
group-onsemi 0:098463de4c5d 341
group-onsemi 0:098463de4c5d 342 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
group-onsemi 0:098463de4c5d 343 (i) == 1 ? MXC_BASE_UART1 : 0)
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
group-onsemi 0:098463de4c5d 346 (i) == 1 ? MXC_UART1 : 0)
group-onsemi 0:098463de4c5d 347
group-onsemi 0:098463de4c5d 348 #define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
group-onsemi 0:098463de4c5d 349 #define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12)
group-onsemi 0:098463de4c5d 350
group-onsemi 0:098463de4c5d 351
group-onsemi 0:098463de4c5d 352 /*******************************************************************************/
group-onsemi 0:098463de4c5d 353 /* I2C Master Interface */
group-onsemi 0:098463de4c5d 354
group-onsemi 0:098463de4c5d 355 #define MXC_CFG_I2CM_INSTANCES (2)
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 #define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
group-onsemi 0:098463de4c5d 358 #define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
group-onsemi 0:098463de4c5d 359 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
group-onsemi 0:098463de4c5d 360 #define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL)
group-onsemi 0:098463de4c5d 361 #define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL)
group-onsemi 0:098463de4c5d 362
group-onsemi 0:098463de4c5d 363 #define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
group-onsemi 0:098463de4c5d 364 #define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
group-onsemi 0:098463de4c5d 365 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
group-onsemi 0:098463de4c5d 366 #define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL)
group-onsemi 0:098463de4c5d 367 #define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL)
group-onsemi 0:098463de4c5d 368
group-onsemi 0:098463de4c5d 369 #define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
group-onsemi 0:098463de4c5d 370 (i) == 1 ? I2CM1_IRQn : 0)
group-onsemi 0:098463de4c5d 371
group-onsemi 0:098463de4c5d 372 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
group-onsemi 0:098463de4c5d 373 (i) == 1 ? MXC_BASE_I2CM1 : 0)
group-onsemi 0:098463de4c5d 374
group-onsemi 0:098463de4c5d 375 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
group-onsemi 0:098463de4c5d 376 (i) == 1 ? MXC_I2CM1 : 0)
group-onsemi 0:098463de4c5d 377
group-onsemi 0:098463de4c5d 378 #define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \
group-onsemi 0:098463de4c5d 379 (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
group-onsemi 0:098463de4c5d 380
group-onsemi 0:098463de4c5d 381 #define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \
group-onsemi 0:098463de4c5d 382 (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 #define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
group-onsemi 0:098463de4c5d 385 #define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13)
group-onsemi 0:098463de4c5d 386
group-onsemi 0:098463de4c5d 387
group-onsemi 0:098463de4c5d 388 /*******************************************************************************/
group-onsemi 0:098463de4c5d 389 /* I2C Slave Interface */
group-onsemi 0:098463de4c5d 390
group-onsemi 0:098463de4c5d 391 #define MXC_CFG_I2CS_INSTANCES (1)
group-onsemi 0:098463de4c5d 392
group-onsemi 0:098463de4c5d 393 #define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
group-onsemi 0:098463de4c5d 394 #define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
group-onsemi 0:098463de4c5d 395 #define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
group-onsemi 0:098463de4c5d 396
group-onsemi 0:098463de4c5d 397 #define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
group-onsemi 0:098463de4c5d 398 #define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400
group-onsemi 0:098463de4c5d 401
group-onsemi 0:098463de4c5d 402 /*******************************************************************************/
group-onsemi 0:098463de4c5d 403 /* DACs */
group-onsemi 0:098463de4c5d 404
group-onsemi 0:098463de4c5d 405 #define MXC_CFG_DAC_INSTANCES (4)
group-onsemi 0:098463de4c5d 406 #define MXC_CFG_DAC_FIFO_DEPTH (32)
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 #define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
group-onsemi 0:098463de4c5d 409 #define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
group-onsemi 0:098463de4c5d 410 #define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
group-onsemi 0:098463de4c5d 411 #define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
group-onsemi 0:098463de4c5d 412 #define MXC_DAC0_WIDTH ((uint8_t)(2))
group-onsemi 0:098463de4c5d 413
group-onsemi 0:098463de4c5d 414 #define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
group-onsemi 0:098463de4c5d 415 #define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
group-onsemi 0:098463de4c5d 416 #define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
group-onsemi 0:098463de4c5d 417 #define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
group-onsemi 0:098463de4c5d 418 #define MXC_DAC1_WIDTH ((uint8_t)(2))
group-onsemi 0:098463de4c5d 419
group-onsemi 0:098463de4c5d 420 #define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
group-onsemi 0:098463de4c5d 421 #define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
group-onsemi 0:098463de4c5d 422 #define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
group-onsemi 0:098463de4c5d 423 #define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
group-onsemi 0:098463de4c5d 424 #define MXC_DAC2_WIDTH ((uint8_t)(1))
group-onsemi 0:098463de4c5d 425
group-onsemi 0:098463de4c5d 426 #define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
group-onsemi 0:098463de4c5d 427 #define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
group-onsemi 0:098463de4c5d 428 #define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
group-onsemi 0:098463de4c5d 429 #define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
group-onsemi 0:098463de4c5d 430 #define MXC_DAC3_WIDTH ((uint8_t)(1))
group-onsemi 0:098463de4c5d 431
group-onsemi 0:098463de4c5d 432
group-onsemi 0:098463de4c5d 433 #define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
group-onsemi 0:098463de4c5d 434 (i) == 1 ? DAC1_IRQn : \
group-onsemi 0:098463de4c5d 435 (i) == 2 ? DAC2_IRQn : \
group-onsemi 0:098463de4c5d 436 (i) == 3 ? DAC3_IRQn : 0)
group-onsemi 0:098463de4c5d 437
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
group-onsemi 0:098463de4c5d 440 i == 1 ? MXC_BASE_DAC1 : \
group-onsemi 0:098463de4c5d 441 i == 2 ? MXC_BASE_DAC2 : \
group-onsemi 0:098463de4c5d 442 i == 3 ? MXC_BASE_DAC3 : 0)
group-onsemi 0:098463de4c5d 443
group-onsemi 0:098463de4c5d 444 #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
group-onsemi 0:098463de4c5d 445 i == 1 ? MXC_BASE_DAC1_FIFO : \
group-onsemi 0:098463de4c5d 446 i == 2 ? MXC_BASE_DAC2_FIFO : \
group-onsemi 0:098463de4c5d 447 i == 3 ? MXC_BASE_DAC3_FIFO : 0)
group-onsemi 0:098463de4c5d 448
group-onsemi 0:098463de4c5d 449 #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
group-onsemi 0:098463de4c5d 450 i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
group-onsemi 0:098463de4c5d 451 i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
group-onsemi 0:098463de4c5d 452 i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
group-onsemi 0:098463de4c5d 453
group-onsemi 0:098463de4c5d 454 #define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
group-onsemi 0:098463de4c5d 455 i == 1 ? MXC_DAC1 : \
group-onsemi 0:098463de4c5d 456 i == 2 ? MXC_DAC2 : \
group-onsemi 0:098463de4c5d 457 i == 3 ? MXC_DAC3 : 0)
group-onsemi 0:098463de4c5d 458
group-onsemi 0:098463de4c5d 459 #define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
group-onsemi 0:098463de4c5d 460 i == 1 ? MXC_DAC1_WIDTH : \
group-onsemi 0:098463de4c5d 461 i == 2 ? MXC_DAC2_WIDTH : \
group-onsemi 0:098463de4c5d 462 i == 3 ? MXC_DAC3_WIDTH : 0)
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464
group-onsemi 0:098463de4c5d 465 /*******************************************************************************/
group-onsemi 0:098463de4c5d 466 /* Analog Front End */
group-onsemi 0:098463de4c5d 467
group-onsemi 0:098463de4c5d 468 #define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
group-onsemi 0:098463de4c5d 469 #define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
group-onsemi 0:098463de4c5d 470
group-onsemi 0:098463de4c5d 471
group-onsemi 0:098463de4c5d 472
group-onsemi 0:098463de4c5d 473 /*******************************************************************************/
group-onsemi 0:098463de4c5d 474 /* ADC */
group-onsemi 0:098463de4c5d 475
group-onsemi 0:098463de4c5d 476 #define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 #define MXC_BASE_ADC ((uint32_t)0x40054000UL)
group-onsemi 0:098463de4c5d 479 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
group-onsemi 0:098463de4c5d 480
group-onsemi 0:098463de4c5d 481 #define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
group-onsemi 0:098463de4c5d 482 #define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
group-onsemi 0:098463de4c5d 483
group-onsemi 0:098463de4c5d 484 #define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
group-onsemi 0:098463de4c5d 485 #define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
group-onsemi 0:098463de4c5d 486
group-onsemi 0:098463de4c5d 487
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 /*******************************************************************************/
group-onsemi 0:098463de4c5d 490 /* Peripheral Management Unit (PMU) - formerly DMA Controller */
group-onsemi 0:098463de4c5d 491
group-onsemi 0:098463de4c5d 492 #define MXC_CFG_PMU_CHANNELS (6)
group-onsemi 0:098463de4c5d 493
group-onsemi 0:098463de4c5d 494 #define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
group-onsemi 0:098463de4c5d 495 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
group-onsemi 0:098463de4c5d 496 #define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
group-onsemi 0:098463de4c5d 497 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
group-onsemi 0:098463de4c5d 498 #define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
group-onsemi 0:098463de4c5d 499 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
group-onsemi 0:098463de4c5d 500 #define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
group-onsemi 0:098463de4c5d 501 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
group-onsemi 0:098463de4c5d 502 #define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
group-onsemi 0:098463de4c5d 503 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
group-onsemi 0:098463de4c5d 504 #define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
group-onsemi 0:098463de4c5d 505 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
group-onsemi 0:098463de4c5d 506
group-onsemi 0:098463de4c5d 507 #define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
group-onsemi 0:098463de4c5d 508 #define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
group-onsemi 0:098463de4c5d 509 /*******************************************************************************/
group-onsemi 0:098463de4c5d 510
group-onsemi 0:098463de4c5d 511 typedef enum {
group-onsemi 0:098463de4c5d 512 PMU_IRQ_DAC0_FIFO_AE,
group-onsemi 0:098463de4c5d 513 PMU_IRQ_DAC1_FIFO_AE,
group-onsemi 0:098463de4c5d 514 PMU_IRQ_DAC2_FIFO_AE,
group-onsemi 0:098463de4c5d 515 PMU_IRQ_DAC3_FIFO_AE,
group-onsemi 0:098463de4c5d 516 PMU_IRQ_DAC0_DONE,
group-onsemi 0:098463de4c5d 517 PMU_IRQ_DAC1_DONE,
group-onsemi 0:098463de4c5d 518 PMU_IRQ_DAC2_DONE,
group-onsemi 0:098463de4c5d 519 PMU_IRQ_DAC3_DONE,
group-onsemi 0:098463de4c5d 520 PMU_IRQ_ADC_FIFO_AF,
group-onsemi 0:098463de4c5d 521 PMU_IRQ_ADC_DONE,
group-onsemi 0:098463de4c5d 522 PMU_IRQ_I2C_MST0_DONE,
group-onsemi 0:098463de4c5d 523 PMU_IRQ_I2C_MST1_DONE,
group-onsemi 0:098463de4c5d 524 PMU_IRQ_SPI0_RSLTS_DONE,
group-onsemi 0:098463de4c5d 525 PMU_IRQ_SPI1_RSLTS_DONE,
group-onsemi 0:098463de4c5d 526 PMU_IRQ_SPI2_RSLTS_DONE,
group-onsemi 0:098463de4c5d 527 PMU_IRQ_MAA_DONE,
group-onsemi 0:098463de4c5d 528 PMU_IRQ_SPI0_TX_FIFO_AE,
group-onsemi 0:098463de4c5d 529 PMU_IRQ_SPI0_RSLTS_FIFO_AF,
group-onsemi 0:098463de4c5d 530 PMU_IRQ_SPI1_TX_FIFO_AE,
group-onsemi 0:098463de4c5d 531 PMU_IRQ_SPI1_RSLTS_FIFO_AF,
group-onsemi 0:098463de4c5d 532 PMU_IRQ_SPI2_TX_FIFO_AE,
group-onsemi 0:098463de4c5d 533 PMU_IRQ_SPI3_RSLTS_FIFO_AF,
group-onsemi 0:098463de4c5d 534 PMU_IRQ_I2C_MST0_TRANS_FIFO,
group-onsemi 0:098463de4c5d 535 PMU_IRQ_I2C_MST0_RSLT_FIFO,
group-onsemi 0:098463de4c5d 536 PMU_IRQ_I2C_MST1_TRANS_FIFO,
group-onsemi 0:098463de4c5d 537 PMU_IRQ_I2C_MST2_RSLT_FIFO,
group-onsemi 0:098463de4c5d 538 PMU_IRQ_I2C_SLV_TRANS_FIFO,
group-onsemi 0:098463de4c5d 539 PMU_IRQ_I2C_SLV_RSLT_FIFO,
group-onsemi 0:098463de4c5d 540 PMU_IRQ_UART0_TX_FIFO,
group-onsemi 0:098463de4c5d 541 PMU_IRQ_UART0_RX_FIFO,
group-onsemi 0:098463de4c5d 542 PMU_IRQ_UART1_TX_FIFO,
group-onsemi 0:098463de4c5d 543 PMU_IRQ_UART1_RX_FIFO,
group-onsemi 0:098463de4c5d 544 PMU_IRQ_SPI0_EXCP,
group-onsemi 0:098463de4c5d 545 PMU_IRQ_SPI1_EXCP,
group-onsemi 0:098463de4c5d 546 PMU_IRQ_SPI2_EXCP,
group-onsemi 0:098463de4c5d 547 PMU_IRQ_RSVD0,
group-onsemi 0:098463de4c5d 548 PMU_IRQ_I2C_MST0_EXCP,
group-onsemi 0:098463de4c5d 549 PMU_IRQ_I2C_MST1_EXCP,
group-onsemi 0:098463de4c5d 550 PMU_IRQ_I2C_SLV_EXCP,
group-onsemi 0:098463de4c5d 551 PMU_IRQ_RSVD1,
group-onsemi 0:098463de4c5d 552 PMU_IRQ_GPIO0,
group-onsemi 0:098463de4c5d 553 PMU_IRQ_GPIO1,
group-onsemi 0:098463de4c5d 554 PMU_IRQ_GPIO2,
group-onsemi 0:098463de4c5d 555 PMU_IRQ_GPIO3,
group-onsemi 0:098463de4c5d 556 PMU_IRQ_GPIO4,
group-onsemi 0:098463de4c5d 557 PMU_IRQ_GPIO5,
group-onsemi 0:098463de4c5d 558 PMU_IRQ_GPIO6,
group-onsemi 0:098463de4c5d 559 PMU_IRQ_GPIO7,
group-onsemi 0:098463de4c5d 560 PMU_IRQ_GPIO8,
group-onsemi 0:098463de4c5d 561 PMU_IRQ_AFE_COMP_NMI,
group-onsemi 0:098463de4c5d 562 PMU_IRQ_AES_ENGINE,
group-onsemi 0:098463de4c5d 563 } pmu_int_mask_t;
group-onsemi 0:098463de4c5d 564
group-onsemi 0:098463de4c5d 565 /*******************************************************************************/
group-onsemi 0:098463de4c5d 566 /* USB */
group-onsemi 0:098463de4c5d 567
group-onsemi 0:098463de4c5d 568 #define MXC_BASE_USB ((uint32_t)0x4010C000UL)
group-onsemi 0:098463de4c5d 569 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
group-onsemi 0:098463de4c5d 570
group-onsemi 0:098463de4c5d 571 #define MXC_USB_MAX_PACKET (64)
group-onsemi 0:098463de4c5d 572 #define MXC_USB_NUM_EP (8)
group-onsemi 0:098463de4c5d 573
group-onsemi 0:098463de4c5d 574
group-onsemi 0:098463de4c5d 575 /*******************************************************************************/
group-onsemi 0:098463de4c5d 576 /* Instruction Cache Controller */
group-onsemi 0:098463de4c5d 577
group-onsemi 0:098463de4c5d 578 #define MXC_BASE_ICC ((uint32_t)0x40080000UL)
group-onsemi 0:098463de4c5d 579 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
group-onsemi 0:098463de4c5d 580
group-onsemi 0:098463de4c5d 581 /* System Manager */
group-onsemi 0:098463de4c5d 582
group-onsemi 0:098463de4c5d 583 #define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
group-onsemi 0:098463de4c5d 584
group-onsemi 0:098463de4c5d 585 /*******************************************************************************/
group-onsemi 0:098463de4c5d 586 /* Clock Manager */
group-onsemi 0:098463de4c5d 587
group-onsemi 0:098463de4c5d 588 #define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
group-onsemi 0:098463de4c5d 589 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
group-onsemi 0:098463de4c5d 590
group-onsemi 0:098463de4c5d 591
group-onsemi 0:098463de4c5d 592 /*******************************************************************************/
group-onsemi 0:098463de4c5d 593 /* Power Manager */
group-onsemi 0:098463de4c5d 594
group-onsemi 0:098463de4c5d 595 #define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
group-onsemi 0:098463de4c5d 596 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
group-onsemi 0:098463de4c5d 597
group-onsemi 0:098463de4c5d 598 /*******************************************************************************/
group-onsemi 0:098463de4c5d 599 /* I/O Manager */
group-onsemi 0:098463de4c5d 600
group-onsemi 0:098463de4c5d 601 #define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
group-onsemi 0:098463de4c5d 602 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
group-onsemi 0:098463de4c5d 603
group-onsemi 0:098463de4c5d 604
group-onsemi 0:098463de4c5d 605 /*******************************************************************************/
group-onsemi 0:098463de4c5d 606 /* RTC: Timer/Alarms */
group-onsemi 0:098463de4c5d 607
group-onsemi 0:098463de4c5d 608 #define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
group-onsemi 0:098463de4c5d 609 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
group-onsemi 0:098463de4c5d 610
group-onsemi 0:098463de4c5d 611 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
group-onsemi 0:098463de4c5d 612 i == 1 ? RTC1_IRQn : \
group-onsemi 0:098463de4c5d 613 i == 2 ? RTC2_IRQn : \
group-onsemi 0:098463de4c5d 614 i == 3 ? RTC3_IRQn : 0)
group-onsemi 0:098463de4c5d 615
group-onsemi 0:098463de4c5d 616 #define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
group-onsemi 0:098463de4c5d 617 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
group-onsemi 0:098463de4c5d 618 /*******************************************************************************/
group-onsemi 0:098463de4c5d 619 /* RTC: Power Sequencer */
group-onsemi 0:098463de4c5d 620
group-onsemi 0:098463de4c5d 621 #define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
group-onsemi 0:098463de4c5d 622 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
group-onsemi 0:098463de4c5d 623
group-onsemi 0:098463de4c5d 624 /*******************************************************************************/
group-onsemi 0:098463de4c5d 625 /* Trim Shadow Registers */
group-onsemi 0:098463de4c5d 626
group-onsemi 0:098463de4c5d 627 #define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
group-onsemi 0:098463de4c5d 628 #define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
group-onsemi 0:098463de4c5d 629
group-onsemi 0:098463de4c5d 630 /*******************************************************************************/
group-onsemi 0:098463de4c5d 631 /* Flash Memory Controller / Security */
group-onsemi 0:098463de4c5d 632
group-onsemi 0:098463de4c5d 633 #define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
group-onsemi 0:098463de4c5d 634 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
group-onsemi 0:098463de4c5d 635 #define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
group-onsemi 0:098463de4c5d 636 #define MXC_FLC_PAGE_SIZE_SHIFT 11
group-onsemi 0:098463de4c5d 637 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
group-onsemi 0:098463de4c5d 638 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
group-onsemi 0:098463de4c5d 639
group-onsemi 0:098463de4c5d 640 /*******************************************************************************/
group-onsemi 0:098463de4c5d 641
group-onsemi 0:098463de4c5d 642 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
group-onsemi 0:098463de4c5d 643
group-onsemi 0:098463de4c5d 644 /*******************************************************************************/
group-onsemi 0:098463de4c5d 645
group-onsemi 0:098463de4c5d 646 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
group-onsemi 0:098463de4c5d 647 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
group-onsemi 0:098463de4c5d 648 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
group-onsemi 0:098463de4c5d 649 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
group-onsemi 0:098463de4c5d 650
group-onsemi 0:098463de4c5d 651 /*******************************************************************************/
group-onsemi 0:098463de4c5d 652
group-onsemi 0:098463de4c5d 653 #endif /* _MAX32610_H_ */