ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32600/serial_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include <string.h>
group-onsemi 0:098463de4c5d 35 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "serial_api.h"
group-onsemi 0:098463de4c5d 38 #include "gpio_api.h"
group-onsemi 0:098463de4c5d 39 #include "uart_regs.h"
group-onsemi 0:098463de4c5d 40 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 41 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 #define UART_NUM 2
group-onsemi 0:098463de4c5d 44 #define DEFAULT_BAUD 9600
group-onsemi 0:098463de4c5d 45 #define DEFAULT_STOP 1
group-onsemi 0:098463de4c5d 46 #define DEFAULT_PARITY ParityNone
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \
group-onsemi 0:098463de4c5d 49 MXC_F_UART_INTFL_RX_PARITY_ERROR | \
group-onsemi 0:098463de4c5d 50 MXC_F_UART_INTFL_RX_OVERRUN)
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 // Variables for managing the stdio UART
group-onsemi 0:098463de4c5d 53 int stdio_uart_inited;
group-onsemi 0:098463de4c5d 54 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 // Variables for interrupt driven
group-onsemi 0:098463de4c5d 57 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 58 static uint32_t serial_irq_ids[UART_NUM];
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 //******************************************************************************
group-onsemi 0:098463de4c5d 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 62 {
group-onsemi 0:098463de4c5d 63 // Determine which uart is associated with each pin
group-onsemi 0:098463de4c5d 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 // Make sure that both pins are pointing to the same uart
group-onsemi 0:098463de4c5d 69 MBED_ASSERT(uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 // Set the obj pointer to the proper uart
group-onsemi 0:098463de4c5d 72 obj->uart = (mxc_uart_regs_t*)uart;
group-onsemi 0:098463de4c5d 73
group-onsemi 0:098463de4c5d 74 // Set the uart index
group-onsemi 0:098463de4c5d 75 obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart);
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 // Configure the pins
group-onsemi 0:098463de4c5d 78 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 79 pinmap_pinout(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 // Flush the RX and TX FIFOs, clear the settings
group-onsemi 0:098463de4c5d 82 obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH);
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 // Disable interrupts
group-onsemi 0:098463de4c5d 85 obj->uart->inten = 0;
group-onsemi 0:098463de4c5d 86 obj->uart->intfl = 0;
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 // Configure to default settings
group-onsemi 0:098463de4c5d 89 serial_baud(obj, DEFAULT_BAUD);
group-onsemi 0:098463de4c5d 90 serial_format(obj, 8, ParityNone, 1);
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 // Manage stdio UART
group-onsemi 0:098463de4c5d 93 if(uart == STDIO_UART) {
group-onsemi 0:098463de4c5d 94 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 95 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 96 }
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 //******************************************************************************
group-onsemi 0:098463de4c5d 100 void serial_baud(serial_t *obj, int baudrate)
group-onsemi 0:098463de4c5d 101 {
group-onsemi 0:098463de4c5d 102 uint32_t idiv = 0, ddiv = 0, div = 0;
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 // Calculate the integer and decimal portions
group-onsemi 0:098463de4c5d 105 div = SystemCoreClock / ((baudrate / 100) * 128);
group-onsemi 0:098463de4c5d 106 idiv = (div / 100);
group-onsemi 0:098463de4c5d 107 ddiv = (div - idiv * 100) * 128 / 100;
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 obj->uart->baud_int = idiv;
group-onsemi 0:098463de4c5d 110 obj->uart->baud_div_128 = ddiv;
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 // Enable the baud clock
group-onsemi 0:098463de4c5d 113 obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN;
group-onsemi 0:098463de4c5d 114 }
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 //******************************************************************************
group-onsemi 0:098463de4c5d 117 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
group-onsemi 0:098463de4c5d 118 {
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 // Check the validity of the inputs
group-onsemi 0:098463de4c5d 121 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
group-onsemi 0:098463de4c5d 122 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
group-onsemi 0:098463de4c5d 123 (parity == ParityEven) || (parity == ParityForced1) ||
group-onsemi 0:098463de4c5d 124 (parity == ParityForced0));
group-onsemi 0:098463de4c5d 125 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 // Adjust the stop and data bits
group-onsemi 0:098463de4c5d 128 stop_bits -= 1;
group-onsemi 0:098463de4c5d 129 data_bits -= 5;
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 // Adjust the parity setting
group-onsemi 0:098463de4c5d 132 int paren = 0, mode = 0;
group-onsemi 0:098463de4c5d 133 switch (parity) {
group-onsemi 0:098463de4c5d 134 case ParityNone:
group-onsemi 0:098463de4c5d 135 paren = 0;
group-onsemi 0:098463de4c5d 136 mode = 0;
group-onsemi 0:098463de4c5d 137 break;
group-onsemi 0:098463de4c5d 138 case ParityOdd :
group-onsemi 0:098463de4c5d 139 paren = 1;
group-onsemi 0:098463de4c5d 140 mode = 0;
group-onsemi 0:098463de4c5d 141 break;
group-onsemi 0:098463de4c5d 142 case ParityEven:
group-onsemi 0:098463de4c5d 143 paren = 1;
group-onsemi 0:098463de4c5d 144 mode = 1;
group-onsemi 0:098463de4c5d 145 break;
group-onsemi 0:098463de4c5d 146 case ParityForced1:
group-onsemi 0:098463de4c5d 147 // Hardware does not support forced parity
group-onsemi 0:098463de4c5d 148 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 149 break;
group-onsemi 0:098463de4c5d 150 case ParityForced0:
group-onsemi 0:098463de4c5d 151 // Hardware does not support forced parity
group-onsemi 0:098463de4c5d 152 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 153 break;
group-onsemi 0:098463de4c5d 154 default:
group-onsemi 0:098463de4c5d 155 paren = 1;
group-onsemi 0:098463de4c5d 156 mode = 0;
group-onsemi 0:098463de4c5d 157 break;
group-onsemi 0:098463de4c5d 158 }
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) |
group-onsemi 0:098463de4c5d 161 (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) |
group-onsemi 0:098463de4c5d 162 (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) |
group-onsemi 0:098463de4c5d 163 (mode << MXC_F_UART_CTRL_PARITY_MODE_POS));
group-onsemi 0:098463de4c5d 164 }
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 //******************************************************************************
group-onsemi 0:098463de4c5d 167 void uart_handler(mxc_uart_regs_t* uart, int id)
group-onsemi 0:098463de4c5d 168 {
group-onsemi 0:098463de4c5d 169 // Check for errors or RX Threshold
group-onsemi 0:098463de4c5d 170 if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) {
group-onsemi 0:098463de4c5d 171 irq_handler(serial_irq_ids[id], RxIrq);
group-onsemi 0:098463de4c5d 172 uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS);
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 // Check for TX Threshold
group-onsemi 0:098463de4c5d 176 if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) {
group-onsemi 0:098463de4c5d 177 irq_handler(serial_irq_ids[id], TxIrq);
group-onsemi 0:098463de4c5d 178 uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY);
group-onsemi 0:098463de4c5d 179 }
group-onsemi 0:098463de4c5d 180 }
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 void uart0_handler(void)
group-onsemi 0:098463de4c5d 183 {
group-onsemi 0:098463de4c5d 184 uart_handler(MXC_UART0, 0);
group-onsemi 0:098463de4c5d 185 }
group-onsemi 0:098463de4c5d 186 void uart1_handler(void)
group-onsemi 0:098463de4c5d 187 {
group-onsemi 0:098463de4c5d 188 uart_handler(MXC_UART1, 1);
group-onsemi 0:098463de4c5d 189 }
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 //******************************************************************************
group-onsemi 0:098463de4c5d 192 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 193 {
group-onsemi 0:098463de4c5d 194 irq_handler = handler;
group-onsemi 0:098463de4c5d 195 serial_irq_ids[obj->index] = id;
group-onsemi 0:098463de4c5d 196 }
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 //******************************************************************************
group-onsemi 0:098463de4c5d 199 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
group-onsemi 0:098463de4c5d 200 {
group-onsemi 0:098463de4c5d 201 if(obj->index == 0) {
group-onsemi 0:098463de4c5d 202 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
group-onsemi 0:098463de4c5d 203 NVIC_EnableIRQ(UART0_IRQn);
group-onsemi 0:098463de4c5d 204 } else {
group-onsemi 0:098463de4c5d 205 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
group-onsemi 0:098463de4c5d 206 NVIC_EnableIRQ(UART1_IRQn);
group-onsemi 0:098463de4c5d 207 }
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 if(irq == RxIrq) {
group-onsemi 0:098463de4c5d 210 // Set the RX FIFO Threshold to 1
group-onsemi 0:098463de4c5d 211 obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD;
group-onsemi 0:098463de4c5d 212 obj->uart->ctrl |= 0x1;
group-onsemi 0:098463de4c5d 213 // Enable RX FIFO Threshold Interrupt
group-onsemi 0:098463de4c5d 214 if(enable) {
group-onsemi 0:098463de4c5d 215 // Clear pending interrupts
group-onsemi 0:098463de4c5d 216 obj->uart->intfl = 0;
group-onsemi 0:098463de4c5d 217 obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
group-onsemi 0:098463de4c5d 218 UART_ERRORS);
group-onsemi 0:098463de4c5d 219 } else {
group-onsemi 0:098463de4c5d 220 // Clear pending interrupts
group-onsemi 0:098463de4c5d 221 obj->uart->intfl = 0;
group-onsemi 0:098463de4c5d 222 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
group-onsemi 0:098463de4c5d 223 UART_ERRORS);
group-onsemi 0:098463de4c5d 224 }
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 } else if (irq == TxIrq) {
group-onsemi 0:098463de4c5d 227 // Enable TX Almost empty Interrupt
group-onsemi 0:098463de4c5d 228 if(enable) {
group-onsemi 0:098463de4c5d 229 // Clear pending interrupts
group-onsemi 0:098463de4c5d 230 obj->uart->intfl = 0;
group-onsemi 0:098463de4c5d 231 obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
group-onsemi 0:098463de4c5d 232 } else {
group-onsemi 0:098463de4c5d 233 // Clear pending interrupts
group-onsemi 0:098463de4c5d 234 obj->uart->intfl = 0;
group-onsemi 0:098463de4c5d 235 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
group-onsemi 0:098463de4c5d 236 }
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 } else {
group-onsemi 0:098463de4c5d 239 MBED_ASSERT(0);
group-onsemi 0:098463de4c5d 240 }
group-onsemi 0:098463de4c5d 241 }
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244 //******************************************************************************
group-onsemi 0:098463de4c5d 245 int serial_getc(serial_t *obj)
group-onsemi 0:098463de4c5d 246 {
group-onsemi 0:098463de4c5d 247 int c;
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 // Wait for data to be available
group-onsemi 0:098463de4c5d 250 while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
group-onsemi 0:098463de4c5d 251 c = obj->uart->tx_rx_fifo & 0xFF;
group-onsemi 0:098463de4c5d 252
group-onsemi 0:098463de4c5d 253 return c;
group-onsemi 0:098463de4c5d 254 }
group-onsemi 0:098463de4c5d 255
group-onsemi 0:098463de4c5d 256 //******************************************************************************
group-onsemi 0:098463de4c5d 257 void serial_putc(serial_t *obj, int c)
group-onsemi 0:098463de4c5d 258 {
group-onsemi 0:098463de4c5d 259 // Wait for TXFIFO to not be full
group-onsemi 0:098463de4c5d 260 while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
group-onsemi 0:098463de4c5d 261 obj->uart->tx_rx_fifo = c;
group-onsemi 0:098463de4c5d 262 }
group-onsemi 0:098463de4c5d 263
group-onsemi 0:098463de4c5d 264 //******************************************************************************
group-onsemi 0:098463de4c5d 265 int serial_readable(serial_t *obj)
group-onsemi 0:098463de4c5d 266 {
group-onsemi 0:098463de4c5d 267 return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY));
group-onsemi 0:098463de4c5d 268 }
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 //******************************************************************************
group-onsemi 0:098463de4c5d 271 int serial_writable(serial_t *obj)
group-onsemi 0:098463de4c5d 272 {
group-onsemi 0:098463de4c5d 273 return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL));
group-onsemi 0:098463de4c5d 274 }
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 //******************************************************************************
group-onsemi 0:098463de4c5d 277 void serial_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 278 {
group-onsemi 0:098463de4c5d 279 // Clear the rx and tx fifos
group-onsemi 0:098463de4c5d 280 obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH );
group-onsemi 0:098463de4c5d 281 }
group-onsemi 0:098463de4c5d 282
group-onsemi 0:098463de4c5d 283 //******************************************************************************
group-onsemi 0:098463de4c5d 284 void serial_break_set(serial_t *obj)
group-onsemi 0:098463de4c5d 285 {
group-onsemi 0:098463de4c5d 286 // Make sure that nothing is being sent
group-onsemi 0:098463de4c5d 287 while (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_EMPTY));
group-onsemi 0:098463de4c5d 288 while (obj->uart->status & MXC_F_UART_STATUS_TX_BUSY);
group-onsemi 0:098463de4c5d 289
group-onsemi 0:098463de4c5d 290 // Configure the GPIO to outpu 0
group-onsemi 0:098463de4c5d 291 gpio_t tx_gpio;
group-onsemi 0:098463de4c5d 292 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 293 case UART_0:
group-onsemi 0:098463de4c5d 294 gpio_init_out(&tx_gpio, UART0_TX);
group-onsemi 0:098463de4c5d 295 break;
group-onsemi 0:098463de4c5d 296 case UART_1:
group-onsemi 0:098463de4c5d 297 gpio_init_out(&tx_gpio, UART1_TX);
group-onsemi 0:098463de4c5d 298 break;
group-onsemi 0:098463de4c5d 299 default:
group-onsemi 0:098463de4c5d 300 gpio_init_out(&tx_gpio, (PinName)NC);
group-onsemi 0:098463de4c5d 301 break;
group-onsemi 0:098463de4c5d 302 }
group-onsemi 0:098463de4c5d 303
group-onsemi 0:098463de4c5d 304 gpio_write(&tx_gpio, 0);
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 // GPIO is setup now, but we need to maps gpio to the pin
group-onsemi 0:098463de4c5d 307 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 308 case UART_0:
group-onsemi 0:098463de4c5d 309 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_CORE_IO;
group-onsemi 0:098463de4c5d 310 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
group-onsemi 0:098463de4c5d 311 break;
group-onsemi 0:098463de4c5d 312 case UART_1:
group-onsemi 0:098463de4c5d 313 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_CORE_IO;
group-onsemi 0:098463de4c5d 314 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
group-onsemi 0:098463de4c5d 315 break;
group-onsemi 0:098463de4c5d 316 default:
group-onsemi 0:098463de4c5d 317 break;
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319 }
group-onsemi 0:098463de4c5d 320
group-onsemi 0:098463de4c5d 321 //******************************************************************************
group-onsemi 0:098463de4c5d 322 void serial_break_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 323 {
group-onsemi 0:098463de4c5d 324 // Configure the GPIO to output 1
group-onsemi 0:098463de4c5d 325 gpio_t tx_gpio;
group-onsemi 0:098463de4c5d 326 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 327 case UART_0:
group-onsemi 0:098463de4c5d 328 gpio_init_out(&tx_gpio, UART0_TX);
group-onsemi 0:098463de4c5d 329 break;
group-onsemi 0:098463de4c5d 330 case UART_1:
group-onsemi 0:098463de4c5d 331 gpio_init_out(&tx_gpio, UART1_TX);
group-onsemi 0:098463de4c5d 332 break;
group-onsemi 0:098463de4c5d 333 default:
group-onsemi 0:098463de4c5d 334 gpio_init_out(&tx_gpio, (PinName)NC);
group-onsemi 0:098463de4c5d 335 break;
group-onsemi 0:098463de4c5d 336 }
group-onsemi 0:098463de4c5d 337
group-onsemi 0:098463de4c5d 338 gpio_write(&tx_gpio, 1);
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 // Renable UART
group-onsemi 0:098463de4c5d 341 switch (((UARTName)(obj->uart))) {
group-onsemi 0:098463de4c5d 342 case UART_0:
group-onsemi 0:098463de4c5d 343 serial_pinout_tx(UART0_TX);
group-onsemi 0:098463de4c5d 344 break;
group-onsemi 0:098463de4c5d 345 case UART_1:
group-onsemi 0:098463de4c5d 346 serial_pinout_tx(UART1_TX);
group-onsemi 0:098463de4c5d 347 break;
group-onsemi 0:098463de4c5d 348 default:
group-onsemi 0:098463de4c5d 349 serial_pinout_tx((PinName)NC);
group-onsemi 0:098463de4c5d 350 break;
group-onsemi 0:098463de4c5d 351 }
group-onsemi 0:098463de4c5d 352 }
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354 //******************************************************************************
group-onsemi 0:098463de4c5d 355 void serial_pinout_tx(PinName tx)
group-onsemi 0:098463de4c5d 356 {
group-onsemi 0:098463de4c5d 357 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 358 }
group-onsemi 0:098463de4c5d 359
group-onsemi 0:098463de4c5d 360
group-onsemi 0:098463de4c5d 361 //******************************************************************************
group-onsemi 0:098463de4c5d 362 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
group-onsemi 0:098463de4c5d 363 {
group-onsemi 0:098463de4c5d 364 if(FlowControlNone == type) {
group-onsemi 0:098463de4c5d 365 // Disable hardware flow control
group-onsemi 0:098463de4c5d 366 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN);
group-onsemi 0:098463de4c5d 367 return;
group-onsemi 0:098463de4c5d 368 }
group-onsemi 0:098463de4c5d 369
group-onsemi 0:098463de4c5d 370 // Check to see if we can use HW flow control
group-onsemi 0:098463de4c5d 371 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 372 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 373 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
group-onsemi 0:098463de4c5d 374
group-onsemi 0:098463de4c5d 375 if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) {
group-onsemi 0:098463de4c5d 376 // Make sure pin is in the PinMap
group-onsemi 0:098463de4c5d 377 MBED_ASSERT(uart_cts != (UARTName)NC);
group-onsemi 0:098463de4c5d 378
group-onsemi 0:098463de4c5d 379 // Enable the pin for CTS function
group-onsemi 0:098463de4c5d 380 pinmap_pinout(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 381 }
group-onsemi 0:098463de4c5d 382
group-onsemi 0:098463de4c5d 383 if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) {
group-onsemi 0:098463de4c5d 384 // Make sure pin is in the PinMap
group-onsemi 0:098463de4c5d 385 MBED_ASSERT(uart_rts != (UARTName)NC);
group-onsemi 0:098463de4c5d 386
group-onsemi 0:098463de4c5d 387 // Enable the pin for RTS function
group-onsemi 0:098463de4c5d 388 pinmap_pinout(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 389 }
group-onsemi 0:098463de4c5d 390
group-onsemi 0:098463de4c5d 391 if(FlowControlRTSCTS == type){
group-onsemi 0:098463de4c5d 392 // Make sure that the pins are pointing to the same UART
group-onsemi 0:098463de4c5d 393 MBED_ASSERT(uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 394 }
group-onsemi 0:098463de4c5d 395
group-onsemi 0:098463de4c5d 396 // Enable hardware flow control
group-onsemi 0:098463de4c5d 397 obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN;
group-onsemi 0:098463de4c5d 398 }