ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32600/rtc_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "rtc_api.h"
group-onsemi 0:098463de4c5d 35 #include "lp_ticker_api.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis.h"
group-onsemi 0:098463de4c5d 37 #include "rtc_regs.h"
group-onsemi 0:098463de4c5d 38 #include "pwrseq_regs.h"
group-onsemi 0:098463de4c5d 39 #include "clkman_regs.h"
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
group-onsemi 0:098463de4c5d 42 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 #define WINDOW 1000
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 static int rtc_inited = 0;
group-onsemi 0:098463de4c5d 47 static volatile uint32_t overflow_cnt = 0;
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 static uint64_t rtc_read64(void);
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 //******************************************************************************
group-onsemi 0:098463de4c5d 52 static void overflow_handler(void)
group-onsemi 0:098463de4c5d 53 {
group-onsemi 0:098463de4c5d 54 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 55 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
group-onsemi 0:098463de4c5d 56 overflow_cnt++;
group-onsemi 0:098463de4c5d 57 }
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 //******************************************************************************
group-onsemi 0:098463de4c5d 60 void rtc_init(void)
group-onsemi 0:098463de4c5d 61 {
group-onsemi 0:098463de4c5d 62 if (rtc_inited) {
group-onsemi 0:098463de4c5d 63 return;
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65 rtc_inited = 1;
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 overflow_cnt = 0;
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 // Enable the clock to the synchronizer
group-onsemi 0:098463de4c5d 70 MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 // Enable the clock to the RTC
group-onsemi 0:098463de4c5d 73 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 // Prepare interrupt handlers
group-onsemi 0:098463de4c5d 76 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
group-onsemi 0:098463de4c5d 77 NVIC_EnableIRQ(RTC0_IRQn);
group-onsemi 0:098463de4c5d 78 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
group-onsemi 0:098463de4c5d 79 NVIC_EnableIRQ(RTC3_IRQn);
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 // Enable wakeup on RTC rollover
group-onsemi 0:098463de4c5d 82 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
group-onsemi 0:098463de4c5d 85 * if it is already running.
group-onsemi 0:098463de4c5d 86 */
group-onsemi 0:098463de4c5d 87 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
group-onsemi 0:098463de4c5d 88 // Set the clock divider
group-onsemi 0:098463de4c5d 89 MXC_RTCTMR->prescale = PRESCALE_VAL;
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 // Enable the overflow interrupt
group-onsemi 0:098463de4c5d 92 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 // Restart the timer from 0
group-onsemi 0:098463de4c5d 95 MXC_RTCTMR->timer = 0;
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 // Enable the RTC
group-onsemi 0:098463de4c5d 98 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
group-onsemi 0:098463de4c5d 99 }
group-onsemi 0:098463de4c5d 100 }
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 //******************************************************************************
group-onsemi 0:098463de4c5d 103 void lp_ticker_init(void)
group-onsemi 0:098463de4c5d 104 {
group-onsemi 0:098463de4c5d 105 rtc_init();
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 //******************************************************************************
group-onsemi 0:098463de4c5d 109 void rtc_free(void)
group-onsemi 0:098463de4c5d 110 {
group-onsemi 0:098463de4c5d 111 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
group-onsemi 0:098463de4c5d 112 // Clear and disable RTC
group-onsemi 0:098463de4c5d 113 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
group-onsemi 0:098463de4c5d 114 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 // Wait for pending transactions
group-onsemi 0:098463de4c5d 117 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
group-onsemi 0:098463de4c5d 118 }
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 // Disable the clock to the RTC
group-onsemi 0:098463de4c5d 121 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 // Disable the clock to the synchronizer
group-onsemi 0:098463de4c5d 124 MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED;
group-onsemi 0:098463de4c5d 125 }
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 //******************************************************************************
group-onsemi 0:098463de4c5d 128 int rtc_isenabled(void)
group-onsemi 0:098463de4c5d 129 {
group-onsemi 0:098463de4c5d 130 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133 //******************************************************************************
group-onsemi 0:098463de4c5d 134 time_t rtc_read(void)
group-onsemi 0:098463de4c5d 135 {
group-onsemi 0:098463de4c5d 136 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
group-onsemi 0:098463de4c5d 137 uint32_t ovf1, ovf2;
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 // Ensure coherency between overflow_cnt and timer
group-onsemi 0:098463de4c5d 140 do {
group-onsemi 0:098463de4c5d 141 ovf_cnt_1 = overflow_cnt;
group-onsemi 0:098463de4c5d 142 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 143 timer_cnt = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 144 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 145 ovf_cnt_2 = overflow_cnt;
group-onsemi 0:098463de4c5d 146 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 // Account for an unserviced interrupt
group-onsemi 0:098463de4c5d 149 if (ovf1) {
group-onsemi 0:098463de4c5d 150 ovf_cnt_1++;
group-onsemi 0:098463de4c5d 151 }
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
group-onsemi 0:098463de4c5d 154 }
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 //******************************************************************************
group-onsemi 0:098463de4c5d 157 static uint64_t rtc_read64(void)
group-onsemi 0:098463de4c5d 158 {
group-onsemi 0:098463de4c5d 159 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
group-onsemi 0:098463de4c5d 160 uint32_t ovf1, ovf2;
group-onsemi 0:098463de4c5d 161 uint64_t current_us;
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 // Ensure coherency between overflow_cnt and timer
group-onsemi 0:098463de4c5d 164 do {
group-onsemi 0:098463de4c5d 165 ovf_cnt_1 = overflow_cnt;
group-onsemi 0:098463de4c5d 166 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 167 timer_cnt = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 168 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
group-onsemi 0:098463de4c5d 169 ovf_cnt_2 = overflow_cnt;
group-onsemi 0:098463de4c5d 170 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 // Account for an unserviced interrupt
group-onsemi 0:098463de4c5d 173 if (ovf1) {
group-onsemi 0:098463de4c5d 174 ovf_cnt_1++;
group-onsemi 0:098463de4c5d 175 }
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 return current_us;
group-onsemi 0:098463de4c5d 180 }
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 //******************************************************************************
group-onsemi 0:098463de4c5d 183 void rtc_write(time_t t)
group-onsemi 0:098463de4c5d 184 {
group-onsemi 0:098463de4c5d 185 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
group-onsemi 0:098463de4c5d 186 MXC_RTCTMR->timer = t << SHIFT_AMT;
group-onsemi 0:098463de4c5d 187 overflow_cnt = t >> (32 - SHIFT_AMT);
group-onsemi 0:098463de4c5d 188 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
group-onsemi 0:098463de4c5d 189 }
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 //******************************************************************************
group-onsemi 0:098463de4c5d 192 void lp_ticker_set_interrupt(timestamp_t timestamp)
group-onsemi 0:098463de4c5d 193 {
group-onsemi 0:098463de4c5d 194 uint32_t comp_value;
group-onsemi 0:098463de4c5d 195 uint64_t curr_ts64;
group-onsemi 0:098463de4c5d 196 uint64_t ts64;
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 // Note: interrupts are disabled before this function is called.
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200 // Disable the alarm while it is prepared
group-onsemi 0:098463de4c5d 201 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 curr_ts64 = rtc_read64();
group-onsemi 0:098463de4c5d 204 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 // If this event is older than a recent window, it must be in the future
group-onsemi 0:098463de4c5d 207 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
group-onsemi 0:098463de4c5d 208 ts64 += 0x100000000ULL;
group-onsemi 0:098463de4c5d 209 }
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 uint32_t timer = MXC_RTCTMR->timer;
group-onsemi 0:098463de4c5d 212 if (ts64 <= curr_ts64) {
group-onsemi 0:098463de4c5d 213 // This event has already occurred. Set the alarm to expire immediately.
group-onsemi 0:098463de4c5d 214 comp_value = timer + 1;
group-onsemi 0:098463de4c5d 215 } else {
group-onsemi 0:098463de4c5d 216 comp_value = (ts64 << SHIFT_AMT) / 1000000;
group-onsemi 0:098463de4c5d 217 }
group-onsemi 0:098463de4c5d 218
group-onsemi 0:098463de4c5d 219 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
group-onsemi 0:098463de4c5d 220 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
group-onsemi 0:098463de4c5d 221 comp_value = timer + 2;
group-onsemi 0:098463de4c5d 222 }
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 MXC_RTCTMR->comp[0] = comp_value;
group-onsemi 0:098463de4c5d 225 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0; // clear interrupt
group-onsemi 0:098463de4c5d 226 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 // Enable wakeup from RTC
group-onsemi 0:098463de4c5d 229 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 //******************************************************************************
group-onsemi 0:098463de4c5d 233 inline void lp_ticker_disable_interrupt(void)
group-onsemi 0:098463de4c5d 234 {
group-onsemi 0:098463de4c5d 235 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
group-onsemi 0:098463de4c5d 236 }
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 //******************************************************************************
group-onsemi 0:098463de4c5d 239 inline void lp_ticker_clear_interrupt(void)
group-onsemi 0:098463de4c5d 240 {
group-onsemi 0:098463de4c5d 241 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
group-onsemi 0:098463de4c5d 242 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
group-onsemi 0:098463de4c5d 243 }
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 //******************************************************************************
group-onsemi 0:098463de4c5d 246 inline uint32_t lp_ticker_read(void)
group-onsemi 0:098463de4c5d 247 {
group-onsemi 0:098463de4c5d 248 return rtc_read64();
group-onsemi 0:098463de4c5d 249 }