ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Freescale/TARGET_KLXX/sleep.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "sleep_api.h"
group-onsemi 0:098463de4c5d 17 #include "cmsis.h"
group-onsemi 0:098463de4c5d 18 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 //Normal wait mode
group-onsemi 0:098463de4c5d 21 void sleep(void)
group-onsemi 0:098463de4c5d 22 {
group-onsemi 0:098463de4c5d 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 //Normal sleep mode for ARM core:
group-onsemi 0:098463de4c5d 26 SCB->SCR = 0;
group-onsemi 0:098463de4c5d 27 __WFI();
group-onsemi 0:098463de4c5d 28 }
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 //Very low-power stop mode
group-onsemi 0:098463de4c5d 31 void deepsleep(void)
group-onsemi 0:098463de4c5d 32 {
group-onsemi 0:098463de4c5d 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
group-onsemi 0:098463de4c5d 34 uint8_t ADC_HSC = 0;
group-onsemi 0:098463de4c5d 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
group-onsemi 0:098463de4c5d 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
group-onsemi 0:098463de4c5d 37 ADC_HSC = 1;
group-onsemi 0:098463de4c5d 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
group-onsemi 0:098463de4c5d 39 }
group-onsemi 0:098463de4c5d 40 }
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #if ! defined(TARGET_KL43Z)
group-onsemi 0:098463de4c5d 43 //Check if PLL/FLL is enabled:
group-onsemi 0:098463de4c5d 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
group-onsemi 0:098463de4c5d 45 #endif
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
group-onsemi 0:098463de4c5d 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 //Deep sleep for ARM core:
group-onsemi 0:098463de4c5d 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 __WFI();
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 #if ! defined(TARGET_KL43Z)
group-onsemi 0:098463de4c5d 56 //Switch back to PLL as clock source if needed
group-onsemi 0:098463de4c5d 57 //The interrupt that woke up the device will run at reduced speed
group-onsemi 0:098463de4c5d 58 if (PLL_FLL_en) {
group-onsemi 0:098463de4c5d 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
group-onsemi 0:098463de4c5d 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
group-onsemi 0:098463de4c5d 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
group-onsemi 0:098463de4c5d 62 #endif
group-onsemi 0:098463de4c5d 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65 #endif
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 if (ADC_HSC) {
group-onsemi 0:098463de4c5d 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
group-onsemi 0:098463de4c5d 69 }
group-onsemi 0:098463de4c5d 70 }