ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #if DEVICE_RTC
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #include "rtc_api.h"
group-onsemi 0:098463de4c5d 20 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 21 #include "clk_freqs.h"
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 static void init(void) {
group-onsemi 0:098463de4c5d 24 // enable RTC clock
group-onsemi 0:098463de4c5d 25 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 // select RTC clock source
group-onsemi 0:098463de4c5d 28 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 // Enable external crystal source if clock source is 32KHz
group-onsemi 0:098463de4c5d 31 if (extosc_frequency()==32768) {
group-onsemi 0:098463de4c5d 32 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
group-onsemi 0:098463de4c5d 33 }
group-onsemi 0:098463de4c5d 34 else{
group-onsemi 0:098463de4c5d 35 // If main clock is NOT 32KHz crystal, use external 32KHz clock source defined in PeripheralPins.c
group-onsemi 0:098463de4c5d 36 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral);
group-onsemi 0:098463de4c5d 37 pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC)
group-onsemi 0:098463de4c5d 38 }
group-onsemi 0:098463de4c5d 39 }
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 void rtc_init(void) {
group-onsemi 0:098463de4c5d 42 init();
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 // Configure the TSR. default value: 1
group-onsemi 0:098463de4c5d 45 RTC->TSR = 1;
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 // Configure Time Compensation Register to calibrate RTC accuracy
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 // dissable LRL lock
group-onsemi 0:098463de4c5d 50 RTC->LR &= ~RTC_LR_LRL_MASK;
group-onsemi 0:098463de4c5d 51 // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction
group-onsemi 0:098463de4c5d 52 RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0);
group-onsemi 0:098463de4c5d 53 /*
group-onsemi 0:098463de4c5d 54 RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256.
group-onsemi 0:098463de4c5d 55 0x05 will apply the compensation once every 4 seconds.
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 RTC_TCR_TCR(x) sets the Register Overflow
group-onsemi 0:098463de4c5d 58 0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128)
group-onsemi 0:098463de4c5d 59 ... ... RTC runs slower
group-onsemi 0:098463de4c5d 60 0xFF Time Prescaler Register overflows every 32769 clock cycles.
group-onsemi 0:098463de4c5d 61 0x00 Time Prescaler Register overflows every 32768 clock cycles, Default.
group-onsemi 0:098463de4c5d 62 0x01 Time Prescaler Register overflows every 32767 clock cycles.
group-onsemi 0:098463de4c5d 63 ... ... RTC runs faster
group-onsemi 0:098463de4c5d 64 0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128)
group-onsemi 0:098463de4c5d 65 */
group-onsemi 0:098463de4c5d 66 // enable TCL lock
group-onsemi 0:098463de4c5d 67 RTC->LR |= RTC_LR_TCL_MASK;
group-onsemi 0:098463de4c5d 68 // enable LRL lock
group-onsemi 0:098463de4c5d 69 RTC->LR |= RTC_LR_LRL_MASK;
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 // enable counter
group-onsemi 0:098463de4c5d 72 RTC->SR |= RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 73 }
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 void rtc_free(void) {
group-onsemi 0:098463de4c5d 76 // [TODO]
group-onsemi 0:098463de4c5d 77 }
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79 /*
group-onsemi 0:098463de4c5d 80 * Little check routine to see if the RTC has been enabled
group-onsemi 0:098463de4c5d 81 * 0 = Disabled, 1 = Enabled
group-onsemi 0:098463de4c5d 82 */
group-onsemi 0:098463de4c5d 83 int rtc_isenabled(void) {
group-onsemi 0:098463de4c5d 84 // even if the RTC module is enabled,
group-onsemi 0:098463de4c5d 85 // as we use RTC_CLKIN and an external clock,
group-onsemi 0:098463de4c5d 86 // we need to reconfigure the pins. That is why we
group-onsemi 0:098463de4c5d 87 // call init() if the rtc is enabled
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 // if RTC not enabled return 0
group-onsemi 0:098463de4c5d 90 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
group-onsemi 0:098463de4c5d 91 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
group-onsemi 0:098463de4c5d 92 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
group-onsemi 0:098463de4c5d 93 return 0;
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 init();
group-onsemi 0:098463de4c5d 96 return 1;
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 time_t rtc_read(void) {
group-onsemi 0:098463de4c5d 100 return RTC->TSR;
group-onsemi 0:098463de4c5d 101 }
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 void rtc_write(time_t t) {
group-onsemi 0:098463de4c5d 104 // disable counter
group-onsemi 0:098463de4c5d 105 RTC->SR &= ~RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 // we do not write 0 into TSR
group-onsemi 0:098463de4c5d 108 // to avoid invalid time
group-onsemi 0:098463de4c5d 109 if (t == 0)
group-onsemi 0:098463de4c5d 110 t = 1;
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 // write seconds
group-onsemi 0:098463de4c5d 113 RTC->TSR = t;
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 // re-enable counter
group-onsemi 0:098463de4c5d 116 RTC->SR |= RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 117 }
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 #endif