ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #ifndef MBED_CLK_FREQS_H
group-onsemi 0:098463de4c5d 17 #define MBED_CLK_FREQS_H
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 20 extern "C" {
group-onsemi 0:098463de4c5d 21 #endif
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 //Get the peripheral bus clock frequency
group-onsemi 0:098463de4c5d 26 static inline uint32_t bus_frequency(void) {
group-onsemi 0:098463de4c5d 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
group-onsemi 0:098463de4c5d 28 }
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 #if defined(TARGET_KL43Z)
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 static inline uint32_t extosc_frequency(void) {
group-onsemi 0:098463de4c5d 33 return CPU_XTAL_CLK_HZ;
group-onsemi 0:098463de4c5d 34 }
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 static inline uint32_t fastirc_frequency(void) {
group-onsemi 0:098463de4c5d 37 return CPU_INT_FAST_CLK_HZ;
group-onsemi 0:098463de4c5d 38 }
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 static inline uint32_t mcgirc_frequency(void) {
group-onsemi 0:098463de4c5d 41 uint32_t mcgirc_clock = 0;
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
group-onsemi 0:098463de4c5d 44 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
group-onsemi 0:098463de4c5d 45 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
group-onsemi 0:098463de4c5d 46 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
group-onsemi 0:098463de4c5d 47 }
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 return mcgirc_clock;
group-onsemi 0:098463de4c5d 50 }
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 #else
group-onsemi 0:098463de4c5d 53
group-onsemi 0:098463de4c5d 54 //Get external oscillator (crystal) frequency
group-onsemi 0:098463de4c5d 55 static uint32_t extosc_frequency(void) {
group-onsemi 0:098463de4c5d 56 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
group-onsemi 0:098463de4c5d 59 return MCGClock;
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 uint32_t divider, multiplier;
group-onsemi 0:098463de4c5d 62 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
group-onsemi 0:098463de4c5d 63 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
group-onsemi 0:098463de4c5d 64 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
group-onsemi 0:098463de4c5d 65 #endif
group-onsemi 0:098463de4c5d 66 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
group-onsemi 0:098463de4c5d 67 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
group-onsemi 0:098463de4c5d 68 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
group-onsemi 0:098463de4c5d 69 divider <<= 5u;
group-onsemi 0:098463de4c5d 70 /* Select correct multiplier to calculate the MCG output clock */
group-onsemi 0:098463de4c5d 71 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
group-onsemi 0:098463de4c5d 72 case 0x0u:
group-onsemi 0:098463de4c5d 73 multiplier = 640u;
group-onsemi 0:098463de4c5d 74 break;
group-onsemi 0:098463de4c5d 75 case 0x20u:
group-onsemi 0:098463de4c5d 76 multiplier = 1280u;
group-onsemi 0:098463de4c5d 77 break;
group-onsemi 0:098463de4c5d 78 case 0x40u:
group-onsemi 0:098463de4c5d 79 multiplier = 1920u;
group-onsemi 0:098463de4c5d 80 break;
group-onsemi 0:098463de4c5d 81 case 0x60u:
group-onsemi 0:098463de4c5d 82 multiplier = 2560u;
group-onsemi 0:098463de4c5d 83 break;
group-onsemi 0:098463de4c5d 84 case 0x80u:
group-onsemi 0:098463de4c5d 85 multiplier = 732u;
group-onsemi 0:098463de4c5d 86 break;
group-onsemi 0:098463de4c5d 87 case 0xA0u:
group-onsemi 0:098463de4c5d 88 multiplier = 1464u;
group-onsemi 0:098463de4c5d 89 break;
group-onsemi 0:098463de4c5d 90 case 0xC0u:
group-onsemi 0:098463de4c5d 91 multiplier = 2197u;
group-onsemi 0:098463de4c5d 92 break;
group-onsemi 0:098463de4c5d 93 case 0xE0u:
group-onsemi 0:098463de4c5d 94 default:
group-onsemi 0:098463de4c5d 95 multiplier = 2929u;
group-onsemi 0:098463de4c5d 96 break;
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 return MCGClock * divider / multiplier;
group-onsemi 0:098463de4c5d 100 }
group-onsemi 0:098463de4c5d 101 #ifdef MCG_C5_PLLCLKEN0_MASK
group-onsemi 0:098463de4c5d 102 } else { //PLL is selected
group-onsemi 0:098463de4c5d 103 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
group-onsemi 0:098463de4c5d 104 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
group-onsemi 0:098463de4c5d 105 return MCGClock * divider / multiplier;
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107 }
group-onsemi 0:098463de4c5d 108 #endif
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 //In all other cases either there is no crystal or we cannot determine it
group-onsemi 0:098463de4c5d 111 //For example when the FLL is running on the internal reference, and there is also an
group-onsemi 0:098463de4c5d 112 //external crystal. However these are unlikely situations
group-onsemi 0:098463de4c5d 113 return 0;
group-onsemi 0:098463de4c5d 114 }
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
group-onsemi 0:098463de4c5d 117 static uint32_t mcgpllfll_frequency(void) {
group-onsemi 0:098463de4c5d 118 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
group-onsemi 0:098463de4c5d 119 return 0;
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
group-onsemi 0:098463de4c5d 122 #ifdef MCG_C5_PLLCLKEN0_MASK
group-onsemi 0:098463de4c5d 123 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
group-onsemi 0:098463de4c5d 124 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
group-onsemi 0:098463de4c5d 125 #endif
group-onsemi 0:098463de4c5d 126 return MCGClock;
group-onsemi 0:098463de4c5d 127 #ifdef MCG_C5_PLLCLKEN0_MASK
group-onsemi 0:098463de4c5d 128 } else { //PLL is selected
group-onsemi 0:098463de4c5d 129 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
group-onsemi 0:098463de4c5d 130 return (MCGClock >> 1);
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132 #endif
group-onsemi 0:098463de4c5d 133
group-onsemi 0:098463de4c5d 134 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
group-onsemi 0:098463de4c5d 135 //for the peripherals, this is however an unlikely setup
group-onsemi 0:098463de4c5d 136 }
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 #endif
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 141 }
group-onsemi 0:098463de4c5d 142 #endif
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 #endif