ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_cmFunc.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file core_cmFunc.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-M Core Function Access Header File
group-onsemi 0:098463de4c5d 4 * @version V4.10
group-onsemi 0:098463de4c5d 5 * @date 18. March 2015
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @note
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 ******************************************************************************/
group-onsemi 0:098463de4c5d 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 All rights reserved.
group-onsemi 0:098463de4c5d 13 Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 14 modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 - Redistributions of source code must retain the above copyright
group-onsemi 0:098463de4c5d 16 notice, this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 - Redistributions in binary form must reproduce the above copyright
group-onsemi 0:098463de4c5d 18 notice, this list of conditions and the following disclaimer in the
group-onsemi 0:098463de4c5d 19 documentation and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 - Neither the name of ARM nor the names of its contributors may be used
group-onsemi 0:098463de4c5d 21 to endorse or promote products derived from this software without
group-onsemi 0:098463de4c5d 22 specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi 0:098463de4c5d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi 0:098463de4c5d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi 0:098463de4c5d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi 0:098463de4c5d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi 0:098463de4c5d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi 0:098463de4c5d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi 0:098463de4c5d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi 0:098463de4c5d 34 POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 35 ---------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #ifndef __CORE_CMFUNC_H
group-onsemi 0:098463de4c5d 39 #define __CORE_CMFUNC_H
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 /* ########################### Core Function Access ########################### */
group-onsemi 0:098463de4c5d 43 /** \ingroup CMSIS_Core_FunctionInterface
group-onsemi 0:098463de4c5d 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
group-onsemi 0:098463de4c5d 45 @{
group-onsemi 0:098463de4c5d 46 */
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
group-onsemi 0:098463de4c5d 49 /* ARM armcc specific functions */
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 #if (__ARMCC_VERSION < 400677)
group-onsemi 0:098463de4c5d 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
group-onsemi 0:098463de4c5d 53 #endif
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 /* intrinsic void __enable_irq(); */
group-onsemi 0:098463de4c5d 56 /* intrinsic void __disable_irq(); */
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 /** \brief Get Control Register
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 This function returns the content of the Control Register.
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 \return Control Register value
group-onsemi 0:098463de4c5d 63 */
group-onsemi 0:098463de4c5d 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
group-onsemi 0:098463de4c5d 65 {
group-onsemi 0:098463de4c5d 66 register uint32_t __regControl __ASM("control");
group-onsemi 0:098463de4c5d 67 return(__regControl);
group-onsemi 0:098463de4c5d 68 }
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 /** \brief Set Control Register
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 This function writes the given value to the Control Register.
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 \param [in] control Control Register value to set
group-onsemi 0:098463de4c5d 76 */
group-onsemi 0:098463de4c5d 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
group-onsemi 0:098463de4c5d 78 {
group-onsemi 0:098463de4c5d 79 register uint32_t __regControl __ASM("control");
group-onsemi 0:098463de4c5d 80 __regControl = control;
group-onsemi 0:098463de4c5d 81 }
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 /** \brief Get IPSR Register
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 This function returns the content of the IPSR Register.
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 \return IPSR Register value
group-onsemi 0:098463de4c5d 89 */
group-onsemi 0:098463de4c5d 90 __STATIC_INLINE uint32_t __get_IPSR(void)
group-onsemi 0:098463de4c5d 91 {
group-onsemi 0:098463de4c5d 92 register uint32_t __regIPSR __ASM("ipsr");
group-onsemi 0:098463de4c5d 93 return(__regIPSR);
group-onsemi 0:098463de4c5d 94 }
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 /** \brief Get APSR Register
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 This function returns the content of the APSR Register.
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 \return APSR Register value
group-onsemi 0:098463de4c5d 102 */
group-onsemi 0:098463de4c5d 103 __STATIC_INLINE uint32_t __get_APSR(void)
group-onsemi 0:098463de4c5d 104 {
group-onsemi 0:098463de4c5d 105 register uint32_t __regAPSR __ASM("apsr");
group-onsemi 0:098463de4c5d 106 return(__regAPSR);
group-onsemi 0:098463de4c5d 107 }
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 /** \brief Get xPSR Register
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 This function returns the content of the xPSR Register.
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 \return xPSR Register value
group-onsemi 0:098463de4c5d 115 */
group-onsemi 0:098463de4c5d 116 __STATIC_INLINE uint32_t __get_xPSR(void)
group-onsemi 0:098463de4c5d 117 {
group-onsemi 0:098463de4c5d 118 register uint32_t __regXPSR __ASM("xpsr");
group-onsemi 0:098463de4c5d 119 return(__regXPSR);
group-onsemi 0:098463de4c5d 120 }
group-onsemi 0:098463de4c5d 121
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 /** \brief Get Process Stack Pointer
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 This function returns the current value of the Process Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 \return PSP Register value
group-onsemi 0:098463de4c5d 128 */
group-onsemi 0:098463de4c5d 129 __STATIC_INLINE uint32_t __get_PSP(void)
group-onsemi 0:098463de4c5d 130 {
group-onsemi 0:098463de4c5d 131 register uint32_t __regProcessStackPointer __ASM("psp");
group-onsemi 0:098463de4c5d 132 return(__regProcessStackPointer);
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 /** \brief Set Process Stack Pointer
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 This function assigns the given value to the Process Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 \param [in] topOfProcStack Process Stack Pointer value to set
group-onsemi 0:098463de4c5d 141 */
group-onsemi 0:098463de4c5d 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
group-onsemi 0:098463de4c5d 143 {
group-onsemi 0:098463de4c5d 144 register uint32_t __regProcessStackPointer __ASM("psp");
group-onsemi 0:098463de4c5d 145 __regProcessStackPointer = topOfProcStack;
group-onsemi 0:098463de4c5d 146 }
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 /** \brief Get Main Stack Pointer
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 This function returns the current value of the Main Stack Pointer (MSP).
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 \return MSP Register value
group-onsemi 0:098463de4c5d 154 */
group-onsemi 0:098463de4c5d 155 __STATIC_INLINE uint32_t __get_MSP(void)
group-onsemi 0:098463de4c5d 156 {
group-onsemi 0:098463de4c5d 157 register uint32_t __regMainStackPointer __ASM("msp");
group-onsemi 0:098463de4c5d 158 return(__regMainStackPointer);
group-onsemi 0:098463de4c5d 159 }
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 /** \brief Set Main Stack Pointer
group-onsemi 0:098463de4c5d 163
group-onsemi 0:098463de4c5d 164 This function assigns the given value to the Main Stack Pointer (MSP).
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 \param [in] topOfMainStack Main Stack Pointer value to set
group-onsemi 0:098463de4c5d 167 */
group-onsemi 0:098463de4c5d 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
group-onsemi 0:098463de4c5d 169 {
group-onsemi 0:098463de4c5d 170 register uint32_t __regMainStackPointer __ASM("msp");
group-onsemi 0:098463de4c5d 171 __regMainStackPointer = topOfMainStack;
group-onsemi 0:098463de4c5d 172 }
group-onsemi 0:098463de4c5d 173
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 /** \brief Get Priority Mask
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 \return Priority Mask value
group-onsemi 0:098463de4c5d 180 */
group-onsemi 0:098463de4c5d 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
group-onsemi 0:098463de4c5d 182 {
group-onsemi 0:098463de4c5d 183 register uint32_t __regPriMask __ASM("primask");
group-onsemi 0:098463de4c5d 184 return(__regPriMask);
group-onsemi 0:098463de4c5d 185 }
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 /** \brief Set Priority Mask
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190 This function assigns the given value to the Priority Mask Register.
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 \param [in] priMask Priority Mask
group-onsemi 0:098463de4c5d 193 */
group-onsemi 0:098463de4c5d 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
group-onsemi 0:098463de4c5d 195 {
group-onsemi 0:098463de4c5d 196 register uint32_t __regPriMask __ASM("primask");
group-onsemi 0:098463de4c5d 197 __regPriMask = (priMask);
group-onsemi 0:098463de4c5d 198 }
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200
group-onsemi 0:098463de4c5d 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 /** \brief Enable FIQ
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 206 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 207 */
group-onsemi 0:098463de4c5d 208 #define __enable_fault_irq __enable_fiq
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 /** \brief Disable FIQ
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 214 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 215 */
group-onsemi 0:098463de4c5d 216 #define __disable_fault_irq __disable_fiq
group-onsemi 0:098463de4c5d 217
group-onsemi 0:098463de4c5d 218
group-onsemi 0:098463de4c5d 219 /** \brief Get Base Priority
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221 This function returns the current value of the Base Priority register.
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 \return Base Priority register value
group-onsemi 0:098463de4c5d 224 */
group-onsemi 0:098463de4c5d 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
group-onsemi 0:098463de4c5d 226 {
group-onsemi 0:098463de4c5d 227 register uint32_t __regBasePri __ASM("basepri");
group-onsemi 0:098463de4c5d 228 return(__regBasePri);
group-onsemi 0:098463de4c5d 229 }
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 /** \brief Set Base Priority
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 This function assigns the given value to the Base Priority register.
group-onsemi 0:098463de4c5d 235
group-onsemi 0:098463de4c5d 236 \param [in] basePri Base Priority value to set
group-onsemi 0:098463de4c5d 237 */
group-onsemi 0:098463de4c5d 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
group-onsemi 0:098463de4c5d 239 {
group-onsemi 0:098463de4c5d 240 register uint32_t __regBasePri __ASM("basepri");
group-onsemi 0:098463de4c5d 241 __regBasePri = (basePri & 0xff);
group-onsemi 0:098463de4c5d 242 }
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 /** \brief Set Base Priority with condition
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
group-onsemi 0:098463de4c5d 248 or the new value increases the BASEPRI priority level.
group-onsemi 0:098463de4c5d 249
group-onsemi 0:098463de4c5d 250 \param [in] basePri Base Priority value to set
group-onsemi 0:098463de4c5d 251 */
group-onsemi 0:098463de4c5d 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
group-onsemi 0:098463de4c5d 253 {
group-onsemi 0:098463de4c5d 254 register uint32_t __regBasePriMax __ASM("basepri_max");
group-onsemi 0:098463de4c5d 255 __regBasePriMax = (basePri & 0xff);
group-onsemi 0:098463de4c5d 256 }
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258
group-onsemi 0:098463de4c5d 259 /** \brief Get Fault Mask
group-onsemi 0:098463de4c5d 260
group-onsemi 0:098463de4c5d 261 This function returns the current value of the Fault Mask register.
group-onsemi 0:098463de4c5d 262
group-onsemi 0:098463de4c5d 263 \return Fault Mask register value
group-onsemi 0:098463de4c5d 264 */
group-onsemi 0:098463de4c5d 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
group-onsemi 0:098463de4c5d 266 {
group-onsemi 0:098463de4c5d 267 register uint32_t __regFaultMask __ASM("faultmask");
group-onsemi 0:098463de4c5d 268 return(__regFaultMask);
group-onsemi 0:098463de4c5d 269 }
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271
group-onsemi 0:098463de4c5d 272 /** \brief Set Fault Mask
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 This function assigns the given value to the Fault Mask register.
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 \param [in] faultMask Fault Mask value to set
group-onsemi 0:098463de4c5d 277 */
group-onsemi 0:098463de4c5d 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
group-onsemi 0:098463de4c5d 279 {
group-onsemi 0:098463de4c5d 280 register uint32_t __regFaultMask __ASM("faultmask");
group-onsemi 0:098463de4c5d 281 __regFaultMask = (faultMask & (uint32_t)1);
group-onsemi 0:098463de4c5d 282 }
group-onsemi 0:098463de4c5d 283
group-onsemi 0:098463de4c5d 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
group-onsemi 0:098463de4c5d 285
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
group-onsemi 0:098463de4c5d 288
group-onsemi 0:098463de4c5d 289 /** \brief Get FPSCR
group-onsemi 0:098463de4c5d 290
group-onsemi 0:098463de4c5d 291 This function returns the current value of the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 292
group-onsemi 0:098463de4c5d 293 \return Floating Point Status/Control register value
group-onsemi 0:098463de4c5d 294 */
group-onsemi 0:098463de4c5d 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
group-onsemi 0:098463de4c5d 296 {
group-onsemi 0:098463de4c5d 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 298 register uint32_t __regfpscr __ASM("fpscr");
group-onsemi 0:098463de4c5d 299 return(__regfpscr);
group-onsemi 0:098463de4c5d 300 #else
group-onsemi 0:098463de4c5d 301 return(0);
group-onsemi 0:098463de4c5d 302 #endif
group-onsemi 0:098463de4c5d 303 }
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 /** \brief Set FPSCR
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 This function assigns the given value to the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 309
group-onsemi 0:098463de4c5d 310 \param [in] fpscr Floating Point Status/Control value to set
group-onsemi 0:098463de4c5d 311 */
group-onsemi 0:098463de4c5d 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
group-onsemi 0:098463de4c5d 313 {
group-onsemi 0:098463de4c5d 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 315 register uint32_t __regfpscr __ASM("fpscr");
group-onsemi 0:098463de4c5d 316 __regfpscr = (fpscr);
group-onsemi 0:098463de4c5d 317 #endif
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
group-onsemi 0:098463de4c5d 321
group-onsemi 0:098463de4c5d 322
group-onsemi 0:098463de4c5d 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
group-onsemi 0:098463de4c5d 324 /* GNU gcc specific functions */
group-onsemi 0:098463de4c5d 325
group-onsemi 0:098463de4c5d 326 /** \brief Enable IRQ Interrupts
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
group-onsemi 0:098463de4c5d 329 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 330 */
group-onsemi 0:098463de4c5d 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
group-onsemi 0:098463de4c5d 332 {
group-onsemi 0:098463de4c5d 333 __ASM volatile ("cpsie i" : : : "memory");
group-onsemi 0:098463de4c5d 334 }
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336
group-onsemi 0:098463de4c5d 337 /** \brief Disable IRQ Interrupts
group-onsemi 0:098463de4c5d 338
group-onsemi 0:098463de4c5d 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
group-onsemi 0:098463de4c5d 340 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 341 */
group-onsemi 0:098463de4c5d 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
group-onsemi 0:098463de4c5d 343 {
group-onsemi 0:098463de4c5d 344 __ASM volatile ("cpsid i" : : : "memory");
group-onsemi 0:098463de4c5d 345 }
group-onsemi 0:098463de4c5d 346
group-onsemi 0:098463de4c5d 347
group-onsemi 0:098463de4c5d 348 /** \brief Get Control Register
group-onsemi 0:098463de4c5d 349
group-onsemi 0:098463de4c5d 350 This function returns the content of the Control Register.
group-onsemi 0:098463de4c5d 351
group-onsemi 0:098463de4c5d 352 \return Control Register value
group-onsemi 0:098463de4c5d 353 */
group-onsemi 0:098463de4c5d 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
group-onsemi 0:098463de4c5d 355 {
group-onsemi 0:098463de4c5d 356 uint32_t result;
group-onsemi 0:098463de4c5d 357
group-onsemi 0:098463de4c5d 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
group-onsemi 0:098463de4c5d 359 return(result);
group-onsemi 0:098463de4c5d 360 }
group-onsemi 0:098463de4c5d 361
group-onsemi 0:098463de4c5d 362
group-onsemi 0:098463de4c5d 363 /** \brief Set Control Register
group-onsemi 0:098463de4c5d 364
group-onsemi 0:098463de4c5d 365 This function writes the given value to the Control Register.
group-onsemi 0:098463de4c5d 366
group-onsemi 0:098463de4c5d 367 \param [in] control Control Register value to set
group-onsemi 0:098463de4c5d 368 */
group-onsemi 0:098463de4c5d 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
group-onsemi 0:098463de4c5d 370 {
group-onsemi 0:098463de4c5d 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
group-onsemi 0:098463de4c5d 372 }
group-onsemi 0:098463de4c5d 373
group-onsemi 0:098463de4c5d 374
group-onsemi 0:098463de4c5d 375 /** \brief Get IPSR Register
group-onsemi 0:098463de4c5d 376
group-onsemi 0:098463de4c5d 377 This function returns the content of the IPSR Register.
group-onsemi 0:098463de4c5d 378
group-onsemi 0:098463de4c5d 379 \return IPSR Register value
group-onsemi 0:098463de4c5d 380 */
group-onsemi 0:098463de4c5d 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
group-onsemi 0:098463de4c5d 382 {
group-onsemi 0:098463de4c5d 383 uint32_t result;
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
group-onsemi 0:098463de4c5d 386 return(result);
group-onsemi 0:098463de4c5d 387 }
group-onsemi 0:098463de4c5d 388
group-onsemi 0:098463de4c5d 389
group-onsemi 0:098463de4c5d 390 /** \brief Get APSR Register
group-onsemi 0:098463de4c5d 391
group-onsemi 0:098463de4c5d 392 This function returns the content of the APSR Register.
group-onsemi 0:098463de4c5d 393
group-onsemi 0:098463de4c5d 394 \return APSR Register value
group-onsemi 0:098463de4c5d 395 */
group-onsemi 0:098463de4c5d 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
group-onsemi 0:098463de4c5d 397 {
group-onsemi 0:098463de4c5d 398 uint32_t result;
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
group-onsemi 0:098463de4c5d 401 return(result);
group-onsemi 0:098463de4c5d 402 }
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404
group-onsemi 0:098463de4c5d 405 /** \brief Get xPSR Register
group-onsemi 0:098463de4c5d 406
group-onsemi 0:098463de4c5d 407 This function returns the content of the xPSR Register.
group-onsemi 0:098463de4c5d 408
group-onsemi 0:098463de4c5d 409 \return xPSR Register value
group-onsemi 0:098463de4c5d 410 */
group-onsemi 0:098463de4c5d 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
group-onsemi 0:098463de4c5d 412 {
group-onsemi 0:098463de4c5d 413 uint32_t result;
group-onsemi 0:098463de4c5d 414
group-onsemi 0:098463de4c5d 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
group-onsemi 0:098463de4c5d 416 return(result);
group-onsemi 0:098463de4c5d 417 }
group-onsemi 0:098463de4c5d 418
group-onsemi 0:098463de4c5d 419
group-onsemi 0:098463de4c5d 420 /** \brief Get Process Stack Pointer
group-onsemi 0:098463de4c5d 421
group-onsemi 0:098463de4c5d 422 This function returns the current value of the Process Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 \return PSP Register value
group-onsemi 0:098463de4c5d 425 */
group-onsemi 0:098463de4c5d 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
group-onsemi 0:098463de4c5d 427 {
group-onsemi 0:098463de4c5d 428 register uint32_t result;
group-onsemi 0:098463de4c5d 429
group-onsemi 0:098463de4c5d 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
group-onsemi 0:098463de4c5d 431 return(result);
group-onsemi 0:098463de4c5d 432 }
group-onsemi 0:098463de4c5d 433
group-onsemi 0:098463de4c5d 434
group-onsemi 0:098463de4c5d 435 /** \brief Set Process Stack Pointer
group-onsemi 0:098463de4c5d 436
group-onsemi 0:098463de4c5d 437 This function assigns the given value to the Process Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 \param [in] topOfProcStack Process Stack Pointer value to set
group-onsemi 0:098463de4c5d 440 */
group-onsemi 0:098463de4c5d 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
group-onsemi 0:098463de4c5d 442 {
group-onsemi 0:098463de4c5d 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
group-onsemi 0:098463de4c5d 444 }
group-onsemi 0:098463de4c5d 445
group-onsemi 0:098463de4c5d 446
group-onsemi 0:098463de4c5d 447 /** \brief Get Main Stack Pointer
group-onsemi 0:098463de4c5d 448
group-onsemi 0:098463de4c5d 449 This function returns the current value of the Main Stack Pointer (MSP).
group-onsemi 0:098463de4c5d 450
group-onsemi 0:098463de4c5d 451 \return MSP Register value
group-onsemi 0:098463de4c5d 452 */
group-onsemi 0:098463de4c5d 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
group-onsemi 0:098463de4c5d 454 {
group-onsemi 0:098463de4c5d 455 register uint32_t result;
group-onsemi 0:098463de4c5d 456
group-onsemi 0:098463de4c5d 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
group-onsemi 0:098463de4c5d 458 return(result);
group-onsemi 0:098463de4c5d 459 }
group-onsemi 0:098463de4c5d 460
group-onsemi 0:098463de4c5d 461
group-onsemi 0:098463de4c5d 462 /** \brief Set Main Stack Pointer
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464 This function assigns the given value to the Main Stack Pointer (MSP).
group-onsemi 0:098463de4c5d 465
group-onsemi 0:098463de4c5d 466 \param [in] topOfMainStack Main Stack Pointer value to set
group-onsemi 0:098463de4c5d 467 */
group-onsemi 0:098463de4c5d 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
group-onsemi 0:098463de4c5d 469 {
group-onsemi 0:098463de4c5d 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
group-onsemi 0:098463de4c5d 471 }
group-onsemi 0:098463de4c5d 472
group-onsemi 0:098463de4c5d 473
group-onsemi 0:098463de4c5d 474 /** \brief Get Priority Mask
group-onsemi 0:098463de4c5d 475
group-onsemi 0:098463de4c5d 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 \return Priority Mask value
group-onsemi 0:098463de4c5d 479 */
group-onsemi 0:098463de4c5d 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
group-onsemi 0:098463de4c5d 481 {
group-onsemi 0:098463de4c5d 482 uint32_t result;
group-onsemi 0:098463de4c5d 483
group-onsemi 0:098463de4c5d 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
group-onsemi 0:098463de4c5d 485 return(result);
group-onsemi 0:098463de4c5d 486 }
group-onsemi 0:098463de4c5d 487
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 /** \brief Set Priority Mask
group-onsemi 0:098463de4c5d 490
group-onsemi 0:098463de4c5d 491 This function assigns the given value to the Priority Mask Register.
group-onsemi 0:098463de4c5d 492
group-onsemi 0:098463de4c5d 493 \param [in] priMask Priority Mask
group-onsemi 0:098463de4c5d 494 */
group-onsemi 0:098463de4c5d 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
group-onsemi 0:098463de4c5d 496 {
group-onsemi 0:098463de4c5d 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
group-onsemi 0:098463de4c5d 498 }
group-onsemi 0:098463de4c5d 499
group-onsemi 0:098463de4c5d 500
group-onsemi 0:098463de4c5d 501 #if (__CORTEX_M >= 0x03)
group-onsemi 0:098463de4c5d 502
group-onsemi 0:098463de4c5d 503 /** \brief Enable FIQ
group-onsemi 0:098463de4c5d 504
group-onsemi 0:098463de4c5d 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 506 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 507 */
group-onsemi 0:098463de4c5d 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
group-onsemi 0:098463de4c5d 509 {
group-onsemi 0:098463de4c5d 510 __ASM volatile ("cpsie f" : : : "memory");
group-onsemi 0:098463de4c5d 511 }
group-onsemi 0:098463de4c5d 512
group-onsemi 0:098463de4c5d 513
group-onsemi 0:098463de4c5d 514 /** \brief Disable FIQ
group-onsemi 0:098463de4c5d 515
group-onsemi 0:098463de4c5d 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 517 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 518 */
group-onsemi 0:098463de4c5d 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
group-onsemi 0:098463de4c5d 520 {
group-onsemi 0:098463de4c5d 521 __ASM volatile ("cpsid f" : : : "memory");
group-onsemi 0:098463de4c5d 522 }
group-onsemi 0:098463de4c5d 523
group-onsemi 0:098463de4c5d 524
group-onsemi 0:098463de4c5d 525 /** \brief Get Base Priority
group-onsemi 0:098463de4c5d 526
group-onsemi 0:098463de4c5d 527 This function returns the current value of the Base Priority register.
group-onsemi 0:098463de4c5d 528
group-onsemi 0:098463de4c5d 529 \return Base Priority register value
group-onsemi 0:098463de4c5d 530 */
group-onsemi 0:098463de4c5d 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
group-onsemi 0:098463de4c5d 532 {
group-onsemi 0:098463de4c5d 533 uint32_t result;
group-onsemi 0:098463de4c5d 534
group-onsemi 0:098463de4c5d 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
group-onsemi 0:098463de4c5d 536 return(result);
group-onsemi 0:098463de4c5d 537 }
group-onsemi 0:098463de4c5d 538
group-onsemi 0:098463de4c5d 539
group-onsemi 0:098463de4c5d 540 /** \brief Set Base Priority
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 This function assigns the given value to the Base Priority register.
group-onsemi 0:098463de4c5d 543
group-onsemi 0:098463de4c5d 544 \param [in] basePri Base Priority value to set
group-onsemi 0:098463de4c5d 545 */
group-onsemi 0:098463de4c5d 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
group-onsemi 0:098463de4c5d 547 {
group-onsemi 0:098463de4c5d 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
group-onsemi 0:098463de4c5d 549 }
group-onsemi 0:098463de4c5d 550
group-onsemi 0:098463de4c5d 551
group-onsemi 0:098463de4c5d 552 /** \brief Set Base Priority with condition
group-onsemi 0:098463de4c5d 553
group-onsemi 0:098463de4c5d 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
group-onsemi 0:098463de4c5d 555 or the new value increases the BASEPRI priority level.
group-onsemi 0:098463de4c5d 556
group-onsemi 0:098463de4c5d 557 \param [in] basePri Base Priority value to set
group-onsemi 0:098463de4c5d 558 */
group-onsemi 0:098463de4c5d 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
group-onsemi 0:098463de4c5d 560 {
group-onsemi 0:098463de4c5d 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
group-onsemi 0:098463de4c5d 562 }
group-onsemi 0:098463de4c5d 563
group-onsemi 0:098463de4c5d 564
group-onsemi 0:098463de4c5d 565 /** \brief Get Fault Mask
group-onsemi 0:098463de4c5d 566
group-onsemi 0:098463de4c5d 567 This function returns the current value of the Fault Mask register.
group-onsemi 0:098463de4c5d 568
group-onsemi 0:098463de4c5d 569 \return Fault Mask register value
group-onsemi 0:098463de4c5d 570 */
group-onsemi 0:098463de4c5d 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
group-onsemi 0:098463de4c5d 572 {
group-onsemi 0:098463de4c5d 573 uint32_t result;
group-onsemi 0:098463de4c5d 574
group-onsemi 0:098463de4c5d 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
group-onsemi 0:098463de4c5d 576 return(result);
group-onsemi 0:098463de4c5d 577 }
group-onsemi 0:098463de4c5d 578
group-onsemi 0:098463de4c5d 579
group-onsemi 0:098463de4c5d 580 /** \brief Set Fault Mask
group-onsemi 0:098463de4c5d 581
group-onsemi 0:098463de4c5d 582 This function assigns the given value to the Fault Mask register.
group-onsemi 0:098463de4c5d 583
group-onsemi 0:098463de4c5d 584 \param [in] faultMask Fault Mask value to set
group-onsemi 0:098463de4c5d 585 */
group-onsemi 0:098463de4c5d 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
group-onsemi 0:098463de4c5d 587 {
group-onsemi 0:098463de4c5d 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
group-onsemi 0:098463de4c5d 589 }
group-onsemi 0:098463de4c5d 590
group-onsemi 0:098463de4c5d 591 #endif /* (__CORTEX_M >= 0x03) */
group-onsemi 0:098463de4c5d 592
group-onsemi 0:098463de4c5d 593
group-onsemi 0:098463de4c5d 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
group-onsemi 0:098463de4c5d 595
group-onsemi 0:098463de4c5d 596 /** \brief Get FPSCR
group-onsemi 0:098463de4c5d 597
group-onsemi 0:098463de4c5d 598 This function returns the current value of the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 599
group-onsemi 0:098463de4c5d 600 \return Floating Point Status/Control register value
group-onsemi 0:098463de4c5d 601 */
group-onsemi 0:098463de4c5d 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
group-onsemi 0:098463de4c5d 603 {
group-onsemi 0:098463de4c5d 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 605 uint32_t result;
group-onsemi 0:098463de4c5d 606
group-onsemi 0:098463de4c5d 607 /* Empty asm statement works as a scheduling barrier */
group-onsemi 0:098463de4c5d 608 __ASM volatile ("");
group-onsemi 0:098463de4c5d 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
group-onsemi 0:098463de4c5d 610 __ASM volatile ("");
group-onsemi 0:098463de4c5d 611 return(result);
group-onsemi 0:098463de4c5d 612 #else
group-onsemi 0:098463de4c5d 613 return(0);
group-onsemi 0:098463de4c5d 614 #endif
group-onsemi 0:098463de4c5d 615 }
group-onsemi 0:098463de4c5d 616
group-onsemi 0:098463de4c5d 617
group-onsemi 0:098463de4c5d 618 /** \brief Set FPSCR
group-onsemi 0:098463de4c5d 619
group-onsemi 0:098463de4c5d 620 This function assigns the given value to the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 621
group-onsemi 0:098463de4c5d 622 \param [in] fpscr Floating Point Status/Control value to set
group-onsemi 0:098463de4c5d 623 */
group-onsemi 0:098463de4c5d 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
group-onsemi 0:098463de4c5d 625 {
group-onsemi 0:098463de4c5d 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 627 /* Empty asm statement works as a scheduling barrier */
group-onsemi 0:098463de4c5d 628 __ASM volatile ("");
group-onsemi 0:098463de4c5d 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
group-onsemi 0:098463de4c5d 630 __ASM volatile ("");
group-onsemi 0:098463de4c5d 631 #endif
group-onsemi 0:098463de4c5d 632 }
group-onsemi 0:098463de4c5d 633
group-onsemi 0:098463de4c5d 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
group-onsemi 0:098463de4c5d 635
group-onsemi 0:098463de4c5d 636
group-onsemi 0:098463de4c5d 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
group-onsemi 0:098463de4c5d 638 /* IAR iccarm specific functions */
group-onsemi 0:098463de4c5d 639 #include <cmsis_iar.h>
group-onsemi 0:098463de4c5d 640
group-onsemi 0:098463de4c5d 641
group-onsemi 0:098463de4c5d 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
group-onsemi 0:098463de4c5d 643 /* TI CCS specific functions */
group-onsemi 0:098463de4c5d 644 #include <cmsis_ccs.h>
group-onsemi 0:098463de4c5d 645
group-onsemi 0:098463de4c5d 646
group-onsemi 0:098463de4c5d 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
group-onsemi 0:098463de4c5d 648 /* TASKING carm specific functions */
group-onsemi 0:098463de4c5d 649 /*
group-onsemi 0:098463de4c5d 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
group-onsemi 0:098463de4c5d 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
group-onsemi 0:098463de4c5d 652 * Including the CMSIS ones.
group-onsemi 0:098463de4c5d 653 */
group-onsemi 0:098463de4c5d 654
group-onsemi 0:098463de4c5d 655
group-onsemi 0:098463de4c5d 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
group-onsemi 0:098463de4c5d 657 /* Cosmic specific functions */
group-onsemi 0:098463de4c5d 658 #include <cmsis_csm.h>
group-onsemi 0:098463de4c5d 659
group-onsemi 0:098463de4c5d 660 #endif
group-onsemi 0:098463de4c5d 661
group-onsemi 0:098463de4c5d 662 /*@} end of CMSIS_Core_RegAccFunctions */
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 #endif /* __CORE_CMFUNC_H */