mbed-os - 5.2.1 - Updated I2C files

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5.2.1 - Updated I2C files

Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_cm7.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:: jacobjohnson
Date:: Mon Feb 27 17:45:05 2017 +0000
Revision:: 1:f30bdcd2b33b
Parent:: 0:098463de4c5d

changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

User	Revision	Line number	New contents of line
group-onsemi	0:098463de4c5d	1	/************************************************************************//
group-onsemi	0:098463de4c5d	2	* @file core_cm7.h
group-onsemi	0:098463de4c5d	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
group-onsemi	0:098463de4c5d	4	* @version V4.10
group-onsemi	0:098463de4c5d	5	* @date 18. March 2015
group-onsemi	0:098463de4c5d	6	*
group-onsemi	0:098463de4c5d	7	* @note
group-onsemi	0:098463de4c5d	8	*
group-onsemi	0:098463de4c5d	9	******************************************************************************/
group-onsemi	0:098463de4c5d	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
group-onsemi	0:098463de4c5d	11
group-onsemi	0:098463de4c5d	12	All rights reserved.
group-onsemi	0:098463de4c5d	13	Redistribution and use in source and binary forms, with or without
group-onsemi	0:098463de4c5d	14	modification, are permitted provided that the following conditions are met:
group-onsemi	0:098463de4c5d	15	- Redistributions of source code must retain the above copyright
group-onsemi	0:098463de4c5d	16	notice, this list of conditions and the following disclaimer.
group-onsemi	0:098463de4c5d	17	- Redistributions in binary form must reproduce the above copyright
group-onsemi	0:098463de4c5d	18	notice, this list of conditions and the following disclaimer in the
group-onsemi	0:098463de4c5d	19	documentation and/or other materials provided with the distribution.
group-onsemi	0:098463de4c5d	20	- Neither the name of ARM nor the names of its contributors may be used
group-onsemi	0:098463de4c5d	21	to endorse or promote products derived from this software without
group-onsemi	0:098463de4c5d	22	specific prior written permission.
group-onsemi	0:098463de4c5d	23	*
group-onsemi	0:098463de4c5d	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi	0:098463de4c5d	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi	0:098463de4c5d	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi	0:098463de4c5d	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi	0:098463de4c5d	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi	0:098463de4c5d	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi	0:098463de4c5d	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi	0:098463de4c5d	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi	0:098463de4c5d	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi	0:098463de4c5d	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi	0:098463de4c5d	34	POSSIBILITY OF SUCH DAMAGE.
group-onsemi	0:098463de4c5d	35	---------------------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	36
group-onsemi	0:098463de4c5d	37
group-onsemi	0:098463de4c5d	38	#if defined ( __ICCARM__ )
group-onsemi	0:098463de4c5d	39	#pragma system_include /* treat file as system include file for MISRA check */
group-onsemi	0:098463de4c5d	40	#endif
group-onsemi	0:098463de4c5d	41
group-onsemi	0:098463de4c5d	42	#ifndef __CORE_CM7_H_GENERIC
group-onsemi	0:098463de4c5d	43	#define __CORE_CM7_H_GENERIC
group-onsemi	0:098463de4c5d	44
group-onsemi	0:098463de4c5d	45	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	46	extern "C" {
group-onsemi	0:098463de4c5d	47	#endif
group-onsemi	0:098463de4c5d	48
group-onsemi	0:098463de4c5d	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
group-onsemi	0:098463de4c5d	50	CMSIS violates the following MISRA-C:2004 rules:
group-onsemi	0:098463de4c5d	51
group-onsemi	0:098463de4c5d	52	\li Required Rule 8.5, object/function definition in header file.<br>
group-onsemi	0:098463de4c5d	53	Function definitions in header files are used to allow 'inlining'.
group-onsemi	0:098463de4c5d	54
group-onsemi	0:098463de4c5d	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
group-onsemi	0:098463de4c5d	56	Unions are used for effective representation of core registers.
group-onsemi	0:098463de4c5d	57
group-onsemi	0:098463de4c5d	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
group-onsemi	0:098463de4c5d	59	Function-like macros are used to allow more efficient code.
group-onsemi	0:098463de4c5d	60	*/
group-onsemi	0:098463de4c5d	61
group-onsemi	0:098463de4c5d	62
group-onsemi	0:098463de4c5d	63	/*******************************************************************************
group-onsemi	0:098463de4c5d	64	* CMSIS definitions
group-onsemi	0:098463de4c5d	65	******************************************************************************/
group-onsemi	0:098463de4c5d	66	/** \ingroup Cortex_M7
group-onsemi	0:098463de4c5d	67	@{
group-onsemi	0:098463de4c5d	68	*/
group-onsemi	0:098463de4c5d	69
group-onsemi	0:098463de4c5d	70	/* CMSIS CM7 definitions */
group-onsemi	0:098463de4c5d	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
group-onsemi	0:098463de4c5d	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
group-onsemi	0:098463de4c5d	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
group-onsemi	0:098463de4c5d	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
group-onsemi	0:098463de4c5d	75
group-onsemi	0:098463de4c5d	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
group-onsemi	0:098463de4c5d	77
group-onsemi	0:098463de4c5d	78
group-onsemi	0:098463de4c5d	79	#if defined ( __CC_ARM )
group-onsemi	0:098463de4c5d	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
group-onsemi	0:098463de4c5d	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
group-onsemi	0:098463de4c5d	82	#define __STATIC_INLINE static __inline
group-onsemi	0:098463de4c5d	83
group-onsemi	0:098463de4c5d	84	#elif defined ( __GNUC__ )
group-onsemi	0:098463de4c5d	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
group-onsemi	0:098463de4c5d	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
group-onsemi	0:098463de4c5d	87	#define __STATIC_INLINE static inline
group-onsemi	0:098463de4c5d	88
group-onsemi	0:098463de4c5d	89	#elif defined ( __ICCARM__ )
group-onsemi	0:098463de4c5d	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
group-onsemi	0:098463de4c5d	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
group-onsemi	0:098463de4c5d	92	#define __STATIC_INLINE static inline
group-onsemi	0:098463de4c5d	93
group-onsemi	0:098463de4c5d	94	#elif defined ( __TMS470__ )
group-onsemi	0:098463de4c5d	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
group-onsemi	0:098463de4c5d	96	#define __STATIC_INLINE static inline
group-onsemi	0:098463de4c5d	97
group-onsemi	0:098463de4c5d	98	#elif defined ( __TASKING__ )
group-onsemi	0:098463de4c5d	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
group-onsemi	0:098463de4c5d	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
group-onsemi	0:098463de4c5d	101	#define __STATIC_INLINE static inline
group-onsemi	0:098463de4c5d	102
group-onsemi	0:098463de4c5d	103	#elif defined ( __CSMC__ )
group-onsemi	0:098463de4c5d	104	#define __packed
group-onsemi	0:098463de4c5d	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
group-onsemi	0:098463de4c5d	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
group-onsemi	0:098463de4c5d	107	#define __STATIC_INLINE static inline
group-onsemi	0:098463de4c5d	108
group-onsemi	0:098463de4c5d	109	#endif
group-onsemi	0:098463de4c5d	110
group-onsemi	0:098463de4c5d	111	/** __FPU_USED indicates whether an FPU is used or not.
group-onsemi	0:098463de4c5d	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
group-onsemi	0:098463de4c5d	113	*/
group-onsemi	0:098463de4c5d	114	#if defined ( __CC_ARM )
group-onsemi	0:098463de4c5d	115	#if defined __TARGET_FPU_VFP
group-onsemi	0:098463de4c5d	116	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	117	#define __FPU_USED 1
group-onsemi	0:098463de4c5d	118	#else
group-onsemi	0:098463de4c5d	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi	0:098463de4c5d	120	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	121	#endif
group-onsemi	0:098463de4c5d	122	#else
group-onsemi	0:098463de4c5d	123	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	124	#endif
group-onsemi	0:098463de4c5d	125
group-onsemi	0:098463de4c5d	126	#elif defined ( __GNUC__ )
group-onsemi	0:098463de4c5d	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
group-onsemi	0:098463de4c5d	128	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	129	#define __FPU_USED 1
group-onsemi	0:098463de4c5d	130	#else
group-onsemi	0:098463de4c5d	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi	0:098463de4c5d	132	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	133	#endif
group-onsemi	0:098463de4c5d	134	#else
group-onsemi	0:098463de4c5d	135	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	136	#endif
group-onsemi	0:098463de4c5d	137
group-onsemi	0:098463de4c5d	138	#elif defined ( __ICCARM__ )
group-onsemi	0:098463de4c5d	139	#if defined __ARMVFP__
group-onsemi	0:098463de4c5d	140	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	141	#define __FPU_USED 1
group-onsemi	0:098463de4c5d	142	#else
group-onsemi	0:098463de4c5d	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi	0:098463de4c5d	144	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	145	#endif
group-onsemi	0:098463de4c5d	146	#else
group-onsemi	0:098463de4c5d	147	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	148	#endif
group-onsemi	0:098463de4c5d	149
group-onsemi	0:098463de4c5d	150	#elif defined ( __TMS470__ )
group-onsemi	0:098463de4c5d	151	#if defined __TI_VFP_SUPPORT__
group-onsemi	0:098463de4c5d	152	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	153	#define __FPU_USED 1
group-onsemi	0:098463de4c5d	154	#else
group-onsemi	0:098463de4c5d	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi	0:098463de4c5d	156	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	157	#endif
group-onsemi	0:098463de4c5d	158	#else
group-onsemi	0:098463de4c5d	159	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	160	#endif
group-onsemi	0:098463de4c5d	161
group-onsemi	0:098463de4c5d	162	#elif defined ( __TASKING__ )
group-onsemi	0:098463de4c5d	163	#if defined __FPU_VFP__
group-onsemi	0:098463de4c5d	164	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	165	#define __FPU_USED 1
group-onsemi	0:098463de4c5d	166	#else
group-onsemi	0:098463de4c5d	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi	0:098463de4c5d	168	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	169	#endif
group-onsemi	0:098463de4c5d	170	#else
group-onsemi	0:098463de4c5d	171	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	172	#endif
group-onsemi	0:098463de4c5d	173
group-onsemi	0:098463de4c5d	174	#elif defined ( __CSMC__ ) /* Cosmic */
group-onsemi	0:098463de4c5d	175	#if ( __CSMC__ & 0x400) // FPU present for parser
group-onsemi	0:098463de4c5d	176	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	177	#define __FPU_USED 1
group-onsemi	0:098463de4c5d	178	#else
group-onsemi	0:098463de4c5d	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi	0:098463de4c5d	180	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	181	#endif
group-onsemi	0:098463de4c5d	182	#else
group-onsemi	0:098463de4c5d	183	#define __FPU_USED 0
group-onsemi	0:098463de4c5d	184	#endif
group-onsemi	0:098463de4c5d	185	#endif
group-onsemi	0:098463de4c5d	186
group-onsemi	0:098463de4c5d	187	#include <stdint.h> /* standard types definitions */
group-onsemi	0:098463de4c5d	188	#include <core_cmInstr.h> /* Core Instruction Access */
group-onsemi	0:098463de4c5d	189	#include <core_cmFunc.h> /* Core Function Access */
group-onsemi	0:098463de4c5d	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
group-onsemi	0:098463de4c5d	191
group-onsemi	0:098463de4c5d	192	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	193	}
group-onsemi	0:098463de4c5d	194	#endif
group-onsemi	0:098463de4c5d	195
group-onsemi	0:098463de4c5d	196	#endif /* __CORE_CM7_H_GENERIC */
group-onsemi	0:098463de4c5d	197
group-onsemi	0:098463de4c5d	198	#ifndef __CMSIS_GENERIC
group-onsemi	0:098463de4c5d	199
group-onsemi	0:098463de4c5d	200	#ifndef __CORE_CM7_H_DEPENDANT
group-onsemi	0:098463de4c5d	201	#define __CORE_CM7_H_DEPENDANT
group-onsemi	0:098463de4c5d	202
group-onsemi	0:098463de4c5d	203	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	204	extern "C" {
group-onsemi	0:098463de4c5d	205	#endif
group-onsemi	0:098463de4c5d	206
group-onsemi	0:098463de4c5d	207	/* check device defines and use defaults */
group-onsemi	0:098463de4c5d	208	#if defined __CHECK_DEVICE_DEFINES
group-onsemi	0:098463de4c5d	209	#ifndef __CM7_REV
group-onsemi	0:098463de4c5d	210	#define __CM7_REV 0x0000
group-onsemi	0:098463de4c5d	211	#warning "__CM7_REV not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	212	#endif
group-onsemi	0:098463de4c5d	213
group-onsemi	0:098463de4c5d	214	#ifndef __FPU_PRESENT
group-onsemi	0:098463de4c5d	215	#define __FPU_PRESENT 0
group-onsemi	0:098463de4c5d	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	217	#endif
group-onsemi	0:098463de4c5d	218
group-onsemi	0:098463de4c5d	219	#ifndef __MPU_PRESENT
group-onsemi	0:098463de4c5d	220	#define __MPU_PRESENT 0
group-onsemi	0:098463de4c5d	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	222	#endif
group-onsemi	0:098463de4c5d	223
group-onsemi	0:098463de4c5d	224	#ifndef __ICACHE_PRESENT
group-onsemi	0:098463de4c5d	225	#define __ICACHE_PRESENT 0
group-onsemi	0:098463de4c5d	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	227	#endif
group-onsemi	0:098463de4c5d	228
group-onsemi	0:098463de4c5d	229	#ifndef __DCACHE_PRESENT
group-onsemi	0:098463de4c5d	230	#define __DCACHE_PRESENT 0
group-onsemi	0:098463de4c5d	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	232	#endif
group-onsemi	0:098463de4c5d	233
group-onsemi	0:098463de4c5d	234	#ifndef __DTCM_PRESENT
group-onsemi	0:098463de4c5d	235	#define __DTCM_PRESENT 0
group-onsemi	0:098463de4c5d	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	237	#endif
group-onsemi	0:098463de4c5d	238
group-onsemi	0:098463de4c5d	239	#ifndef __NVIC_PRIO_BITS
group-onsemi	0:098463de4c5d	240	#define __NVIC_PRIO_BITS 3
group-onsemi	0:098463de4c5d	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	242	#endif
group-onsemi	0:098463de4c5d	243
group-onsemi	0:098463de4c5d	244	#ifndef __Vendor_SysTickConfig
group-onsemi	0:098463de4c5d	245	#define __Vendor_SysTickConfig 0
group-onsemi	0:098463de4c5d	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
group-onsemi	0:098463de4c5d	247	#endif
group-onsemi	0:098463de4c5d	248	#endif
group-onsemi	0:098463de4c5d	249
group-onsemi	0:098463de4c5d	250	/* IO definitions (access restrictions to peripheral registers) */
group-onsemi	0:098463de4c5d	251	/**
group-onsemi	0:098463de4c5d	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
group-onsemi	0:098463de4c5d	253
group-onsemi	0:098463de4c5d	254	<strong>IO Type Qualifiers</strong> are used
group-onsemi	0:098463de4c5d	255	\li to specify the access to peripheral variables.
group-onsemi	0:098463de4c5d	256	\li for automatic generation of peripheral register debug information.
group-onsemi	0:098463de4c5d	257	*/
group-onsemi	0:098463de4c5d	258	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	259	#define __I volatile /!< Defines 'read only' permissions /
group-onsemi	0:098463de4c5d	260	#else
group-onsemi	0:098463de4c5d	261	#define __I volatile const /!< Defines 'read only' permissions /
group-onsemi	0:098463de4c5d	262	#endif
group-onsemi	0:098463de4c5d	263	#define __O volatile /!< Defines 'write only' permissions /
group-onsemi	0:098463de4c5d	264	#define __IO volatile /!< Defines 'read / write' permissions /
group-onsemi	0:098463de4c5d	265
group-onsemi	0:098463de4c5d	266	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	267	#define __IM volatile /!< Defines 'read only' permissions /
group-onsemi	0:098463de4c5d	268	#else
group-onsemi	0:098463de4c5d	269	#define __IM volatile const /!< Defines 'read only' permissions /
group-onsemi	0:098463de4c5d	270	#endif
group-onsemi	0:098463de4c5d	271	#define __OM volatile /!< Defines 'write only' permissions /
group-onsemi	0:098463de4c5d	272	#define __IOM volatile /!< Defines 'read / write' permissions /
group-onsemi	0:098463de4c5d	273
group-onsemi	0:098463de4c5d	274	/@} end of group Cortex_M7 /
group-onsemi	0:098463de4c5d	275
group-onsemi	0:098463de4c5d	276
group-onsemi	0:098463de4c5d	277
group-onsemi	0:098463de4c5d	278	/*******************************************************************************
group-onsemi	0:098463de4c5d	279	* Register Abstraction
group-onsemi	0:098463de4c5d	280	Core Register contain:
group-onsemi	0:098463de4c5d	281	- Core Register
group-onsemi	0:098463de4c5d	282	- Core NVIC Register
group-onsemi	0:098463de4c5d	283	- Core SCB Register
group-onsemi	0:098463de4c5d	284	- Core SysTick Register
group-onsemi	0:098463de4c5d	285	- Core Debug Register
group-onsemi	0:098463de4c5d	286	- Core MPU Register
group-onsemi	0:098463de4c5d	287	- Core FPU Register
group-onsemi	0:098463de4c5d	288	******************************************************************************/
group-onsemi	0:098463de4c5d	289	/** \defgroup CMSIS_core_register Defines and Type Definitions
group-onsemi	0:098463de4c5d	290	\brief Type definitions and defines for Cortex-M processor based devices.
group-onsemi	0:098463de4c5d	291	*/
group-onsemi	0:098463de4c5d	292
group-onsemi	0:098463de4c5d	293	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	294	\defgroup CMSIS_CORE Status and Control Registers
group-onsemi	0:098463de4c5d	295	\brief Core Register type definitions.
group-onsemi	0:098463de4c5d	296	@{
group-onsemi	0:098463de4c5d	297	*/
group-onsemi	0:098463de4c5d	298
group-onsemi	0:098463de4c5d	299	/** \brief Union type to access the Application Program Status Register (APSR).
group-onsemi	0:098463de4c5d	300	*/
group-onsemi	0:098463de4c5d	301	typedef union
group-onsemi	0:098463de4c5d	302	{
group-onsemi	0:098463de4c5d	303	struct
group-onsemi	0:098463de4c5d	304	{
group-onsemi	0:098463de4c5d	305	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
group-onsemi	0:098463de4c5d	306	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
group-onsemi	0:098463de4c5d	307	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
group-onsemi	0:098463de4c5d	308	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
group-onsemi	0:098463de4c5d	309	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
group-onsemi	0:098463de4c5d	310	uint32_t C:1; /!< bit: 29 Carry condition code flag /
group-onsemi	0:098463de4c5d	311	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
group-onsemi	0:098463de4c5d	312	uint32_t N:1; /!< bit: 31 Negative condition code flag /
group-onsemi	0:098463de4c5d	313	} b; /!< Structure used for bit access /
group-onsemi	0:098463de4c5d	314	uint32_t w; /!< Type used for word access /
group-onsemi	0:098463de4c5d	315	} APSR_Type;
group-onsemi	0:098463de4c5d	316
group-onsemi	0:098463de4c5d	317	/* APSR Register Definitions */
group-onsemi	0:098463de4c5d	318	#define APSR_N_Pos 31 /!< APSR: N Position /
group-onsemi	0:098463de4c5d	319	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
group-onsemi	0:098463de4c5d	320
group-onsemi	0:098463de4c5d	321	#define APSR_Z_Pos 30 /!< APSR: Z Position /
group-onsemi	0:098463de4c5d	322	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
group-onsemi	0:098463de4c5d	323
group-onsemi	0:098463de4c5d	324	#define APSR_C_Pos 29 /!< APSR: C Position /
group-onsemi	0:098463de4c5d	325	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
group-onsemi	0:098463de4c5d	326
group-onsemi	0:098463de4c5d	327	#define APSR_V_Pos 28 /!< APSR: V Position /
group-onsemi	0:098463de4c5d	328	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
group-onsemi	0:098463de4c5d	329
group-onsemi	0:098463de4c5d	330	#define APSR_Q_Pos 27 /!< APSR: Q Position /
group-onsemi	0:098463de4c5d	331	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
group-onsemi	0:098463de4c5d	332
group-onsemi	0:098463de4c5d	333	#define APSR_GE_Pos 16 /!< APSR: GE Position /
group-onsemi	0:098463de4c5d	334	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
group-onsemi	0:098463de4c5d	335
group-onsemi	0:098463de4c5d	336
group-onsemi	0:098463de4c5d	337	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
group-onsemi	0:098463de4c5d	338	*/
group-onsemi	0:098463de4c5d	339	typedef union
group-onsemi	0:098463de4c5d	340	{
group-onsemi	0:098463de4c5d	341	struct
group-onsemi	0:098463de4c5d	342	{
group-onsemi	0:098463de4c5d	343	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
group-onsemi	0:098463de4c5d	344	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
group-onsemi	0:098463de4c5d	345	} b; /!< Structure used for bit access /
group-onsemi	0:098463de4c5d	346	uint32_t w; /!< Type used for word access /
group-onsemi	0:098463de4c5d	347	} IPSR_Type;
group-onsemi	0:098463de4c5d	348
group-onsemi	0:098463de4c5d	349	/* IPSR Register Definitions */
group-onsemi	0:098463de4c5d	350	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
group-onsemi	0:098463de4c5d	351	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
group-onsemi	0:098463de4c5d	352
group-onsemi	0:098463de4c5d	353
group-onsemi	0:098463de4c5d	354	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
group-onsemi	0:098463de4c5d	355	*/
group-onsemi	0:098463de4c5d	356	typedef union
group-onsemi	0:098463de4c5d	357	{
group-onsemi	0:098463de4c5d	358	struct
group-onsemi	0:098463de4c5d	359	{
group-onsemi	0:098463de4c5d	360	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
group-onsemi	0:098463de4c5d	361	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
group-onsemi	0:098463de4c5d	362	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
group-onsemi	0:098463de4c5d	363	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
group-onsemi	0:098463de4c5d	364	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
group-onsemi	0:098463de4c5d	365	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
group-onsemi	0:098463de4c5d	366	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
group-onsemi	0:098463de4c5d	367	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
group-onsemi	0:098463de4c5d	368	uint32_t C:1; /!< bit: 29 Carry condition code flag /
group-onsemi	0:098463de4c5d	369	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
group-onsemi	0:098463de4c5d	370	uint32_t N:1; /!< bit: 31 Negative condition code flag /
group-onsemi	0:098463de4c5d	371	} b; /!< Structure used for bit access /
group-onsemi	0:098463de4c5d	372	uint32_t w; /!< Type used for word access /
group-onsemi	0:098463de4c5d	373	} xPSR_Type;
group-onsemi	0:098463de4c5d	374
group-onsemi	0:098463de4c5d	375	/* xPSR Register Definitions */
group-onsemi	0:098463de4c5d	376	#define xPSR_N_Pos 31 /!< xPSR: N Position /
group-onsemi	0:098463de4c5d	377	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
group-onsemi	0:098463de4c5d	378
group-onsemi	0:098463de4c5d	379	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
group-onsemi	0:098463de4c5d	380	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
group-onsemi	0:098463de4c5d	381
group-onsemi	0:098463de4c5d	382	#define xPSR_C_Pos 29 /!< xPSR: C Position /
group-onsemi	0:098463de4c5d	383	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
group-onsemi	0:098463de4c5d	384
group-onsemi	0:098463de4c5d	385	#define xPSR_V_Pos 28 /!< xPSR: V Position /
group-onsemi	0:098463de4c5d	386	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
group-onsemi	0:098463de4c5d	387
group-onsemi	0:098463de4c5d	388	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
group-onsemi	0:098463de4c5d	389	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
group-onsemi	0:098463de4c5d	390
group-onsemi	0:098463de4c5d	391	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
group-onsemi	0:098463de4c5d	392	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
group-onsemi	0:098463de4c5d	393
group-onsemi	0:098463de4c5d	394	#define xPSR_T_Pos 24 /!< xPSR: T Position /
group-onsemi	0:098463de4c5d	395	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
group-onsemi	0:098463de4c5d	396
group-onsemi	0:098463de4c5d	397	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
group-onsemi	0:098463de4c5d	398	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
group-onsemi	0:098463de4c5d	399
group-onsemi	0:098463de4c5d	400	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
group-onsemi	0:098463de4c5d	401	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
group-onsemi	0:098463de4c5d	402
group-onsemi	0:098463de4c5d	403
group-onsemi	0:098463de4c5d	404	/** \brief Union type to access the Control Registers (CONTROL).
group-onsemi	0:098463de4c5d	405	*/
group-onsemi	0:098463de4c5d	406	typedef union
group-onsemi	0:098463de4c5d	407	{
group-onsemi	0:098463de4c5d	408	struct
group-onsemi	0:098463de4c5d	409	{
group-onsemi	0:098463de4c5d	410	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
group-onsemi	0:098463de4c5d	411	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
group-onsemi	0:098463de4c5d	412	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
group-onsemi	0:098463de4c5d	413	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
group-onsemi	0:098463de4c5d	414	} b; /!< Structure used for bit access /
group-onsemi	0:098463de4c5d	415	uint32_t w; /!< Type used for word access /
group-onsemi	0:098463de4c5d	416	} CONTROL_Type;
group-onsemi	0:098463de4c5d	417
group-onsemi	0:098463de4c5d	418	/* CONTROL Register Definitions */
group-onsemi	0:098463de4c5d	419	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
group-onsemi	0:098463de4c5d	420	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
group-onsemi	0:098463de4c5d	421
group-onsemi	0:098463de4c5d	422	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
group-onsemi	0:098463de4c5d	423	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
group-onsemi	0:098463de4c5d	424
group-onsemi	0:098463de4c5d	425	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
group-onsemi	0:098463de4c5d	426	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
group-onsemi	0:098463de4c5d	427
group-onsemi	0:098463de4c5d	428	/@} end of group CMSIS_CORE /
group-onsemi	0:098463de4c5d	429
group-onsemi	0:098463de4c5d	430
group-onsemi	0:098463de4c5d	431	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	432	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
group-onsemi	0:098463de4c5d	433	\brief Type definitions for the NVIC Registers
group-onsemi	0:098463de4c5d	434	@{
group-onsemi	0:098463de4c5d	435	*/
group-onsemi	0:098463de4c5d	436
group-onsemi	0:098463de4c5d	437	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
group-onsemi	0:098463de4c5d	438	*/
group-onsemi	0:098463de4c5d	439	typedef struct
group-onsemi	0:098463de4c5d	440	{
group-onsemi	0:098463de4c5d	441	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
group-onsemi	0:098463de4c5d	442	uint32_t RESERVED0[24];
group-onsemi	0:098463de4c5d	443	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
group-onsemi	0:098463de4c5d	444	uint32_t RSERVED1[24];
group-onsemi	0:098463de4c5d	445	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
group-onsemi	0:098463de4c5d	446	uint32_t RESERVED2[24];
group-onsemi	0:098463de4c5d	447	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
group-onsemi	0:098463de4c5d	448	uint32_t RESERVED3[24];
group-onsemi	0:098463de4c5d	449	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
group-onsemi	0:098463de4c5d	450	uint32_t RESERVED4[56];
group-onsemi	0:098463de4c5d	451	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
group-onsemi	0:098463de4c5d	452	uint32_t RESERVED5[644];
group-onsemi	0:098463de4c5d	453	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
group-onsemi	0:098463de4c5d	454	} NVIC_Type;
group-onsemi	0:098463de4c5d	455
group-onsemi	0:098463de4c5d	456	/* Software Triggered Interrupt Register Definitions */
group-onsemi	0:098463de4c5d	457	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
group-onsemi	0:098463de4c5d	458	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
group-onsemi	0:098463de4c5d	459
group-onsemi	0:098463de4c5d	460	/@} end of group CMSIS_NVIC /
group-onsemi	0:098463de4c5d	461
group-onsemi	0:098463de4c5d	462
group-onsemi	0:098463de4c5d	463	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	464	\defgroup CMSIS_SCB System Control Block (SCB)
group-onsemi	0:098463de4c5d	465	\brief Type definitions for the System Control Block Registers
group-onsemi	0:098463de4c5d	466	@{
group-onsemi	0:098463de4c5d	467	*/
group-onsemi	0:098463de4c5d	468
group-onsemi	0:098463de4c5d	469	/** \brief Structure type to access the System Control Block (SCB).
group-onsemi	0:098463de4c5d	470	*/
group-onsemi	0:098463de4c5d	471	typedef struct
group-onsemi	0:098463de4c5d	472	{
group-onsemi	0:098463de4c5d	473	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
group-onsemi	0:098463de4c5d	474	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
group-onsemi	0:098463de4c5d	475	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
group-onsemi	0:098463de4c5d	476	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
group-onsemi	0:098463de4c5d	477	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
group-onsemi	0:098463de4c5d	478	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
group-onsemi	0:098463de4c5d	479	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
group-onsemi	0:098463de4c5d	480	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
group-onsemi	0:098463de4c5d	481	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
group-onsemi	0:098463de4c5d	482	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
group-onsemi	0:098463de4c5d	483	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
group-onsemi	0:098463de4c5d	484	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
group-onsemi	0:098463de4c5d	485	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
group-onsemi	0:098463de4c5d	486	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
group-onsemi	0:098463de4c5d	487	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
group-onsemi	0:098463de4c5d	488	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
group-onsemi	0:098463de4c5d	489	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
group-onsemi	0:098463de4c5d	490	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
group-onsemi	0:098463de4c5d	491	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
group-onsemi	0:098463de4c5d	492	uint32_t RESERVED0[1];
group-onsemi	0:098463de4c5d	493	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
group-onsemi	0:098463de4c5d	494	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
group-onsemi	0:098463de4c5d	495	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
group-onsemi	0:098463de4c5d	496	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
group-onsemi	0:098463de4c5d	497	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
group-onsemi	0:098463de4c5d	498	uint32_t RESERVED3[93];
group-onsemi	0:098463de4c5d	499	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
group-onsemi	0:098463de4c5d	500	uint32_t RESERVED4[15];
group-onsemi	0:098463de4c5d	501	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
group-onsemi	0:098463de4c5d	502	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
group-onsemi	0:098463de4c5d	503	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
group-onsemi	0:098463de4c5d	504	uint32_t RESERVED5[1];
group-onsemi	0:098463de4c5d	505	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
group-onsemi	0:098463de4c5d	506	uint32_t RESERVED6[1];
group-onsemi	0:098463de4c5d	507	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
group-onsemi	0:098463de4c5d	508	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
group-onsemi	0:098463de4c5d	509	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
group-onsemi	0:098463de4c5d	510	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
group-onsemi	0:098463de4c5d	511	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
group-onsemi	0:098463de4c5d	512	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
group-onsemi	0:098463de4c5d	513	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
group-onsemi	0:098463de4c5d	514	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
group-onsemi	0:098463de4c5d	515	uint32_t RESERVED7[6];
group-onsemi	0:098463de4c5d	516	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
group-onsemi	0:098463de4c5d	517	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
group-onsemi	0:098463de4c5d	518	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
group-onsemi	0:098463de4c5d	519	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
group-onsemi	0:098463de4c5d	520	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
group-onsemi	0:098463de4c5d	521	uint32_t RESERVED8[1];
group-onsemi	0:098463de4c5d	522	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
group-onsemi	0:098463de4c5d	523	} SCB_Type;
group-onsemi	0:098463de4c5d	524
group-onsemi	0:098463de4c5d	525	/* SCB CPUID Register Definitions */
group-onsemi	0:098463de4c5d	526	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
group-onsemi	0:098463de4c5d	527	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
group-onsemi	0:098463de4c5d	528
group-onsemi	0:098463de4c5d	529	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
group-onsemi	0:098463de4c5d	530	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
group-onsemi	0:098463de4c5d	531
group-onsemi	0:098463de4c5d	532	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
group-onsemi	0:098463de4c5d	533	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
group-onsemi	0:098463de4c5d	534
group-onsemi	0:098463de4c5d	535	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
group-onsemi	0:098463de4c5d	536	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
group-onsemi	0:098463de4c5d	537
group-onsemi	0:098463de4c5d	538	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
group-onsemi	0:098463de4c5d	539	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
group-onsemi	0:098463de4c5d	540
group-onsemi	0:098463de4c5d	541	/* SCB Interrupt Control State Register Definitions */
group-onsemi	0:098463de4c5d	542	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
group-onsemi	0:098463de4c5d	543	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
group-onsemi	0:098463de4c5d	544
group-onsemi	0:098463de4c5d	545	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
group-onsemi	0:098463de4c5d	546	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
group-onsemi	0:098463de4c5d	547
group-onsemi	0:098463de4c5d	548	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
group-onsemi	0:098463de4c5d	549	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
group-onsemi	0:098463de4c5d	550
group-onsemi	0:098463de4c5d	551	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
group-onsemi	0:098463de4c5d	552	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
group-onsemi	0:098463de4c5d	553
group-onsemi	0:098463de4c5d	554	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
group-onsemi	0:098463de4c5d	555	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
group-onsemi	0:098463de4c5d	556
group-onsemi	0:098463de4c5d	557	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
group-onsemi	0:098463de4c5d	558	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
group-onsemi	0:098463de4c5d	559
group-onsemi	0:098463de4c5d	560	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
group-onsemi	0:098463de4c5d	561	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
group-onsemi	0:098463de4c5d	562
group-onsemi	0:098463de4c5d	563	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
group-onsemi	0:098463de4c5d	564	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
group-onsemi	0:098463de4c5d	565
group-onsemi	0:098463de4c5d	566	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
group-onsemi	0:098463de4c5d	567	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
group-onsemi	0:098463de4c5d	568
group-onsemi	0:098463de4c5d	569	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
group-onsemi	0:098463de4c5d	570	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
group-onsemi	0:098463de4c5d	571
group-onsemi	0:098463de4c5d	572	/* SCB Vector Table Offset Register Definitions */
group-onsemi	0:098463de4c5d	573	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
group-onsemi	0:098463de4c5d	574	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
group-onsemi	0:098463de4c5d	575
group-onsemi	0:098463de4c5d	576	/* SCB Application Interrupt and Reset Control Register Definitions */
group-onsemi	0:098463de4c5d	577	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
group-onsemi	0:098463de4c5d	578	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
group-onsemi	0:098463de4c5d	579
group-onsemi	0:098463de4c5d	580	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
group-onsemi	0:098463de4c5d	581	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
group-onsemi	0:098463de4c5d	582
group-onsemi	0:098463de4c5d	583	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
group-onsemi	0:098463de4c5d	584	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
group-onsemi	0:098463de4c5d	585
group-onsemi	0:098463de4c5d	586	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
group-onsemi	0:098463de4c5d	587	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
group-onsemi	0:098463de4c5d	588
group-onsemi	0:098463de4c5d	589	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
group-onsemi	0:098463de4c5d	590	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
group-onsemi	0:098463de4c5d	591
group-onsemi	0:098463de4c5d	592	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
group-onsemi	0:098463de4c5d	593	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
group-onsemi	0:098463de4c5d	594
group-onsemi	0:098463de4c5d	595	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
group-onsemi	0:098463de4c5d	596	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
group-onsemi	0:098463de4c5d	597
group-onsemi	0:098463de4c5d	598	/* SCB System Control Register Definitions */
group-onsemi	0:098463de4c5d	599	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
group-onsemi	0:098463de4c5d	600	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
group-onsemi	0:098463de4c5d	601
group-onsemi	0:098463de4c5d	602	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
group-onsemi	0:098463de4c5d	603	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
group-onsemi	0:098463de4c5d	604
group-onsemi	0:098463de4c5d	605	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
group-onsemi	0:098463de4c5d	606	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
group-onsemi	0:098463de4c5d	607
group-onsemi	0:098463de4c5d	608	/* SCB Configuration Control Register Definitions */
group-onsemi	0:098463de4c5d	609	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
group-onsemi	0:098463de4c5d	610	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
group-onsemi	0:098463de4c5d	611
group-onsemi	0:098463de4c5d	612	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
group-onsemi	0:098463de4c5d	613	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
group-onsemi	0:098463de4c5d	614
group-onsemi	0:098463de4c5d	615	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
group-onsemi	0:098463de4c5d	616	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
group-onsemi	0:098463de4c5d	617
group-onsemi	0:098463de4c5d	618	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
group-onsemi	0:098463de4c5d	619	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
group-onsemi	0:098463de4c5d	620
group-onsemi	0:098463de4c5d	621	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
group-onsemi	0:098463de4c5d	622	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
group-onsemi	0:098463de4c5d	623
group-onsemi	0:098463de4c5d	624	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
group-onsemi	0:098463de4c5d	625	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
group-onsemi	0:098463de4c5d	626
group-onsemi	0:098463de4c5d	627	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
group-onsemi	0:098463de4c5d	628	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
group-onsemi	0:098463de4c5d	629
group-onsemi	0:098463de4c5d	630	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
group-onsemi	0:098463de4c5d	631	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
group-onsemi	0:098463de4c5d	632
group-onsemi	0:098463de4c5d	633	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
group-onsemi	0:098463de4c5d	634	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
group-onsemi	0:098463de4c5d	635
group-onsemi	0:098463de4c5d	636	/* SCB System Handler Control and State Register Definitions */
group-onsemi	0:098463de4c5d	637	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
group-onsemi	0:098463de4c5d	638	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
group-onsemi	0:098463de4c5d	639
group-onsemi	0:098463de4c5d	640	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
group-onsemi	0:098463de4c5d	641	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
group-onsemi	0:098463de4c5d	642
group-onsemi	0:098463de4c5d	643	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
group-onsemi	0:098463de4c5d	644	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
group-onsemi	0:098463de4c5d	645
group-onsemi	0:098463de4c5d	646	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
group-onsemi	0:098463de4c5d	647	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
group-onsemi	0:098463de4c5d	648
group-onsemi	0:098463de4c5d	649	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
group-onsemi	0:098463de4c5d	650	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
group-onsemi	0:098463de4c5d	651
group-onsemi	0:098463de4c5d	652	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
group-onsemi	0:098463de4c5d	653	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
group-onsemi	0:098463de4c5d	654
group-onsemi	0:098463de4c5d	655	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
group-onsemi	0:098463de4c5d	656	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
group-onsemi	0:098463de4c5d	657
group-onsemi	0:098463de4c5d	658	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
group-onsemi	0:098463de4c5d	659	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
group-onsemi	0:098463de4c5d	660
group-onsemi	0:098463de4c5d	661	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
group-onsemi	0:098463de4c5d	662	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
group-onsemi	0:098463de4c5d	663
group-onsemi	0:098463de4c5d	664	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
group-onsemi	0:098463de4c5d	665	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
group-onsemi	0:098463de4c5d	666
group-onsemi	0:098463de4c5d	667	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
group-onsemi	0:098463de4c5d	668	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
group-onsemi	0:098463de4c5d	669
group-onsemi	0:098463de4c5d	670	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
group-onsemi	0:098463de4c5d	671	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
group-onsemi	0:098463de4c5d	672
group-onsemi	0:098463de4c5d	673	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
group-onsemi	0:098463de4c5d	674	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
group-onsemi	0:098463de4c5d	675
group-onsemi	0:098463de4c5d	676	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
group-onsemi	0:098463de4c5d	677	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
group-onsemi	0:098463de4c5d	678
group-onsemi	0:098463de4c5d	679	/* SCB Configurable Fault Status Registers Definitions */
group-onsemi	0:098463de4c5d	680	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
group-onsemi	0:098463de4c5d	681	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
group-onsemi	0:098463de4c5d	682
group-onsemi	0:098463de4c5d	683	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
group-onsemi	0:098463de4c5d	684	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
group-onsemi	0:098463de4c5d	685
group-onsemi	0:098463de4c5d	686	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
group-onsemi	0:098463de4c5d	687	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
group-onsemi	0:098463de4c5d	688
group-onsemi	0:098463de4c5d	689	/* SCB Hard Fault Status Registers Definitions */
group-onsemi	0:098463de4c5d	690	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
group-onsemi	0:098463de4c5d	691	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
group-onsemi	0:098463de4c5d	692
group-onsemi	0:098463de4c5d	693	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
group-onsemi	0:098463de4c5d	694	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
group-onsemi	0:098463de4c5d	695
group-onsemi	0:098463de4c5d	696	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
group-onsemi	0:098463de4c5d	697	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
group-onsemi	0:098463de4c5d	698
group-onsemi	0:098463de4c5d	699	/* SCB Debug Fault Status Register Definitions */
group-onsemi	0:098463de4c5d	700	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
group-onsemi	0:098463de4c5d	701	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
group-onsemi	0:098463de4c5d	702
group-onsemi	0:098463de4c5d	703	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
group-onsemi	0:098463de4c5d	704	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
group-onsemi	0:098463de4c5d	705
group-onsemi	0:098463de4c5d	706	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
group-onsemi	0:098463de4c5d	707	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
group-onsemi	0:098463de4c5d	708
group-onsemi	0:098463de4c5d	709	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
group-onsemi	0:098463de4c5d	710	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
group-onsemi	0:098463de4c5d	711
group-onsemi	0:098463de4c5d	712	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
group-onsemi	0:098463de4c5d	713	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
group-onsemi	0:098463de4c5d	714
group-onsemi	0:098463de4c5d	715	/* Cache Level ID register */
group-onsemi	0:098463de4c5d	716	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
group-onsemi	0:098463de4c5d	717	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
group-onsemi	0:098463de4c5d	718
group-onsemi	0:098463de4c5d	719	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
group-onsemi	0:098463de4c5d	720	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
group-onsemi	0:098463de4c5d	721
group-onsemi	0:098463de4c5d	722	/* Cache Type register */
group-onsemi	0:098463de4c5d	723	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
group-onsemi	0:098463de4c5d	724	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
group-onsemi	0:098463de4c5d	725
group-onsemi	0:098463de4c5d	726	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
group-onsemi	0:098463de4c5d	727	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
group-onsemi	0:098463de4c5d	728
group-onsemi	0:098463de4c5d	729	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
group-onsemi	0:098463de4c5d	730	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
group-onsemi	0:098463de4c5d	731
group-onsemi	0:098463de4c5d	732	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
group-onsemi	0:098463de4c5d	733	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
group-onsemi	0:098463de4c5d	734
group-onsemi	0:098463de4c5d	735	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
group-onsemi	0:098463de4c5d	736	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
group-onsemi	0:098463de4c5d	737
group-onsemi	0:098463de4c5d	738	/* Cache Size ID Register */
group-onsemi	0:098463de4c5d	739	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
group-onsemi	0:098463de4c5d	740	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
group-onsemi	0:098463de4c5d	741
group-onsemi	0:098463de4c5d	742	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
group-onsemi	0:098463de4c5d	743	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
group-onsemi	0:098463de4c5d	744
group-onsemi	0:098463de4c5d	745	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
group-onsemi	0:098463de4c5d	746	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
group-onsemi	0:098463de4c5d	747
group-onsemi	0:098463de4c5d	748	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
group-onsemi	0:098463de4c5d	749	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
group-onsemi	0:098463de4c5d	750
group-onsemi	0:098463de4c5d	751	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
group-onsemi	0:098463de4c5d	752	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
group-onsemi	0:098463de4c5d	753
group-onsemi	0:098463de4c5d	754	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
group-onsemi	0:098463de4c5d	755	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
group-onsemi	0:098463de4c5d	756
group-onsemi	0:098463de4c5d	757	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
group-onsemi	0:098463de4c5d	758	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
group-onsemi	0:098463de4c5d	759
group-onsemi	0:098463de4c5d	760	/* Cache Size Selection Register */
group-onsemi	0:098463de4c5d	761	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
group-onsemi	0:098463de4c5d	762	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
group-onsemi	0:098463de4c5d	763
group-onsemi	0:098463de4c5d	764	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
group-onsemi	0:098463de4c5d	765	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
group-onsemi	0:098463de4c5d	766
group-onsemi	0:098463de4c5d	767	/* SCB Software Triggered Interrupt Register */
group-onsemi	0:098463de4c5d	768	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
group-onsemi	0:098463de4c5d	769	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
group-onsemi	0:098463de4c5d	770
group-onsemi	0:098463de4c5d	771	/* Instruction Tightly-Coupled Memory Control Register*/
group-onsemi	0:098463de4c5d	772	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
group-onsemi	0:098463de4c5d	773	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
group-onsemi	0:098463de4c5d	774
group-onsemi	0:098463de4c5d	775	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
group-onsemi	0:098463de4c5d	776	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
group-onsemi	0:098463de4c5d	777
group-onsemi	0:098463de4c5d	778	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
group-onsemi	0:098463de4c5d	779	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
group-onsemi	0:098463de4c5d	780
group-onsemi	0:098463de4c5d	781	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
group-onsemi	0:098463de4c5d	782	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
group-onsemi	0:098463de4c5d	783
group-onsemi	0:098463de4c5d	784	/* Data Tightly-Coupled Memory Control Registers */
group-onsemi	0:098463de4c5d	785	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
group-onsemi	0:098463de4c5d	786	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
group-onsemi	0:098463de4c5d	787
group-onsemi	0:098463de4c5d	788	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
group-onsemi	0:098463de4c5d	789	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
group-onsemi	0:098463de4c5d	790
group-onsemi	0:098463de4c5d	791	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
group-onsemi	0:098463de4c5d	792	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
group-onsemi	0:098463de4c5d	793
group-onsemi	0:098463de4c5d	794	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
group-onsemi	0:098463de4c5d	795	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
group-onsemi	0:098463de4c5d	796
group-onsemi	0:098463de4c5d	797	/* AHBP Control Register */
group-onsemi	0:098463de4c5d	798	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
group-onsemi	0:098463de4c5d	799	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
group-onsemi	0:098463de4c5d	800
group-onsemi	0:098463de4c5d	801	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
group-onsemi	0:098463de4c5d	802	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
group-onsemi	0:098463de4c5d	803
group-onsemi	0:098463de4c5d	804	/* L1 Cache Control Register */
group-onsemi	0:098463de4c5d	805	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
group-onsemi	0:098463de4c5d	806	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
group-onsemi	0:098463de4c5d	807
group-onsemi	0:098463de4c5d	808	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
group-onsemi	0:098463de4c5d	809	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
group-onsemi	0:098463de4c5d	810
group-onsemi	0:098463de4c5d	811	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
group-onsemi	0:098463de4c5d	812	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
group-onsemi	0:098463de4c5d	813
group-onsemi	0:098463de4c5d	814	/* AHBS control register */
group-onsemi	0:098463de4c5d	815	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
group-onsemi	0:098463de4c5d	816	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
group-onsemi	0:098463de4c5d	817
group-onsemi	0:098463de4c5d	818	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
group-onsemi	0:098463de4c5d	819	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
group-onsemi	0:098463de4c5d	820
group-onsemi	0:098463de4c5d	821	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
group-onsemi	0:098463de4c5d	822	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
group-onsemi	0:098463de4c5d	823
group-onsemi	0:098463de4c5d	824	/* Auxiliary Bus Fault Status Register */
group-onsemi	0:098463de4c5d	825	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
group-onsemi	0:098463de4c5d	826	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
group-onsemi	0:098463de4c5d	827
group-onsemi	0:098463de4c5d	828	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
group-onsemi	0:098463de4c5d	829	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
group-onsemi	0:098463de4c5d	830
group-onsemi	0:098463de4c5d	831	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
group-onsemi	0:098463de4c5d	832	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
group-onsemi	0:098463de4c5d	833
group-onsemi	0:098463de4c5d	834	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
group-onsemi	0:098463de4c5d	835	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
group-onsemi	0:098463de4c5d	836
group-onsemi	0:098463de4c5d	837	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
group-onsemi	0:098463de4c5d	838	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
group-onsemi	0:098463de4c5d	839
group-onsemi	0:098463de4c5d	840	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
group-onsemi	0:098463de4c5d	841	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
group-onsemi	0:098463de4c5d	842
group-onsemi	0:098463de4c5d	843	/@} end of group CMSIS_SCB /
group-onsemi	0:098463de4c5d	844
group-onsemi	0:098463de4c5d	845
group-onsemi	0:098463de4c5d	846	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	847	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
group-onsemi	0:098463de4c5d	848	\brief Type definitions for the System Control and ID Register not in the SCB
group-onsemi	0:098463de4c5d	849	@{
group-onsemi	0:098463de4c5d	850	*/
group-onsemi	0:098463de4c5d	851
group-onsemi	0:098463de4c5d	852	/** \brief Structure type to access the System Control and ID Register not in the SCB.
group-onsemi	0:098463de4c5d	853	*/
group-onsemi	0:098463de4c5d	854	typedef struct
group-onsemi	0:098463de4c5d	855	{
group-onsemi	0:098463de4c5d	856	uint32_t RESERVED0[1];
group-onsemi	0:098463de4c5d	857	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
group-onsemi	0:098463de4c5d	858	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
group-onsemi	0:098463de4c5d	859	} SCnSCB_Type;
group-onsemi	0:098463de4c5d	860
group-onsemi	0:098463de4c5d	861	/* Interrupt Controller Type Register Definitions */
group-onsemi	0:098463de4c5d	862	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
group-onsemi	0:098463de4c5d	863	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
group-onsemi	0:098463de4c5d	864
group-onsemi	0:098463de4c5d	865	/* Auxiliary Control Register Definitions */
group-onsemi	0:098463de4c5d	866	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
group-onsemi	0:098463de4c5d	867	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
group-onsemi	0:098463de4c5d	868
group-onsemi	0:098463de4c5d	869	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
group-onsemi	0:098463de4c5d	870	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
group-onsemi	0:098463de4c5d	871
group-onsemi	0:098463de4c5d	872	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
group-onsemi	0:098463de4c5d	873	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
group-onsemi	0:098463de4c5d	874
group-onsemi	0:098463de4c5d	875	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
group-onsemi	0:098463de4c5d	876	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
group-onsemi	0:098463de4c5d	877
group-onsemi	0:098463de4c5d	878	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
group-onsemi	0:098463de4c5d	879	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
group-onsemi	0:098463de4c5d	880
group-onsemi	0:098463de4c5d	881	/@} end of group CMSIS_SCnotSCB /
group-onsemi	0:098463de4c5d	882
group-onsemi	0:098463de4c5d	883
group-onsemi	0:098463de4c5d	884	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	885	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
group-onsemi	0:098463de4c5d	886	\brief Type definitions for the System Timer Registers.
group-onsemi	0:098463de4c5d	887	@{
group-onsemi	0:098463de4c5d	888	*/
group-onsemi	0:098463de4c5d	889
group-onsemi	0:098463de4c5d	890	/** \brief Structure type to access the System Timer (SysTick).
group-onsemi	0:098463de4c5d	891	*/
group-onsemi	0:098463de4c5d	892	typedef struct
group-onsemi	0:098463de4c5d	893	{
group-onsemi	0:098463de4c5d	894	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
group-onsemi	0:098463de4c5d	895	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
group-onsemi	0:098463de4c5d	896	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
group-onsemi	0:098463de4c5d	897	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
group-onsemi	0:098463de4c5d	898	} SysTick_Type;
group-onsemi	0:098463de4c5d	899
group-onsemi	0:098463de4c5d	900	/* SysTick Control / Status Register Definitions */
group-onsemi	0:098463de4c5d	901	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
group-onsemi	0:098463de4c5d	902	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
group-onsemi	0:098463de4c5d	903
group-onsemi	0:098463de4c5d	904	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
group-onsemi	0:098463de4c5d	905	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
group-onsemi	0:098463de4c5d	906
group-onsemi	0:098463de4c5d	907	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
group-onsemi	0:098463de4c5d	908	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
group-onsemi	0:098463de4c5d	909
group-onsemi	0:098463de4c5d	910	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
group-onsemi	0:098463de4c5d	911	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
group-onsemi	0:098463de4c5d	912
group-onsemi	0:098463de4c5d	913	/* SysTick Reload Register Definitions */
group-onsemi	0:098463de4c5d	914	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
group-onsemi	0:098463de4c5d	915	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
group-onsemi	0:098463de4c5d	916
group-onsemi	0:098463de4c5d	917	/* SysTick Current Register Definitions */
group-onsemi	0:098463de4c5d	918	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
group-onsemi	0:098463de4c5d	919	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
group-onsemi	0:098463de4c5d	920
group-onsemi	0:098463de4c5d	921	/* SysTick Calibration Register Definitions */
group-onsemi	0:098463de4c5d	922	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
group-onsemi	0:098463de4c5d	923	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
group-onsemi	0:098463de4c5d	924
group-onsemi	0:098463de4c5d	925	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
group-onsemi	0:098463de4c5d	926	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
group-onsemi	0:098463de4c5d	927
group-onsemi	0:098463de4c5d	928	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
group-onsemi	0:098463de4c5d	929	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
group-onsemi	0:098463de4c5d	930
group-onsemi	0:098463de4c5d	931	/@} end of group CMSIS_SysTick /
group-onsemi	0:098463de4c5d	932
group-onsemi	0:098463de4c5d	933
group-onsemi	0:098463de4c5d	934	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	935	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
group-onsemi	0:098463de4c5d	936	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
group-onsemi	0:098463de4c5d	937	@{
group-onsemi	0:098463de4c5d	938	*/
group-onsemi	0:098463de4c5d	939
group-onsemi	0:098463de4c5d	940	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
group-onsemi	0:098463de4c5d	941	*/
group-onsemi	0:098463de4c5d	942	typedef struct
group-onsemi	0:098463de4c5d	943	{
group-onsemi	0:098463de4c5d	944	__O union
group-onsemi	0:098463de4c5d	945	{
group-onsemi	0:098463de4c5d	946	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
group-onsemi	0:098463de4c5d	947	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
group-onsemi	0:098463de4c5d	948	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
group-onsemi	0:098463de4c5d	949	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
group-onsemi	0:098463de4c5d	950	uint32_t RESERVED0[864];
group-onsemi	0:098463de4c5d	951	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
group-onsemi	0:098463de4c5d	952	uint32_t RESERVED1[15];
group-onsemi	0:098463de4c5d	953	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
group-onsemi	0:098463de4c5d	954	uint32_t RESERVED2[15];
group-onsemi	0:098463de4c5d	955	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
group-onsemi	0:098463de4c5d	956	uint32_t RESERVED3[29];
group-onsemi	0:098463de4c5d	957	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
group-onsemi	0:098463de4c5d	958	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
group-onsemi	0:098463de4c5d	959	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
group-onsemi	0:098463de4c5d	960	uint32_t RESERVED4[43];
group-onsemi	0:098463de4c5d	961	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
group-onsemi	0:098463de4c5d	962	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
group-onsemi	0:098463de4c5d	963	uint32_t RESERVED5[6];
group-onsemi	0:098463de4c5d	964	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
group-onsemi	0:098463de4c5d	965	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
group-onsemi	0:098463de4c5d	966	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
group-onsemi	0:098463de4c5d	967	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
group-onsemi	0:098463de4c5d	968	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
group-onsemi	0:098463de4c5d	969	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
group-onsemi	0:098463de4c5d	970	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
group-onsemi	0:098463de4c5d	971	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
group-onsemi	0:098463de4c5d	972	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
group-onsemi	0:098463de4c5d	973	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
group-onsemi	0:098463de4c5d	974	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
group-onsemi	0:098463de4c5d	975	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
group-onsemi	0:098463de4c5d	976	} ITM_Type;
group-onsemi	0:098463de4c5d	977
group-onsemi	0:098463de4c5d	978	/* ITM Trace Privilege Register Definitions */
group-onsemi	0:098463de4c5d	979	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
group-onsemi	0:098463de4c5d	980	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
group-onsemi	0:098463de4c5d	981
group-onsemi	0:098463de4c5d	982	/* ITM Trace Control Register Definitions */
group-onsemi	0:098463de4c5d	983	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
group-onsemi	0:098463de4c5d	984	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
group-onsemi	0:098463de4c5d	985
group-onsemi	0:098463de4c5d	986	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
group-onsemi	0:098463de4c5d	987	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
group-onsemi	0:098463de4c5d	988
group-onsemi	0:098463de4c5d	989	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
group-onsemi	0:098463de4c5d	990	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
group-onsemi	0:098463de4c5d	991
group-onsemi	0:098463de4c5d	992	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
group-onsemi	0:098463de4c5d	993	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
group-onsemi	0:098463de4c5d	994
group-onsemi	0:098463de4c5d	995	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
group-onsemi	0:098463de4c5d	996	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
group-onsemi	0:098463de4c5d	997
group-onsemi	0:098463de4c5d	998	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
group-onsemi	0:098463de4c5d	999	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
group-onsemi	0:098463de4c5d	1000
group-onsemi	0:098463de4c5d	1001	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
group-onsemi	0:098463de4c5d	1002	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
group-onsemi	0:098463de4c5d	1003
group-onsemi	0:098463de4c5d	1004	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
group-onsemi	0:098463de4c5d	1005	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
group-onsemi	0:098463de4c5d	1006
group-onsemi	0:098463de4c5d	1007	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
group-onsemi	0:098463de4c5d	1008	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
group-onsemi	0:098463de4c5d	1009
group-onsemi	0:098463de4c5d	1010	/* ITM Integration Write Register Definitions */
group-onsemi	0:098463de4c5d	1011	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
group-onsemi	0:098463de4c5d	1012	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
group-onsemi	0:098463de4c5d	1013
group-onsemi	0:098463de4c5d	1014	/* ITM Integration Read Register Definitions */
group-onsemi	0:098463de4c5d	1015	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
group-onsemi	0:098463de4c5d	1016	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
group-onsemi	0:098463de4c5d	1017
group-onsemi	0:098463de4c5d	1018	/* ITM Integration Mode Control Register Definitions */
group-onsemi	0:098463de4c5d	1019	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
group-onsemi	0:098463de4c5d	1020	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
group-onsemi	0:098463de4c5d	1021
group-onsemi	0:098463de4c5d	1022	/* ITM Lock Status Register Definitions */
group-onsemi	0:098463de4c5d	1023	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
group-onsemi	0:098463de4c5d	1024	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
group-onsemi	0:098463de4c5d	1025
group-onsemi	0:098463de4c5d	1026	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
group-onsemi	0:098463de4c5d	1027	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
group-onsemi	0:098463de4c5d	1028
group-onsemi	0:098463de4c5d	1029	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
group-onsemi	0:098463de4c5d	1030	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
group-onsemi	0:098463de4c5d	1031
group-onsemi	0:098463de4c5d	1032	/@}/ /* end of group CMSIS_ITM */
group-onsemi	0:098463de4c5d	1033
group-onsemi	0:098463de4c5d	1034
group-onsemi	0:098463de4c5d	1035	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	1036	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
group-onsemi	0:098463de4c5d	1037	\brief Type definitions for the Data Watchpoint and Trace (DWT)
group-onsemi	0:098463de4c5d	1038	@{
group-onsemi	0:098463de4c5d	1039	*/
group-onsemi	0:098463de4c5d	1040
group-onsemi	0:098463de4c5d	1041	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
group-onsemi	0:098463de4c5d	1042	*/
group-onsemi	0:098463de4c5d	1043	typedef struct
group-onsemi	0:098463de4c5d	1044	{
group-onsemi	0:098463de4c5d	1045	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
group-onsemi	0:098463de4c5d	1046	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
group-onsemi	0:098463de4c5d	1047	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
group-onsemi	0:098463de4c5d	1048	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
group-onsemi	0:098463de4c5d	1049	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
group-onsemi	0:098463de4c5d	1050	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
group-onsemi	0:098463de4c5d	1051	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
group-onsemi	0:098463de4c5d	1052	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
group-onsemi	0:098463de4c5d	1053	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
group-onsemi	0:098463de4c5d	1054	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
group-onsemi	0:098463de4c5d	1055	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
group-onsemi	0:098463de4c5d	1056	uint32_t RESERVED0[1];
group-onsemi	0:098463de4c5d	1057	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
group-onsemi	0:098463de4c5d	1058	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
group-onsemi	0:098463de4c5d	1059	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
group-onsemi	0:098463de4c5d	1060	uint32_t RESERVED1[1];
group-onsemi	0:098463de4c5d	1061	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
group-onsemi	0:098463de4c5d	1062	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
group-onsemi	0:098463de4c5d	1063	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
group-onsemi	0:098463de4c5d	1064	uint32_t RESERVED2[1];
group-onsemi	0:098463de4c5d	1065	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
group-onsemi	0:098463de4c5d	1066	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
group-onsemi	0:098463de4c5d	1067	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
group-onsemi	0:098463de4c5d	1068	uint32_t RESERVED3[981];
group-onsemi	0:098463de4c5d	1069	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
group-onsemi	0:098463de4c5d	1070	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
group-onsemi	0:098463de4c5d	1071	} DWT_Type;
group-onsemi	0:098463de4c5d	1072
group-onsemi	0:098463de4c5d	1073	/* DWT Control Register Definitions */
group-onsemi	0:098463de4c5d	1074	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
group-onsemi	0:098463de4c5d	1075	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
group-onsemi	0:098463de4c5d	1076
group-onsemi	0:098463de4c5d	1077	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
group-onsemi	0:098463de4c5d	1078	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
group-onsemi	0:098463de4c5d	1079
group-onsemi	0:098463de4c5d	1080	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
group-onsemi	0:098463de4c5d	1081	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
group-onsemi	0:098463de4c5d	1082
group-onsemi	0:098463de4c5d	1083	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
group-onsemi	0:098463de4c5d	1084	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
group-onsemi	0:098463de4c5d	1085
group-onsemi	0:098463de4c5d	1086	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
group-onsemi	0:098463de4c5d	1087	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
group-onsemi	0:098463de4c5d	1088
group-onsemi	0:098463de4c5d	1089	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
group-onsemi	0:098463de4c5d	1090	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
group-onsemi	0:098463de4c5d	1091
group-onsemi	0:098463de4c5d	1092	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
group-onsemi	0:098463de4c5d	1093	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
group-onsemi	0:098463de4c5d	1094
group-onsemi	0:098463de4c5d	1095	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
group-onsemi	0:098463de4c5d	1096	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
group-onsemi	0:098463de4c5d	1097
group-onsemi	0:098463de4c5d	1098	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
group-onsemi	0:098463de4c5d	1099	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
group-onsemi	0:098463de4c5d	1100
group-onsemi	0:098463de4c5d	1101	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
group-onsemi	0:098463de4c5d	1102	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
group-onsemi	0:098463de4c5d	1103
group-onsemi	0:098463de4c5d	1104	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
group-onsemi	0:098463de4c5d	1105	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
group-onsemi	0:098463de4c5d	1106
group-onsemi	0:098463de4c5d	1107	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
group-onsemi	0:098463de4c5d	1108	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
group-onsemi	0:098463de4c5d	1109
group-onsemi	0:098463de4c5d	1110	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
group-onsemi	0:098463de4c5d	1111	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
group-onsemi	0:098463de4c5d	1112
group-onsemi	0:098463de4c5d	1113	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
group-onsemi	0:098463de4c5d	1114	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
group-onsemi	0:098463de4c5d	1115
group-onsemi	0:098463de4c5d	1116	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
group-onsemi	0:098463de4c5d	1117	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
group-onsemi	0:098463de4c5d	1118
group-onsemi	0:098463de4c5d	1119	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
group-onsemi	0:098463de4c5d	1120	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
group-onsemi	0:098463de4c5d	1121
group-onsemi	0:098463de4c5d	1122	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
group-onsemi	0:098463de4c5d	1123	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
group-onsemi	0:098463de4c5d	1124
group-onsemi	0:098463de4c5d	1125	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
group-onsemi	0:098463de4c5d	1126	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
group-onsemi	0:098463de4c5d	1127
group-onsemi	0:098463de4c5d	1128	/* DWT CPI Count Register Definitions */
group-onsemi	0:098463de4c5d	1129	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
group-onsemi	0:098463de4c5d	1130	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
group-onsemi	0:098463de4c5d	1131
group-onsemi	0:098463de4c5d	1132	/* DWT Exception Overhead Count Register Definitions */
group-onsemi	0:098463de4c5d	1133	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
group-onsemi	0:098463de4c5d	1134	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
group-onsemi	0:098463de4c5d	1135
group-onsemi	0:098463de4c5d	1136	/* DWT Sleep Count Register Definitions */
group-onsemi	0:098463de4c5d	1137	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
group-onsemi	0:098463de4c5d	1138	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
group-onsemi	0:098463de4c5d	1139
group-onsemi	0:098463de4c5d	1140	/* DWT LSU Count Register Definitions */
group-onsemi	0:098463de4c5d	1141	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
group-onsemi	0:098463de4c5d	1142	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
group-onsemi	0:098463de4c5d	1143
group-onsemi	0:098463de4c5d	1144	/* DWT Folded-instruction Count Register Definitions */
group-onsemi	0:098463de4c5d	1145	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
group-onsemi	0:098463de4c5d	1146	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
group-onsemi	0:098463de4c5d	1147
group-onsemi	0:098463de4c5d	1148	/* DWT Comparator Mask Register Definitions */
group-onsemi	0:098463de4c5d	1149	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
group-onsemi	0:098463de4c5d	1150	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
group-onsemi	0:098463de4c5d	1151
group-onsemi	0:098463de4c5d	1152	/* DWT Comparator Function Register Definitions */
group-onsemi	0:098463de4c5d	1153	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
group-onsemi	0:098463de4c5d	1154	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
group-onsemi	0:098463de4c5d	1155
group-onsemi	0:098463de4c5d	1156	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
group-onsemi	0:098463de4c5d	1157	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
group-onsemi	0:098463de4c5d	1158
group-onsemi	0:098463de4c5d	1159	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
group-onsemi	0:098463de4c5d	1160	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
group-onsemi	0:098463de4c5d	1161
group-onsemi	0:098463de4c5d	1162	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
group-onsemi	0:098463de4c5d	1163	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
group-onsemi	0:098463de4c5d	1164
group-onsemi	0:098463de4c5d	1165	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
group-onsemi	0:098463de4c5d	1166	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
group-onsemi	0:098463de4c5d	1167
group-onsemi	0:098463de4c5d	1168	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
group-onsemi	0:098463de4c5d	1169	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
group-onsemi	0:098463de4c5d	1170
group-onsemi	0:098463de4c5d	1171	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
group-onsemi	0:098463de4c5d	1172	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
group-onsemi	0:098463de4c5d	1173
group-onsemi	0:098463de4c5d	1174	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
group-onsemi	0:098463de4c5d	1175	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
group-onsemi	0:098463de4c5d	1176
group-onsemi	0:098463de4c5d	1177	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
group-onsemi	0:098463de4c5d	1178	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
group-onsemi	0:098463de4c5d	1179
group-onsemi	0:098463de4c5d	1180	/@}/ /* end of group CMSIS_DWT */
group-onsemi	0:098463de4c5d	1181
group-onsemi	0:098463de4c5d	1182
group-onsemi	0:098463de4c5d	1183	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	1184	\defgroup CMSIS_TPI Trace Port Interface (TPI)
group-onsemi	0:098463de4c5d	1185	\brief Type definitions for the Trace Port Interface (TPI)
group-onsemi	0:098463de4c5d	1186	@{
group-onsemi	0:098463de4c5d	1187	*/
group-onsemi	0:098463de4c5d	1188
group-onsemi	0:098463de4c5d	1189	/** \brief Structure type to access the Trace Port Interface Register (TPI).
group-onsemi	0:098463de4c5d	1190	*/
group-onsemi	0:098463de4c5d	1191	typedef struct
group-onsemi	0:098463de4c5d	1192	{
group-onsemi	0:098463de4c5d	1193	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
group-onsemi	0:098463de4c5d	1194	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
group-onsemi	0:098463de4c5d	1195	uint32_t RESERVED0[2];
group-onsemi	0:098463de4c5d	1196	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
group-onsemi	0:098463de4c5d	1197	uint32_t RESERVED1[55];
group-onsemi	0:098463de4c5d	1198	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
group-onsemi	0:098463de4c5d	1199	uint32_t RESERVED2[131];
group-onsemi	0:098463de4c5d	1200	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
group-onsemi	0:098463de4c5d	1201	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
group-onsemi	0:098463de4c5d	1202	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
group-onsemi	0:098463de4c5d	1203	uint32_t RESERVED3[759];
group-onsemi	0:098463de4c5d	1204	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
group-onsemi	0:098463de4c5d	1205	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
group-onsemi	0:098463de4c5d	1206	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
group-onsemi	0:098463de4c5d	1207	uint32_t RESERVED4[1];
group-onsemi	0:098463de4c5d	1208	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
group-onsemi	0:098463de4c5d	1209	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
group-onsemi	0:098463de4c5d	1210	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
group-onsemi	0:098463de4c5d	1211	uint32_t RESERVED5[39];
group-onsemi	0:098463de4c5d	1212	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
group-onsemi	0:098463de4c5d	1213	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
group-onsemi	0:098463de4c5d	1214	uint32_t RESERVED7[8];
group-onsemi	0:098463de4c5d	1215	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
group-onsemi	0:098463de4c5d	1216	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
group-onsemi	0:098463de4c5d	1217	} TPI_Type;
group-onsemi	0:098463de4c5d	1218
group-onsemi	0:098463de4c5d	1219	/* TPI Asynchronous Clock Prescaler Register Definitions */
group-onsemi	0:098463de4c5d	1220	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
group-onsemi	0:098463de4c5d	1221	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
group-onsemi	0:098463de4c5d	1222
group-onsemi	0:098463de4c5d	1223	/* TPI Selected Pin Protocol Register Definitions */
group-onsemi	0:098463de4c5d	1224	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
group-onsemi	0:098463de4c5d	1225	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
group-onsemi	0:098463de4c5d	1226
group-onsemi	0:098463de4c5d	1227	/* TPI Formatter and Flush Status Register Definitions */
group-onsemi	0:098463de4c5d	1228	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
group-onsemi	0:098463de4c5d	1229	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
group-onsemi	0:098463de4c5d	1230
group-onsemi	0:098463de4c5d	1231	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
group-onsemi	0:098463de4c5d	1232	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
group-onsemi	0:098463de4c5d	1233
group-onsemi	0:098463de4c5d	1234	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
group-onsemi	0:098463de4c5d	1235	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
group-onsemi	0:098463de4c5d	1236
group-onsemi	0:098463de4c5d	1237	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
group-onsemi	0:098463de4c5d	1238	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
group-onsemi	0:098463de4c5d	1239
group-onsemi	0:098463de4c5d	1240	/* TPI Formatter and Flush Control Register Definitions */
group-onsemi	0:098463de4c5d	1241	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
group-onsemi	0:098463de4c5d	1242	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
group-onsemi	0:098463de4c5d	1243
group-onsemi	0:098463de4c5d	1244	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
group-onsemi	0:098463de4c5d	1245	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
group-onsemi	0:098463de4c5d	1246
group-onsemi	0:098463de4c5d	1247	/* TPI TRIGGER Register Definitions */
group-onsemi	0:098463de4c5d	1248	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
group-onsemi	0:098463de4c5d	1249	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
group-onsemi	0:098463de4c5d	1250
group-onsemi	0:098463de4c5d	1251	/* TPI Integration ETM Data Register Definitions (FIFO0) */
group-onsemi	0:098463de4c5d	1252	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
group-onsemi	0:098463de4c5d	1253	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
group-onsemi	0:098463de4c5d	1254
group-onsemi	0:098463de4c5d	1255	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
group-onsemi	0:098463de4c5d	1256	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
group-onsemi	0:098463de4c5d	1257
group-onsemi	0:098463de4c5d	1258	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
group-onsemi	0:098463de4c5d	1259	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
group-onsemi	0:098463de4c5d	1260
group-onsemi	0:098463de4c5d	1261	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
group-onsemi	0:098463de4c5d	1262	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
group-onsemi	0:098463de4c5d	1263
group-onsemi	0:098463de4c5d	1264	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
group-onsemi	0:098463de4c5d	1265	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
group-onsemi	0:098463de4c5d	1266
group-onsemi	0:098463de4c5d	1267	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
group-onsemi	0:098463de4c5d	1268	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
group-onsemi	0:098463de4c5d	1269
group-onsemi	0:098463de4c5d	1270	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
group-onsemi	0:098463de4c5d	1271	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
group-onsemi	0:098463de4c5d	1272
group-onsemi	0:098463de4c5d	1273	/* TPI ITATBCTR2 Register Definitions */
group-onsemi	0:098463de4c5d	1274	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
group-onsemi	0:098463de4c5d	1275	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
group-onsemi	0:098463de4c5d	1276
group-onsemi	0:098463de4c5d	1277	/* TPI Integration ITM Data Register Definitions (FIFO1) */
group-onsemi	0:098463de4c5d	1278	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
group-onsemi	0:098463de4c5d	1279	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
group-onsemi	0:098463de4c5d	1280
group-onsemi	0:098463de4c5d	1281	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
group-onsemi	0:098463de4c5d	1282	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
group-onsemi	0:098463de4c5d	1283
group-onsemi	0:098463de4c5d	1284	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
group-onsemi	0:098463de4c5d	1285	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
group-onsemi	0:098463de4c5d	1286
group-onsemi	0:098463de4c5d	1287	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
group-onsemi	0:098463de4c5d	1288	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
group-onsemi	0:098463de4c5d	1289
group-onsemi	0:098463de4c5d	1290	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
group-onsemi	0:098463de4c5d	1291	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
group-onsemi	0:098463de4c5d	1292
group-onsemi	0:098463de4c5d	1293	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
group-onsemi	0:098463de4c5d	1294	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
group-onsemi	0:098463de4c5d	1295
group-onsemi	0:098463de4c5d	1296	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
group-onsemi	0:098463de4c5d	1297	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
group-onsemi	0:098463de4c5d	1298
group-onsemi	0:098463de4c5d	1299	/* TPI ITATBCTR0 Register Definitions */
group-onsemi	0:098463de4c5d	1300	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
group-onsemi	0:098463de4c5d	1301	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
group-onsemi	0:098463de4c5d	1302
group-onsemi	0:098463de4c5d	1303	/* TPI Integration Mode Control Register Definitions */
group-onsemi	0:098463de4c5d	1304	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
group-onsemi	0:098463de4c5d	1305	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
group-onsemi	0:098463de4c5d	1306
group-onsemi	0:098463de4c5d	1307	/* TPI DEVID Register Definitions */
group-onsemi	0:098463de4c5d	1308	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
group-onsemi	0:098463de4c5d	1309	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
group-onsemi	0:098463de4c5d	1310
group-onsemi	0:098463de4c5d	1311	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
group-onsemi	0:098463de4c5d	1312	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
group-onsemi	0:098463de4c5d	1313
group-onsemi	0:098463de4c5d	1314	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
group-onsemi	0:098463de4c5d	1315	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
group-onsemi	0:098463de4c5d	1316
group-onsemi	0:098463de4c5d	1317	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
group-onsemi	0:098463de4c5d	1318	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
group-onsemi	0:098463de4c5d	1319
group-onsemi	0:098463de4c5d	1320	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
group-onsemi	0:098463de4c5d	1321	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
group-onsemi	0:098463de4c5d	1322
group-onsemi	0:098463de4c5d	1323	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
group-onsemi	0:098463de4c5d	1324	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
group-onsemi	0:098463de4c5d	1325
group-onsemi	0:098463de4c5d	1326	/* TPI DEVTYPE Register Definitions */
group-onsemi	0:098463de4c5d	1327	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
group-onsemi	0:098463de4c5d	1328	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
group-onsemi	0:098463de4c5d	1329
group-onsemi	0:098463de4c5d	1330	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
group-onsemi	0:098463de4c5d	1331	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
group-onsemi	0:098463de4c5d	1332
group-onsemi	0:098463de4c5d	1333	/@}/ /* end of group CMSIS_TPI */
group-onsemi	0:098463de4c5d	1334
group-onsemi	0:098463de4c5d	1335
group-onsemi	0:098463de4c5d	1336	#if (__MPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	1337	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	1338	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
group-onsemi	0:098463de4c5d	1339	\brief Type definitions for the Memory Protection Unit (MPU)
group-onsemi	0:098463de4c5d	1340	@{
group-onsemi	0:098463de4c5d	1341	*/
group-onsemi	0:098463de4c5d	1342
group-onsemi	0:098463de4c5d	1343	/** \brief Structure type to access the Memory Protection Unit (MPU).
group-onsemi	0:098463de4c5d	1344	*/
group-onsemi	0:098463de4c5d	1345	typedef struct
group-onsemi	0:098463de4c5d	1346	{
group-onsemi	0:098463de4c5d	1347	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
group-onsemi	0:098463de4c5d	1348	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
group-onsemi	0:098463de4c5d	1349	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
group-onsemi	0:098463de4c5d	1350	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
group-onsemi	0:098463de4c5d	1351	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
group-onsemi	0:098463de4c5d	1352	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
group-onsemi	0:098463de4c5d	1353	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
group-onsemi	0:098463de4c5d	1354	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
group-onsemi	0:098463de4c5d	1355	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
group-onsemi	0:098463de4c5d	1356	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
group-onsemi	0:098463de4c5d	1357	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
group-onsemi	0:098463de4c5d	1358	} MPU_Type;
group-onsemi	0:098463de4c5d	1359
group-onsemi	0:098463de4c5d	1360	/* MPU Type Register */
group-onsemi	0:098463de4c5d	1361	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
group-onsemi	0:098463de4c5d	1362	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
group-onsemi	0:098463de4c5d	1363
group-onsemi	0:098463de4c5d	1364	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
group-onsemi	0:098463de4c5d	1365	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
group-onsemi	0:098463de4c5d	1366
group-onsemi	0:098463de4c5d	1367	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
group-onsemi	0:098463de4c5d	1368	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
group-onsemi	0:098463de4c5d	1369
group-onsemi	0:098463de4c5d	1370	/* MPU Control Register */
group-onsemi	0:098463de4c5d	1371	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
group-onsemi	0:098463de4c5d	1372	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
group-onsemi	0:098463de4c5d	1373
group-onsemi	0:098463de4c5d	1374	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
group-onsemi	0:098463de4c5d	1375	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
group-onsemi	0:098463de4c5d	1376
group-onsemi	0:098463de4c5d	1377	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
group-onsemi	0:098463de4c5d	1378	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
group-onsemi	0:098463de4c5d	1379
group-onsemi	0:098463de4c5d	1380	/* MPU Region Number Register */
group-onsemi	0:098463de4c5d	1381	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
group-onsemi	0:098463de4c5d	1382	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
group-onsemi	0:098463de4c5d	1383
group-onsemi	0:098463de4c5d	1384	/* MPU Region Base Address Register */
group-onsemi	0:098463de4c5d	1385	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
group-onsemi	0:098463de4c5d	1386	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
group-onsemi	0:098463de4c5d	1387
group-onsemi	0:098463de4c5d	1388	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
group-onsemi	0:098463de4c5d	1389	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
group-onsemi	0:098463de4c5d	1390
group-onsemi	0:098463de4c5d	1391	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
group-onsemi	0:098463de4c5d	1392	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
group-onsemi	0:098463de4c5d	1393
group-onsemi	0:098463de4c5d	1394	/* MPU Region Attribute and Size Register */
group-onsemi	0:098463de4c5d	1395	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
group-onsemi	0:098463de4c5d	1396	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
group-onsemi	0:098463de4c5d	1397
group-onsemi	0:098463de4c5d	1398	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
group-onsemi	0:098463de4c5d	1399	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
group-onsemi	0:098463de4c5d	1400
group-onsemi	0:098463de4c5d	1401	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
group-onsemi	0:098463de4c5d	1402	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
group-onsemi	0:098463de4c5d	1403
group-onsemi	0:098463de4c5d	1404	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
group-onsemi	0:098463de4c5d	1405	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
group-onsemi	0:098463de4c5d	1406
group-onsemi	0:098463de4c5d	1407	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
group-onsemi	0:098463de4c5d	1408	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
group-onsemi	0:098463de4c5d	1409
group-onsemi	0:098463de4c5d	1410	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
group-onsemi	0:098463de4c5d	1411	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
group-onsemi	0:098463de4c5d	1412
group-onsemi	0:098463de4c5d	1413	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
group-onsemi	0:098463de4c5d	1414	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
group-onsemi	0:098463de4c5d	1415
group-onsemi	0:098463de4c5d	1416	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
group-onsemi	0:098463de4c5d	1417	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
group-onsemi	0:098463de4c5d	1418
group-onsemi	0:098463de4c5d	1419	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
group-onsemi	0:098463de4c5d	1420	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
group-onsemi	0:098463de4c5d	1421
group-onsemi	0:098463de4c5d	1422	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
group-onsemi	0:098463de4c5d	1423	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
group-onsemi	0:098463de4c5d	1424
group-onsemi	0:098463de4c5d	1425	/@} end of group CMSIS_MPU /
group-onsemi	0:098463de4c5d	1426	#endif
group-onsemi	0:098463de4c5d	1427
group-onsemi	0:098463de4c5d	1428
group-onsemi	0:098463de4c5d	1429	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	1430	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	1431	\defgroup CMSIS_FPU Floating Point Unit (FPU)
group-onsemi	0:098463de4c5d	1432	\brief Type definitions for the Floating Point Unit (FPU)
group-onsemi	0:098463de4c5d	1433	@{
group-onsemi	0:098463de4c5d	1434	*/
group-onsemi	0:098463de4c5d	1435
group-onsemi	0:098463de4c5d	1436	/** \brief Structure type to access the Floating Point Unit (FPU).
group-onsemi	0:098463de4c5d	1437	*/
group-onsemi	0:098463de4c5d	1438	typedef struct
group-onsemi	0:098463de4c5d	1439	{
group-onsemi	0:098463de4c5d	1440	uint32_t RESERVED0[1];
group-onsemi	0:098463de4c5d	1441	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
group-onsemi	0:098463de4c5d	1442	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
group-onsemi	0:098463de4c5d	1443	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
group-onsemi	0:098463de4c5d	1444	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
group-onsemi	0:098463de4c5d	1445	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
group-onsemi	0:098463de4c5d	1446	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
group-onsemi	0:098463de4c5d	1447	} FPU_Type;
group-onsemi	0:098463de4c5d	1448
group-onsemi	0:098463de4c5d	1449	/* Floating-Point Context Control Register */
group-onsemi	0:098463de4c5d	1450	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
group-onsemi	0:098463de4c5d	1451	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
group-onsemi	0:098463de4c5d	1452
group-onsemi	0:098463de4c5d	1453	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
group-onsemi	0:098463de4c5d	1454	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
group-onsemi	0:098463de4c5d	1455
group-onsemi	0:098463de4c5d	1456	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
group-onsemi	0:098463de4c5d	1457	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
group-onsemi	0:098463de4c5d	1458
group-onsemi	0:098463de4c5d	1459	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
group-onsemi	0:098463de4c5d	1460	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
group-onsemi	0:098463de4c5d	1461
group-onsemi	0:098463de4c5d	1462	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
group-onsemi	0:098463de4c5d	1463	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
group-onsemi	0:098463de4c5d	1464
group-onsemi	0:098463de4c5d	1465	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
group-onsemi	0:098463de4c5d	1466	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
group-onsemi	0:098463de4c5d	1467
group-onsemi	0:098463de4c5d	1468	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
group-onsemi	0:098463de4c5d	1469	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
group-onsemi	0:098463de4c5d	1470
group-onsemi	0:098463de4c5d	1471	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
group-onsemi	0:098463de4c5d	1472	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
group-onsemi	0:098463de4c5d	1473
group-onsemi	0:098463de4c5d	1474	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
group-onsemi	0:098463de4c5d	1475	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
group-onsemi	0:098463de4c5d	1476
group-onsemi	0:098463de4c5d	1477	/* Floating-Point Context Address Register */
group-onsemi	0:098463de4c5d	1478	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
group-onsemi	0:098463de4c5d	1479	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
group-onsemi	0:098463de4c5d	1480
group-onsemi	0:098463de4c5d	1481	/* Floating-Point Default Status Control Register */
group-onsemi	0:098463de4c5d	1482	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
group-onsemi	0:098463de4c5d	1483	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
group-onsemi	0:098463de4c5d	1484
group-onsemi	0:098463de4c5d	1485	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
group-onsemi	0:098463de4c5d	1486	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
group-onsemi	0:098463de4c5d	1487
group-onsemi	0:098463de4c5d	1488	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
group-onsemi	0:098463de4c5d	1489	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
group-onsemi	0:098463de4c5d	1490
group-onsemi	0:098463de4c5d	1491	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
group-onsemi	0:098463de4c5d	1492	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
group-onsemi	0:098463de4c5d	1493
group-onsemi	0:098463de4c5d	1494	/* Media and FP Feature Register 0 */
group-onsemi	0:098463de4c5d	1495	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
group-onsemi	0:098463de4c5d	1496	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
group-onsemi	0:098463de4c5d	1497
group-onsemi	0:098463de4c5d	1498	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
group-onsemi	0:098463de4c5d	1499	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
group-onsemi	0:098463de4c5d	1500
group-onsemi	0:098463de4c5d	1501	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
group-onsemi	0:098463de4c5d	1502	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
group-onsemi	0:098463de4c5d	1503
group-onsemi	0:098463de4c5d	1504	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
group-onsemi	0:098463de4c5d	1505	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
group-onsemi	0:098463de4c5d	1506
group-onsemi	0:098463de4c5d	1507	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
group-onsemi	0:098463de4c5d	1508	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
group-onsemi	0:098463de4c5d	1509
group-onsemi	0:098463de4c5d	1510	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
group-onsemi	0:098463de4c5d	1511	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
group-onsemi	0:098463de4c5d	1512
group-onsemi	0:098463de4c5d	1513	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
group-onsemi	0:098463de4c5d	1514	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
group-onsemi	0:098463de4c5d	1515
group-onsemi	0:098463de4c5d	1516	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
group-onsemi	0:098463de4c5d	1517	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
group-onsemi	0:098463de4c5d	1518
group-onsemi	0:098463de4c5d	1519	/* Media and FP Feature Register 1 */
group-onsemi	0:098463de4c5d	1520	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
group-onsemi	0:098463de4c5d	1521	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
group-onsemi	0:098463de4c5d	1522
group-onsemi	0:098463de4c5d	1523	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
group-onsemi	0:098463de4c5d	1524	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
group-onsemi	0:098463de4c5d	1525
group-onsemi	0:098463de4c5d	1526	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
group-onsemi	0:098463de4c5d	1527	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
group-onsemi	0:098463de4c5d	1528
group-onsemi	0:098463de4c5d	1529	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
group-onsemi	0:098463de4c5d	1530	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
group-onsemi	0:098463de4c5d	1531
group-onsemi	0:098463de4c5d	1532	/* Media and FP Feature Register 2 */
group-onsemi	0:098463de4c5d	1533
group-onsemi	0:098463de4c5d	1534	/@} end of group CMSIS_FPU /
group-onsemi	0:098463de4c5d	1535	#endif
group-onsemi	0:098463de4c5d	1536
group-onsemi	0:098463de4c5d	1537
group-onsemi	0:098463de4c5d	1538	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	1539	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
group-onsemi	0:098463de4c5d	1540	\brief Type definitions for the Core Debug Registers
group-onsemi	0:098463de4c5d	1541	@{
group-onsemi	0:098463de4c5d	1542	*/
group-onsemi	0:098463de4c5d	1543
group-onsemi	0:098463de4c5d	1544	/** \brief Structure type to access the Core Debug Register (CoreDebug).
group-onsemi	0:098463de4c5d	1545	*/
group-onsemi	0:098463de4c5d	1546	typedef struct
group-onsemi	0:098463de4c5d	1547	{
group-onsemi	0:098463de4c5d	1548	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
group-onsemi	0:098463de4c5d	1549	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
group-onsemi	0:098463de4c5d	1550	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
group-onsemi	0:098463de4c5d	1551	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
group-onsemi	0:098463de4c5d	1552	} CoreDebug_Type;
group-onsemi	0:098463de4c5d	1553
group-onsemi	0:098463de4c5d	1554	/* Debug Halting Control and Status Register */
group-onsemi	0:098463de4c5d	1555	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
group-onsemi	0:098463de4c5d	1556	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
group-onsemi	0:098463de4c5d	1557
group-onsemi	0:098463de4c5d	1558	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
group-onsemi	0:098463de4c5d	1559	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
group-onsemi	0:098463de4c5d	1560
group-onsemi	0:098463de4c5d	1561	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
group-onsemi	0:098463de4c5d	1562	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
group-onsemi	0:098463de4c5d	1563
group-onsemi	0:098463de4c5d	1564	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
group-onsemi	0:098463de4c5d	1565	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
group-onsemi	0:098463de4c5d	1566
group-onsemi	0:098463de4c5d	1567	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
group-onsemi	0:098463de4c5d	1568	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
group-onsemi	0:098463de4c5d	1569
group-onsemi	0:098463de4c5d	1570	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
group-onsemi	0:098463de4c5d	1571	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
group-onsemi	0:098463de4c5d	1572
group-onsemi	0:098463de4c5d	1573	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
group-onsemi	0:098463de4c5d	1574	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
group-onsemi	0:098463de4c5d	1575
group-onsemi	0:098463de4c5d	1576	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
group-onsemi	0:098463de4c5d	1577	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
group-onsemi	0:098463de4c5d	1578
group-onsemi	0:098463de4c5d	1579	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
group-onsemi	0:098463de4c5d	1580	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
group-onsemi	0:098463de4c5d	1581
group-onsemi	0:098463de4c5d	1582	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
group-onsemi	0:098463de4c5d	1583	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
group-onsemi	0:098463de4c5d	1584
group-onsemi	0:098463de4c5d	1585	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
group-onsemi	0:098463de4c5d	1586	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
group-onsemi	0:098463de4c5d	1587
group-onsemi	0:098463de4c5d	1588	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
group-onsemi	0:098463de4c5d	1589	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
group-onsemi	0:098463de4c5d	1590
group-onsemi	0:098463de4c5d	1591	/* Debug Core Register Selector Register */
group-onsemi	0:098463de4c5d	1592	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
group-onsemi	0:098463de4c5d	1593	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
group-onsemi	0:098463de4c5d	1594
group-onsemi	0:098463de4c5d	1595	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
group-onsemi	0:098463de4c5d	1596	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
group-onsemi	0:098463de4c5d	1597
group-onsemi	0:098463de4c5d	1598	/* Debug Exception and Monitor Control Register */
group-onsemi	0:098463de4c5d	1599	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
group-onsemi	0:098463de4c5d	1600	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
group-onsemi	0:098463de4c5d	1601
group-onsemi	0:098463de4c5d	1602	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
group-onsemi	0:098463de4c5d	1603	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
group-onsemi	0:098463de4c5d	1604
group-onsemi	0:098463de4c5d	1605	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
group-onsemi	0:098463de4c5d	1606	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
group-onsemi	0:098463de4c5d	1607
group-onsemi	0:098463de4c5d	1608	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
group-onsemi	0:098463de4c5d	1609	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
group-onsemi	0:098463de4c5d	1610
group-onsemi	0:098463de4c5d	1611	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
group-onsemi	0:098463de4c5d	1612	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
group-onsemi	0:098463de4c5d	1613
group-onsemi	0:098463de4c5d	1614	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
group-onsemi	0:098463de4c5d	1615	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
group-onsemi	0:098463de4c5d	1616
group-onsemi	0:098463de4c5d	1617	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
group-onsemi	0:098463de4c5d	1618	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
group-onsemi	0:098463de4c5d	1619
group-onsemi	0:098463de4c5d	1620	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
group-onsemi	0:098463de4c5d	1621	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
group-onsemi	0:098463de4c5d	1622
group-onsemi	0:098463de4c5d	1623	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
group-onsemi	0:098463de4c5d	1624	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
group-onsemi	0:098463de4c5d	1625
group-onsemi	0:098463de4c5d	1626	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
group-onsemi	0:098463de4c5d	1627	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
group-onsemi	0:098463de4c5d	1628
group-onsemi	0:098463de4c5d	1629	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
group-onsemi	0:098463de4c5d	1630	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
group-onsemi	0:098463de4c5d	1631
group-onsemi	0:098463de4c5d	1632	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
group-onsemi	0:098463de4c5d	1633	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
group-onsemi	0:098463de4c5d	1634
group-onsemi	0:098463de4c5d	1635	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
group-onsemi	0:098463de4c5d	1636	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
group-onsemi	0:098463de4c5d	1637
group-onsemi	0:098463de4c5d	1638	/@} end of group CMSIS_CoreDebug /
group-onsemi	0:098463de4c5d	1639
group-onsemi	0:098463de4c5d	1640
group-onsemi	0:098463de4c5d	1641	/** \ingroup CMSIS_core_register
group-onsemi	0:098463de4c5d	1642	\defgroup CMSIS_core_base Core Definitions
group-onsemi	0:098463de4c5d	1643	\brief Definitions for base addresses, unions, and structures.
group-onsemi	0:098463de4c5d	1644	@{
group-onsemi	0:098463de4c5d	1645	*/
group-onsemi	0:098463de4c5d	1646
group-onsemi	0:098463de4c5d	1647	/* Memory mapping of Cortex-M4 Hardware */
group-onsemi	0:098463de4c5d	1648	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
group-onsemi	0:098463de4c5d	1649	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
group-onsemi	0:098463de4c5d	1650	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
group-onsemi	0:098463de4c5d	1651	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
group-onsemi	0:098463de4c5d	1652	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
group-onsemi	0:098463de4c5d	1653	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
group-onsemi	0:098463de4c5d	1654	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
group-onsemi	0:098463de4c5d	1655	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
group-onsemi	0:098463de4c5d	1656
group-onsemi	0:098463de4c5d	1657	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
group-onsemi	0:098463de4c5d	1658	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
group-onsemi	0:098463de4c5d	1659	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
group-onsemi	0:098463de4c5d	1660	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
group-onsemi	0:098463de4c5d	1661	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
group-onsemi	0:098463de4c5d	1662	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
group-onsemi	0:098463de4c5d	1663	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
group-onsemi	0:098463de4c5d	1664	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
group-onsemi	0:098463de4c5d	1665
group-onsemi	0:098463de4c5d	1666	#if (__MPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	1667	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
group-onsemi	0:098463de4c5d	1668	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
group-onsemi	0:098463de4c5d	1669	#endif
group-onsemi	0:098463de4c5d	1670
group-onsemi	0:098463de4c5d	1671	#if (__FPU_PRESENT == 1)
group-onsemi	0:098463de4c5d	1672	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
group-onsemi	0:098463de4c5d	1673	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
group-onsemi	0:098463de4c5d	1674	#endif
group-onsemi	0:098463de4c5d	1675
group-onsemi	0:098463de4c5d	1676	/@} /
group-onsemi	0:098463de4c5d	1677
group-onsemi	0:098463de4c5d	1678
group-onsemi	0:098463de4c5d	1679
group-onsemi	0:098463de4c5d	1680	/*******************************************************************************
group-onsemi	0:098463de4c5d	1681	* Hardware Abstraction Layer
group-onsemi	0:098463de4c5d	1682	Core Function Interface contains:
group-onsemi	0:098463de4c5d	1683	- Core NVIC Functions
group-onsemi	0:098463de4c5d	1684	- Core SysTick Functions
group-onsemi	0:098463de4c5d	1685	- Core Debug Functions
group-onsemi	0:098463de4c5d	1686	- Core Register Access Functions
group-onsemi	0:098463de4c5d	1687	******************************************************************************/
group-onsemi	0:098463de4c5d	1688	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
group-onsemi	0:098463de4c5d	1689	*/
group-onsemi	0:098463de4c5d	1690
group-onsemi	0:098463de4c5d	1691
group-onsemi	0:098463de4c5d	1692
group-onsemi	0:098463de4c5d	1693	/* ########################## NVIC functions #################################### */
group-onsemi	0:098463de4c5d	1694	/** \ingroup CMSIS_Core_FunctionInterface
group-onsemi	0:098463de4c5d	1695	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
group-onsemi	0:098463de4c5d	1696	\brief Functions that manage interrupts and exceptions via the NVIC.
group-onsemi	0:098463de4c5d	1697	@{
group-onsemi	0:098463de4c5d	1698	*/
group-onsemi	0:098463de4c5d	1699
group-onsemi	0:098463de4c5d	1700	/** \brief Set Priority Grouping
group-onsemi	0:098463de4c5d	1701
group-onsemi	0:098463de4c5d	1702	The function sets the priority grouping field using the required unlock sequence.
group-onsemi	0:098463de4c5d	1703	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
group-onsemi	0:098463de4c5d	1704	Only values from 0..7 are used.
group-onsemi	0:098463de4c5d	1705	In case of a conflict between priority grouping and available
group-onsemi	0:098463de4c5d	1706	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
group-onsemi	0:098463de4c5d	1707
group-onsemi	0:098463de4c5d	1708	\param [in] PriorityGroup Priority grouping field.
group-onsemi	0:098463de4c5d	1709	*/
group-onsemi	0:098463de4c5d	1710	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
group-onsemi	0:098463de4c5d	1711	{
group-onsemi	0:098463de4c5d	1712	uint32_t reg_value;
group-onsemi	0:098463de4c5d	1713	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
group-onsemi	0:098463de4c5d	1714
group-onsemi	0:098463de4c5d	1715	reg_value = SCB->AIRCR; /* read old register configuration */
group-onsemi	0:098463de4c5d	1716	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
group-onsemi	0:098463de4c5d	1717	reg_value = (reg_value \|
group-onsemi	0:098463de4c5d	1718	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
group-onsemi	0:098463de4c5d	1719	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
group-onsemi	0:098463de4c5d	1720	SCB->AIRCR = reg_value;
group-onsemi	0:098463de4c5d	1721	}
group-onsemi	0:098463de4c5d	1722
group-onsemi	0:098463de4c5d	1723
group-onsemi	0:098463de4c5d	1724	/** \brief Get Priority Grouping
group-onsemi	0:098463de4c5d	1725
group-onsemi	0:098463de4c5d	1726	The function reads the priority grouping field from the NVIC Interrupt Controller.
group-onsemi	0:098463de4c5d	1727
group-onsemi	0:098463de4c5d	1728	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
group-onsemi	0:098463de4c5d	1729	*/
group-onsemi	0:098463de4c5d	1730	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
group-onsemi	0:098463de4c5d	1731	{
group-onsemi	0:098463de4c5d	1732	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
group-onsemi	0:098463de4c5d	1733	}
group-onsemi	0:098463de4c5d	1734
group-onsemi	0:098463de4c5d	1735
group-onsemi	0:098463de4c5d	1736	/** \brief Enable External Interrupt
group-onsemi	0:098463de4c5d	1737
group-onsemi	0:098463de4c5d	1738	The function enables a device-specific interrupt in the NVIC interrupt controller.
group-onsemi	0:098463de4c5d	1739
group-onsemi	0:098463de4c5d	1740	\param [in] IRQn External interrupt number. Value cannot be negative.
group-onsemi	0:098463de4c5d	1741	*/
group-onsemi	0:098463de4c5d	1742	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1743	{
group-onsemi	0:098463de4c5d	1744	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi	0:098463de4c5d	1745	}
group-onsemi	0:098463de4c5d	1746
group-onsemi	0:098463de4c5d	1747
group-onsemi	0:098463de4c5d	1748	/** \brief Disable External Interrupt
group-onsemi	0:098463de4c5d	1749
group-onsemi	0:098463de4c5d	1750	The function disables a device-specific interrupt in the NVIC interrupt controller.
group-onsemi	0:098463de4c5d	1751
group-onsemi	0:098463de4c5d	1752	\param [in] IRQn External interrupt number. Value cannot be negative.
group-onsemi	0:098463de4c5d	1753	*/
group-onsemi	0:098463de4c5d	1754	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1755	{
group-onsemi	0:098463de4c5d	1756	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi	0:098463de4c5d	1757	__DSB();
group-onsemi	0:098463de4c5d	1758	__ISB();
group-onsemi	0:098463de4c5d	1759	}
group-onsemi	0:098463de4c5d	1760
group-onsemi	0:098463de4c5d	1761
group-onsemi	0:098463de4c5d	1762	/** \brief Get Pending Interrupt
group-onsemi	0:098463de4c5d	1763
group-onsemi	0:098463de4c5d	1764	The function reads the pending register in the NVIC and returns the pending bit
group-onsemi	0:098463de4c5d	1765	for the specified interrupt.
group-onsemi	0:098463de4c5d	1766
group-onsemi	0:098463de4c5d	1767	\param [in] IRQn Interrupt number.
group-onsemi	0:098463de4c5d	1768
group-onsemi	0:098463de4c5d	1769	\return 0 Interrupt status is not pending.
group-onsemi	0:098463de4c5d	1770	\return 1 Interrupt status is pending.
group-onsemi	0:098463de4c5d	1771	*/
group-onsemi	0:098463de4c5d	1772	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1773	{
group-onsemi	0:098463de4c5d	1774	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
group-onsemi	0:098463de4c5d	1775	}
group-onsemi	0:098463de4c5d	1776
group-onsemi	0:098463de4c5d	1777
group-onsemi	0:098463de4c5d	1778	/** \brief Set Pending Interrupt
group-onsemi	0:098463de4c5d	1779
group-onsemi	0:098463de4c5d	1780	The function sets the pending bit of an external interrupt.
group-onsemi	0:098463de4c5d	1781
group-onsemi	0:098463de4c5d	1782	\param [in] IRQn Interrupt number. Value cannot be negative.
group-onsemi	0:098463de4c5d	1783	*/
group-onsemi	0:098463de4c5d	1784	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1785	{
group-onsemi	0:098463de4c5d	1786	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi	0:098463de4c5d	1787	}
group-onsemi	0:098463de4c5d	1788
group-onsemi	0:098463de4c5d	1789
group-onsemi	0:098463de4c5d	1790	/** \brief Clear Pending Interrupt
group-onsemi	0:098463de4c5d	1791
group-onsemi	0:098463de4c5d	1792	The function clears the pending bit of an external interrupt.
group-onsemi	0:098463de4c5d	1793
group-onsemi	0:098463de4c5d	1794	\param [in] IRQn External interrupt number. Value cannot be negative.
group-onsemi	0:098463de4c5d	1795	*/
group-onsemi	0:098463de4c5d	1796	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1797	{
group-onsemi	0:098463de4c5d	1798	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi	0:098463de4c5d	1799	}
group-onsemi	0:098463de4c5d	1800
group-onsemi	0:098463de4c5d	1801
group-onsemi	0:098463de4c5d	1802	/** \brief Get Active Interrupt
group-onsemi	0:098463de4c5d	1803
group-onsemi	0:098463de4c5d	1804	The function reads the active register in NVIC and returns the active bit.
group-onsemi	0:098463de4c5d	1805
group-onsemi	0:098463de4c5d	1806	\param [in] IRQn Interrupt number.
group-onsemi	0:098463de4c5d	1807
group-onsemi	0:098463de4c5d	1808	\return 0 Interrupt status is not active.
group-onsemi	0:098463de4c5d	1809	\return 1 Interrupt status is active.
group-onsemi	0:098463de4c5d	1810	*/
group-onsemi	0:098463de4c5d	1811	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1812	{
group-onsemi	0:098463de4c5d	1813	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
group-onsemi	0:098463de4c5d	1814	}
group-onsemi	0:098463de4c5d	1815
group-onsemi	0:098463de4c5d	1816
group-onsemi	0:098463de4c5d	1817	/** \brief Set Interrupt Priority
group-onsemi	0:098463de4c5d	1818
group-onsemi	0:098463de4c5d	1819	The function sets the priority of an interrupt.
group-onsemi	0:098463de4c5d	1820
group-onsemi	0:098463de4c5d	1821	\note The priority cannot be set for every core interrupt.
group-onsemi	0:098463de4c5d	1822
group-onsemi	0:098463de4c5d	1823	\param [in] IRQn Interrupt number.
group-onsemi	0:098463de4c5d	1824	\param [in] priority Priority to set.
group-onsemi	0:098463de4c5d	1825	*/
group-onsemi	0:098463de4c5d	1826	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
group-onsemi	0:098463de4c5d	1827	{
group-onsemi	0:098463de4c5d	1828	if((int32_t)IRQn < 0) {
group-onsemi	0:098463de4c5d	1829	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
group-onsemi	0:098463de4c5d	1830	}
group-onsemi	0:098463de4c5d	1831	else {
group-onsemi	0:098463de4c5d	1832	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
group-onsemi	0:098463de4c5d	1833	}
group-onsemi	0:098463de4c5d	1834	}
group-onsemi	0:098463de4c5d	1835
group-onsemi	0:098463de4c5d	1836
group-onsemi	0:098463de4c5d	1837	/** \brief Get Interrupt Priority
group-onsemi	0:098463de4c5d	1838
group-onsemi	0:098463de4c5d	1839	The function reads the priority of an interrupt. The interrupt
group-onsemi	0:098463de4c5d	1840	number can be positive to specify an external (device specific)
group-onsemi	0:098463de4c5d	1841	interrupt, or negative to specify an internal (core) interrupt.
group-onsemi	0:098463de4c5d	1842
group-onsemi	0:098463de4c5d	1843
group-onsemi	0:098463de4c5d	1844	\param [in] IRQn Interrupt number.
group-onsemi	0:098463de4c5d	1845	\return Interrupt Priority. Value is aligned automatically to the implemented
group-onsemi	0:098463de4c5d	1846	priority bits of the microcontroller.
group-onsemi	0:098463de4c5d	1847	*/
group-onsemi	0:098463de4c5d	1848	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
group-onsemi	0:098463de4c5d	1849	{
group-onsemi	0:098463de4c5d	1850
group-onsemi	0:098463de4c5d	1851	if((int32_t)IRQn < 0) {
group-onsemi	0:098463de4c5d	1852	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
group-onsemi	0:098463de4c5d	1853	}
group-onsemi	0:098463de4c5d	1854	else {
group-onsemi	0:098463de4c5d	1855	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
group-onsemi	0:098463de4c5d	1856	}
group-onsemi	0:098463de4c5d	1857	}
group-onsemi	0:098463de4c5d	1858
group-onsemi	0:098463de4c5d	1859
group-onsemi	0:098463de4c5d	1860	/** \brief Encode Priority
group-onsemi	0:098463de4c5d	1861
group-onsemi	0:098463de4c5d	1862	The function encodes the priority for an interrupt with the given priority group,
group-onsemi	0:098463de4c5d	1863	preemptive priority value, and subpriority value.
group-onsemi	0:098463de4c5d	1864	In case of a conflict between priority grouping and available
group-onsemi	0:098463de4c5d	1865	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
group-onsemi	0:098463de4c5d	1866
group-onsemi	0:098463de4c5d	1867	\param [in] PriorityGroup Used priority group.
group-onsemi	0:098463de4c5d	1868	\param [in] PreemptPriority Preemptive priority value (starting from 0).
group-onsemi	0:098463de4c5d	1869	\param [in] SubPriority Subpriority value (starting from 0).
group-onsemi	0:098463de4c5d	1870	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
group-onsemi	0:098463de4c5d	1871	*/
group-onsemi	0:098463de4c5d	1872	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
group-onsemi	0:098463de4c5d	1873	{
group-onsemi	0:098463de4c5d	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
group-onsemi	0:098463de4c5d	1875	uint32_t PreemptPriorityBits;
group-onsemi	0:098463de4c5d	1876	uint32_t SubPriorityBits;
group-onsemi	0:098463de4c5d	1877
group-onsemi	0:098463de4c5d	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
group-onsemi	0:098463de4c5d	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
group-onsemi	0:098463de4c5d	1880
group-onsemi	0:098463de4c5d	1881	return (
group-onsemi	0:098463de4c5d	1882	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
group-onsemi	0:098463de4c5d	1883	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
group-onsemi	0:098463de4c5d	1884	);
group-onsemi	0:098463de4c5d	1885	}
group-onsemi	0:098463de4c5d	1886
group-onsemi	0:098463de4c5d	1887
group-onsemi	0:098463de4c5d	1888	/** \brief Decode Priority
group-onsemi	0:098463de4c5d	1889
group-onsemi	0:098463de4c5d	1890	The function decodes an interrupt priority value with a given priority group to
group-onsemi	0:098463de4c5d	1891	preemptive priority value and subpriority value.
group-onsemi	0:098463de4c5d	1892	In case of a conflict between priority grouping and available
group-onsemi	0:098463de4c5d	1893	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
group-onsemi	0:098463de4c5d	1894
group-onsemi	0:098463de4c5d	1895	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
group-onsemi	0:098463de4c5d	1896	\param [in] PriorityGroup Used priority group.
group-onsemi	0:098463de4c5d	1897	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
group-onsemi	0:098463de4c5d	1898	\param [out] pSubPriority Subpriority value (starting from 0).
group-onsemi	0:098463de4c5d	1899	*/
group-onsemi	0:098463de4c5d	1900	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
group-onsemi	0:098463de4c5d	1901	{
group-onsemi	0:098463de4c5d	1902	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
group-onsemi	0:098463de4c5d	1903	uint32_t PreemptPriorityBits;
group-onsemi	0:098463de4c5d	1904	uint32_t SubPriorityBits;
group-onsemi	0:098463de4c5d	1905
group-onsemi	0:098463de4c5d	1906	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
group-onsemi	0:098463de4c5d	1907	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
group-onsemi	0:098463de4c5d	1908
group-onsemi	0:098463de4c5d	1909	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
group-onsemi	0:098463de4c5d	1910	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
group-onsemi	0:098463de4c5d	1911	}
group-onsemi	0:098463de4c5d	1912
group-onsemi	0:098463de4c5d	1913
group-onsemi	0:098463de4c5d	1914	/** \brief System Reset
group-onsemi	0:098463de4c5d	1915
group-onsemi	0:098463de4c5d	1916	The function initiates a system reset request to reset the MCU.
group-onsemi	0:098463de4c5d	1917	*/
group-onsemi	0:098463de4c5d	1918	__STATIC_INLINE void NVIC_SystemReset(void)
group-onsemi	0:098463de4c5d	1919	{
group-onsemi	0:098463de4c5d	1920	__DSB(); /* Ensure all outstanding memory accesses included
group-onsemi	0:098463de4c5d	1921	buffered write are completed before reset */
group-onsemi	0:098463de4c5d	1922	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
group-onsemi	0:098463de4c5d	1923	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
group-onsemi	0:098463de4c5d	1924	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
group-onsemi	0:098463de4c5d	1925	__DSB(); /* Ensure completion of memory access */
group-onsemi	0:098463de4c5d	1926	while(1) { __NOP(); } /* wait until reset */
group-onsemi	0:098463de4c5d	1927	}
group-onsemi	0:098463de4c5d	1928
group-onsemi	0:098463de4c5d	1929	/@} end of CMSIS_Core_NVICFunctions /
group-onsemi	0:098463de4c5d	1930
group-onsemi	0:098463de4c5d	1931
group-onsemi	0:098463de4c5d	1932	/* ########################## FPU functions #################################### */
group-onsemi	0:098463de4c5d	1933	/** \ingroup CMSIS_Core_FunctionInterface
group-onsemi	0:098463de4c5d	1934	\defgroup CMSIS_Core_FpuFunctions FPU Functions
group-onsemi	0:098463de4c5d	1935	\brief Function that provides FPU type.
group-onsemi	0:098463de4c5d	1936	@{
group-onsemi	0:098463de4c5d	1937	*/
group-onsemi	0:098463de4c5d	1938
group-onsemi	0:098463de4c5d	1939	/**
group-onsemi	0:098463de4c5d	1940	\fn uint32_t SCB_GetFPUType(void)
group-onsemi	0:098463de4c5d	1941	\brief get FPU type
group-onsemi	0:098463de4c5d	1942	\returns
group-onsemi	0:098463de4c5d	1943	- \b 0: No FPU
group-onsemi	0:098463de4c5d	1944	- \b 1: Single precision FPU
group-onsemi	0:098463de4c5d	1945	- \b 2: Double + Single precision FPU
group-onsemi	0:098463de4c5d	1946	*/
group-onsemi	0:098463de4c5d	1947	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
group-onsemi	0:098463de4c5d	1948	{
group-onsemi	0:098463de4c5d	1949	uint32_t mvfr0;
group-onsemi	0:098463de4c5d	1950
group-onsemi	0:098463de4c5d	1951	mvfr0 = SCB->MVFR0;
group-onsemi	0:098463de4c5d	1952	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
group-onsemi	0:098463de4c5d	1953	return 2UL; // Double + Single precision FPU
group-onsemi	0:098463de4c5d	1954	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
group-onsemi	0:098463de4c5d	1955	return 1UL; // Single precision FPU
group-onsemi	0:098463de4c5d	1956	} else {
group-onsemi	0:098463de4c5d	1957	return 0UL; // No FPU
group-onsemi	0:098463de4c5d	1958	}
group-onsemi	0:098463de4c5d	1959	}
group-onsemi	0:098463de4c5d	1960
group-onsemi	0:098463de4c5d	1961
group-onsemi	0:098463de4c5d	1962	/@} end of CMSIS_Core_FpuFunctions /
group-onsemi	0:098463de4c5d	1963
group-onsemi	0:098463de4c5d	1964
group-onsemi	0:098463de4c5d	1965
group-onsemi	0:098463de4c5d	1966	/* ########################## Cache functions #################################### */
group-onsemi	0:098463de4c5d	1967	/** \ingroup CMSIS_Core_FunctionInterface
group-onsemi	0:098463de4c5d	1968	\defgroup CMSIS_Core_CacheFunctions Cache Functions
group-onsemi	0:098463de4c5d	1969	\brief Functions that configure Instruction and Data cache.
group-onsemi	0:098463de4c5d	1970	@{
group-onsemi	0:098463de4c5d	1971	*/
group-onsemi	0:098463de4c5d	1972
group-onsemi	0:098463de4c5d	1973	/* Cache Size ID Register Macros */
group-onsemi	0:098463de4c5d	1974	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
group-onsemi	0:098463de4c5d	1975	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
group-onsemi	0:098463de4c5d	1976	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
group-onsemi	0:098463de4c5d	1977
group-onsemi	0:098463de4c5d	1978
group-onsemi	0:098463de4c5d	1979	/** \brief Enable I-Cache
group-onsemi	0:098463de4c5d	1980
group-onsemi	0:098463de4c5d	1981	The function turns on I-Cache
group-onsemi	0:098463de4c5d	1982	*/
group-onsemi	0:098463de4c5d	1983	__STATIC_INLINE void SCB_EnableICache (void)
group-onsemi	0:098463de4c5d	1984	{
group-onsemi	0:098463de4c5d	1985	#if (__ICACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	1986	__DSB();
group-onsemi	0:098463de4c5d	1987	__ISB();
group-onsemi	0:098463de4c5d	1988	SCB->ICIALLU = 0UL; // invalidate I-Cache
group-onsemi	0:098463de4c5d	1989	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
group-onsemi	0:098463de4c5d	1990	__DSB();
group-onsemi	0:098463de4c5d	1991	__ISB();
group-onsemi	0:098463de4c5d	1992	#endif
group-onsemi	0:098463de4c5d	1993	}
group-onsemi	0:098463de4c5d	1994
group-onsemi	0:098463de4c5d	1995
group-onsemi	0:098463de4c5d	1996	/** \brief Disable I-Cache
group-onsemi	0:098463de4c5d	1997
group-onsemi	0:098463de4c5d	1998	The function turns off I-Cache
group-onsemi	0:098463de4c5d	1999	*/
group-onsemi	0:098463de4c5d	2000	__STATIC_INLINE void SCB_DisableICache (void)
group-onsemi	0:098463de4c5d	2001	{
group-onsemi	0:098463de4c5d	2002	#if (__ICACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2003	__DSB();
group-onsemi	0:098463de4c5d	2004	__ISB();
group-onsemi	0:098463de4c5d	2005	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
group-onsemi	0:098463de4c5d	2006	SCB->ICIALLU = 0UL; // invalidate I-Cache
group-onsemi	0:098463de4c5d	2007	__DSB();
group-onsemi	0:098463de4c5d	2008	__ISB();
group-onsemi	0:098463de4c5d	2009	#endif
group-onsemi	0:098463de4c5d	2010	}
group-onsemi	0:098463de4c5d	2011
group-onsemi	0:098463de4c5d	2012
group-onsemi	0:098463de4c5d	2013	/** \brief Invalidate I-Cache
group-onsemi	0:098463de4c5d	2014
group-onsemi	0:098463de4c5d	2015	The function invalidates I-Cache
group-onsemi	0:098463de4c5d	2016	*/
group-onsemi	0:098463de4c5d	2017	__STATIC_INLINE void SCB_InvalidateICache (void)
group-onsemi	0:098463de4c5d	2018	{
group-onsemi	0:098463de4c5d	2019	#if (__ICACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2020	__DSB();
group-onsemi	0:098463de4c5d	2021	__ISB();
group-onsemi	0:098463de4c5d	2022	SCB->ICIALLU = 0UL;
group-onsemi	0:098463de4c5d	2023	__DSB();
group-onsemi	0:098463de4c5d	2024	__ISB();
group-onsemi	0:098463de4c5d	2025	#endif
group-onsemi	0:098463de4c5d	2026	}
group-onsemi	0:098463de4c5d	2027
group-onsemi	0:098463de4c5d	2028
group-onsemi	0:098463de4c5d	2029	/** \brief Enable D-Cache
group-onsemi	0:098463de4c5d	2030
group-onsemi	0:098463de4c5d	2031	The function turns on D-Cache
group-onsemi	0:098463de4c5d	2032	*/
group-onsemi	0:098463de4c5d	2033	__STATIC_INLINE void SCB_EnableDCache (void)
group-onsemi	0:098463de4c5d	2034	{
group-onsemi	0:098463de4c5d	2035	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2036	uint32_t ccsidr, sshift, wshift, sw;
group-onsemi	0:098463de4c5d	2037	uint32_t sets, ways;
group-onsemi	0:098463de4c5d	2038
group-onsemi	0:098463de4c5d	2039	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
group-onsemi	0:098463de4c5d	2040	ccsidr = SCB->CCSIDR;
group-onsemi	0:098463de4c5d	2041	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
group-onsemi	0:098463de4c5d	2042	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
group-onsemi	0:098463de4c5d	2043	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
group-onsemi	0:098463de4c5d	2044	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
group-onsemi	0:098463de4c5d	2045
group-onsemi	0:098463de4c5d	2046	__DSB();
group-onsemi	0:098463de4c5d	2047
group-onsemi	0:098463de4c5d	2048	do { // invalidate D-Cache
group-onsemi	0:098463de4c5d	2049	uint32_t tmpways = ways;
group-onsemi	0:098463de4c5d	2050	do {
group-onsemi	0:098463de4c5d	2051	sw = ((tmpways << wshift) \| (sets << sshift));
group-onsemi	0:098463de4c5d	2052	SCB->DCISW = sw;
group-onsemi	0:098463de4c5d	2053	} while(tmpways--);
group-onsemi	0:098463de4c5d	2054	} while(sets--);
group-onsemi	0:098463de4c5d	2055	__DSB();
group-onsemi	0:098463de4c5d	2056
group-onsemi	0:098463de4c5d	2057	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
group-onsemi	0:098463de4c5d	2058
group-onsemi	0:098463de4c5d	2059	__DSB();
group-onsemi	0:098463de4c5d	2060	__ISB();
group-onsemi	0:098463de4c5d	2061	#endif
group-onsemi	0:098463de4c5d	2062	}
group-onsemi	0:098463de4c5d	2063
group-onsemi	0:098463de4c5d	2064
group-onsemi	0:098463de4c5d	2065	/** \brief Disable D-Cache
group-onsemi	0:098463de4c5d	2066
group-onsemi	0:098463de4c5d	2067	The function turns off D-Cache
group-onsemi	0:098463de4c5d	2068	*/
group-onsemi	0:098463de4c5d	2069	__STATIC_INLINE void SCB_DisableDCache (void)
group-onsemi	0:098463de4c5d	2070	{
group-onsemi	0:098463de4c5d	2071	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2072	uint32_t ccsidr, sshift, wshift, sw;
group-onsemi	0:098463de4c5d	2073	uint32_t sets, ways;
group-onsemi	0:098463de4c5d	2074
group-onsemi	0:098463de4c5d	2075	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
group-onsemi	0:098463de4c5d	2076	ccsidr = SCB->CCSIDR;
group-onsemi	0:098463de4c5d	2077	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
group-onsemi	0:098463de4c5d	2078	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
group-onsemi	0:098463de4c5d	2079	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
group-onsemi	0:098463de4c5d	2080	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
group-onsemi	0:098463de4c5d	2081
group-onsemi	0:098463de4c5d	2082	__DSB();
group-onsemi	0:098463de4c5d	2083
group-onsemi	0:098463de4c5d	2084	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
group-onsemi	0:098463de4c5d	2085
group-onsemi	0:098463de4c5d	2086	do { // clean & invalidate D-Cache
group-onsemi	0:098463de4c5d	2087	uint32_t tmpways = ways;
group-onsemi	0:098463de4c5d	2088	do {
group-onsemi	0:098463de4c5d	2089	sw = ((tmpways << wshift) \| (sets << sshift));
group-onsemi	0:098463de4c5d	2090	SCB->DCCISW = sw;
group-onsemi	0:098463de4c5d	2091	} while(tmpways--);
group-onsemi	0:098463de4c5d	2092	} while(sets--);
group-onsemi	0:098463de4c5d	2093
group-onsemi	0:098463de4c5d	2094
group-onsemi	0:098463de4c5d	2095	__DSB();
group-onsemi	0:098463de4c5d	2096	__ISB();
group-onsemi	0:098463de4c5d	2097	#endif
group-onsemi	0:098463de4c5d	2098	}
group-onsemi	0:098463de4c5d	2099
group-onsemi	0:098463de4c5d	2100
group-onsemi	0:098463de4c5d	2101	/** \brief Invalidate D-Cache
group-onsemi	0:098463de4c5d	2102
group-onsemi	0:098463de4c5d	2103	The function invalidates D-Cache
group-onsemi	0:098463de4c5d	2104	*/
group-onsemi	0:098463de4c5d	2105	__STATIC_INLINE void SCB_InvalidateDCache (void)
group-onsemi	0:098463de4c5d	2106	{
group-onsemi	0:098463de4c5d	2107	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2108	uint32_t ccsidr, sshift, wshift, sw;
group-onsemi	0:098463de4c5d	2109	uint32_t sets, ways;
group-onsemi	0:098463de4c5d	2110
group-onsemi	0:098463de4c5d	2111	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
group-onsemi	0:098463de4c5d	2112	ccsidr = SCB->CCSIDR;
group-onsemi	0:098463de4c5d	2113	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
group-onsemi	0:098463de4c5d	2114	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
group-onsemi	0:098463de4c5d	2115	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
group-onsemi	0:098463de4c5d	2116	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
group-onsemi	0:098463de4c5d	2117
group-onsemi	0:098463de4c5d	2118	__DSB();
group-onsemi	0:098463de4c5d	2119
group-onsemi	0:098463de4c5d	2120	do { // invalidate D-Cache
group-onsemi	0:098463de4c5d	2121	uint32_t tmpways = ways;
group-onsemi	0:098463de4c5d	2122	do {
group-onsemi	0:098463de4c5d	2123	sw = ((tmpways << wshift) \| (sets << sshift));
group-onsemi	0:098463de4c5d	2124	SCB->DCISW = sw;
group-onsemi	0:098463de4c5d	2125	} while(tmpways--);
group-onsemi	0:098463de4c5d	2126	} while(sets--);
group-onsemi	0:098463de4c5d	2127
group-onsemi	0:098463de4c5d	2128	__DSB();
group-onsemi	0:098463de4c5d	2129	__ISB();
group-onsemi	0:098463de4c5d	2130	#endif
group-onsemi	0:098463de4c5d	2131	}
group-onsemi	0:098463de4c5d	2132
group-onsemi	0:098463de4c5d	2133
group-onsemi	0:098463de4c5d	2134	/** \brief Clean D-Cache
group-onsemi	0:098463de4c5d	2135
group-onsemi	0:098463de4c5d	2136	The function cleans D-Cache
group-onsemi	0:098463de4c5d	2137	*/
group-onsemi	0:098463de4c5d	2138	__STATIC_INLINE void SCB_CleanDCache (void)
group-onsemi	0:098463de4c5d	2139	{
group-onsemi	0:098463de4c5d	2140	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2141	uint32_t ccsidr, sshift, wshift, sw;
group-onsemi	0:098463de4c5d	2142	uint32_t sets, ways;
group-onsemi	0:098463de4c5d	2143
group-onsemi	0:098463de4c5d	2144	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
group-onsemi	0:098463de4c5d	2145	ccsidr = SCB->CCSIDR;
group-onsemi	0:098463de4c5d	2146	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
group-onsemi	0:098463de4c5d	2147	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
group-onsemi	0:098463de4c5d	2148	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
group-onsemi	0:098463de4c5d	2149	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
group-onsemi	0:098463de4c5d	2150
group-onsemi	0:098463de4c5d	2151	__DSB();
group-onsemi	0:098463de4c5d	2152
group-onsemi	0:098463de4c5d	2153	do { // clean D-Cache
group-onsemi	0:098463de4c5d	2154	uint32_t tmpways = ways;
group-onsemi	0:098463de4c5d	2155	do {
group-onsemi	0:098463de4c5d	2156	sw = ((tmpways << wshift) \| (sets << sshift));
group-onsemi	0:098463de4c5d	2157	SCB->DCCSW = sw;
group-onsemi	0:098463de4c5d	2158	} while(tmpways--);
group-onsemi	0:098463de4c5d	2159	} while(sets--);
group-onsemi	0:098463de4c5d	2160
group-onsemi	0:098463de4c5d	2161	__DSB();
group-onsemi	0:098463de4c5d	2162	__ISB();
group-onsemi	0:098463de4c5d	2163	#endif
group-onsemi	0:098463de4c5d	2164	}
group-onsemi	0:098463de4c5d	2165
group-onsemi	0:098463de4c5d	2166
group-onsemi	0:098463de4c5d	2167	/** \brief Clean & Invalidate D-Cache
group-onsemi	0:098463de4c5d	2168
group-onsemi	0:098463de4c5d	2169	The function cleans and Invalidates D-Cache
group-onsemi	0:098463de4c5d	2170	*/
group-onsemi	0:098463de4c5d	2171	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
group-onsemi	0:098463de4c5d	2172	{
group-onsemi	0:098463de4c5d	2173	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2174	uint32_t ccsidr, sshift, wshift, sw;
group-onsemi	0:098463de4c5d	2175	uint32_t sets, ways;
group-onsemi	0:098463de4c5d	2176
group-onsemi	0:098463de4c5d	2177	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
group-onsemi	0:098463de4c5d	2178	ccsidr = SCB->CCSIDR;
group-onsemi	0:098463de4c5d	2179	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
group-onsemi	0:098463de4c5d	2180	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
group-onsemi	0:098463de4c5d	2181	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
group-onsemi	0:098463de4c5d	2182	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
group-onsemi	0:098463de4c5d	2183
group-onsemi	0:098463de4c5d	2184	__DSB();
group-onsemi	0:098463de4c5d	2185
group-onsemi	0:098463de4c5d	2186	do { // clean & invalidate D-Cache
group-onsemi	0:098463de4c5d	2187	uint32_t tmpways = ways;
group-onsemi	0:098463de4c5d	2188	do {
group-onsemi	0:098463de4c5d	2189	sw = ((tmpways << wshift) \| (sets << sshift));
group-onsemi	0:098463de4c5d	2190	SCB->DCCISW = sw;
group-onsemi	0:098463de4c5d	2191	} while(tmpways--);
group-onsemi	0:098463de4c5d	2192	} while(sets--);
group-onsemi	0:098463de4c5d	2193
group-onsemi	0:098463de4c5d	2194	__DSB();
group-onsemi	0:098463de4c5d	2195	__ISB();
group-onsemi	0:098463de4c5d	2196	#endif
group-onsemi	0:098463de4c5d	2197	}
group-onsemi	0:098463de4c5d	2198
group-onsemi	0:098463de4c5d	2199
group-onsemi	0:098463de4c5d	2200	/**
group-onsemi	0:098463de4c5d	2201	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
group-onsemi	0:098463de4c5d	2202	\brief D-Cache Invalidate by address
group-onsemi	0:098463de4c5d	2203	\param[in] addr address (aligned to 32-byte boundary)
group-onsemi	0:098463de4c5d	2204	\param[in] dsize size of memory block (in number of bytes)
group-onsemi	0:098463de4c5d	2205	*/
group-onsemi	0:098463de4c5d	2206	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
group-onsemi	0:098463de4c5d	2207	{
group-onsemi	0:098463de4c5d	2208	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2209	int32_t op_size = dsize;
group-onsemi	0:098463de4c5d	2210	uint32_t op_addr = (uint32_t)addr;
group-onsemi	0:098463de4c5d	2211	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
group-onsemi	0:098463de4c5d	2212
group-onsemi	0:098463de4c5d	2213	__DSB();
group-onsemi	0:098463de4c5d	2214
group-onsemi	0:098463de4c5d	2215	while (op_size > 0) {
group-onsemi	0:098463de4c5d	2216	SCB->DCIMVAC = op_addr;
group-onsemi	0:098463de4c5d	2217	op_addr += linesize;
group-onsemi	0:098463de4c5d	2218	op_size -= (int32_t)linesize;
group-onsemi	0:098463de4c5d	2219	}
group-onsemi	0:098463de4c5d	2220
group-onsemi	0:098463de4c5d	2221	__DSB();
group-onsemi	0:098463de4c5d	2222	__ISB();
group-onsemi	0:098463de4c5d	2223	#endif
group-onsemi	0:098463de4c5d	2224	}
group-onsemi	0:098463de4c5d	2225
group-onsemi	0:098463de4c5d	2226
group-onsemi	0:098463de4c5d	2227	/**
group-onsemi	0:098463de4c5d	2228	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
group-onsemi	0:098463de4c5d	2229	\brief D-Cache Clean by address
group-onsemi	0:098463de4c5d	2230	\param[in] addr address (aligned to 32-byte boundary)
group-onsemi	0:098463de4c5d	2231	\param[in] dsize size of memory block (in number of bytes)
group-onsemi	0:098463de4c5d	2232	*/
group-onsemi	0:098463de4c5d	2233	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
group-onsemi	0:098463de4c5d	2234	{
group-onsemi	0:098463de4c5d	2235	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2236	int32_t op_size = dsize;
group-onsemi	0:098463de4c5d	2237	uint32_t op_addr = (uint32_t) addr;
group-onsemi	0:098463de4c5d	2238	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
group-onsemi	0:098463de4c5d	2239
group-onsemi	0:098463de4c5d	2240	__DSB();
group-onsemi	0:098463de4c5d	2241
group-onsemi	0:098463de4c5d	2242	while (op_size > 0) {
group-onsemi	0:098463de4c5d	2243	SCB->DCCMVAC = op_addr;
group-onsemi	0:098463de4c5d	2244	op_addr += linesize;
group-onsemi	0:098463de4c5d	2245	op_size -= (int32_t)linesize;
group-onsemi	0:098463de4c5d	2246	}
group-onsemi	0:098463de4c5d	2247
group-onsemi	0:098463de4c5d	2248	__DSB();
group-onsemi	0:098463de4c5d	2249	__ISB();
group-onsemi	0:098463de4c5d	2250	#endif
group-onsemi	0:098463de4c5d	2251	}
group-onsemi	0:098463de4c5d	2252
group-onsemi	0:098463de4c5d	2253
group-onsemi	0:098463de4c5d	2254	/**
group-onsemi	0:098463de4c5d	2255	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
group-onsemi	0:098463de4c5d	2256	\brief D-Cache Clean and Invalidate by address
group-onsemi	0:098463de4c5d	2257	\param[in] addr address (aligned to 32-byte boundary)
group-onsemi	0:098463de4c5d	2258	\param[in] dsize size of memory block (in number of bytes)
group-onsemi	0:098463de4c5d	2259	*/
group-onsemi	0:098463de4c5d	2260	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
group-onsemi	0:098463de4c5d	2261	{
group-onsemi	0:098463de4c5d	2262	#if (__DCACHE_PRESENT == 1)
group-onsemi	0:098463de4c5d	2263	int32_t op_size = dsize;
group-onsemi	0:098463de4c5d	2264	uint32_t op_addr = (uint32_t) addr;
group-onsemi	0:098463de4c5d	2265	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
group-onsemi	0:098463de4c5d	2266
group-onsemi	0:098463de4c5d	2267	__DSB();
group-onsemi	0:098463de4c5d	2268
group-onsemi	0:098463de4c5d	2269	while (op_size > 0) {
group-onsemi	0:098463de4c5d	2270	SCB->DCCIMVAC = op_addr;
group-onsemi	0:098463de4c5d	2271	op_addr += linesize;
group-onsemi	0:098463de4c5d	2272	op_size -= (int32_t)linesize;
group-onsemi	0:098463de4c5d	2273	}
group-onsemi	0:098463de4c5d	2274
group-onsemi	0:098463de4c5d	2275	__DSB();
group-onsemi	0:098463de4c5d	2276	__ISB();
group-onsemi	0:098463de4c5d	2277	#endif
group-onsemi	0:098463de4c5d	2278	}
group-onsemi	0:098463de4c5d	2279
group-onsemi	0:098463de4c5d	2280
group-onsemi	0:098463de4c5d	2281	/@} end of CMSIS_Core_CacheFunctions /
group-onsemi	0:098463de4c5d	2282
group-onsemi	0:098463de4c5d	2283
group-onsemi	0:098463de4c5d	2284
group-onsemi	0:098463de4c5d	2285	/* ################################## SysTick function ############################################ */
group-onsemi	0:098463de4c5d	2286	/** \ingroup CMSIS_Core_FunctionInterface
group-onsemi	0:098463de4c5d	2287	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
group-onsemi	0:098463de4c5d	2288	\brief Functions that configure the System.
group-onsemi	0:098463de4c5d	2289	@{
group-onsemi	0:098463de4c5d	2290	*/
group-onsemi	0:098463de4c5d	2291
group-onsemi	0:098463de4c5d	2292	#if (__Vendor_SysTickConfig == 0)
group-onsemi	0:098463de4c5d	2293
group-onsemi	0:098463de4c5d	2294	/** \brief System Tick Configuration
group-onsemi	0:098463de4c5d	2295
group-onsemi	0:098463de4c5d	2296	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
group-onsemi	0:098463de4c5d	2297	Counter is in free running mode to generate periodic interrupts.
group-onsemi	0:098463de4c5d	2298
group-onsemi	0:098463de4c5d	2299	\param [in] ticks Number of ticks between two interrupts.
group-onsemi	0:098463de4c5d	2300
group-onsemi	0:098463de4c5d	2301	\return 0 Function succeeded.
group-onsemi	0:098463de4c5d	2302	\return 1 Function failed.
group-onsemi	0:098463de4c5d	2303
group-onsemi	0:098463de4c5d	2304	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
group-onsemi	0:098463de4c5d	2305	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
group-onsemi	0:098463de4c5d	2306	must contain a vendor-specific implementation of this function.
group-onsemi	0:098463de4c5d	2307
group-onsemi	0:098463de4c5d	2308	*/
group-onsemi	0:098463de4c5d	2309	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
group-onsemi	0:098463de4c5d	2310	{
group-onsemi	0:098463de4c5d	2311	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
group-onsemi	0:098463de4c5d	2312
group-onsemi	0:098463de4c5d	2313	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
group-onsemi	0:098463de4c5d	2314	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
group-onsemi	0:098463de4c5d	2315	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
group-onsemi	0:098463de4c5d	2316	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
group-onsemi	0:098463de4c5d	2317	SysTick_CTRL_TICKINT_Msk \|
group-onsemi	0:098463de4c5d	2318	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
group-onsemi	0:098463de4c5d	2319	return (0UL); /* Function successful */
group-onsemi	0:098463de4c5d	2320	}
group-onsemi	0:098463de4c5d	2321
group-onsemi	0:098463de4c5d	2322	#endif
group-onsemi	0:098463de4c5d	2323
group-onsemi	0:098463de4c5d	2324	/@} end of CMSIS_Core_SysTickFunctions /
group-onsemi	0:098463de4c5d	2325
group-onsemi	0:098463de4c5d	2326
group-onsemi	0:098463de4c5d	2327
group-onsemi	0:098463de4c5d	2328	/* ##################################### Debug In/Output function ########################################### */
group-onsemi	0:098463de4c5d	2329	/** \ingroup CMSIS_Core_FunctionInterface
group-onsemi	0:098463de4c5d	2330	\defgroup CMSIS_core_DebugFunctions ITM Functions
group-onsemi	0:098463de4c5d	2331	\brief Functions that access the ITM debug interface.
group-onsemi	0:098463de4c5d	2332	@{
group-onsemi	0:098463de4c5d	2333	*/
group-onsemi	0:098463de4c5d	2334
group-onsemi	0:098463de4c5d	2335	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
group-onsemi	0:098463de4c5d	2336	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
group-onsemi	0:098463de4c5d	2337
group-onsemi	0:098463de4c5d	2338
group-onsemi	0:098463de4c5d	2339	/** \brief ITM Send Character
group-onsemi	0:098463de4c5d	2340
group-onsemi	0:098463de4c5d	2341	The function transmits a character via the ITM channel 0, and
group-onsemi	0:098463de4c5d	2342	\li Just returns when no debugger is connected that has booked the output.
group-onsemi	0:098463de4c5d	2343	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
group-onsemi	0:098463de4c5d	2344
group-onsemi	0:098463de4c5d	2345	\param [in] ch Character to transmit.
group-onsemi	0:098463de4c5d	2346
group-onsemi	0:098463de4c5d	2347	\returns Character to transmit.
group-onsemi	0:098463de4c5d	2348	*/
group-onsemi	0:098463de4c5d	2349	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
group-onsemi	0:098463de4c5d	2350	{
group-onsemi	0:098463de4c5d	2351	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
group-onsemi	0:098463de4c5d	2352	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
group-onsemi	0:098463de4c5d	2353	{
group-onsemi	0:098463de4c5d	2354	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
group-onsemi	0:098463de4c5d	2355	ITM->PORT[0].u8 = (uint8_t)ch;
group-onsemi	0:098463de4c5d	2356	}
group-onsemi	0:098463de4c5d	2357	return (ch);
group-onsemi	0:098463de4c5d	2358	}
group-onsemi	0:098463de4c5d	2359
group-onsemi	0:098463de4c5d	2360
group-onsemi	0:098463de4c5d	2361	/** \brief ITM Receive Character
group-onsemi	0:098463de4c5d	2362
group-onsemi	0:098463de4c5d	2363	The function inputs a character via the external variable \ref ITM_RxBuffer.
group-onsemi	0:098463de4c5d	2364
group-onsemi	0:098463de4c5d	2365	\return Received character.
group-onsemi	0:098463de4c5d	2366	\return -1 No character pending.
group-onsemi	0:098463de4c5d	2367	*/
group-onsemi	0:098463de4c5d	2368	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
group-onsemi	0:098463de4c5d	2369	int32_t ch = -1; /* no character available */
group-onsemi	0:098463de4c5d	2370
group-onsemi	0:098463de4c5d	2371	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
group-onsemi	0:098463de4c5d	2372	ch = ITM_RxBuffer;
group-onsemi	0:098463de4c5d	2373	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
group-onsemi	0:098463de4c5d	2374	}
group-onsemi	0:098463de4c5d	2375
group-onsemi	0:098463de4c5d	2376	return (ch);
group-onsemi	0:098463de4c5d	2377	}
group-onsemi	0:098463de4c5d	2378
group-onsemi	0:098463de4c5d	2379
group-onsemi	0:098463de4c5d	2380	/** \brief ITM Check Character
group-onsemi	0:098463de4c5d	2381
group-onsemi	0:098463de4c5d	2382	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
group-onsemi	0:098463de4c5d	2383
group-onsemi	0:098463de4c5d	2384	\return 0 No character available.
group-onsemi	0:098463de4c5d	2385	\return 1 Character available.
group-onsemi	0:098463de4c5d	2386	*/
group-onsemi	0:098463de4c5d	2387	__STATIC_INLINE int32_t ITM_CheckChar (void) {
group-onsemi	0:098463de4c5d	2388
group-onsemi	0:098463de4c5d	2389	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
group-onsemi	0:098463de4c5d	2390	return (0); /* no character available */
group-onsemi	0:098463de4c5d	2391	} else {
group-onsemi	0:098463de4c5d	2392	return (1); /* character available */
group-onsemi	0:098463de4c5d	2393	}
group-onsemi	0:098463de4c5d	2394	}
group-onsemi	0:098463de4c5d	2395
group-onsemi	0:098463de4c5d	2396	/@} end of CMSIS_core_DebugFunctions /
group-onsemi	0:098463de4c5d	2397
group-onsemi	0:098463de4c5d	2398
group-onsemi	0:098463de4c5d	2399
group-onsemi	0:098463de4c5d	2400
group-onsemi	0:098463de4c5d	2401	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	2402	}
group-onsemi	0:098463de4c5d	2403	#endif
group-onsemi	0:098463de4c5d	2404
group-onsemi	0:098463de4c5d	2405	#endif /* __CORE_CM7_H_DEPENDANT */
group-onsemi	0:098463de4c5d	2406
group-onsemi	0:098463de4c5d	2407	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	25 Jan 2017
Imports:	32
Forks:	0
Commits:	2
Dependents:	3
Dependencies:	0
Followers:	15

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cmsis/core_cm7.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

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