ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_cm3.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file core_cm3.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
group-onsemi 0:098463de4c5d 4 * @version V4.10
group-onsemi 0:098463de4c5d 5 * @date 18. March 2015
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @note
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 ******************************************************************************/
group-onsemi 0:098463de4c5d 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 All rights reserved.
group-onsemi 0:098463de4c5d 13 Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 14 modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 - Redistributions of source code must retain the above copyright
group-onsemi 0:098463de4c5d 16 notice, this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 - Redistributions in binary form must reproduce the above copyright
group-onsemi 0:098463de4c5d 18 notice, this list of conditions and the following disclaimer in the
group-onsemi 0:098463de4c5d 19 documentation and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 - Neither the name of ARM nor the names of its contributors may be used
group-onsemi 0:098463de4c5d 21 to endorse or promote products derived from this software without
group-onsemi 0:098463de4c5d 22 specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi 0:098463de4c5d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi 0:098463de4c5d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi 0:098463de4c5d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi 0:098463de4c5d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi 0:098463de4c5d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi 0:098463de4c5d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi 0:098463de4c5d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi 0:098463de4c5d 34 POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 35 ---------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #if defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 39 #pragma system_include /* treat file as system include file for MISRA check */
group-onsemi 0:098463de4c5d 40 #endif
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #ifndef __CORE_CM3_H_GENERIC
group-onsemi 0:098463de4c5d 43 #define __CORE_CM3_H_GENERIC
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 46 extern "C" {
group-onsemi 0:098463de4c5d 47 #endif
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
group-onsemi 0:098463de4c5d 50 CMSIS violates the following MISRA-C:2004 rules:
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 \li Required Rule 8.5, object/function definition in header file.<br>
group-onsemi 0:098463de4c5d 53 Function definitions in header files are used to allow 'inlining'.
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
group-onsemi 0:098463de4c5d 56 Unions are used for effective representation of core registers.
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
group-onsemi 0:098463de4c5d 59 Function-like macros are used to allow more efficient code.
group-onsemi 0:098463de4c5d 60 */
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 /*******************************************************************************
group-onsemi 0:098463de4c5d 64 * CMSIS definitions
group-onsemi 0:098463de4c5d 65 ******************************************************************************/
group-onsemi 0:098463de4c5d 66 /** \ingroup Cortex_M3
group-onsemi 0:098463de4c5d 67 @{
group-onsemi 0:098463de4c5d 68 */
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 /* CMSIS CM3 definitions */
group-onsemi 0:098463de4c5d 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
group-onsemi 0:098463de4c5d 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
group-onsemi 0:098463de4c5d 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
group-onsemi 0:098463de4c5d 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
group-onsemi 0:098463de4c5d 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
group-onsemi 0:098463de4c5d 82 #define __STATIC_INLINE static __inline
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 #elif defined ( __GNUC__ )
group-onsemi 0:098463de4c5d 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
group-onsemi 0:098463de4c5d 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
group-onsemi 0:098463de4c5d 87 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 #elif defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
group-onsemi 0:098463de4c5d 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
group-onsemi 0:098463de4c5d 92 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 #elif defined ( __TMS470__ )
group-onsemi 0:098463de4c5d 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
group-onsemi 0:098463de4c5d 96 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 #elif defined ( __TASKING__ )
group-onsemi 0:098463de4c5d 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
group-onsemi 0:098463de4c5d 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
group-onsemi 0:098463de4c5d 101 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 #elif defined ( __CSMC__ )
group-onsemi 0:098463de4c5d 104 #define __packed
group-onsemi 0:098463de4c5d 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
group-onsemi 0:098463de4c5d 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
group-onsemi 0:098463de4c5d 107 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 #endif
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /** __FPU_USED indicates whether an FPU is used or not.
group-onsemi 0:098463de4c5d 112 This core does not support an FPU at all
group-onsemi 0:098463de4c5d 113 */
group-onsemi 0:098463de4c5d 114 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 117 #if defined __TARGET_FPU_VFP
group-onsemi 0:098463de4c5d 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 119 #endif
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 #elif defined ( __GNUC__ )
group-onsemi 0:098463de4c5d 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
group-onsemi 0:098463de4c5d 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 124 #endif
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126 #elif defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 127 #if defined __ARMVFP__
group-onsemi 0:098463de4c5d 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 129 #endif
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 #elif defined ( __TMS470__ )
group-onsemi 0:098463de4c5d 132 #if defined __TI__VFP_SUPPORT____
group-onsemi 0:098463de4c5d 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 134 #endif
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 #elif defined ( __TASKING__ )
group-onsemi 0:098463de4c5d 137 #if defined __FPU_VFP__
group-onsemi 0:098463de4c5d 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 139 #endif
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141 #elif defined ( __CSMC__ ) /* Cosmic */
group-onsemi 0:098463de4c5d 142 #if ( __CSMC__ & 0x400) // FPU present for parser
group-onsemi 0:098463de4c5d 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 144 #endif
group-onsemi 0:098463de4c5d 145 #endif
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 #include <stdint.h> /* standard types definitions */
group-onsemi 0:098463de4c5d 148 #include <core_cmInstr.h> /* Core Instruction Access */
group-onsemi 0:098463de4c5d 149 #include <core_cmFunc.h> /* Core Function Access */
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 152 }
group-onsemi 0:098463de4c5d 153 #endif
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 #endif /* __CORE_CM3_H_GENERIC */
group-onsemi 0:098463de4c5d 156
group-onsemi 0:098463de4c5d 157 #ifndef __CMSIS_GENERIC
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 #ifndef __CORE_CM3_H_DEPENDANT
group-onsemi 0:098463de4c5d 160 #define __CORE_CM3_H_DEPENDANT
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 163 extern "C" {
group-onsemi 0:098463de4c5d 164 #endif
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 /* check device defines and use defaults */
group-onsemi 0:098463de4c5d 167 #if defined __CHECK_DEVICE_DEFINES
group-onsemi 0:098463de4c5d 168 #ifndef __CM3_REV
group-onsemi 0:098463de4c5d 169 #define __CM3_REV 0x0200
group-onsemi 0:098463de4c5d 170 #warning "__CM3_REV not defined in device header file; using default!"
group-onsemi 0:098463de4c5d 171 #endif
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 #ifndef __MPU_PRESENT
group-onsemi 0:098463de4c5d 174 #define __MPU_PRESENT 0
group-onsemi 0:098463de4c5d 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
group-onsemi 0:098463de4c5d 176 #endif
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 #ifndef __NVIC_PRIO_BITS
group-onsemi 0:098463de4c5d 179 #define __NVIC_PRIO_BITS 4
group-onsemi 0:098463de4c5d 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
group-onsemi 0:098463de4c5d 181 #endif
group-onsemi 0:098463de4c5d 182
group-onsemi 0:098463de4c5d 183 #ifndef __Vendor_SysTickConfig
group-onsemi 0:098463de4c5d 184 #define __Vendor_SysTickConfig 0
group-onsemi 0:098463de4c5d 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
group-onsemi 0:098463de4c5d 186 #endif
group-onsemi 0:098463de4c5d 187 #endif
group-onsemi 0:098463de4c5d 188
group-onsemi 0:098463de4c5d 189 /* IO definitions (access restrictions to peripheral registers) */
group-onsemi 0:098463de4c5d 190 /**
group-onsemi 0:098463de4c5d 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 <strong>IO Type Qualifiers</strong> are used
group-onsemi 0:098463de4c5d 194 \li to specify the access to peripheral variables.
group-onsemi 0:098463de4c5d 195 \li for automatic generation of peripheral register debug information.
group-onsemi 0:098463de4c5d 196 */
group-onsemi 0:098463de4c5d 197 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 198 #define __I volatile /*!< Defines 'read only' permissions */
group-onsemi 0:098463de4c5d 199 #else
group-onsemi 0:098463de4c5d 200 #define __I volatile const /*!< Defines 'read only' permissions */
group-onsemi 0:098463de4c5d 201 #endif
group-onsemi 0:098463de4c5d 202 #define __O volatile /*!< Defines 'write only' permissions */
group-onsemi 0:098463de4c5d 203 #define __IO volatile /*!< Defines 'read / write' permissions */
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 206 #define __IM volatile /*!< Defines 'read only' permissions */
group-onsemi 0:098463de4c5d 207 #else
group-onsemi 0:098463de4c5d 208 #define __IM volatile const /*!< Defines 'read only' permissions */
group-onsemi 0:098463de4c5d 209 #endif
group-onsemi 0:098463de4c5d 210 #define __OM volatile /*!< Defines 'write only' permissions */
group-onsemi 0:098463de4c5d 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 /*@} end of group Cortex_M3 */
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 /*******************************************************************************
group-onsemi 0:098463de4c5d 218 * Register Abstraction
group-onsemi 0:098463de4c5d 219 Core Register contain:
group-onsemi 0:098463de4c5d 220 - Core Register
group-onsemi 0:098463de4c5d 221 - Core NVIC Register
group-onsemi 0:098463de4c5d 222 - Core SCB Register
group-onsemi 0:098463de4c5d 223 - Core SysTick Register
group-onsemi 0:098463de4c5d 224 - Core Debug Register
group-onsemi 0:098463de4c5d 225 - Core MPU Register
group-onsemi 0:098463de4c5d 226 ******************************************************************************/
group-onsemi 0:098463de4c5d 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
group-onsemi 0:098463de4c5d 228 \brief Type definitions and defines for Cortex-M processor based devices.
group-onsemi 0:098463de4c5d 229 */
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 232 \defgroup CMSIS_CORE Status and Control Registers
group-onsemi 0:098463de4c5d 233 \brief Core Register type definitions.
group-onsemi 0:098463de4c5d 234 @{
group-onsemi 0:098463de4c5d 235 */
group-onsemi 0:098463de4c5d 236
group-onsemi 0:098463de4c5d 237 /** \brief Union type to access the Application Program Status Register (APSR).
group-onsemi 0:098463de4c5d 238 */
group-onsemi 0:098463de4c5d 239 typedef union
group-onsemi 0:098463de4c5d 240 {
group-onsemi 0:098463de4c5d 241 struct
group-onsemi 0:098463de4c5d 242 {
group-onsemi 0:098463de4c5d 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
group-onsemi 0:098463de4c5d 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
group-onsemi 0:098463de4c5d 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
group-onsemi 0:098463de4c5d 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
group-onsemi 0:098463de4c5d 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
group-onsemi 0:098463de4c5d 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
group-onsemi 0:098463de4c5d 249 } b; /*!< Structure used for bit access */
group-onsemi 0:098463de4c5d 250 uint32_t w; /*!< Type used for word access */
group-onsemi 0:098463de4c5d 251 } APSR_Type;
group-onsemi 0:098463de4c5d 252
group-onsemi 0:098463de4c5d 253 /* APSR Register Definitions */
group-onsemi 0:098463de4c5d 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
group-onsemi 0:098463de4c5d 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
group-onsemi 0:098463de4c5d 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
group-onsemi 0:098463de4c5d 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
group-onsemi 0:098463de4c5d 262
group-onsemi 0:098463de4c5d 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
group-onsemi 0:098463de4c5d 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
group-onsemi 0:098463de4c5d 265
group-onsemi 0:098463de4c5d 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
group-onsemi 0:098463de4c5d 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
group-onsemi 0:098463de4c5d 268
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
group-onsemi 0:098463de4c5d 271 */
group-onsemi 0:098463de4c5d 272 typedef union
group-onsemi 0:098463de4c5d 273 {
group-onsemi 0:098463de4c5d 274 struct
group-onsemi 0:098463de4c5d 275 {
group-onsemi 0:098463de4c5d 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
group-onsemi 0:098463de4c5d 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
group-onsemi 0:098463de4c5d 278 } b; /*!< Structure used for bit access */
group-onsemi 0:098463de4c5d 279 uint32_t w; /*!< Type used for word access */
group-onsemi 0:098463de4c5d 280 } IPSR_Type;
group-onsemi 0:098463de4c5d 281
group-onsemi 0:098463de4c5d 282 /* IPSR Register Definitions */
group-onsemi 0:098463de4c5d 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
group-onsemi 0:098463de4c5d 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
group-onsemi 0:098463de4c5d 285
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
group-onsemi 0:098463de4c5d 288 */
group-onsemi 0:098463de4c5d 289 typedef union
group-onsemi 0:098463de4c5d 290 {
group-onsemi 0:098463de4c5d 291 struct
group-onsemi 0:098463de4c5d 292 {
group-onsemi 0:098463de4c5d 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
group-onsemi 0:098463de4c5d 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
group-onsemi 0:098463de4c5d 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
group-onsemi 0:098463de4c5d 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
group-onsemi 0:098463de4c5d 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
group-onsemi 0:098463de4c5d 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
group-onsemi 0:098463de4c5d 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
group-onsemi 0:098463de4c5d 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
group-onsemi 0:098463de4c5d 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
group-onsemi 0:098463de4c5d 302 } b; /*!< Structure used for bit access */
group-onsemi 0:098463de4c5d 303 uint32_t w; /*!< Type used for word access */
group-onsemi 0:098463de4c5d 304 } xPSR_Type;
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 /* xPSR Register Definitions */
group-onsemi 0:098463de4c5d 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
group-onsemi 0:098463de4c5d 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
group-onsemi 0:098463de4c5d 309
group-onsemi 0:098463de4c5d 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
group-onsemi 0:098463de4c5d 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
group-onsemi 0:098463de4c5d 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
group-onsemi 0:098463de4c5d 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
group-onsemi 0:098463de4c5d 318
group-onsemi 0:098463de4c5d 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
group-onsemi 0:098463de4c5d 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
group-onsemi 0:098463de4c5d 321
group-onsemi 0:098463de4c5d 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
group-onsemi 0:098463de4c5d 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
group-onsemi 0:098463de4c5d 324
group-onsemi 0:098463de4c5d 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
group-onsemi 0:098463de4c5d 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
group-onsemi 0:098463de4c5d 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
group-onsemi 0:098463de4c5d 330
group-onsemi 0:098463de4c5d 331
group-onsemi 0:098463de4c5d 332 /** \brief Union type to access the Control Registers (CONTROL).
group-onsemi 0:098463de4c5d 333 */
group-onsemi 0:098463de4c5d 334 typedef union
group-onsemi 0:098463de4c5d 335 {
group-onsemi 0:098463de4c5d 336 struct
group-onsemi 0:098463de4c5d 337 {
group-onsemi 0:098463de4c5d 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
group-onsemi 0:098463de4c5d 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
group-onsemi 0:098463de4c5d 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
group-onsemi 0:098463de4c5d 341 } b; /*!< Structure used for bit access */
group-onsemi 0:098463de4c5d 342 uint32_t w; /*!< Type used for word access */
group-onsemi 0:098463de4c5d 343 } CONTROL_Type;
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 /* CONTROL Register Definitions */
group-onsemi 0:098463de4c5d 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
group-onsemi 0:098463de4c5d 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
group-onsemi 0:098463de4c5d 348
group-onsemi 0:098463de4c5d 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
group-onsemi 0:098463de4c5d 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
group-onsemi 0:098463de4c5d 351
group-onsemi 0:098463de4c5d 352 /*@} end of group CMSIS_CORE */
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354
group-onsemi 0:098463de4c5d 355 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
group-onsemi 0:098463de4c5d 357 \brief Type definitions for the NVIC Registers
group-onsemi 0:098463de4c5d 358 @{
group-onsemi 0:098463de4c5d 359 */
group-onsemi 0:098463de4c5d 360
group-onsemi 0:098463de4c5d 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
group-onsemi 0:098463de4c5d 362 */
group-onsemi 0:098463de4c5d 363 typedef struct
group-onsemi 0:098463de4c5d 364 {
group-onsemi 0:098463de4c5d 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
group-onsemi 0:098463de4c5d 366 uint32_t RESERVED0[24];
group-onsemi 0:098463de4c5d 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
group-onsemi 0:098463de4c5d 368 uint32_t RSERVED1[24];
group-onsemi 0:098463de4c5d 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
group-onsemi 0:098463de4c5d 370 uint32_t RESERVED2[24];
group-onsemi 0:098463de4c5d 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
group-onsemi 0:098463de4c5d 372 uint32_t RESERVED3[24];
group-onsemi 0:098463de4c5d 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
group-onsemi 0:098463de4c5d 374 uint32_t RESERVED4[56];
group-onsemi 0:098463de4c5d 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
group-onsemi 0:098463de4c5d 376 uint32_t RESERVED5[644];
group-onsemi 0:098463de4c5d 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
group-onsemi 0:098463de4c5d 378 } NVIC_Type;
group-onsemi 0:098463de4c5d 379
group-onsemi 0:098463de4c5d 380 /* Software Triggered Interrupt Register Definitions */
group-onsemi 0:098463de4c5d 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
group-onsemi 0:098463de4c5d 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 /*@} end of group CMSIS_NVIC */
group-onsemi 0:098463de4c5d 385
group-onsemi 0:098463de4c5d 386
group-onsemi 0:098463de4c5d 387 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 388 \defgroup CMSIS_SCB System Control Block (SCB)
group-onsemi 0:098463de4c5d 389 \brief Type definitions for the System Control Block Registers
group-onsemi 0:098463de4c5d 390 @{
group-onsemi 0:098463de4c5d 391 */
group-onsemi 0:098463de4c5d 392
group-onsemi 0:098463de4c5d 393 /** \brief Structure type to access the System Control Block (SCB).
group-onsemi 0:098463de4c5d 394 */
group-onsemi 0:098463de4c5d 395 typedef struct
group-onsemi 0:098463de4c5d 396 {
group-onsemi 0:098463de4c5d 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
group-onsemi 0:098463de4c5d 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
group-onsemi 0:098463de4c5d 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
group-onsemi 0:098463de4c5d 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
group-onsemi 0:098463de4c5d 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
group-onsemi 0:098463de4c5d 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
group-onsemi 0:098463de4c5d 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
group-onsemi 0:098463de4c5d 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
group-onsemi 0:098463de4c5d 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
group-onsemi 0:098463de4c5d 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
group-onsemi 0:098463de4c5d 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
group-onsemi 0:098463de4c5d 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
group-onsemi 0:098463de4c5d 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
group-onsemi 0:098463de4c5d 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
group-onsemi 0:098463de4c5d 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
group-onsemi 0:098463de4c5d 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
group-onsemi 0:098463de4c5d 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
group-onsemi 0:098463de4c5d 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
group-onsemi 0:098463de4c5d 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
group-onsemi 0:098463de4c5d 416 uint32_t RESERVED0[5];
group-onsemi 0:098463de4c5d 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
group-onsemi 0:098463de4c5d 418 } SCB_Type;
group-onsemi 0:098463de4c5d 419
group-onsemi 0:098463de4c5d 420 /* SCB CPUID Register Definitions */
group-onsemi 0:098463de4c5d 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
group-onsemi 0:098463de4c5d 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
group-onsemi 0:098463de4c5d 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
group-onsemi 0:098463de4c5d 426
group-onsemi 0:098463de4c5d 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
group-onsemi 0:098463de4c5d 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
group-onsemi 0:098463de4c5d 429
group-onsemi 0:098463de4c5d 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
group-onsemi 0:098463de4c5d 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
group-onsemi 0:098463de4c5d 432
group-onsemi 0:098463de4c5d 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
group-onsemi 0:098463de4c5d 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
group-onsemi 0:098463de4c5d 435
group-onsemi 0:098463de4c5d 436 /* SCB Interrupt Control State Register Definitions */
group-onsemi 0:098463de4c5d 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
group-onsemi 0:098463de4c5d 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
group-onsemi 0:098463de4c5d 439
group-onsemi 0:098463de4c5d 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
group-onsemi 0:098463de4c5d 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
group-onsemi 0:098463de4c5d 442
group-onsemi 0:098463de4c5d 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
group-onsemi 0:098463de4c5d 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
group-onsemi 0:098463de4c5d 445
group-onsemi 0:098463de4c5d 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
group-onsemi 0:098463de4c5d 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
group-onsemi 0:098463de4c5d 448
group-onsemi 0:098463de4c5d 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
group-onsemi 0:098463de4c5d 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
group-onsemi 0:098463de4c5d 451
group-onsemi 0:098463de4c5d 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
group-onsemi 0:098463de4c5d 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
group-onsemi 0:098463de4c5d 454
group-onsemi 0:098463de4c5d 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
group-onsemi 0:098463de4c5d 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
group-onsemi 0:098463de4c5d 457
group-onsemi 0:098463de4c5d 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
group-onsemi 0:098463de4c5d 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
group-onsemi 0:098463de4c5d 460
group-onsemi 0:098463de4c5d 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
group-onsemi 0:098463de4c5d 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
group-onsemi 0:098463de4c5d 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
group-onsemi 0:098463de4c5d 466
group-onsemi 0:098463de4c5d 467 /* SCB Vector Table Offset Register Definitions */
group-onsemi 0:098463de4c5d 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
group-onsemi 0:098463de4c5d 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
group-onsemi 0:098463de4c5d 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
group-onsemi 0:098463de4c5d 471
group-onsemi 0:098463de4c5d 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
group-onsemi 0:098463de4c5d 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
group-onsemi 0:098463de4c5d 474 #else
group-onsemi 0:098463de4c5d 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
group-onsemi 0:098463de4c5d 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
group-onsemi 0:098463de4c5d 477 #endif
group-onsemi 0:098463de4c5d 478
group-onsemi 0:098463de4c5d 479 /* SCB Application Interrupt and Reset Control Register Definitions */
group-onsemi 0:098463de4c5d 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
group-onsemi 0:098463de4c5d 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
group-onsemi 0:098463de4c5d 482
group-onsemi 0:098463de4c5d 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
group-onsemi 0:098463de4c5d 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
group-onsemi 0:098463de4c5d 485
group-onsemi 0:098463de4c5d 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
group-onsemi 0:098463de4c5d 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
group-onsemi 0:098463de4c5d 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
group-onsemi 0:098463de4c5d 491
group-onsemi 0:098463de4c5d 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
group-onsemi 0:098463de4c5d 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
group-onsemi 0:098463de4c5d 494
group-onsemi 0:098463de4c5d 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
group-onsemi 0:098463de4c5d 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
group-onsemi 0:098463de4c5d 497
group-onsemi 0:098463de4c5d 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
group-onsemi 0:098463de4c5d 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
group-onsemi 0:098463de4c5d 500
group-onsemi 0:098463de4c5d 501 /* SCB System Control Register Definitions */
group-onsemi 0:098463de4c5d 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
group-onsemi 0:098463de4c5d 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
group-onsemi 0:098463de4c5d 504
group-onsemi 0:098463de4c5d 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
group-onsemi 0:098463de4c5d 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
group-onsemi 0:098463de4c5d 507
group-onsemi 0:098463de4c5d 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
group-onsemi 0:098463de4c5d 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
group-onsemi 0:098463de4c5d 510
group-onsemi 0:098463de4c5d 511 /* SCB Configuration Control Register Definitions */
group-onsemi 0:098463de4c5d 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
group-onsemi 0:098463de4c5d 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
group-onsemi 0:098463de4c5d 514
group-onsemi 0:098463de4c5d 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
group-onsemi 0:098463de4c5d 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
group-onsemi 0:098463de4c5d 517
group-onsemi 0:098463de4c5d 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
group-onsemi 0:098463de4c5d 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
group-onsemi 0:098463de4c5d 520
group-onsemi 0:098463de4c5d 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
group-onsemi 0:098463de4c5d 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
group-onsemi 0:098463de4c5d 523
group-onsemi 0:098463de4c5d 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
group-onsemi 0:098463de4c5d 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
group-onsemi 0:098463de4c5d 526
group-onsemi 0:098463de4c5d 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
group-onsemi 0:098463de4c5d 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
group-onsemi 0:098463de4c5d 529
group-onsemi 0:098463de4c5d 530 /* SCB System Handler Control and State Register Definitions */
group-onsemi 0:098463de4c5d 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
group-onsemi 0:098463de4c5d 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
group-onsemi 0:098463de4c5d 533
group-onsemi 0:098463de4c5d 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
group-onsemi 0:098463de4c5d 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
group-onsemi 0:098463de4c5d 536
group-onsemi 0:098463de4c5d 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
group-onsemi 0:098463de4c5d 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
group-onsemi 0:098463de4c5d 539
group-onsemi 0:098463de4c5d 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
group-onsemi 0:098463de4c5d 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
group-onsemi 0:098463de4c5d 542
group-onsemi 0:098463de4c5d 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
group-onsemi 0:098463de4c5d 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
group-onsemi 0:098463de4c5d 545
group-onsemi 0:098463de4c5d 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
group-onsemi 0:098463de4c5d 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
group-onsemi 0:098463de4c5d 548
group-onsemi 0:098463de4c5d 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
group-onsemi 0:098463de4c5d 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
group-onsemi 0:098463de4c5d 551
group-onsemi 0:098463de4c5d 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
group-onsemi 0:098463de4c5d 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
group-onsemi 0:098463de4c5d 554
group-onsemi 0:098463de4c5d 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
group-onsemi 0:098463de4c5d 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
group-onsemi 0:098463de4c5d 557
group-onsemi 0:098463de4c5d 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
group-onsemi 0:098463de4c5d 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
group-onsemi 0:098463de4c5d 560
group-onsemi 0:098463de4c5d 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
group-onsemi 0:098463de4c5d 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
group-onsemi 0:098463de4c5d 563
group-onsemi 0:098463de4c5d 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
group-onsemi 0:098463de4c5d 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
group-onsemi 0:098463de4c5d 566
group-onsemi 0:098463de4c5d 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
group-onsemi 0:098463de4c5d 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
group-onsemi 0:098463de4c5d 569
group-onsemi 0:098463de4c5d 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
group-onsemi 0:098463de4c5d 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
group-onsemi 0:098463de4c5d 572
group-onsemi 0:098463de4c5d 573 /* SCB Configurable Fault Status Registers Definitions */
group-onsemi 0:098463de4c5d 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
group-onsemi 0:098463de4c5d 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
group-onsemi 0:098463de4c5d 576
group-onsemi 0:098463de4c5d 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
group-onsemi 0:098463de4c5d 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
group-onsemi 0:098463de4c5d 579
group-onsemi 0:098463de4c5d 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
group-onsemi 0:098463de4c5d 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
group-onsemi 0:098463de4c5d 582
group-onsemi 0:098463de4c5d 583 /* SCB Hard Fault Status Registers Definitions */
group-onsemi 0:098463de4c5d 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
group-onsemi 0:098463de4c5d 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
group-onsemi 0:098463de4c5d 586
group-onsemi 0:098463de4c5d 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
group-onsemi 0:098463de4c5d 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
group-onsemi 0:098463de4c5d 589
group-onsemi 0:098463de4c5d 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
group-onsemi 0:098463de4c5d 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
group-onsemi 0:098463de4c5d 592
group-onsemi 0:098463de4c5d 593 /* SCB Debug Fault Status Register Definitions */
group-onsemi 0:098463de4c5d 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
group-onsemi 0:098463de4c5d 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
group-onsemi 0:098463de4c5d 596
group-onsemi 0:098463de4c5d 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
group-onsemi 0:098463de4c5d 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
group-onsemi 0:098463de4c5d 599
group-onsemi 0:098463de4c5d 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
group-onsemi 0:098463de4c5d 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
group-onsemi 0:098463de4c5d 602
group-onsemi 0:098463de4c5d 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
group-onsemi 0:098463de4c5d 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
group-onsemi 0:098463de4c5d 605
group-onsemi 0:098463de4c5d 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
group-onsemi 0:098463de4c5d 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
group-onsemi 0:098463de4c5d 608
group-onsemi 0:098463de4c5d 609 /*@} end of group CMSIS_SCB */
group-onsemi 0:098463de4c5d 610
group-onsemi 0:098463de4c5d 611
group-onsemi 0:098463de4c5d 612 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
group-onsemi 0:098463de4c5d 614 \brief Type definitions for the System Control and ID Register not in the SCB
group-onsemi 0:098463de4c5d 615 @{
group-onsemi 0:098463de4c5d 616 */
group-onsemi 0:098463de4c5d 617
group-onsemi 0:098463de4c5d 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
group-onsemi 0:098463de4c5d 619 */
group-onsemi 0:098463de4c5d 620 typedef struct
group-onsemi 0:098463de4c5d 621 {
group-onsemi 0:098463de4c5d 622 uint32_t RESERVED0[1];
group-onsemi 0:098463de4c5d 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
group-onsemi 0:098463de4c5d 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
group-onsemi 0:098463de4c5d 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
group-onsemi 0:098463de4c5d 626 #else
group-onsemi 0:098463de4c5d 627 uint32_t RESERVED1[1];
group-onsemi 0:098463de4c5d 628 #endif
group-onsemi 0:098463de4c5d 629 } SCnSCB_Type;
group-onsemi 0:098463de4c5d 630
group-onsemi 0:098463de4c5d 631 /* Interrupt Controller Type Register Definitions */
group-onsemi 0:098463de4c5d 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
group-onsemi 0:098463de4c5d 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
group-onsemi 0:098463de4c5d 634
group-onsemi 0:098463de4c5d 635 /* Auxiliary Control Register Definitions */
group-onsemi 0:098463de4c5d 636
group-onsemi 0:098463de4c5d 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
group-onsemi 0:098463de4c5d 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
group-onsemi 0:098463de4c5d 639
group-onsemi 0:098463de4c5d 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
group-onsemi 0:098463de4c5d 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
group-onsemi 0:098463de4c5d 642
group-onsemi 0:098463de4c5d 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
group-onsemi 0:098463de4c5d 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
group-onsemi 0:098463de4c5d 645
group-onsemi 0:098463de4c5d 646 /*@} end of group CMSIS_SCnotSCB */
group-onsemi 0:098463de4c5d 647
group-onsemi 0:098463de4c5d 648
group-onsemi 0:098463de4c5d 649 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
group-onsemi 0:098463de4c5d 651 \brief Type definitions for the System Timer Registers.
group-onsemi 0:098463de4c5d 652 @{
group-onsemi 0:098463de4c5d 653 */
group-onsemi 0:098463de4c5d 654
group-onsemi 0:098463de4c5d 655 /** \brief Structure type to access the System Timer (SysTick).
group-onsemi 0:098463de4c5d 656 */
group-onsemi 0:098463de4c5d 657 typedef struct
group-onsemi 0:098463de4c5d 658 {
group-onsemi 0:098463de4c5d 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
group-onsemi 0:098463de4c5d 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
group-onsemi 0:098463de4c5d 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
group-onsemi 0:098463de4c5d 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
group-onsemi 0:098463de4c5d 663 } SysTick_Type;
group-onsemi 0:098463de4c5d 664
group-onsemi 0:098463de4c5d 665 /* SysTick Control / Status Register Definitions */
group-onsemi 0:098463de4c5d 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
group-onsemi 0:098463de4c5d 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
group-onsemi 0:098463de4c5d 668
group-onsemi 0:098463de4c5d 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
group-onsemi 0:098463de4c5d 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
group-onsemi 0:098463de4c5d 671
group-onsemi 0:098463de4c5d 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
group-onsemi 0:098463de4c5d 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
group-onsemi 0:098463de4c5d 674
group-onsemi 0:098463de4c5d 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
group-onsemi 0:098463de4c5d 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
group-onsemi 0:098463de4c5d 677
group-onsemi 0:098463de4c5d 678 /* SysTick Reload Register Definitions */
group-onsemi 0:098463de4c5d 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
group-onsemi 0:098463de4c5d 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
group-onsemi 0:098463de4c5d 681
group-onsemi 0:098463de4c5d 682 /* SysTick Current Register Definitions */
group-onsemi 0:098463de4c5d 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
group-onsemi 0:098463de4c5d 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
group-onsemi 0:098463de4c5d 685
group-onsemi 0:098463de4c5d 686 /* SysTick Calibration Register Definitions */
group-onsemi 0:098463de4c5d 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
group-onsemi 0:098463de4c5d 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
group-onsemi 0:098463de4c5d 689
group-onsemi 0:098463de4c5d 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
group-onsemi 0:098463de4c5d 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
group-onsemi 0:098463de4c5d 692
group-onsemi 0:098463de4c5d 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
group-onsemi 0:098463de4c5d 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
group-onsemi 0:098463de4c5d 695
group-onsemi 0:098463de4c5d 696 /*@} end of group CMSIS_SysTick */
group-onsemi 0:098463de4c5d 697
group-onsemi 0:098463de4c5d 698
group-onsemi 0:098463de4c5d 699 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
group-onsemi 0:098463de4c5d 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
group-onsemi 0:098463de4c5d 702 @{
group-onsemi 0:098463de4c5d 703 */
group-onsemi 0:098463de4c5d 704
group-onsemi 0:098463de4c5d 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
group-onsemi 0:098463de4c5d 706 */
group-onsemi 0:098463de4c5d 707 typedef struct
group-onsemi 0:098463de4c5d 708 {
group-onsemi 0:098463de4c5d 709 __O union
group-onsemi 0:098463de4c5d 710 {
group-onsemi 0:098463de4c5d 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
group-onsemi 0:098463de4c5d 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
group-onsemi 0:098463de4c5d 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
group-onsemi 0:098463de4c5d 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
group-onsemi 0:098463de4c5d 715 uint32_t RESERVED0[864];
group-onsemi 0:098463de4c5d 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
group-onsemi 0:098463de4c5d 717 uint32_t RESERVED1[15];
group-onsemi 0:098463de4c5d 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
group-onsemi 0:098463de4c5d 719 uint32_t RESERVED2[15];
group-onsemi 0:098463de4c5d 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
group-onsemi 0:098463de4c5d 721 uint32_t RESERVED3[29];
group-onsemi 0:098463de4c5d 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
group-onsemi 0:098463de4c5d 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
group-onsemi 0:098463de4c5d 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
group-onsemi 0:098463de4c5d 725 uint32_t RESERVED4[43];
group-onsemi 0:098463de4c5d 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
group-onsemi 0:098463de4c5d 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
group-onsemi 0:098463de4c5d 728 uint32_t RESERVED5[6];
group-onsemi 0:098463de4c5d 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
group-onsemi 0:098463de4c5d 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
group-onsemi 0:098463de4c5d 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
group-onsemi 0:098463de4c5d 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
group-onsemi 0:098463de4c5d 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
group-onsemi 0:098463de4c5d 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
group-onsemi 0:098463de4c5d 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
group-onsemi 0:098463de4c5d 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
group-onsemi 0:098463de4c5d 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
group-onsemi 0:098463de4c5d 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
group-onsemi 0:098463de4c5d 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
group-onsemi 0:098463de4c5d 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
group-onsemi 0:098463de4c5d 741 } ITM_Type;
group-onsemi 0:098463de4c5d 742
group-onsemi 0:098463de4c5d 743 /* ITM Trace Privilege Register Definitions */
group-onsemi 0:098463de4c5d 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
group-onsemi 0:098463de4c5d 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
group-onsemi 0:098463de4c5d 746
group-onsemi 0:098463de4c5d 747 /* ITM Trace Control Register Definitions */
group-onsemi 0:098463de4c5d 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
group-onsemi 0:098463de4c5d 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
group-onsemi 0:098463de4c5d 750
group-onsemi 0:098463de4c5d 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
group-onsemi 0:098463de4c5d 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
group-onsemi 0:098463de4c5d 753
group-onsemi 0:098463de4c5d 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
group-onsemi 0:098463de4c5d 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
group-onsemi 0:098463de4c5d 756
group-onsemi 0:098463de4c5d 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
group-onsemi 0:098463de4c5d 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
group-onsemi 0:098463de4c5d 759
group-onsemi 0:098463de4c5d 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
group-onsemi 0:098463de4c5d 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
group-onsemi 0:098463de4c5d 762
group-onsemi 0:098463de4c5d 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
group-onsemi 0:098463de4c5d 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
group-onsemi 0:098463de4c5d 765
group-onsemi 0:098463de4c5d 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
group-onsemi 0:098463de4c5d 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
group-onsemi 0:098463de4c5d 768
group-onsemi 0:098463de4c5d 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
group-onsemi 0:098463de4c5d 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
group-onsemi 0:098463de4c5d 771
group-onsemi 0:098463de4c5d 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
group-onsemi 0:098463de4c5d 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
group-onsemi 0:098463de4c5d 774
group-onsemi 0:098463de4c5d 775 /* ITM Integration Write Register Definitions */
group-onsemi 0:098463de4c5d 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
group-onsemi 0:098463de4c5d 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
group-onsemi 0:098463de4c5d 778
group-onsemi 0:098463de4c5d 779 /* ITM Integration Read Register Definitions */
group-onsemi 0:098463de4c5d 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
group-onsemi 0:098463de4c5d 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
group-onsemi 0:098463de4c5d 782
group-onsemi 0:098463de4c5d 783 /* ITM Integration Mode Control Register Definitions */
group-onsemi 0:098463de4c5d 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
group-onsemi 0:098463de4c5d 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
group-onsemi 0:098463de4c5d 786
group-onsemi 0:098463de4c5d 787 /* ITM Lock Status Register Definitions */
group-onsemi 0:098463de4c5d 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
group-onsemi 0:098463de4c5d 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
group-onsemi 0:098463de4c5d 790
group-onsemi 0:098463de4c5d 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
group-onsemi 0:098463de4c5d 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
group-onsemi 0:098463de4c5d 793
group-onsemi 0:098463de4c5d 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
group-onsemi 0:098463de4c5d 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
group-onsemi 0:098463de4c5d 796
group-onsemi 0:098463de4c5d 797 /*@}*/ /* end of group CMSIS_ITM */
group-onsemi 0:098463de4c5d 798
group-onsemi 0:098463de4c5d 799
group-onsemi 0:098463de4c5d 800 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
group-onsemi 0:098463de4c5d 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
group-onsemi 0:098463de4c5d 803 @{
group-onsemi 0:098463de4c5d 804 */
group-onsemi 0:098463de4c5d 805
group-onsemi 0:098463de4c5d 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
group-onsemi 0:098463de4c5d 807 */
group-onsemi 0:098463de4c5d 808 typedef struct
group-onsemi 0:098463de4c5d 809 {
group-onsemi 0:098463de4c5d 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
group-onsemi 0:098463de4c5d 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
group-onsemi 0:098463de4c5d 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
group-onsemi 0:098463de4c5d 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
group-onsemi 0:098463de4c5d 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
group-onsemi 0:098463de4c5d 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
group-onsemi 0:098463de4c5d 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
group-onsemi 0:098463de4c5d 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
group-onsemi 0:098463de4c5d 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
group-onsemi 0:098463de4c5d 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
group-onsemi 0:098463de4c5d 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
group-onsemi 0:098463de4c5d 821 uint32_t RESERVED0[1];
group-onsemi 0:098463de4c5d 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
group-onsemi 0:098463de4c5d 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
group-onsemi 0:098463de4c5d 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
group-onsemi 0:098463de4c5d 825 uint32_t RESERVED1[1];
group-onsemi 0:098463de4c5d 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
group-onsemi 0:098463de4c5d 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
group-onsemi 0:098463de4c5d 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
group-onsemi 0:098463de4c5d 829 uint32_t RESERVED2[1];
group-onsemi 0:098463de4c5d 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
group-onsemi 0:098463de4c5d 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
group-onsemi 0:098463de4c5d 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
group-onsemi 0:098463de4c5d 833 } DWT_Type;
group-onsemi 0:098463de4c5d 834
group-onsemi 0:098463de4c5d 835 /* DWT Control Register Definitions */
group-onsemi 0:098463de4c5d 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
group-onsemi 0:098463de4c5d 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
group-onsemi 0:098463de4c5d 838
group-onsemi 0:098463de4c5d 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
group-onsemi 0:098463de4c5d 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
group-onsemi 0:098463de4c5d 841
group-onsemi 0:098463de4c5d 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
group-onsemi 0:098463de4c5d 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
group-onsemi 0:098463de4c5d 844
group-onsemi 0:098463de4c5d 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
group-onsemi 0:098463de4c5d 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
group-onsemi 0:098463de4c5d 847
group-onsemi 0:098463de4c5d 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
group-onsemi 0:098463de4c5d 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
group-onsemi 0:098463de4c5d 850
group-onsemi 0:098463de4c5d 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
group-onsemi 0:098463de4c5d 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
group-onsemi 0:098463de4c5d 853
group-onsemi 0:098463de4c5d 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
group-onsemi 0:098463de4c5d 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
group-onsemi 0:098463de4c5d 856
group-onsemi 0:098463de4c5d 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
group-onsemi 0:098463de4c5d 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
group-onsemi 0:098463de4c5d 859
group-onsemi 0:098463de4c5d 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
group-onsemi 0:098463de4c5d 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
group-onsemi 0:098463de4c5d 862
group-onsemi 0:098463de4c5d 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
group-onsemi 0:098463de4c5d 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
group-onsemi 0:098463de4c5d 865
group-onsemi 0:098463de4c5d 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
group-onsemi 0:098463de4c5d 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
group-onsemi 0:098463de4c5d 868
group-onsemi 0:098463de4c5d 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
group-onsemi 0:098463de4c5d 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
group-onsemi 0:098463de4c5d 871
group-onsemi 0:098463de4c5d 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
group-onsemi 0:098463de4c5d 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
group-onsemi 0:098463de4c5d 874
group-onsemi 0:098463de4c5d 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
group-onsemi 0:098463de4c5d 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
group-onsemi 0:098463de4c5d 877
group-onsemi 0:098463de4c5d 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
group-onsemi 0:098463de4c5d 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
group-onsemi 0:098463de4c5d 880
group-onsemi 0:098463de4c5d 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
group-onsemi 0:098463de4c5d 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
group-onsemi 0:098463de4c5d 883
group-onsemi 0:098463de4c5d 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
group-onsemi 0:098463de4c5d 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
group-onsemi 0:098463de4c5d 886
group-onsemi 0:098463de4c5d 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
group-onsemi 0:098463de4c5d 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
group-onsemi 0:098463de4c5d 889
group-onsemi 0:098463de4c5d 890 /* DWT CPI Count Register Definitions */
group-onsemi 0:098463de4c5d 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
group-onsemi 0:098463de4c5d 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
group-onsemi 0:098463de4c5d 893
group-onsemi 0:098463de4c5d 894 /* DWT Exception Overhead Count Register Definitions */
group-onsemi 0:098463de4c5d 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
group-onsemi 0:098463de4c5d 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
group-onsemi 0:098463de4c5d 897
group-onsemi 0:098463de4c5d 898 /* DWT Sleep Count Register Definitions */
group-onsemi 0:098463de4c5d 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
group-onsemi 0:098463de4c5d 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
group-onsemi 0:098463de4c5d 901
group-onsemi 0:098463de4c5d 902 /* DWT LSU Count Register Definitions */
group-onsemi 0:098463de4c5d 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
group-onsemi 0:098463de4c5d 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
group-onsemi 0:098463de4c5d 905
group-onsemi 0:098463de4c5d 906 /* DWT Folded-instruction Count Register Definitions */
group-onsemi 0:098463de4c5d 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
group-onsemi 0:098463de4c5d 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
group-onsemi 0:098463de4c5d 909
group-onsemi 0:098463de4c5d 910 /* DWT Comparator Mask Register Definitions */
group-onsemi 0:098463de4c5d 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
group-onsemi 0:098463de4c5d 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
group-onsemi 0:098463de4c5d 913
group-onsemi 0:098463de4c5d 914 /* DWT Comparator Function Register Definitions */
group-onsemi 0:098463de4c5d 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
group-onsemi 0:098463de4c5d 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
group-onsemi 0:098463de4c5d 917
group-onsemi 0:098463de4c5d 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
group-onsemi 0:098463de4c5d 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
group-onsemi 0:098463de4c5d 920
group-onsemi 0:098463de4c5d 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
group-onsemi 0:098463de4c5d 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
group-onsemi 0:098463de4c5d 923
group-onsemi 0:098463de4c5d 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
group-onsemi 0:098463de4c5d 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
group-onsemi 0:098463de4c5d 926
group-onsemi 0:098463de4c5d 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
group-onsemi 0:098463de4c5d 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
group-onsemi 0:098463de4c5d 929
group-onsemi 0:098463de4c5d 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
group-onsemi 0:098463de4c5d 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
group-onsemi 0:098463de4c5d 932
group-onsemi 0:098463de4c5d 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
group-onsemi 0:098463de4c5d 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
group-onsemi 0:098463de4c5d 935
group-onsemi 0:098463de4c5d 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
group-onsemi 0:098463de4c5d 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
group-onsemi 0:098463de4c5d 938
group-onsemi 0:098463de4c5d 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
group-onsemi 0:098463de4c5d 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
group-onsemi 0:098463de4c5d 941
group-onsemi 0:098463de4c5d 942 /*@}*/ /* end of group CMSIS_DWT */
group-onsemi 0:098463de4c5d 943
group-onsemi 0:098463de4c5d 944
group-onsemi 0:098463de4c5d 945 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
group-onsemi 0:098463de4c5d 947 \brief Type definitions for the Trace Port Interface (TPI)
group-onsemi 0:098463de4c5d 948 @{
group-onsemi 0:098463de4c5d 949 */
group-onsemi 0:098463de4c5d 950
group-onsemi 0:098463de4c5d 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
group-onsemi 0:098463de4c5d 952 */
group-onsemi 0:098463de4c5d 953 typedef struct
group-onsemi 0:098463de4c5d 954 {
group-onsemi 0:098463de4c5d 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
group-onsemi 0:098463de4c5d 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
group-onsemi 0:098463de4c5d 957 uint32_t RESERVED0[2];
group-onsemi 0:098463de4c5d 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
group-onsemi 0:098463de4c5d 959 uint32_t RESERVED1[55];
group-onsemi 0:098463de4c5d 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
group-onsemi 0:098463de4c5d 961 uint32_t RESERVED2[131];
group-onsemi 0:098463de4c5d 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
group-onsemi 0:098463de4c5d 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
group-onsemi 0:098463de4c5d 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
group-onsemi 0:098463de4c5d 965 uint32_t RESERVED3[759];
group-onsemi 0:098463de4c5d 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
group-onsemi 0:098463de4c5d 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
group-onsemi 0:098463de4c5d 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
group-onsemi 0:098463de4c5d 969 uint32_t RESERVED4[1];
group-onsemi 0:098463de4c5d 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
group-onsemi 0:098463de4c5d 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
group-onsemi 0:098463de4c5d 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
group-onsemi 0:098463de4c5d 973 uint32_t RESERVED5[39];
group-onsemi 0:098463de4c5d 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
group-onsemi 0:098463de4c5d 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
group-onsemi 0:098463de4c5d 976 uint32_t RESERVED7[8];
group-onsemi 0:098463de4c5d 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
group-onsemi 0:098463de4c5d 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
group-onsemi 0:098463de4c5d 979 } TPI_Type;
group-onsemi 0:098463de4c5d 980
group-onsemi 0:098463de4c5d 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
group-onsemi 0:098463de4c5d 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
group-onsemi 0:098463de4c5d 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
group-onsemi 0:098463de4c5d 984
group-onsemi 0:098463de4c5d 985 /* TPI Selected Pin Protocol Register Definitions */
group-onsemi 0:098463de4c5d 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
group-onsemi 0:098463de4c5d 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
group-onsemi 0:098463de4c5d 988
group-onsemi 0:098463de4c5d 989 /* TPI Formatter and Flush Status Register Definitions */
group-onsemi 0:098463de4c5d 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
group-onsemi 0:098463de4c5d 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
group-onsemi 0:098463de4c5d 992
group-onsemi 0:098463de4c5d 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
group-onsemi 0:098463de4c5d 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
group-onsemi 0:098463de4c5d 995
group-onsemi 0:098463de4c5d 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
group-onsemi 0:098463de4c5d 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
group-onsemi 0:098463de4c5d 998
group-onsemi 0:098463de4c5d 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
group-onsemi 0:098463de4c5d 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
group-onsemi 0:098463de4c5d 1001
group-onsemi 0:098463de4c5d 1002 /* TPI Formatter and Flush Control Register Definitions */
group-onsemi 0:098463de4c5d 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
group-onsemi 0:098463de4c5d 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
group-onsemi 0:098463de4c5d 1005
group-onsemi 0:098463de4c5d 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
group-onsemi 0:098463de4c5d 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
group-onsemi 0:098463de4c5d 1008
group-onsemi 0:098463de4c5d 1009 /* TPI TRIGGER Register Definitions */
group-onsemi 0:098463de4c5d 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
group-onsemi 0:098463de4c5d 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
group-onsemi 0:098463de4c5d 1012
group-onsemi 0:098463de4c5d 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
group-onsemi 0:098463de4c5d 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
group-onsemi 0:098463de4c5d 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
group-onsemi 0:098463de4c5d 1016
group-onsemi 0:098463de4c5d 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
group-onsemi 0:098463de4c5d 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
group-onsemi 0:098463de4c5d 1019
group-onsemi 0:098463de4c5d 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
group-onsemi 0:098463de4c5d 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
group-onsemi 0:098463de4c5d 1022
group-onsemi 0:098463de4c5d 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
group-onsemi 0:098463de4c5d 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
group-onsemi 0:098463de4c5d 1025
group-onsemi 0:098463de4c5d 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
group-onsemi 0:098463de4c5d 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
group-onsemi 0:098463de4c5d 1028
group-onsemi 0:098463de4c5d 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
group-onsemi 0:098463de4c5d 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
group-onsemi 0:098463de4c5d 1031
group-onsemi 0:098463de4c5d 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
group-onsemi 0:098463de4c5d 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
group-onsemi 0:098463de4c5d 1034
group-onsemi 0:098463de4c5d 1035 /* TPI ITATBCTR2 Register Definitions */
group-onsemi 0:098463de4c5d 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
group-onsemi 0:098463de4c5d 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
group-onsemi 0:098463de4c5d 1038
group-onsemi 0:098463de4c5d 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
group-onsemi 0:098463de4c5d 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
group-onsemi 0:098463de4c5d 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
group-onsemi 0:098463de4c5d 1042
group-onsemi 0:098463de4c5d 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
group-onsemi 0:098463de4c5d 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
group-onsemi 0:098463de4c5d 1045
group-onsemi 0:098463de4c5d 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
group-onsemi 0:098463de4c5d 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
group-onsemi 0:098463de4c5d 1048
group-onsemi 0:098463de4c5d 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
group-onsemi 0:098463de4c5d 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
group-onsemi 0:098463de4c5d 1051
group-onsemi 0:098463de4c5d 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
group-onsemi 0:098463de4c5d 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
group-onsemi 0:098463de4c5d 1054
group-onsemi 0:098463de4c5d 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
group-onsemi 0:098463de4c5d 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
group-onsemi 0:098463de4c5d 1057
group-onsemi 0:098463de4c5d 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
group-onsemi 0:098463de4c5d 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
group-onsemi 0:098463de4c5d 1060
group-onsemi 0:098463de4c5d 1061 /* TPI ITATBCTR0 Register Definitions */
group-onsemi 0:098463de4c5d 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
group-onsemi 0:098463de4c5d 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
group-onsemi 0:098463de4c5d 1064
group-onsemi 0:098463de4c5d 1065 /* TPI Integration Mode Control Register Definitions */
group-onsemi 0:098463de4c5d 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
group-onsemi 0:098463de4c5d 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
group-onsemi 0:098463de4c5d 1068
group-onsemi 0:098463de4c5d 1069 /* TPI DEVID Register Definitions */
group-onsemi 0:098463de4c5d 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
group-onsemi 0:098463de4c5d 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
group-onsemi 0:098463de4c5d 1072
group-onsemi 0:098463de4c5d 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
group-onsemi 0:098463de4c5d 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
group-onsemi 0:098463de4c5d 1075
group-onsemi 0:098463de4c5d 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
group-onsemi 0:098463de4c5d 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
group-onsemi 0:098463de4c5d 1078
group-onsemi 0:098463de4c5d 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
group-onsemi 0:098463de4c5d 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
group-onsemi 0:098463de4c5d 1081
group-onsemi 0:098463de4c5d 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
group-onsemi 0:098463de4c5d 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
group-onsemi 0:098463de4c5d 1084
group-onsemi 0:098463de4c5d 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
group-onsemi 0:098463de4c5d 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
group-onsemi 0:098463de4c5d 1087
group-onsemi 0:098463de4c5d 1088 /* TPI DEVTYPE Register Definitions */
group-onsemi 0:098463de4c5d 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
group-onsemi 0:098463de4c5d 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
group-onsemi 0:098463de4c5d 1091
group-onsemi 0:098463de4c5d 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
group-onsemi 0:098463de4c5d 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
group-onsemi 0:098463de4c5d 1094
group-onsemi 0:098463de4c5d 1095 /*@}*/ /* end of group CMSIS_TPI */
group-onsemi 0:098463de4c5d 1096
group-onsemi 0:098463de4c5d 1097
group-onsemi 0:098463de4c5d 1098 #if (__MPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 1099 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
group-onsemi 0:098463de4c5d 1101 \brief Type definitions for the Memory Protection Unit (MPU)
group-onsemi 0:098463de4c5d 1102 @{
group-onsemi 0:098463de4c5d 1103 */
group-onsemi 0:098463de4c5d 1104
group-onsemi 0:098463de4c5d 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
group-onsemi 0:098463de4c5d 1106 */
group-onsemi 0:098463de4c5d 1107 typedef struct
group-onsemi 0:098463de4c5d 1108 {
group-onsemi 0:098463de4c5d 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
group-onsemi 0:098463de4c5d 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
group-onsemi 0:098463de4c5d 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
group-onsemi 0:098463de4c5d 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
group-onsemi 0:098463de4c5d 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
group-onsemi 0:098463de4c5d 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
group-onsemi 0:098463de4c5d 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
group-onsemi 0:098463de4c5d 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
group-onsemi 0:098463de4c5d 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
group-onsemi 0:098463de4c5d 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
group-onsemi 0:098463de4c5d 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
group-onsemi 0:098463de4c5d 1120 } MPU_Type;
group-onsemi 0:098463de4c5d 1121
group-onsemi 0:098463de4c5d 1122 /* MPU Type Register */
group-onsemi 0:098463de4c5d 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
group-onsemi 0:098463de4c5d 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
group-onsemi 0:098463de4c5d 1125
group-onsemi 0:098463de4c5d 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
group-onsemi 0:098463de4c5d 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
group-onsemi 0:098463de4c5d 1128
group-onsemi 0:098463de4c5d 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
group-onsemi 0:098463de4c5d 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
group-onsemi 0:098463de4c5d 1131
group-onsemi 0:098463de4c5d 1132 /* MPU Control Register */
group-onsemi 0:098463de4c5d 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
group-onsemi 0:098463de4c5d 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
group-onsemi 0:098463de4c5d 1135
group-onsemi 0:098463de4c5d 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
group-onsemi 0:098463de4c5d 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
group-onsemi 0:098463de4c5d 1138
group-onsemi 0:098463de4c5d 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
group-onsemi 0:098463de4c5d 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
group-onsemi 0:098463de4c5d 1141
group-onsemi 0:098463de4c5d 1142 /* MPU Region Number Register */
group-onsemi 0:098463de4c5d 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
group-onsemi 0:098463de4c5d 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
group-onsemi 0:098463de4c5d 1145
group-onsemi 0:098463de4c5d 1146 /* MPU Region Base Address Register */
group-onsemi 0:098463de4c5d 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
group-onsemi 0:098463de4c5d 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
group-onsemi 0:098463de4c5d 1149
group-onsemi 0:098463de4c5d 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
group-onsemi 0:098463de4c5d 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
group-onsemi 0:098463de4c5d 1152
group-onsemi 0:098463de4c5d 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
group-onsemi 0:098463de4c5d 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
group-onsemi 0:098463de4c5d 1155
group-onsemi 0:098463de4c5d 1156 /* MPU Region Attribute and Size Register */
group-onsemi 0:098463de4c5d 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
group-onsemi 0:098463de4c5d 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
group-onsemi 0:098463de4c5d 1159
group-onsemi 0:098463de4c5d 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
group-onsemi 0:098463de4c5d 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
group-onsemi 0:098463de4c5d 1162
group-onsemi 0:098463de4c5d 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
group-onsemi 0:098463de4c5d 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
group-onsemi 0:098463de4c5d 1165
group-onsemi 0:098463de4c5d 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
group-onsemi 0:098463de4c5d 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
group-onsemi 0:098463de4c5d 1168
group-onsemi 0:098463de4c5d 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
group-onsemi 0:098463de4c5d 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
group-onsemi 0:098463de4c5d 1171
group-onsemi 0:098463de4c5d 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
group-onsemi 0:098463de4c5d 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
group-onsemi 0:098463de4c5d 1174
group-onsemi 0:098463de4c5d 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
group-onsemi 0:098463de4c5d 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
group-onsemi 0:098463de4c5d 1177
group-onsemi 0:098463de4c5d 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
group-onsemi 0:098463de4c5d 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
group-onsemi 0:098463de4c5d 1180
group-onsemi 0:098463de4c5d 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
group-onsemi 0:098463de4c5d 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
group-onsemi 0:098463de4c5d 1183
group-onsemi 0:098463de4c5d 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
group-onsemi 0:098463de4c5d 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
group-onsemi 0:098463de4c5d 1186
group-onsemi 0:098463de4c5d 1187 /*@} end of group CMSIS_MPU */
group-onsemi 0:098463de4c5d 1188 #endif
group-onsemi 0:098463de4c5d 1189
group-onsemi 0:098463de4c5d 1190
group-onsemi 0:098463de4c5d 1191 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
group-onsemi 0:098463de4c5d 1193 \brief Type definitions for the Core Debug Registers
group-onsemi 0:098463de4c5d 1194 @{
group-onsemi 0:098463de4c5d 1195 */
group-onsemi 0:098463de4c5d 1196
group-onsemi 0:098463de4c5d 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
group-onsemi 0:098463de4c5d 1198 */
group-onsemi 0:098463de4c5d 1199 typedef struct
group-onsemi 0:098463de4c5d 1200 {
group-onsemi 0:098463de4c5d 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
group-onsemi 0:098463de4c5d 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
group-onsemi 0:098463de4c5d 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
group-onsemi 0:098463de4c5d 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
group-onsemi 0:098463de4c5d 1205 } CoreDebug_Type;
group-onsemi 0:098463de4c5d 1206
group-onsemi 0:098463de4c5d 1207 /* Debug Halting Control and Status Register */
group-onsemi 0:098463de4c5d 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
group-onsemi 0:098463de4c5d 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
group-onsemi 0:098463de4c5d 1210
group-onsemi 0:098463de4c5d 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
group-onsemi 0:098463de4c5d 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
group-onsemi 0:098463de4c5d 1213
group-onsemi 0:098463de4c5d 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
group-onsemi 0:098463de4c5d 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
group-onsemi 0:098463de4c5d 1216
group-onsemi 0:098463de4c5d 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
group-onsemi 0:098463de4c5d 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
group-onsemi 0:098463de4c5d 1219
group-onsemi 0:098463de4c5d 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
group-onsemi 0:098463de4c5d 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
group-onsemi 0:098463de4c5d 1222
group-onsemi 0:098463de4c5d 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
group-onsemi 0:098463de4c5d 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
group-onsemi 0:098463de4c5d 1225
group-onsemi 0:098463de4c5d 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
group-onsemi 0:098463de4c5d 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
group-onsemi 0:098463de4c5d 1228
group-onsemi 0:098463de4c5d 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
group-onsemi 0:098463de4c5d 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
group-onsemi 0:098463de4c5d 1231
group-onsemi 0:098463de4c5d 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
group-onsemi 0:098463de4c5d 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
group-onsemi 0:098463de4c5d 1234
group-onsemi 0:098463de4c5d 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
group-onsemi 0:098463de4c5d 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
group-onsemi 0:098463de4c5d 1237
group-onsemi 0:098463de4c5d 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
group-onsemi 0:098463de4c5d 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
group-onsemi 0:098463de4c5d 1240
group-onsemi 0:098463de4c5d 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
group-onsemi 0:098463de4c5d 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
group-onsemi 0:098463de4c5d 1243
group-onsemi 0:098463de4c5d 1244 /* Debug Core Register Selector Register */
group-onsemi 0:098463de4c5d 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
group-onsemi 0:098463de4c5d 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
group-onsemi 0:098463de4c5d 1247
group-onsemi 0:098463de4c5d 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
group-onsemi 0:098463de4c5d 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
group-onsemi 0:098463de4c5d 1250
group-onsemi 0:098463de4c5d 1251 /* Debug Exception and Monitor Control Register */
group-onsemi 0:098463de4c5d 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
group-onsemi 0:098463de4c5d 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
group-onsemi 0:098463de4c5d 1254
group-onsemi 0:098463de4c5d 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
group-onsemi 0:098463de4c5d 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
group-onsemi 0:098463de4c5d 1257
group-onsemi 0:098463de4c5d 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
group-onsemi 0:098463de4c5d 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
group-onsemi 0:098463de4c5d 1260
group-onsemi 0:098463de4c5d 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
group-onsemi 0:098463de4c5d 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
group-onsemi 0:098463de4c5d 1263
group-onsemi 0:098463de4c5d 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
group-onsemi 0:098463de4c5d 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
group-onsemi 0:098463de4c5d 1266
group-onsemi 0:098463de4c5d 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
group-onsemi 0:098463de4c5d 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
group-onsemi 0:098463de4c5d 1269
group-onsemi 0:098463de4c5d 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
group-onsemi 0:098463de4c5d 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
group-onsemi 0:098463de4c5d 1272
group-onsemi 0:098463de4c5d 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
group-onsemi 0:098463de4c5d 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
group-onsemi 0:098463de4c5d 1275
group-onsemi 0:098463de4c5d 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
group-onsemi 0:098463de4c5d 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
group-onsemi 0:098463de4c5d 1278
group-onsemi 0:098463de4c5d 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
group-onsemi 0:098463de4c5d 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
group-onsemi 0:098463de4c5d 1281
group-onsemi 0:098463de4c5d 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
group-onsemi 0:098463de4c5d 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
group-onsemi 0:098463de4c5d 1284
group-onsemi 0:098463de4c5d 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
group-onsemi 0:098463de4c5d 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
group-onsemi 0:098463de4c5d 1287
group-onsemi 0:098463de4c5d 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
group-onsemi 0:098463de4c5d 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
group-onsemi 0:098463de4c5d 1290
group-onsemi 0:098463de4c5d 1291 /*@} end of group CMSIS_CoreDebug */
group-onsemi 0:098463de4c5d 1292
group-onsemi 0:098463de4c5d 1293
group-onsemi 0:098463de4c5d 1294 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 1295 \defgroup CMSIS_core_base Core Definitions
group-onsemi 0:098463de4c5d 1296 \brief Definitions for base addresses, unions, and structures.
group-onsemi 0:098463de4c5d 1297 @{
group-onsemi 0:098463de4c5d 1298 */
group-onsemi 0:098463de4c5d 1299
group-onsemi 0:098463de4c5d 1300 /* Memory mapping of Cortex-M3 Hardware */
group-onsemi 0:098463de4c5d 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
group-onsemi 0:098463de4c5d 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
group-onsemi 0:098463de4c5d 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
group-onsemi 0:098463de4c5d 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
group-onsemi 0:098463de4c5d 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
group-onsemi 0:098463de4c5d 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
group-onsemi 0:098463de4c5d 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
group-onsemi 0:098463de4c5d 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
group-onsemi 0:098463de4c5d 1309
group-onsemi 0:098463de4c5d 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
group-onsemi 0:098463de4c5d 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
group-onsemi 0:098463de4c5d 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
group-onsemi 0:098463de4c5d 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
group-onsemi 0:098463de4c5d 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
group-onsemi 0:098463de4c5d 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
group-onsemi 0:098463de4c5d 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
group-onsemi 0:098463de4c5d 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
group-onsemi 0:098463de4c5d 1318
group-onsemi 0:098463de4c5d 1319 #if (__MPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
group-onsemi 0:098463de4c5d 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
group-onsemi 0:098463de4c5d 1322 #endif
group-onsemi 0:098463de4c5d 1323
group-onsemi 0:098463de4c5d 1324 /*@} */
group-onsemi 0:098463de4c5d 1325
group-onsemi 0:098463de4c5d 1326
group-onsemi 0:098463de4c5d 1327
group-onsemi 0:098463de4c5d 1328 /*******************************************************************************
group-onsemi 0:098463de4c5d 1329 * Hardware Abstraction Layer
group-onsemi 0:098463de4c5d 1330 Core Function Interface contains:
group-onsemi 0:098463de4c5d 1331 - Core NVIC Functions
group-onsemi 0:098463de4c5d 1332 - Core SysTick Functions
group-onsemi 0:098463de4c5d 1333 - Core Debug Functions
group-onsemi 0:098463de4c5d 1334 - Core Register Access Functions
group-onsemi 0:098463de4c5d 1335 ******************************************************************************/
group-onsemi 0:098463de4c5d 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
group-onsemi 0:098463de4c5d 1337 */
group-onsemi 0:098463de4c5d 1338
group-onsemi 0:098463de4c5d 1339
group-onsemi 0:098463de4c5d 1340
group-onsemi 0:098463de4c5d 1341 /* ########################## NVIC functions #################################### */
group-onsemi 0:098463de4c5d 1342 /** \ingroup CMSIS_Core_FunctionInterface
group-onsemi 0:098463de4c5d 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
group-onsemi 0:098463de4c5d 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
group-onsemi 0:098463de4c5d 1345 @{
group-onsemi 0:098463de4c5d 1346 */
group-onsemi 0:098463de4c5d 1347
group-onsemi 0:098463de4c5d 1348 #ifdef CMSIS_NVIC_VIRTUAL
group-onsemi 0:098463de4c5d 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
group-onsemi 0:098463de4c5d 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
group-onsemi 0:098463de4c5d 1351 #endif
group-onsemi 0:098463de4c5d 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
group-onsemi 0:098463de4c5d 1353 #else
group-onsemi 0:098463de4c5d 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
group-onsemi 0:098463de4c5d 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
group-onsemi 0:098463de4c5d 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
group-onsemi 0:098463de4c5d 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
group-onsemi 0:098463de4c5d 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
group-onsemi 0:098463de4c5d 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
group-onsemi 0:098463de4c5d 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
group-onsemi 0:098463de4c5d 1361 #define NVIC_GetActive __NVIC_GetActive
group-onsemi 0:098463de4c5d 1362 #define NVIC_SetPriority __NVIC_SetPriority
group-onsemi 0:098463de4c5d 1363 #define NVIC_GetPriority __NVIC_GetPriority
group-onsemi 0:098463de4c5d 1364 #define NVIC_SystemReset __NVIC_SystemReset
group-onsemi 0:098463de4c5d 1365 #endif /* CMSIS_NVIC_VIRTUAL */
group-onsemi 0:098463de4c5d 1366
group-onsemi 0:098463de4c5d 1367 #ifdef CMSIS_VECTAB_VIRTUAL
group-onsemi 0:098463de4c5d 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
group-onsemi 0:098463de4c5d 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
group-onsemi 0:098463de4c5d 1370 #endif
group-onsemi 0:098463de4c5d 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
group-onsemi 0:098463de4c5d 1372 #else
group-onsemi 0:098463de4c5d 1373 #define NVIC_SetVector __NVIC_SetVector
group-onsemi 0:098463de4c5d 1374 #define NVIC_GetVector __NVIC_GetVector
group-onsemi 0:098463de4c5d 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
group-onsemi 0:098463de4c5d 1376
group-onsemi 0:098463de4c5d 1377 /** \brief Set Priority Grouping
group-onsemi 0:098463de4c5d 1378
group-onsemi 0:098463de4c5d 1379 The function sets the priority grouping field using the required unlock sequence.
group-onsemi 0:098463de4c5d 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
group-onsemi 0:098463de4c5d 1381 Only values from 0..7 are used.
group-onsemi 0:098463de4c5d 1382 In case of a conflict between priority grouping and available
group-onsemi 0:098463de4c5d 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
group-onsemi 0:098463de4c5d 1384
group-onsemi 0:098463de4c5d 1385 \param [in] PriorityGroup Priority grouping field.
group-onsemi 0:098463de4c5d 1386 */
group-onsemi 0:098463de4c5d 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
group-onsemi 0:098463de4c5d 1388 {
group-onsemi 0:098463de4c5d 1389 uint32_t reg_value;
group-onsemi 0:098463de4c5d 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
group-onsemi 0:098463de4c5d 1391
group-onsemi 0:098463de4c5d 1392 reg_value = SCB->AIRCR; /* read old register configuration */
group-onsemi 0:098463de4c5d 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
group-onsemi 0:098463de4c5d 1394 reg_value = (reg_value |
group-onsemi 0:098463de4c5d 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
group-onsemi 0:098463de4c5d 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
group-onsemi 0:098463de4c5d 1397 SCB->AIRCR = reg_value;
group-onsemi 0:098463de4c5d 1398 }
group-onsemi 0:098463de4c5d 1399
group-onsemi 0:098463de4c5d 1400
group-onsemi 0:098463de4c5d 1401 /** \brief Get Priority Grouping
group-onsemi 0:098463de4c5d 1402
group-onsemi 0:098463de4c5d 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
group-onsemi 0:098463de4c5d 1404
group-onsemi 0:098463de4c5d 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
group-onsemi 0:098463de4c5d 1406 */
group-onsemi 0:098463de4c5d 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
group-onsemi 0:098463de4c5d 1408 {
group-onsemi 0:098463de4c5d 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
group-onsemi 0:098463de4c5d 1410 }
group-onsemi 0:098463de4c5d 1411
group-onsemi 0:098463de4c5d 1412
group-onsemi 0:098463de4c5d 1413 /** \brief Enable External Interrupt
group-onsemi 0:098463de4c5d 1414
group-onsemi 0:098463de4c5d 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
group-onsemi 0:098463de4c5d 1416
group-onsemi 0:098463de4c5d 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
group-onsemi 0:098463de4c5d 1418 */
group-onsemi 0:098463de4c5d 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1420 {
group-onsemi 0:098463de4c5d 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi 0:098463de4c5d 1422 }
group-onsemi 0:098463de4c5d 1423
group-onsemi 0:098463de4c5d 1424
group-onsemi 0:098463de4c5d 1425 /** \brief Disable External Interrupt
group-onsemi 0:098463de4c5d 1426
group-onsemi 0:098463de4c5d 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
group-onsemi 0:098463de4c5d 1428
group-onsemi 0:098463de4c5d 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
group-onsemi 0:098463de4c5d 1430 */
group-onsemi 0:098463de4c5d 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1432 {
group-onsemi 0:098463de4c5d 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi 0:098463de4c5d 1434 __DSB();
group-onsemi 0:098463de4c5d 1435 __ISB();
group-onsemi 0:098463de4c5d 1436 }
group-onsemi 0:098463de4c5d 1437
group-onsemi 0:098463de4c5d 1438
group-onsemi 0:098463de4c5d 1439 /** \brief Get Pending Interrupt
group-onsemi 0:098463de4c5d 1440
group-onsemi 0:098463de4c5d 1441 The function reads the pending register in the NVIC and returns the pending bit
group-onsemi 0:098463de4c5d 1442 for the specified interrupt.
group-onsemi 0:098463de4c5d 1443
group-onsemi 0:098463de4c5d 1444 \param [in] IRQn Interrupt number.
group-onsemi 0:098463de4c5d 1445
group-onsemi 0:098463de4c5d 1446 \return 0 Interrupt status is not pending.
group-onsemi 0:098463de4c5d 1447 \return 1 Interrupt status is pending.
group-onsemi 0:098463de4c5d 1448 */
group-onsemi 0:098463de4c5d 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1450 {
group-onsemi 0:098463de4c5d 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
group-onsemi 0:098463de4c5d 1452 }
group-onsemi 0:098463de4c5d 1453
group-onsemi 0:098463de4c5d 1454
group-onsemi 0:098463de4c5d 1455 /** \brief Set Pending Interrupt
group-onsemi 0:098463de4c5d 1456
group-onsemi 0:098463de4c5d 1457 The function sets the pending bit of an external interrupt.
group-onsemi 0:098463de4c5d 1458
group-onsemi 0:098463de4c5d 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
group-onsemi 0:098463de4c5d 1460 */
group-onsemi 0:098463de4c5d 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1462 {
group-onsemi 0:098463de4c5d 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi 0:098463de4c5d 1464 }
group-onsemi 0:098463de4c5d 1465
group-onsemi 0:098463de4c5d 1466
group-onsemi 0:098463de4c5d 1467 /** \brief Clear Pending Interrupt
group-onsemi 0:098463de4c5d 1468
group-onsemi 0:098463de4c5d 1469 The function clears the pending bit of an external interrupt.
group-onsemi 0:098463de4c5d 1470
group-onsemi 0:098463de4c5d 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
group-onsemi 0:098463de4c5d 1472 */
group-onsemi 0:098463de4c5d 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1474 {
group-onsemi 0:098463de4c5d 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
group-onsemi 0:098463de4c5d 1476 }
group-onsemi 0:098463de4c5d 1477
group-onsemi 0:098463de4c5d 1478
group-onsemi 0:098463de4c5d 1479 /** \brief Get Active Interrupt
group-onsemi 0:098463de4c5d 1480
group-onsemi 0:098463de4c5d 1481 The function reads the active register in NVIC and returns the active bit.
group-onsemi 0:098463de4c5d 1482
group-onsemi 0:098463de4c5d 1483 \param [in] IRQn Interrupt number.
group-onsemi 0:098463de4c5d 1484
group-onsemi 0:098463de4c5d 1485 \return 0 Interrupt status is not active.
group-onsemi 0:098463de4c5d 1486 \return 1 Interrupt status is active.
group-onsemi 0:098463de4c5d 1487 */
group-onsemi 0:098463de4c5d 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1489 {
group-onsemi 0:098463de4c5d 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
group-onsemi 0:098463de4c5d 1491 }
group-onsemi 0:098463de4c5d 1492
group-onsemi 0:098463de4c5d 1493
group-onsemi 0:098463de4c5d 1494 /** \brief Set Interrupt Priority
group-onsemi 0:098463de4c5d 1495
group-onsemi 0:098463de4c5d 1496 The function sets the priority of an interrupt.
group-onsemi 0:098463de4c5d 1497
group-onsemi 0:098463de4c5d 1498 \note The priority cannot be set for every core interrupt.
group-onsemi 0:098463de4c5d 1499
group-onsemi 0:098463de4c5d 1500 \param [in] IRQn Interrupt number.
group-onsemi 0:098463de4c5d 1501 \param [in] priority Priority to set.
group-onsemi 0:098463de4c5d 1502 */
group-onsemi 0:098463de4c5d 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
group-onsemi 0:098463de4c5d 1504 {
group-onsemi 0:098463de4c5d 1505 if((int32_t)IRQn < 0) {
group-onsemi 0:098463de4c5d 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
group-onsemi 0:098463de4c5d 1507 }
group-onsemi 0:098463de4c5d 1508 else {
group-onsemi 0:098463de4c5d 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
group-onsemi 0:098463de4c5d 1510 }
group-onsemi 0:098463de4c5d 1511 }
group-onsemi 0:098463de4c5d 1512
group-onsemi 0:098463de4c5d 1513
group-onsemi 0:098463de4c5d 1514 /** \brief Get Interrupt Priority
group-onsemi 0:098463de4c5d 1515
group-onsemi 0:098463de4c5d 1516 The function reads the priority of an interrupt. The interrupt
group-onsemi 0:098463de4c5d 1517 number can be positive to specify an external (device specific)
group-onsemi 0:098463de4c5d 1518 interrupt, or negative to specify an internal (core) interrupt.
group-onsemi 0:098463de4c5d 1519
group-onsemi 0:098463de4c5d 1520
group-onsemi 0:098463de4c5d 1521 \param [in] IRQn Interrupt number.
group-onsemi 0:098463de4c5d 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
group-onsemi 0:098463de4c5d 1523 priority bits of the microcontroller.
group-onsemi 0:098463de4c5d 1524 */
group-onsemi 0:098463de4c5d 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
group-onsemi 0:098463de4c5d 1526 {
group-onsemi 0:098463de4c5d 1527
group-onsemi 0:098463de4c5d 1528 if((int32_t)IRQn < 0) {
group-onsemi 0:098463de4c5d 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
group-onsemi 0:098463de4c5d 1530 }
group-onsemi 0:098463de4c5d 1531 else {
group-onsemi 0:098463de4c5d 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
group-onsemi 0:098463de4c5d 1533 }
group-onsemi 0:098463de4c5d 1534 }
group-onsemi 0:098463de4c5d 1535
group-onsemi 0:098463de4c5d 1536
group-onsemi 0:098463de4c5d 1537 /** \brief Encode Priority
group-onsemi 0:098463de4c5d 1538
group-onsemi 0:098463de4c5d 1539 The function encodes the priority for an interrupt with the given priority group,
group-onsemi 0:098463de4c5d 1540 preemptive priority value, and subpriority value.
group-onsemi 0:098463de4c5d 1541 In case of a conflict between priority grouping and available
group-onsemi 0:098463de4c5d 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
group-onsemi 0:098463de4c5d 1543
group-onsemi 0:098463de4c5d 1544 \param [in] PriorityGroup Used priority group.
group-onsemi 0:098463de4c5d 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
group-onsemi 0:098463de4c5d 1546 \param [in] SubPriority Subpriority value (starting from 0).
group-onsemi 0:098463de4c5d 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
group-onsemi 0:098463de4c5d 1548 */
group-onsemi 0:098463de4c5d 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
group-onsemi 0:098463de4c5d 1550 {
group-onsemi 0:098463de4c5d 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
group-onsemi 0:098463de4c5d 1552 uint32_t PreemptPriorityBits;
group-onsemi 0:098463de4c5d 1553 uint32_t SubPriorityBits;
group-onsemi 0:098463de4c5d 1554
group-onsemi 0:098463de4c5d 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
group-onsemi 0:098463de4c5d 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
group-onsemi 0:098463de4c5d 1557
group-onsemi 0:098463de4c5d 1558 return (
group-onsemi 0:098463de4c5d 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
group-onsemi 0:098463de4c5d 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
group-onsemi 0:098463de4c5d 1561 );
group-onsemi 0:098463de4c5d 1562 }
group-onsemi 0:098463de4c5d 1563
group-onsemi 0:098463de4c5d 1564
group-onsemi 0:098463de4c5d 1565 /** \brief Decode Priority
group-onsemi 0:098463de4c5d 1566
group-onsemi 0:098463de4c5d 1567 The function decodes an interrupt priority value with a given priority group to
group-onsemi 0:098463de4c5d 1568 preemptive priority value and subpriority value.
group-onsemi 0:098463de4c5d 1569 In case of a conflict between priority grouping and available
group-onsemi 0:098463de4c5d 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
group-onsemi 0:098463de4c5d 1571
group-onsemi 0:098463de4c5d 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
group-onsemi 0:098463de4c5d 1573 \param [in] PriorityGroup Used priority group.
group-onsemi 0:098463de4c5d 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
group-onsemi 0:098463de4c5d 1575 \param [out] pSubPriority Subpriority value (starting from 0).
group-onsemi 0:098463de4c5d 1576 */
group-onsemi 0:098463de4c5d 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
group-onsemi 0:098463de4c5d 1578 {
group-onsemi 0:098463de4c5d 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
group-onsemi 0:098463de4c5d 1580 uint32_t PreemptPriorityBits;
group-onsemi 0:098463de4c5d 1581 uint32_t SubPriorityBits;
group-onsemi 0:098463de4c5d 1582
group-onsemi 0:098463de4c5d 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
group-onsemi 0:098463de4c5d 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
group-onsemi 0:098463de4c5d 1585
group-onsemi 0:098463de4c5d 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
group-onsemi 0:098463de4c5d 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
group-onsemi 0:098463de4c5d 1588 }
group-onsemi 0:098463de4c5d 1589
group-onsemi 0:098463de4c5d 1590
group-onsemi 0:098463de4c5d 1591 /** \brief System Reset
group-onsemi 0:098463de4c5d 1592
group-onsemi 0:098463de4c5d 1593 The function initiates a system reset request to reset the MCU.
group-onsemi 0:098463de4c5d 1594 */
group-onsemi 0:098463de4c5d 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
group-onsemi 0:098463de4c5d 1596 {
group-onsemi 0:098463de4c5d 1597 __DSB(); /* Ensure all outstanding memory accesses included
group-onsemi 0:098463de4c5d 1598 buffered write are completed before reset */
group-onsemi 0:098463de4c5d 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
group-onsemi 0:098463de4c5d 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
group-onsemi 0:098463de4c5d 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
group-onsemi 0:098463de4c5d 1602 __DSB(); /* Ensure completion of memory access */
group-onsemi 0:098463de4c5d 1603 while(1) { __NOP(); } /* wait until reset */
group-onsemi 0:098463de4c5d 1604 }
group-onsemi 0:098463de4c5d 1605
group-onsemi 0:098463de4c5d 1606 /*@} end of CMSIS_Core_NVICFunctions */
group-onsemi 0:098463de4c5d 1607
group-onsemi 0:098463de4c5d 1608
group-onsemi 0:098463de4c5d 1609
group-onsemi 0:098463de4c5d 1610 /* ################################## SysTick function ############################################ */
group-onsemi 0:098463de4c5d 1611 /** \ingroup CMSIS_Core_FunctionInterface
group-onsemi 0:098463de4c5d 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
group-onsemi 0:098463de4c5d 1613 \brief Functions that configure the System.
group-onsemi 0:098463de4c5d 1614 @{
group-onsemi 0:098463de4c5d 1615 */
group-onsemi 0:098463de4c5d 1616
group-onsemi 0:098463de4c5d 1617 #if (__Vendor_SysTickConfig == 0)
group-onsemi 0:098463de4c5d 1618
group-onsemi 0:098463de4c5d 1619 /** \brief System Tick Configuration
group-onsemi 0:098463de4c5d 1620
group-onsemi 0:098463de4c5d 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
group-onsemi 0:098463de4c5d 1622 Counter is in free running mode to generate periodic interrupts.
group-onsemi 0:098463de4c5d 1623
group-onsemi 0:098463de4c5d 1624 \param [in] ticks Number of ticks between two interrupts.
group-onsemi 0:098463de4c5d 1625
group-onsemi 0:098463de4c5d 1626 \return 0 Function succeeded.
group-onsemi 0:098463de4c5d 1627 \return 1 Function failed.
group-onsemi 0:098463de4c5d 1628
group-onsemi 0:098463de4c5d 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
group-onsemi 0:098463de4c5d 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
group-onsemi 0:098463de4c5d 1631 must contain a vendor-specific implementation of this function.
group-onsemi 0:098463de4c5d 1632
group-onsemi 0:098463de4c5d 1633 */
group-onsemi 0:098463de4c5d 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
group-onsemi 0:098463de4c5d 1635 {
group-onsemi 0:098463de4c5d 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
group-onsemi 0:098463de4c5d 1637
group-onsemi 0:098463de4c5d 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
group-onsemi 0:098463de4c5d 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
group-onsemi 0:098463de4c5d 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
group-onsemi 0:098463de4c5d 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
group-onsemi 0:098463de4c5d 1642 SysTick_CTRL_TICKINT_Msk |
group-onsemi 0:098463de4c5d 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
group-onsemi 0:098463de4c5d 1644 return (0UL); /* Function successful */
group-onsemi 0:098463de4c5d 1645 }
group-onsemi 0:098463de4c5d 1646
group-onsemi 0:098463de4c5d 1647 #endif
group-onsemi 0:098463de4c5d 1648
group-onsemi 0:098463de4c5d 1649 /*@} end of CMSIS_Core_SysTickFunctions */
group-onsemi 0:098463de4c5d 1650
group-onsemi 0:098463de4c5d 1651
group-onsemi 0:098463de4c5d 1652
group-onsemi 0:098463de4c5d 1653 /* ##################################### Debug In/Output function ########################################### */
group-onsemi 0:098463de4c5d 1654 /** \ingroup CMSIS_Core_FunctionInterface
group-onsemi 0:098463de4c5d 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
group-onsemi 0:098463de4c5d 1656 \brief Functions that access the ITM debug interface.
group-onsemi 0:098463de4c5d 1657 @{
group-onsemi 0:098463de4c5d 1658 */
group-onsemi 0:098463de4c5d 1659
group-onsemi 0:098463de4c5d 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
group-onsemi 0:098463de4c5d 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
group-onsemi 0:098463de4c5d 1662
group-onsemi 0:098463de4c5d 1663
group-onsemi 0:098463de4c5d 1664 /** \brief ITM Send Character
group-onsemi 0:098463de4c5d 1665
group-onsemi 0:098463de4c5d 1666 The function transmits a character via the ITM channel 0, and
group-onsemi 0:098463de4c5d 1667 \li Just returns when no debugger is connected that has booked the output.
group-onsemi 0:098463de4c5d 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
group-onsemi 0:098463de4c5d 1669
group-onsemi 0:098463de4c5d 1670 \param [in] ch Character to transmit.
group-onsemi 0:098463de4c5d 1671
group-onsemi 0:098463de4c5d 1672 \returns Character to transmit.
group-onsemi 0:098463de4c5d 1673 */
group-onsemi 0:098463de4c5d 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
group-onsemi 0:098463de4c5d 1675 {
group-onsemi 0:098463de4c5d 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
group-onsemi 0:098463de4c5d 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
group-onsemi 0:098463de4c5d 1678 {
group-onsemi 0:098463de4c5d 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
group-onsemi 0:098463de4c5d 1680 ITM->PORT[0].u8 = (uint8_t)ch;
group-onsemi 0:098463de4c5d 1681 }
group-onsemi 0:098463de4c5d 1682 return (ch);
group-onsemi 0:098463de4c5d 1683 }
group-onsemi 0:098463de4c5d 1684
group-onsemi 0:098463de4c5d 1685
group-onsemi 0:098463de4c5d 1686 /** \brief ITM Receive Character
group-onsemi 0:098463de4c5d 1687
group-onsemi 0:098463de4c5d 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
group-onsemi 0:098463de4c5d 1689
group-onsemi 0:098463de4c5d 1690 \return Received character.
group-onsemi 0:098463de4c5d 1691 \return -1 No character pending.
group-onsemi 0:098463de4c5d 1692 */
group-onsemi 0:098463de4c5d 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
group-onsemi 0:098463de4c5d 1694 int32_t ch = -1; /* no character available */
group-onsemi 0:098463de4c5d 1695
group-onsemi 0:098463de4c5d 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
group-onsemi 0:098463de4c5d 1697 ch = ITM_RxBuffer;
group-onsemi 0:098463de4c5d 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
group-onsemi 0:098463de4c5d 1699 }
group-onsemi 0:098463de4c5d 1700
group-onsemi 0:098463de4c5d 1701 return (ch);
group-onsemi 0:098463de4c5d 1702 }
group-onsemi 0:098463de4c5d 1703
group-onsemi 0:098463de4c5d 1704
group-onsemi 0:098463de4c5d 1705 /** \brief ITM Check Character
group-onsemi 0:098463de4c5d 1706
group-onsemi 0:098463de4c5d 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
group-onsemi 0:098463de4c5d 1708
group-onsemi 0:098463de4c5d 1709 \return 0 No character available.
group-onsemi 0:098463de4c5d 1710 \return 1 Character available.
group-onsemi 0:098463de4c5d 1711 */
group-onsemi 0:098463de4c5d 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
group-onsemi 0:098463de4c5d 1713
group-onsemi 0:098463de4c5d 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
group-onsemi 0:098463de4c5d 1715 return (0); /* no character available */
group-onsemi 0:098463de4c5d 1716 } else {
group-onsemi 0:098463de4c5d 1717 return (1); /* character available */
group-onsemi 0:098463de4c5d 1718 }
group-onsemi 0:098463de4c5d 1719 }
group-onsemi 0:098463de4c5d 1720
group-onsemi 0:098463de4c5d 1721 /*@} end of CMSIS_core_DebugFunctions */
group-onsemi 0:098463de4c5d 1722
group-onsemi 0:098463de4c5d 1723
group-onsemi 0:098463de4c5d 1724
group-onsemi 0:098463de4c5d 1725
group-onsemi 0:098463de4c5d 1726 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 1727 }
group-onsemi 0:098463de4c5d 1728 #endif
group-onsemi 0:098463de4c5d 1729
group-onsemi 0:098463de4c5d 1730 #endif /* __CORE_CM3_H_DEPENDANT */
group-onsemi 0:098463de4c5d 1731
group-onsemi 0:098463de4c5d 1732 #endif /* __CMSIS_GENERIC */