ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_caFunc.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file core_caFunc.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-A Core Function Access Header File
group-onsemi 0:098463de4c5d 4 * @version V3.10
group-onsemi 0:098463de4c5d 5 * @date 30 Oct 2013
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @note
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 ******************************************************************************/
group-onsemi 0:098463de4c5d 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 All rights reserved.
group-onsemi 0:098463de4c5d 13 Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 14 modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 - Redistributions of source code must retain the above copyright
group-onsemi 0:098463de4c5d 16 notice, this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 - Redistributions in binary form must reproduce the above copyright
group-onsemi 0:098463de4c5d 18 notice, this list of conditions and the following disclaimer in the
group-onsemi 0:098463de4c5d 19 documentation and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 - Neither the name of ARM nor the names of its contributors may be used
group-onsemi 0:098463de4c5d 21 to endorse or promote products derived from this software without
group-onsemi 0:098463de4c5d 22 specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi 0:098463de4c5d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi 0:098463de4c5d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi 0:098463de4c5d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi 0:098463de4c5d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi 0:098463de4c5d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi 0:098463de4c5d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi 0:098463de4c5d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi 0:098463de4c5d 34 POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 35 ---------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #ifndef __CORE_CAFUNC_H__
group-onsemi 0:098463de4c5d 39 #define __CORE_CAFUNC_H__
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 /* ########################### Core Function Access ########################### */
group-onsemi 0:098463de4c5d 43 /** \ingroup CMSIS_Core_FunctionInterface
group-onsemi 0:098463de4c5d 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
group-onsemi 0:098463de4c5d 45 @{
group-onsemi 0:098463de4c5d 46 */
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
group-onsemi 0:098463de4c5d 49 /* ARM armcc specific functions */
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 #if (__ARMCC_VERSION < 400677)
group-onsemi 0:098463de4c5d 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
group-onsemi 0:098463de4c5d 53 #endif
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 #define MODE_USR 0x10
group-onsemi 0:098463de4c5d 56 #define MODE_FIQ 0x11
group-onsemi 0:098463de4c5d 57 #define MODE_IRQ 0x12
group-onsemi 0:098463de4c5d 58 #define MODE_SVC 0x13
group-onsemi 0:098463de4c5d 59 #define MODE_MON 0x16
group-onsemi 0:098463de4c5d 60 #define MODE_ABT 0x17
group-onsemi 0:098463de4c5d 61 #define MODE_HYP 0x1A
group-onsemi 0:098463de4c5d 62 #define MODE_UND 0x1B
group-onsemi 0:098463de4c5d 63 #define MODE_SYS 0x1F
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 /** \brief Get APSR Register
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 This function returns the content of the APSR Register.
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 \return APSR Register value
group-onsemi 0:098463de4c5d 70 */
group-onsemi 0:098463de4c5d 71 __STATIC_INLINE uint32_t __get_APSR(void)
group-onsemi 0:098463de4c5d 72 {
group-onsemi 0:098463de4c5d 73 register uint32_t __regAPSR __ASM("apsr");
group-onsemi 0:098463de4c5d 74 return(__regAPSR);
group-onsemi 0:098463de4c5d 75 }
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 /** \brief Get CPSR Register
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 This function returns the content of the CPSR Register.
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 \return CPSR Register value
group-onsemi 0:098463de4c5d 83 */
group-onsemi 0:098463de4c5d 84 __STATIC_INLINE uint32_t __get_CPSR(void)
group-onsemi 0:098463de4c5d 85 {
group-onsemi 0:098463de4c5d 86 register uint32_t __regCPSR __ASM("cpsr");
group-onsemi 0:098463de4c5d 87 return(__regCPSR);
group-onsemi 0:098463de4c5d 88 }
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 /** \brief Set Stack Pointer
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 This function assigns the given value to the current stack pointer.
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 \param [in] topOfStack Stack Pointer value to set
group-onsemi 0:098463de4c5d 95 */
group-onsemi 0:098463de4c5d 96 register uint32_t __regSP __ASM("sp");
group-onsemi 0:098463de4c5d 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
group-onsemi 0:098463de4c5d 98 {
group-onsemi 0:098463de4c5d 99 __regSP = topOfStack;
group-onsemi 0:098463de4c5d 100 }
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 /** \brief Get link register
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 This function returns the value of the link register
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 \return Value of link register
group-onsemi 0:098463de4c5d 108 */
group-onsemi 0:098463de4c5d 109 register uint32_t __reglr __ASM("lr");
group-onsemi 0:098463de4c5d 110 __STATIC_INLINE uint32_t __get_LR(void)
group-onsemi 0:098463de4c5d 111 {
group-onsemi 0:098463de4c5d 112 return(__reglr);
group-onsemi 0:098463de4c5d 113 }
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 /** \brief Set link register
group-onsemi 0:098463de4c5d 116
group-onsemi 0:098463de4c5d 117 This function sets the value of the link register
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 \param [in] lr LR value to set
group-onsemi 0:098463de4c5d 120 */
group-onsemi 0:098463de4c5d 121 __STATIC_INLINE void __set_LR(uint32_t lr)
group-onsemi 0:098463de4c5d 122 {
group-onsemi 0:098463de4c5d 123 __reglr = lr;
group-onsemi 0:098463de4c5d 124 }
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126 /** \brief Set Process Stack Pointer
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
group-onsemi 0:098463de4c5d 131 */
group-onsemi 0:098463de4c5d 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
group-onsemi 0:098463de4c5d 133 {
group-onsemi 0:098463de4c5d 134 ARM
group-onsemi 0:098463de4c5d 135 PRESERVE8
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
group-onsemi 0:098463de4c5d 138 MRS R1, CPSR
group-onsemi 0:098463de4c5d 139 CPS #MODE_SYS ;no effect in USR mode
group-onsemi 0:098463de4c5d 140 MOV SP, R0
group-onsemi 0:098463de4c5d 141 MSR CPSR_c, R1 ;no effect in USR mode
group-onsemi 0:098463de4c5d 142 ISB
group-onsemi 0:098463de4c5d 143 BX LR
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 }
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 /** \brief Set User Mode
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 This function changes the processor state to User Mode
group-onsemi 0:098463de4c5d 150 */
group-onsemi 0:098463de4c5d 151 __STATIC_ASM void __set_CPS_USR(void)
group-onsemi 0:098463de4c5d 152 {
group-onsemi 0:098463de4c5d 153 ARM
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 CPS #MODE_USR
group-onsemi 0:098463de4c5d 156 BX LR
group-onsemi 0:098463de4c5d 157 }
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 /** \brief Enable FIQ
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 163 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 164 */
group-onsemi 0:098463de4c5d 165 #define __enable_fault_irq __enable_fiq
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 /** \brief Disable FIQ
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 171 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 172 */
group-onsemi 0:098463de4c5d 173 #define __disable_fault_irq __disable_fiq
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175
group-onsemi 0:098463de4c5d 176 /** \brief Get FPSCR
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 This function returns the current value of the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 \return Floating Point Status/Control register value
group-onsemi 0:098463de4c5d 181 */
group-onsemi 0:098463de4c5d 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
group-onsemi 0:098463de4c5d 183 {
group-onsemi 0:098463de4c5d 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 185 register uint32_t __regfpscr __ASM("fpscr");
group-onsemi 0:098463de4c5d 186 return(__regfpscr);
group-onsemi 0:098463de4c5d 187 #else
group-onsemi 0:098463de4c5d 188 return(0);
group-onsemi 0:098463de4c5d 189 #endif
group-onsemi 0:098463de4c5d 190 }
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 /** \brief Set FPSCR
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 This function assigns the given value to the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 196
group-onsemi 0:098463de4c5d 197 \param [in] fpscr Floating Point Status/Control value to set
group-onsemi 0:098463de4c5d 198 */
group-onsemi 0:098463de4c5d 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
group-onsemi 0:098463de4c5d 200 {
group-onsemi 0:098463de4c5d 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 202 register uint32_t __regfpscr __ASM("fpscr");
group-onsemi 0:098463de4c5d 203 __regfpscr = (fpscr);
group-onsemi 0:098463de4c5d 204 #endif
group-onsemi 0:098463de4c5d 205 }
group-onsemi 0:098463de4c5d 206
group-onsemi 0:098463de4c5d 207 /** \brief Get FPEXC
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 This function returns the current value of the Floating Point Exception Control register.
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 \return Floating Point Exception Control register value
group-onsemi 0:098463de4c5d 212 */
group-onsemi 0:098463de4c5d 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
group-onsemi 0:098463de4c5d 214 {
group-onsemi 0:098463de4c5d 215 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 216 register uint32_t __regfpexc __ASM("fpexc");
group-onsemi 0:098463de4c5d 217 return(__regfpexc);
group-onsemi 0:098463de4c5d 218 #else
group-onsemi 0:098463de4c5d 219 return(0);
group-onsemi 0:098463de4c5d 220 #endif
group-onsemi 0:098463de4c5d 221 }
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 /** \brief Set FPEXC
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 This function assigns the given value to the Floating Point Exception Control register.
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 \param [in] fpscr Floating Point Exception Control value to set
group-onsemi 0:098463de4c5d 229 */
group-onsemi 0:098463de4c5d 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
group-onsemi 0:098463de4c5d 231 {
group-onsemi 0:098463de4c5d 232 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 233 register uint32_t __regfpexc __ASM("fpexc");
group-onsemi 0:098463de4c5d 234 __regfpexc = (fpexc);
group-onsemi 0:098463de4c5d 235 #endif
group-onsemi 0:098463de4c5d 236 }
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 /** \brief Get CPACR
group-onsemi 0:098463de4c5d 239
group-onsemi 0:098463de4c5d 240 This function returns the current value of the Coprocessor Access Control register.
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 \return Coprocessor Access Control register value
group-onsemi 0:098463de4c5d 243 */
group-onsemi 0:098463de4c5d 244 __STATIC_INLINE uint32_t __get_CPACR(void)
group-onsemi 0:098463de4c5d 245 {
group-onsemi 0:098463de4c5d 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
group-onsemi 0:098463de4c5d 247 return __regCPACR;
group-onsemi 0:098463de4c5d 248 }
group-onsemi 0:098463de4c5d 249
group-onsemi 0:098463de4c5d 250 /** \brief Set CPACR
group-onsemi 0:098463de4c5d 251
group-onsemi 0:098463de4c5d 252 This function assigns the given value to the Coprocessor Access Control register.
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 \param [in] cpacr Coprocessor Acccess Control value to set
group-onsemi 0:098463de4c5d 255 */
group-onsemi 0:098463de4c5d 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
group-onsemi 0:098463de4c5d 257 {
group-onsemi 0:098463de4c5d 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
group-onsemi 0:098463de4c5d 259 __regCPACR = cpacr;
group-onsemi 0:098463de4c5d 260 __ISB();
group-onsemi 0:098463de4c5d 261 }
group-onsemi 0:098463de4c5d 262
group-onsemi 0:098463de4c5d 263 /** \brief Get CBAR
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 This function returns the value of the Configuration Base Address register.
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 \return Configuration Base Address register value
group-onsemi 0:098463de4c5d 268 */
group-onsemi 0:098463de4c5d 269 __STATIC_INLINE uint32_t __get_CBAR() {
group-onsemi 0:098463de4c5d 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
group-onsemi 0:098463de4c5d 271 return(__regCBAR);
group-onsemi 0:098463de4c5d 272 }
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 /** \brief Get TTBR0
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 This function returns the value of the Translation Table Base Register 0.
group-onsemi 0:098463de4c5d 277
group-onsemi 0:098463de4c5d 278 \return Translation Table Base Register 0 value
group-onsemi 0:098463de4c5d 279 */
group-onsemi 0:098463de4c5d 280 __STATIC_INLINE uint32_t __get_TTBR0() {
group-onsemi 0:098463de4c5d 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
group-onsemi 0:098463de4c5d 282 return(__regTTBR0);
group-onsemi 0:098463de4c5d 283 }
group-onsemi 0:098463de4c5d 284
group-onsemi 0:098463de4c5d 285 /** \brief Set TTBR0
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 This function assigns the given value to the Translation Table Base Register 0.
group-onsemi 0:098463de4c5d 288
group-onsemi 0:098463de4c5d 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
group-onsemi 0:098463de4c5d 290 */
group-onsemi 0:098463de4c5d 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
group-onsemi 0:098463de4c5d 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
group-onsemi 0:098463de4c5d 293 __regTTBR0 = ttbr0;
group-onsemi 0:098463de4c5d 294 __ISB();
group-onsemi 0:098463de4c5d 295 }
group-onsemi 0:098463de4c5d 296
group-onsemi 0:098463de4c5d 297 /** \brief Get DACR
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 This function returns the value of the Domain Access Control Register.
group-onsemi 0:098463de4c5d 300
group-onsemi 0:098463de4c5d 301 \return Domain Access Control Register value
group-onsemi 0:098463de4c5d 302 */
group-onsemi 0:098463de4c5d 303 __STATIC_INLINE uint32_t __get_DACR() {
group-onsemi 0:098463de4c5d 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
group-onsemi 0:098463de4c5d 305 return(__regDACR);
group-onsemi 0:098463de4c5d 306 }
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 /** \brief Set DACR
group-onsemi 0:098463de4c5d 309
group-onsemi 0:098463de4c5d 310 This function assigns the given value to the Domain Access Control Register.
group-onsemi 0:098463de4c5d 311
group-onsemi 0:098463de4c5d 312 \param [in] dacr Domain Access Control Register value to set
group-onsemi 0:098463de4c5d 313 */
group-onsemi 0:098463de4c5d 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
group-onsemi 0:098463de4c5d 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
group-onsemi 0:098463de4c5d 316 __regDACR = dacr;
group-onsemi 0:098463de4c5d 317 __ISB();
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 /******************************** Cache and BTAC enable ****************************************************/
group-onsemi 0:098463de4c5d 321
group-onsemi 0:098463de4c5d 322 /** \brief Set SCTLR
group-onsemi 0:098463de4c5d 323
group-onsemi 0:098463de4c5d 324 This function assigns the given value to the System Control Register.
group-onsemi 0:098463de4c5d 325
group-onsemi 0:098463de4c5d 326 \param [in] sctlr System Control Register value to set
group-onsemi 0:098463de4c5d 327 */
group-onsemi 0:098463de4c5d 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
group-onsemi 0:098463de4c5d 329 {
group-onsemi 0:098463de4c5d 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
group-onsemi 0:098463de4c5d 331 __regSCTLR = sctlr;
group-onsemi 0:098463de4c5d 332 }
group-onsemi 0:098463de4c5d 333
group-onsemi 0:098463de4c5d 334 /** \brief Get SCTLR
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 This function returns the value of the System Control Register.
group-onsemi 0:098463de4c5d 337
group-onsemi 0:098463de4c5d 338 \return System Control Register value
group-onsemi 0:098463de4c5d 339 */
group-onsemi 0:098463de4c5d 340 __STATIC_INLINE uint32_t __get_SCTLR() {
group-onsemi 0:098463de4c5d 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
group-onsemi 0:098463de4c5d 342 return(__regSCTLR);
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 /** \brief Enable Caches
group-onsemi 0:098463de4c5d 346
group-onsemi 0:098463de4c5d 347 Enable Caches
group-onsemi 0:098463de4c5d 348 */
group-onsemi 0:098463de4c5d 349 __STATIC_INLINE void __enable_caches(void) {
group-onsemi 0:098463de4c5d 350 // Set I bit 12 to enable I Cache
group-onsemi 0:098463de4c5d 351 // Set C bit 2 to enable D Cache
group-onsemi 0:098463de4c5d 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
group-onsemi 0:098463de4c5d 353 }
group-onsemi 0:098463de4c5d 354
group-onsemi 0:098463de4c5d 355 /** \brief Disable Caches
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 Disable Caches
group-onsemi 0:098463de4c5d 358 */
group-onsemi 0:098463de4c5d 359 __STATIC_INLINE void __disable_caches(void) {
group-onsemi 0:098463de4c5d 360 // Clear I bit 12 to disable I Cache
group-onsemi 0:098463de4c5d 361 // Clear C bit 2 to disable D Cache
group-onsemi 0:098463de4c5d 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
group-onsemi 0:098463de4c5d 363 __ISB();
group-onsemi 0:098463de4c5d 364 }
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 /** \brief Enable BTAC
group-onsemi 0:098463de4c5d 367
group-onsemi 0:098463de4c5d 368 Enable BTAC
group-onsemi 0:098463de4c5d 369 */
group-onsemi 0:098463de4c5d 370 __STATIC_INLINE void __enable_btac(void) {
group-onsemi 0:098463de4c5d 371 // Set Z bit 11 to enable branch prediction
group-onsemi 0:098463de4c5d 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
group-onsemi 0:098463de4c5d 373 __ISB();
group-onsemi 0:098463de4c5d 374 }
group-onsemi 0:098463de4c5d 375
group-onsemi 0:098463de4c5d 376 /** \brief Disable BTAC
group-onsemi 0:098463de4c5d 377
group-onsemi 0:098463de4c5d 378 Disable BTAC
group-onsemi 0:098463de4c5d 379 */
group-onsemi 0:098463de4c5d 380 __STATIC_INLINE void __disable_btac(void) {
group-onsemi 0:098463de4c5d 381 // Clear Z bit 11 to disable branch prediction
group-onsemi 0:098463de4c5d 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
group-onsemi 0:098463de4c5d 383 }
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385
group-onsemi 0:098463de4c5d 386 /** \brief Enable MMU
group-onsemi 0:098463de4c5d 387
group-onsemi 0:098463de4c5d 388 Enable MMU
group-onsemi 0:098463de4c5d 389 */
group-onsemi 0:098463de4c5d 390 __STATIC_INLINE void __enable_mmu(void) {
group-onsemi 0:098463de4c5d 391 // Set M bit 0 to enable the MMU
group-onsemi 0:098463de4c5d 392 // Set AFE bit to enable simplified access permissions model
group-onsemi 0:098463de4c5d 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
group-onsemi 0:098463de4c5d 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
group-onsemi 0:098463de4c5d 395 __ISB();
group-onsemi 0:098463de4c5d 396 }
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 /** \brief Disable MMU
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400 Disable MMU
group-onsemi 0:098463de4c5d 401 */
group-onsemi 0:098463de4c5d 402 __STATIC_INLINE void __disable_mmu(void) {
group-onsemi 0:098463de4c5d 403 // Clear M bit 0 to disable the MMU
group-onsemi 0:098463de4c5d 404 __set_SCTLR( __get_SCTLR() & ~1);
group-onsemi 0:098463de4c5d 405 __ISB();
group-onsemi 0:098463de4c5d 406 }
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 /******************************** TLB maintenance operations ************************************************/
group-onsemi 0:098463de4c5d 409 /** \brief Invalidate the whole tlb
group-onsemi 0:098463de4c5d 410
group-onsemi 0:098463de4c5d 411 TLBIALL. Invalidate the whole tlb
group-onsemi 0:098463de4c5d 412 */
group-onsemi 0:098463de4c5d 413
group-onsemi 0:098463de4c5d 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
group-onsemi 0:098463de4c5d 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
group-onsemi 0:098463de4c5d 416 __TLBIALL = 0;
group-onsemi 0:098463de4c5d 417 __DSB();
group-onsemi 0:098463de4c5d 418 __ISB();
group-onsemi 0:098463de4c5d 419 }
group-onsemi 0:098463de4c5d 420
group-onsemi 0:098463de4c5d 421 /******************************** BTB maintenance operations ************************************************/
group-onsemi 0:098463de4c5d 422 /** \brief Invalidate entire branch predictor array
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 BPIALL. Branch Predictor Invalidate All.
group-onsemi 0:098463de4c5d 425 */
group-onsemi 0:098463de4c5d 426
group-onsemi 0:098463de4c5d 427 __STATIC_INLINE void __v7_inv_btac(void) {
group-onsemi 0:098463de4c5d 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
group-onsemi 0:098463de4c5d 429 __BPIALL = 0;
group-onsemi 0:098463de4c5d 430 __DSB(); //ensure completion of the invalidation
group-onsemi 0:098463de4c5d 431 __ISB(); //ensure instruction fetch path sees new state
group-onsemi 0:098463de4c5d 432 }
group-onsemi 0:098463de4c5d 433
group-onsemi 0:098463de4c5d 434
group-onsemi 0:098463de4c5d 435 /******************************** L1 cache operations ******************************************************/
group-onsemi 0:098463de4c5d 436
group-onsemi 0:098463de4c5d 437 /** \brief Invalidate the whole I$
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 ICIALLU. Instruction Cache Invalidate All to PoU
group-onsemi 0:098463de4c5d 440 */
group-onsemi 0:098463de4c5d 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
group-onsemi 0:098463de4c5d 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
group-onsemi 0:098463de4c5d 443 __ICIALLU = 0;
group-onsemi 0:098463de4c5d 444 __DSB(); //ensure completion of the invalidation
group-onsemi 0:098463de4c5d 445 __ISB(); //ensure instruction fetch path sees new I cache state
group-onsemi 0:098463de4c5d 446 }
group-onsemi 0:098463de4c5d 447
group-onsemi 0:098463de4c5d 448 /** \brief Clean D$ by MVA
group-onsemi 0:098463de4c5d 449
group-onsemi 0:098463de4c5d 450 DCCMVAC. Data cache clean by MVA to PoC
group-onsemi 0:098463de4c5d 451 */
group-onsemi 0:098463de4c5d 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
group-onsemi 0:098463de4c5d 454 __DCCMVAC = (uint32_t)va;
group-onsemi 0:098463de4c5d 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
group-onsemi 0:098463de4c5d 456 }
group-onsemi 0:098463de4c5d 457
group-onsemi 0:098463de4c5d 458 /** \brief Invalidate D$ by MVA
group-onsemi 0:098463de4c5d 459
group-onsemi 0:098463de4c5d 460 DCIMVAC. Data cache invalidate by MVA to PoC
group-onsemi 0:098463de4c5d 461 */
group-onsemi 0:098463de4c5d 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
group-onsemi 0:098463de4c5d 464 __DCIMVAC = (uint32_t)va;
group-onsemi 0:098463de4c5d 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
group-onsemi 0:098463de4c5d 466 }
group-onsemi 0:098463de4c5d 467
group-onsemi 0:098463de4c5d 468 /** \brief Clean and Invalidate D$ by MVA
group-onsemi 0:098463de4c5d 469
group-onsemi 0:098463de4c5d 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
group-onsemi 0:098463de4c5d 471 */
group-onsemi 0:098463de4c5d 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
group-onsemi 0:098463de4c5d 474 __DCCIMVAC = (uint32_t)va;
group-onsemi 0:098463de4c5d 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
group-onsemi 0:098463de4c5d 476 }
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 /** \brief Clean and Invalidate the entire data or unified cache
group-onsemi 0:098463de4c5d 479
group-onsemi 0:098463de4c5d 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
group-onsemi 0:098463de4c5d 481 */
group-onsemi 0:098463de4c5d 482 #pragma push
group-onsemi 0:098463de4c5d 483 #pragma arm
group-onsemi 0:098463de4c5d 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
group-onsemi 0:098463de4c5d 485 ARM
group-onsemi 0:098463de4c5d 486
group-onsemi 0:098463de4c5d 487 PUSH {R4-R11}
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
group-onsemi 0:098463de4c5d 490 ANDS R3, R6, #0x07000000 // Extract coherency level
group-onsemi 0:098463de4c5d 491 MOV R3, R3, LSR #23 // Total cache levels << 1
group-onsemi 0:098463de4c5d 492 BEQ Finished // If 0, no need to clean
group-onsemi 0:098463de4c5d 493
group-onsemi 0:098463de4c5d 494 MOV R10, #0 // R10 holds current cache level << 1
group-onsemi 0:098463de4c5d 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
group-onsemi 0:098463de4c5d 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
group-onsemi 0:098463de4c5d 497 AND R1, R1, #7 // Isolate those lower 3 bits
group-onsemi 0:098463de4c5d 498 CMP R1, #2
group-onsemi 0:098463de4c5d 499 BLT Skip // No cache or only instruction cache at this level
group-onsemi 0:098463de4c5d 500
group-onsemi 0:098463de4c5d 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
group-onsemi 0:098463de4c5d 502 ISB // ISB to sync the change to the CacheSizeID reg
group-onsemi 0:098463de4c5d 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
group-onsemi 0:098463de4c5d 504 AND R2, R1, #7 // Extract the line length field
group-onsemi 0:098463de4c5d 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
group-onsemi 0:098463de4c5d 506 LDR R4, =0x3FF
group-onsemi 0:098463de4c5d 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
group-onsemi 0:098463de4c5d 508 CLZ R5, R4 // R5 is the bit position of the way size increment
group-onsemi 0:098463de4c5d 509 LDR R7, =0x7FFF
group-onsemi 0:098463de4c5d 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
group-onsemi 0:098463de4c5d 511
group-onsemi 0:098463de4c5d 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
group-onsemi 0:098463de4c5d 513
group-onsemi 0:098463de4c5d 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
group-onsemi 0:098463de4c5d 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
group-onsemi 0:098463de4c5d 516 CMP R0, #0
group-onsemi 0:098463de4c5d 517 BNE Dccsw
group-onsemi 0:098463de4c5d 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
group-onsemi 0:098463de4c5d 519 B cont
group-onsemi 0:098463de4c5d 520 Dccsw CMP R0, #1
group-onsemi 0:098463de4c5d 521 BNE Dccisw
group-onsemi 0:098463de4c5d 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
group-onsemi 0:098463de4c5d 523 B cont
group-onsemi 0:098463de4c5d 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
group-onsemi 0:098463de4c5d 525 cont SUBS R9, R9, #1 // Decrement the Way number
group-onsemi 0:098463de4c5d 526 BGE Loop3
group-onsemi 0:098463de4c5d 527 SUBS R7, R7, #1 // Decrement the Set number
group-onsemi 0:098463de4c5d 528 BGE Loop2
group-onsemi 0:098463de4c5d 529 Skip ADD R10, R10, #2 // Increment the cache number
group-onsemi 0:098463de4c5d 530 CMP R3, R10
group-onsemi 0:098463de4c5d 531 BGT Loop1
group-onsemi 0:098463de4c5d 532
group-onsemi 0:098463de4c5d 533 Finished
group-onsemi 0:098463de4c5d 534 DSB
group-onsemi 0:098463de4c5d 535 POP {R4-R11}
group-onsemi 0:098463de4c5d 536 BX lr
group-onsemi 0:098463de4c5d 537
group-onsemi 0:098463de4c5d 538 }
group-onsemi 0:098463de4c5d 539 #pragma pop
group-onsemi 0:098463de4c5d 540
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 /** \brief Invalidate the whole D$
group-onsemi 0:098463de4c5d 543
group-onsemi 0:098463de4c5d 544 DCISW. Invalidate by Set/Way
group-onsemi 0:098463de4c5d 545 */
group-onsemi 0:098463de4c5d 546
group-onsemi 0:098463de4c5d 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
group-onsemi 0:098463de4c5d 548 __v7_all_cache(0);
group-onsemi 0:098463de4c5d 549 }
group-onsemi 0:098463de4c5d 550
group-onsemi 0:098463de4c5d 551 /** \brief Clean the whole D$
group-onsemi 0:098463de4c5d 552
group-onsemi 0:098463de4c5d 553 DCCSW. Clean by Set/Way
group-onsemi 0:098463de4c5d 554 */
group-onsemi 0:098463de4c5d 555
group-onsemi 0:098463de4c5d 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
group-onsemi 0:098463de4c5d 557 __v7_all_cache(1);
group-onsemi 0:098463de4c5d 558 }
group-onsemi 0:098463de4c5d 559
group-onsemi 0:098463de4c5d 560 /** \brief Clean and invalidate the whole D$
group-onsemi 0:098463de4c5d 561
group-onsemi 0:098463de4c5d 562 DCCISW. Clean and Invalidate by Set/Way
group-onsemi 0:098463de4c5d 563 */
group-onsemi 0:098463de4c5d 564
group-onsemi 0:098463de4c5d 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
group-onsemi 0:098463de4c5d 566 __v7_all_cache(2);
group-onsemi 0:098463de4c5d 567 }
group-onsemi 0:098463de4c5d 568
group-onsemi 0:098463de4c5d 569 #include "core_ca_mmu.h"
group-onsemi 0:098463de4c5d 570
group-onsemi 0:098463de4c5d 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
group-onsemi 0:098463de4c5d 572
group-onsemi 0:098463de4c5d 573 #define __inline inline
group-onsemi 0:098463de4c5d 574
group-onsemi 0:098463de4c5d 575 inline static uint32_t __disable_irq_iar() {
group-onsemi 0:098463de4c5d 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
group-onsemi 0:098463de4c5d 577 __disable_irq();
group-onsemi 0:098463de4c5d 578 return irq_dis;
group-onsemi 0:098463de4c5d 579 }
group-onsemi 0:098463de4c5d 580
group-onsemi 0:098463de4c5d 581 #define MODE_USR 0x10
group-onsemi 0:098463de4c5d 582 #define MODE_FIQ 0x11
group-onsemi 0:098463de4c5d 583 #define MODE_IRQ 0x12
group-onsemi 0:098463de4c5d 584 #define MODE_SVC 0x13
group-onsemi 0:098463de4c5d 585 #define MODE_MON 0x16
group-onsemi 0:098463de4c5d 586 #define MODE_ABT 0x17
group-onsemi 0:098463de4c5d 587 #define MODE_HYP 0x1A
group-onsemi 0:098463de4c5d 588 #define MODE_UND 0x1B
group-onsemi 0:098463de4c5d 589 #define MODE_SYS 0x1F
group-onsemi 0:098463de4c5d 590
group-onsemi 0:098463de4c5d 591 /** \brief Set Process Stack Pointer
group-onsemi 0:098463de4c5d 592
group-onsemi 0:098463de4c5d 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 594
group-onsemi 0:098463de4c5d 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
group-onsemi 0:098463de4c5d 596 */
group-onsemi 0:098463de4c5d 597 // from rt_CMSIS.c
group-onsemi 0:098463de4c5d 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
group-onsemi 0:098463de4c5d 599 __asm(
group-onsemi 0:098463de4c5d 600 " ARM\n"
group-onsemi 0:098463de4c5d 601 // " PRESERVE8\n"
group-onsemi 0:098463de4c5d 602
group-onsemi 0:098463de4c5d 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
group-onsemi 0:098463de4c5d 604 " MRS R1, CPSR \n"
group-onsemi 0:098463de4c5d 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
group-onsemi 0:098463de4c5d 606 " MOV SP, R0 \n"
group-onsemi 0:098463de4c5d 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
group-onsemi 0:098463de4c5d 608 " ISB \n"
group-onsemi 0:098463de4c5d 609 " BX LR \n");
group-onsemi 0:098463de4c5d 610 }
group-onsemi 0:098463de4c5d 611
group-onsemi 0:098463de4c5d 612 /** \brief Set User Mode
group-onsemi 0:098463de4c5d 613
group-onsemi 0:098463de4c5d 614 This function changes the processor state to User Mode
group-onsemi 0:098463de4c5d 615 */
group-onsemi 0:098463de4c5d 616 // from rt_CMSIS.c
group-onsemi 0:098463de4c5d 617 __arm static inline void __set_CPS_USR(void) {
group-onsemi 0:098463de4c5d 618 __asm(
group-onsemi 0:098463de4c5d 619 " ARM \n"
group-onsemi 0:098463de4c5d 620
group-onsemi 0:098463de4c5d 621 " CPS #0x10 \n" // MODE_USR
group-onsemi 0:098463de4c5d 622 " BX LR\n");
group-onsemi 0:098463de4c5d 623 }
group-onsemi 0:098463de4c5d 624
group-onsemi 0:098463de4c5d 625 /** \brief Set TTBR0
group-onsemi 0:098463de4c5d 626
group-onsemi 0:098463de4c5d 627 This function assigns the given value to the Translation Table Base Register 0.
group-onsemi 0:098463de4c5d 628
group-onsemi 0:098463de4c5d 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
group-onsemi 0:098463de4c5d 630 */
group-onsemi 0:098463de4c5d 631 // from mmu_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
group-onsemi 0:098463de4c5d 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
group-onsemi 0:098463de4c5d 634 __ISB();
group-onsemi 0:098463de4c5d 635 }
group-onsemi 0:098463de4c5d 636
group-onsemi 0:098463de4c5d 637 /** \brief Set DACR
group-onsemi 0:098463de4c5d 638
group-onsemi 0:098463de4c5d 639 This function assigns the given value to the Domain Access Control Register.
group-onsemi 0:098463de4c5d 640
group-onsemi 0:098463de4c5d 641 \param [in] dacr Domain Access Control Register value to set
group-onsemi 0:098463de4c5d 642 */
group-onsemi 0:098463de4c5d 643 // from mmu_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
group-onsemi 0:098463de4c5d 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
group-onsemi 0:098463de4c5d 646 __ISB();
group-onsemi 0:098463de4c5d 647 }
group-onsemi 0:098463de4c5d 648
group-onsemi 0:098463de4c5d 649
group-onsemi 0:098463de4c5d 650 /******************************** Cache and BTAC enable ****************************************************/
group-onsemi 0:098463de4c5d 651 /** \brief Set SCTLR
group-onsemi 0:098463de4c5d 652
group-onsemi 0:098463de4c5d 653 This function assigns the given value to the System Control Register.
group-onsemi 0:098463de4c5d 654
group-onsemi 0:098463de4c5d 655 \param [in] sctlr System Control Register value to set
group-onsemi 0:098463de4c5d 656 */
group-onsemi 0:098463de4c5d 657 // from __enable_mmu()
group-onsemi 0:098463de4c5d 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
group-onsemi 0:098463de4c5d 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
group-onsemi 0:098463de4c5d 660 }
group-onsemi 0:098463de4c5d 661
group-onsemi 0:098463de4c5d 662 /** \brief Get SCTLR
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 This function returns the value of the System Control Register.
group-onsemi 0:098463de4c5d 665
group-onsemi 0:098463de4c5d 666 \return System Control Register value
group-onsemi 0:098463de4c5d 667 */
group-onsemi 0:098463de4c5d 668 // from __enable_mmu()
group-onsemi 0:098463de4c5d 669 __STATIC_INLINE uint32_t __get_SCTLR() {
group-onsemi 0:098463de4c5d 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
group-onsemi 0:098463de4c5d 671 return __regSCTLR;
group-onsemi 0:098463de4c5d 672 }
group-onsemi 0:098463de4c5d 673
group-onsemi 0:098463de4c5d 674 /** \brief Enable Caches
group-onsemi 0:098463de4c5d 675
group-onsemi 0:098463de4c5d 676 Enable Caches
group-onsemi 0:098463de4c5d 677 */
group-onsemi 0:098463de4c5d 678 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 679 __STATIC_INLINE void __enable_caches(void) {
group-onsemi 0:098463de4c5d 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
group-onsemi 0:098463de4c5d 681 }
group-onsemi 0:098463de4c5d 682
group-onsemi 0:098463de4c5d 683 /** \brief Enable BTAC
group-onsemi 0:098463de4c5d 684
group-onsemi 0:098463de4c5d 685 Enable BTAC
group-onsemi 0:098463de4c5d 686 */
group-onsemi 0:098463de4c5d 687 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 688 __STATIC_INLINE void __enable_btac(void) {
group-onsemi 0:098463de4c5d 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
group-onsemi 0:098463de4c5d 690 __ISB();
group-onsemi 0:098463de4c5d 691 }
group-onsemi 0:098463de4c5d 692
group-onsemi 0:098463de4c5d 693 /** \brief Enable MMU
group-onsemi 0:098463de4c5d 694
group-onsemi 0:098463de4c5d 695 Enable MMU
group-onsemi 0:098463de4c5d 696 */
group-onsemi 0:098463de4c5d 697 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 698 __STATIC_INLINE void __enable_mmu(void) {
group-onsemi 0:098463de4c5d 699 // Set M bit 0 to enable the MMU
group-onsemi 0:098463de4c5d 700 // Set AFE bit to enable simplified access permissions model
group-onsemi 0:098463de4c5d 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
group-onsemi 0:098463de4c5d 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
group-onsemi 0:098463de4c5d 703 __ISB();
group-onsemi 0:098463de4c5d 704 }
group-onsemi 0:098463de4c5d 705
group-onsemi 0:098463de4c5d 706 /******************************** TLB maintenance operations ************************************************/
group-onsemi 0:098463de4c5d 707 /** \brief Invalidate the whole tlb
group-onsemi 0:098463de4c5d 708
group-onsemi 0:098463de4c5d 709 TLBIALL. Invalidate the whole tlb
group-onsemi 0:098463de4c5d 710 */
group-onsemi 0:098463de4c5d 711 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
group-onsemi 0:098463de4c5d 713 uint32_t val = 0;
group-onsemi 0:098463de4c5d 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
group-onsemi 0:098463de4c5d 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
group-onsemi 0:098463de4c5d 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
group-onsemi 0:098463de4c5d 717 __DSB();
group-onsemi 0:098463de4c5d 718 __ISB();
group-onsemi 0:098463de4c5d 719 }
group-onsemi 0:098463de4c5d 720
group-onsemi 0:098463de4c5d 721 /******************************** BTB maintenance operations ************************************************/
group-onsemi 0:098463de4c5d 722 /** \brief Invalidate entire branch predictor array
group-onsemi 0:098463de4c5d 723
group-onsemi 0:098463de4c5d 724 BPIALL. Branch Predictor Invalidate All.
group-onsemi 0:098463de4c5d 725 */
group-onsemi 0:098463de4c5d 726 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 727 __STATIC_INLINE void __v7_inv_btac(void) {
group-onsemi 0:098463de4c5d 728 uint32_t val = 0;
group-onsemi 0:098463de4c5d 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
group-onsemi 0:098463de4c5d 730 __DSB(); //ensure completion of the invalidation
group-onsemi 0:098463de4c5d 731 __ISB(); //ensure instruction fetch path sees new state
group-onsemi 0:098463de4c5d 732 }
group-onsemi 0:098463de4c5d 733
group-onsemi 0:098463de4c5d 734
group-onsemi 0:098463de4c5d 735 /******************************** L1 cache operations ******************************************************/
group-onsemi 0:098463de4c5d 736
group-onsemi 0:098463de4c5d 737 /** \brief Invalidate the whole I$
group-onsemi 0:098463de4c5d 738
group-onsemi 0:098463de4c5d 739 ICIALLU. Instruction Cache Invalidate All to PoU
group-onsemi 0:098463de4c5d 740 */
group-onsemi 0:098463de4c5d 741 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
group-onsemi 0:098463de4c5d 743 uint32_t val = 0;
group-onsemi 0:098463de4c5d 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
group-onsemi 0:098463de4c5d 745 __DSB(); //ensure completion of the invalidation
group-onsemi 0:098463de4c5d 746 __ISB(); //ensure instruction fetch path sees new I cache state
group-onsemi 0:098463de4c5d 747 }
group-onsemi 0:098463de4c5d 748
group-onsemi 0:098463de4c5d 749 // from __v7_inv_dcache_all()
group-onsemi 0:098463de4c5d 750 __arm static inline void __v7_all_cache(uint32_t op) {
group-onsemi 0:098463de4c5d 751 __asm(
group-onsemi 0:098463de4c5d 752 " ARM \n"
group-onsemi 0:098463de4c5d 753
group-onsemi 0:098463de4c5d 754 " PUSH {R4-R11} \n"
group-onsemi 0:098463de4c5d 755
group-onsemi 0:098463de4c5d 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
group-onsemi 0:098463de4c5d 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
group-onsemi 0:098463de4c5d 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
group-onsemi 0:098463de4c5d 759 " BEQ Finished\n" // If 0, no need to clean
group-onsemi 0:098463de4c5d 760
group-onsemi 0:098463de4c5d 761 " MOV R10, #0\n" // R10 holds current cache level << 1
group-onsemi 0:098463de4c5d 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
group-onsemi 0:098463de4c5d 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
group-onsemi 0:098463de4c5d 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
group-onsemi 0:098463de4c5d 765 " CMP R1, #2 \n"
group-onsemi 0:098463de4c5d 766 " BLT Skip \n" // No cache or only instruction cache at this level
group-onsemi 0:098463de4c5d 767
group-onsemi 0:098463de4c5d 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
group-onsemi 0:098463de4c5d 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
group-onsemi 0:098463de4c5d 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
group-onsemi 0:098463de4c5d 771 " AND R2, R1, #7 \n" // Extract the line length field
group-onsemi 0:098463de4c5d 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
group-onsemi 0:098463de4c5d 773 " movw R4, #0x3FF \n"
group-onsemi 0:098463de4c5d 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
group-onsemi 0:098463de4c5d 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
group-onsemi 0:098463de4c5d 776 " movw R7, #0x7FFF \n"
group-onsemi 0:098463de4c5d 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
group-onsemi 0:098463de4c5d 778
group-onsemi 0:098463de4c5d 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
group-onsemi 0:098463de4c5d 780
group-onsemi 0:098463de4c5d 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
group-onsemi 0:098463de4c5d 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
group-onsemi 0:098463de4c5d 783 " CMP R0, #0 \n"
group-onsemi 0:098463de4c5d 784 " BNE Dccsw \n"
group-onsemi 0:098463de4c5d 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
group-onsemi 0:098463de4c5d 786 " B cont \n"
group-onsemi 0:098463de4c5d 787 "Dccsw: CMP R0, #1 \n"
group-onsemi 0:098463de4c5d 788 " BNE Dccisw \n"
group-onsemi 0:098463de4c5d 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
group-onsemi 0:098463de4c5d 790 " B cont \n"
group-onsemi 0:098463de4c5d 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
group-onsemi 0:098463de4c5d 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
group-onsemi 0:098463de4c5d 793 " BGE Loop3 \n"
group-onsemi 0:098463de4c5d 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
group-onsemi 0:098463de4c5d 795 " BGE Loop2 \n"
group-onsemi 0:098463de4c5d 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
group-onsemi 0:098463de4c5d 797 " CMP R3, R10 \n"
group-onsemi 0:098463de4c5d 798 " BGT Loop1 \n"
group-onsemi 0:098463de4c5d 799
group-onsemi 0:098463de4c5d 800 "Finished: \n"
group-onsemi 0:098463de4c5d 801 " DSB \n"
group-onsemi 0:098463de4c5d 802 " POP {R4-R11} \n"
group-onsemi 0:098463de4c5d 803 " BX lr \n" );
group-onsemi 0:098463de4c5d 804 }
group-onsemi 0:098463de4c5d 805
group-onsemi 0:098463de4c5d 806 /** \brief Invalidate the whole D$
group-onsemi 0:098463de4c5d 807
group-onsemi 0:098463de4c5d 808 DCISW. Invalidate by Set/Way
group-onsemi 0:098463de4c5d 809 */
group-onsemi 0:098463de4c5d 810 // from system_Renesas_RZ_A1.c
group-onsemi 0:098463de4c5d 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
group-onsemi 0:098463de4c5d 812 __v7_all_cache(0);
group-onsemi 0:098463de4c5d 813 }
group-onsemi 0:098463de4c5d 814 /** \brief Clean the whole D$
group-onsemi 0:098463de4c5d 815
group-onsemi 0:098463de4c5d 816 DCCSW. Clean by Set/Way
group-onsemi 0:098463de4c5d 817 */
group-onsemi 0:098463de4c5d 818
group-onsemi 0:098463de4c5d 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
group-onsemi 0:098463de4c5d 820 __v7_all_cache(1);
group-onsemi 0:098463de4c5d 821 }
group-onsemi 0:098463de4c5d 822
group-onsemi 0:098463de4c5d 823 /** \brief Clean and invalidate the whole D$
group-onsemi 0:098463de4c5d 824
group-onsemi 0:098463de4c5d 825 DCCISW. Clean and Invalidate by Set/Way
group-onsemi 0:098463de4c5d 826 */
group-onsemi 0:098463de4c5d 827
group-onsemi 0:098463de4c5d 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
group-onsemi 0:098463de4c5d 829 __v7_all_cache(2);
group-onsemi 0:098463de4c5d 830 }
group-onsemi 0:098463de4c5d 831 /** \brief Clean and Invalidate D$ by MVA
group-onsemi 0:098463de4c5d 832
group-onsemi 0:098463de4c5d 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
group-onsemi 0:098463de4c5d 834 */
group-onsemi 0:098463de4c5d 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
group-onsemi 0:098463de4c5d 837 __DMB();
group-onsemi 0:098463de4c5d 838 }
group-onsemi 0:098463de4c5d 839
group-onsemi 0:098463de4c5d 840 #include "core_ca_mmu.h"
group-onsemi 0:098463de4c5d 841
group-onsemi 0:098463de4c5d 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
group-onsemi 0:098463de4c5d 843 /* GNU gcc specific functions */
group-onsemi 0:098463de4c5d 844
group-onsemi 0:098463de4c5d 845 #define MODE_USR 0x10
group-onsemi 0:098463de4c5d 846 #define MODE_FIQ 0x11
group-onsemi 0:098463de4c5d 847 #define MODE_IRQ 0x12
group-onsemi 0:098463de4c5d 848 #define MODE_SVC 0x13
group-onsemi 0:098463de4c5d 849 #define MODE_MON 0x16
group-onsemi 0:098463de4c5d 850 #define MODE_ABT 0x17
group-onsemi 0:098463de4c5d 851 #define MODE_HYP 0x1A
group-onsemi 0:098463de4c5d 852 #define MODE_UND 0x1B
group-onsemi 0:098463de4c5d 853 #define MODE_SYS 0x1F
group-onsemi 0:098463de4c5d 854
group-onsemi 0:098463de4c5d 855
group-onsemi 0:098463de4c5d 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
group-onsemi 0:098463de4c5d 857 {
group-onsemi 0:098463de4c5d 858 __ASM volatile ("cpsie i");
group-onsemi 0:098463de4c5d 859 }
group-onsemi 0:098463de4c5d 860
group-onsemi 0:098463de4c5d 861 /** \brief Disable IRQ Interrupts
group-onsemi 0:098463de4c5d 862
group-onsemi 0:098463de4c5d 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
group-onsemi 0:098463de4c5d 864 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 865 */
group-onsemi 0:098463de4c5d 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
group-onsemi 0:098463de4c5d 867 {
group-onsemi 0:098463de4c5d 868 uint32_t result;
group-onsemi 0:098463de4c5d 869
group-onsemi 0:098463de4c5d 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
group-onsemi 0:098463de4c5d 871 __ASM volatile ("cpsid i");
group-onsemi 0:098463de4c5d 872 return(result & 0x80);
group-onsemi 0:098463de4c5d 873 }
group-onsemi 0:098463de4c5d 874
group-onsemi 0:098463de4c5d 875
group-onsemi 0:098463de4c5d 876 /** \brief Get APSR Register
group-onsemi 0:098463de4c5d 877
group-onsemi 0:098463de4c5d 878 This function returns the content of the APSR Register.
group-onsemi 0:098463de4c5d 879
group-onsemi 0:098463de4c5d 880 \return APSR Register value
group-onsemi 0:098463de4c5d 881 */
group-onsemi 0:098463de4c5d 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
group-onsemi 0:098463de4c5d 883 {
group-onsemi 0:098463de4c5d 884 #if 1
group-onsemi 0:098463de4c5d 885 register uint32_t __regAPSR;
group-onsemi 0:098463de4c5d 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
group-onsemi 0:098463de4c5d 887 #else
group-onsemi 0:098463de4c5d 888 register uint32_t __regAPSR __ASM("apsr");
group-onsemi 0:098463de4c5d 889 #endif
group-onsemi 0:098463de4c5d 890 return(__regAPSR);
group-onsemi 0:098463de4c5d 891 }
group-onsemi 0:098463de4c5d 892
group-onsemi 0:098463de4c5d 893
group-onsemi 0:098463de4c5d 894 /** \brief Get CPSR Register
group-onsemi 0:098463de4c5d 895
group-onsemi 0:098463de4c5d 896 This function returns the content of the CPSR Register.
group-onsemi 0:098463de4c5d 897
group-onsemi 0:098463de4c5d 898 \return CPSR Register value
group-onsemi 0:098463de4c5d 899 */
group-onsemi 0:098463de4c5d 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
group-onsemi 0:098463de4c5d 901 {
group-onsemi 0:098463de4c5d 902 #if 1
group-onsemi 0:098463de4c5d 903 register uint32_t __regCPSR;
group-onsemi 0:098463de4c5d 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
group-onsemi 0:098463de4c5d 905 #else
group-onsemi 0:098463de4c5d 906 register uint32_t __regCPSR __ASM("cpsr");
group-onsemi 0:098463de4c5d 907 #endif
group-onsemi 0:098463de4c5d 908 return(__regCPSR);
group-onsemi 0:098463de4c5d 909 }
group-onsemi 0:098463de4c5d 910
group-onsemi 0:098463de4c5d 911 #if 0
group-onsemi 0:098463de4c5d 912 /** \brief Set Stack Pointer
group-onsemi 0:098463de4c5d 913
group-onsemi 0:098463de4c5d 914 This function assigns the given value to the current stack pointer.
group-onsemi 0:098463de4c5d 915
group-onsemi 0:098463de4c5d 916 \param [in] topOfStack Stack Pointer value to set
group-onsemi 0:098463de4c5d 917 */
group-onsemi 0:098463de4c5d 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
group-onsemi 0:098463de4c5d 919 {
group-onsemi 0:098463de4c5d 920 register uint32_t __regSP __ASM("sp");
group-onsemi 0:098463de4c5d 921 __regSP = topOfStack;
group-onsemi 0:098463de4c5d 922 }
group-onsemi 0:098463de4c5d 923 #endif
group-onsemi 0:098463de4c5d 924
group-onsemi 0:098463de4c5d 925 /** \brief Get link register
group-onsemi 0:098463de4c5d 926
group-onsemi 0:098463de4c5d 927 This function returns the value of the link register
group-onsemi 0:098463de4c5d 928
group-onsemi 0:098463de4c5d 929 \return Value of link register
group-onsemi 0:098463de4c5d 930 */
group-onsemi 0:098463de4c5d 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
group-onsemi 0:098463de4c5d 932 {
group-onsemi 0:098463de4c5d 933 register uint32_t __reglr __ASM("lr");
group-onsemi 0:098463de4c5d 934 return(__reglr);
group-onsemi 0:098463de4c5d 935 }
group-onsemi 0:098463de4c5d 936
group-onsemi 0:098463de4c5d 937 #if 0
group-onsemi 0:098463de4c5d 938 /** \brief Set link register
group-onsemi 0:098463de4c5d 939
group-onsemi 0:098463de4c5d 940 This function sets the value of the link register
group-onsemi 0:098463de4c5d 941
group-onsemi 0:098463de4c5d 942 \param [in] lr LR value to set
group-onsemi 0:098463de4c5d 943 */
group-onsemi 0:098463de4c5d 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
group-onsemi 0:098463de4c5d 945 {
group-onsemi 0:098463de4c5d 946 register uint32_t __reglr __ASM("lr");
group-onsemi 0:098463de4c5d 947 __reglr = lr;
group-onsemi 0:098463de4c5d 948 }
group-onsemi 0:098463de4c5d 949 #endif
group-onsemi 0:098463de4c5d 950
group-onsemi 0:098463de4c5d 951 /** \brief Set Process Stack Pointer
group-onsemi 0:098463de4c5d 952
group-onsemi 0:098463de4c5d 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
group-onsemi 0:098463de4c5d 954
group-onsemi 0:098463de4c5d 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
group-onsemi 0:098463de4c5d 956 */
group-onsemi 0:098463de4c5d 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
group-onsemi 0:098463de4c5d 958 {
group-onsemi 0:098463de4c5d 959 __asm__ volatile (
group-onsemi 0:098463de4c5d 960 ".ARM;"
group-onsemi 0:098463de4c5d 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
group-onsemi 0:098463de4c5d 962
group-onsemi 0:098463de4c5d 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
group-onsemi 0:098463de4c5d 964 "MRS R1, CPSR;"
group-onsemi 0:098463de4c5d 965 "CPS %0;" /* ;no effect in USR mode */
group-onsemi 0:098463de4c5d 966 "MOV SP, R0;"
group-onsemi 0:098463de4c5d 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
group-onsemi 0:098463de4c5d 968 "ISB;"
group-onsemi 0:098463de4c5d 969 //"BX LR;"
group-onsemi 0:098463de4c5d 970 :
group-onsemi 0:098463de4c5d 971 : "i"(MODE_SYS)
group-onsemi 0:098463de4c5d 972 : "r0", "r1");
group-onsemi 0:098463de4c5d 973 return;
group-onsemi 0:098463de4c5d 974 }
group-onsemi 0:098463de4c5d 975
group-onsemi 0:098463de4c5d 976 /** \brief Set User Mode
group-onsemi 0:098463de4c5d 977
group-onsemi 0:098463de4c5d 978 This function changes the processor state to User Mode
group-onsemi 0:098463de4c5d 979 */
group-onsemi 0:098463de4c5d 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
group-onsemi 0:098463de4c5d 981 {
group-onsemi 0:098463de4c5d 982 __asm__ volatile (
group-onsemi 0:098463de4c5d 983 ".ARM;"
group-onsemi 0:098463de4c5d 984
group-onsemi 0:098463de4c5d 985 "CPS %0;"
group-onsemi 0:098463de4c5d 986 //"BX LR;"
group-onsemi 0:098463de4c5d 987 :
group-onsemi 0:098463de4c5d 988 : "i"(MODE_USR)
group-onsemi 0:098463de4c5d 989 : );
group-onsemi 0:098463de4c5d 990 return;
group-onsemi 0:098463de4c5d 991 }
group-onsemi 0:098463de4c5d 992
group-onsemi 0:098463de4c5d 993
group-onsemi 0:098463de4c5d 994 /** \brief Enable FIQ
group-onsemi 0:098463de4c5d 995
group-onsemi 0:098463de4c5d 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 997 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 998 */
group-onsemi 0:098463de4c5d 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
group-onsemi 0:098463de4c5d 1000
group-onsemi 0:098463de4c5d 1001
group-onsemi 0:098463de4c5d 1002 /** \brief Disable FIQ
group-onsemi 0:098463de4c5d 1003
group-onsemi 0:098463de4c5d 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
group-onsemi 0:098463de4c5d 1005 Can only be executed in Privileged modes.
group-onsemi 0:098463de4c5d 1006 */
group-onsemi 0:098463de4c5d 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
group-onsemi 0:098463de4c5d 1008
group-onsemi 0:098463de4c5d 1009
group-onsemi 0:098463de4c5d 1010 /** \brief Get FPSCR
group-onsemi 0:098463de4c5d 1011
group-onsemi 0:098463de4c5d 1012 This function returns the current value of the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 1013
group-onsemi 0:098463de4c5d 1014 \return Floating Point Status/Control register value
group-onsemi 0:098463de4c5d 1015 */
group-onsemi 0:098463de4c5d 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
group-onsemi 0:098463de4c5d 1017 {
group-onsemi 0:098463de4c5d 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 1019 #if 1
group-onsemi 0:098463de4c5d 1020 uint32_t result;
group-onsemi 0:098463de4c5d 1021
group-onsemi 0:098463de4c5d 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
group-onsemi 0:098463de4c5d 1023 return (result);
group-onsemi 0:098463de4c5d 1024 #else
group-onsemi 0:098463de4c5d 1025 register uint32_t __regfpscr __ASM("fpscr");
group-onsemi 0:098463de4c5d 1026 return(__regfpscr);
group-onsemi 0:098463de4c5d 1027 #endif
group-onsemi 0:098463de4c5d 1028 #else
group-onsemi 0:098463de4c5d 1029 return(0);
group-onsemi 0:098463de4c5d 1030 #endif
group-onsemi 0:098463de4c5d 1031 }
group-onsemi 0:098463de4c5d 1032
group-onsemi 0:098463de4c5d 1033
group-onsemi 0:098463de4c5d 1034 /** \brief Set FPSCR
group-onsemi 0:098463de4c5d 1035
group-onsemi 0:098463de4c5d 1036 This function assigns the given value to the Floating Point Status/Control register.
group-onsemi 0:098463de4c5d 1037
group-onsemi 0:098463de4c5d 1038 \param [in] fpscr Floating Point Status/Control value to set
group-onsemi 0:098463de4c5d 1039 */
group-onsemi 0:098463de4c5d 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
group-onsemi 0:098463de4c5d 1041 {
group-onsemi 0:098463de4c5d 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 1043 #if 1
group-onsemi 0:098463de4c5d 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
group-onsemi 0:098463de4c5d 1045 #else
group-onsemi 0:098463de4c5d 1046 register uint32_t __regfpscr __ASM("fpscr");
group-onsemi 0:098463de4c5d 1047 __regfpscr = (fpscr);
group-onsemi 0:098463de4c5d 1048 #endif
group-onsemi 0:098463de4c5d 1049 #endif
group-onsemi 0:098463de4c5d 1050 }
group-onsemi 0:098463de4c5d 1051
group-onsemi 0:098463de4c5d 1052 /** \brief Get FPEXC
group-onsemi 0:098463de4c5d 1053
group-onsemi 0:098463de4c5d 1054 This function returns the current value of the Floating Point Exception Control register.
group-onsemi 0:098463de4c5d 1055
group-onsemi 0:098463de4c5d 1056 \return Floating Point Exception Control register value
group-onsemi 0:098463de4c5d 1057 */
group-onsemi 0:098463de4c5d 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
group-onsemi 0:098463de4c5d 1059 {
group-onsemi 0:098463de4c5d 1060 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 1061 #if 1
group-onsemi 0:098463de4c5d 1062 uint32_t result;
group-onsemi 0:098463de4c5d 1063
group-onsemi 0:098463de4c5d 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
group-onsemi 0:098463de4c5d 1065 return (result);
group-onsemi 0:098463de4c5d 1066 #else
group-onsemi 0:098463de4c5d 1067 register uint32_t __regfpexc __ASM("fpexc");
group-onsemi 0:098463de4c5d 1068 return(__regfpexc);
group-onsemi 0:098463de4c5d 1069 #endif
group-onsemi 0:098463de4c5d 1070 #else
group-onsemi 0:098463de4c5d 1071 return(0);
group-onsemi 0:098463de4c5d 1072 #endif
group-onsemi 0:098463de4c5d 1073 }
group-onsemi 0:098463de4c5d 1074
group-onsemi 0:098463de4c5d 1075
group-onsemi 0:098463de4c5d 1076 /** \brief Set FPEXC
group-onsemi 0:098463de4c5d 1077
group-onsemi 0:098463de4c5d 1078 This function assigns the given value to the Floating Point Exception Control register.
group-onsemi 0:098463de4c5d 1079
group-onsemi 0:098463de4c5d 1080 \param [in] fpscr Floating Point Exception Control value to set
group-onsemi 0:098463de4c5d 1081 */
group-onsemi 0:098463de4c5d 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
group-onsemi 0:098463de4c5d 1083 {
group-onsemi 0:098463de4c5d 1084 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 1085 #if 1
group-onsemi 0:098463de4c5d 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
group-onsemi 0:098463de4c5d 1087 #else
group-onsemi 0:098463de4c5d 1088 register uint32_t __regfpexc __ASM("fpexc");
group-onsemi 0:098463de4c5d 1089 __regfpexc = (fpexc);
group-onsemi 0:098463de4c5d 1090 #endif
group-onsemi 0:098463de4c5d 1091 #endif
group-onsemi 0:098463de4c5d 1092 }
group-onsemi 0:098463de4c5d 1093
group-onsemi 0:098463de4c5d 1094 /** \brief Get CPACR
group-onsemi 0:098463de4c5d 1095
group-onsemi 0:098463de4c5d 1096 This function returns the current value of the Coprocessor Access Control register.
group-onsemi 0:098463de4c5d 1097
group-onsemi 0:098463de4c5d 1098 \return Coprocessor Access Control register value
group-onsemi 0:098463de4c5d 1099 */
group-onsemi 0:098463de4c5d 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
group-onsemi 0:098463de4c5d 1101 {
group-onsemi 0:098463de4c5d 1102 #if 1
group-onsemi 0:098463de4c5d 1103 register uint32_t __regCPACR;
group-onsemi 0:098463de4c5d 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
group-onsemi 0:098463de4c5d 1105 #else
group-onsemi 0:098463de4c5d 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
group-onsemi 0:098463de4c5d 1107 #endif
group-onsemi 0:098463de4c5d 1108 return __regCPACR;
group-onsemi 0:098463de4c5d 1109 }
group-onsemi 0:098463de4c5d 1110
group-onsemi 0:098463de4c5d 1111 /** \brief Set CPACR
group-onsemi 0:098463de4c5d 1112
group-onsemi 0:098463de4c5d 1113 This function assigns the given value to the Coprocessor Access Control register.
group-onsemi 0:098463de4c5d 1114
group-onsemi 0:098463de4c5d 1115 \param [in] cpacr Coprocessor Acccess Control value to set
group-onsemi 0:098463de4c5d 1116 */
group-onsemi 0:098463de4c5d 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
group-onsemi 0:098463de4c5d 1118 {
group-onsemi 0:098463de4c5d 1119 #if 1
group-onsemi 0:098463de4c5d 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
group-onsemi 0:098463de4c5d 1121 #else
group-onsemi 0:098463de4c5d 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
group-onsemi 0:098463de4c5d 1123 __regCPACR = cpacr;
group-onsemi 0:098463de4c5d 1124 #endif
group-onsemi 0:098463de4c5d 1125 __ISB();
group-onsemi 0:098463de4c5d 1126 }
group-onsemi 0:098463de4c5d 1127
group-onsemi 0:098463de4c5d 1128 /** \brief Get CBAR
group-onsemi 0:098463de4c5d 1129
group-onsemi 0:098463de4c5d 1130 This function returns the value of the Configuration Base Address register.
group-onsemi 0:098463de4c5d 1131
group-onsemi 0:098463de4c5d 1132 \return Configuration Base Address register value
group-onsemi 0:098463de4c5d 1133 */
group-onsemi 0:098463de4c5d 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
group-onsemi 0:098463de4c5d 1135 #if 1
group-onsemi 0:098463de4c5d 1136 register uint32_t __regCBAR;
group-onsemi 0:098463de4c5d 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
group-onsemi 0:098463de4c5d 1138 #else
group-onsemi 0:098463de4c5d 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
group-onsemi 0:098463de4c5d 1140 #endif
group-onsemi 0:098463de4c5d 1141 return(__regCBAR);
group-onsemi 0:098463de4c5d 1142 }
group-onsemi 0:098463de4c5d 1143
group-onsemi 0:098463de4c5d 1144 /** \brief Get TTBR0
group-onsemi 0:098463de4c5d 1145
group-onsemi 0:098463de4c5d 1146 This function returns the value of the Translation Table Base Register 0.
group-onsemi 0:098463de4c5d 1147
group-onsemi 0:098463de4c5d 1148 \return Translation Table Base Register 0 value
group-onsemi 0:098463de4c5d 1149 */
group-onsemi 0:098463de4c5d 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
group-onsemi 0:098463de4c5d 1151 #if 1
group-onsemi 0:098463de4c5d 1152 register uint32_t __regTTBR0;
group-onsemi 0:098463de4c5d 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
group-onsemi 0:098463de4c5d 1154 #else
group-onsemi 0:098463de4c5d 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
group-onsemi 0:098463de4c5d 1156 #endif
group-onsemi 0:098463de4c5d 1157 return(__regTTBR0);
group-onsemi 0:098463de4c5d 1158 }
group-onsemi 0:098463de4c5d 1159
group-onsemi 0:098463de4c5d 1160 /** \brief Set TTBR0
group-onsemi 0:098463de4c5d 1161
group-onsemi 0:098463de4c5d 1162 This function assigns the given value to the Translation Table Base Register 0.
group-onsemi 0:098463de4c5d 1163
group-onsemi 0:098463de4c5d 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
group-onsemi 0:098463de4c5d 1165 */
group-onsemi 0:098463de4c5d 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
group-onsemi 0:098463de4c5d 1167 #if 1
group-onsemi 0:098463de4c5d 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
group-onsemi 0:098463de4c5d 1169 #else
group-onsemi 0:098463de4c5d 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
group-onsemi 0:098463de4c5d 1171 __regTTBR0 = ttbr0;
group-onsemi 0:098463de4c5d 1172 #endif
group-onsemi 0:098463de4c5d 1173 __ISB();
group-onsemi 0:098463de4c5d 1174 }
group-onsemi 0:098463de4c5d 1175
group-onsemi 0:098463de4c5d 1176 /** \brief Get DACR
group-onsemi 0:098463de4c5d 1177
group-onsemi 0:098463de4c5d 1178 This function returns the value of the Domain Access Control Register.
group-onsemi 0:098463de4c5d 1179
group-onsemi 0:098463de4c5d 1180 \return Domain Access Control Register value
group-onsemi 0:098463de4c5d 1181 */
group-onsemi 0:098463de4c5d 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
group-onsemi 0:098463de4c5d 1183 #if 1
group-onsemi 0:098463de4c5d 1184 register uint32_t __regDACR;
group-onsemi 0:098463de4c5d 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
group-onsemi 0:098463de4c5d 1186 #else
group-onsemi 0:098463de4c5d 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
group-onsemi 0:098463de4c5d 1188 #endif
group-onsemi 0:098463de4c5d 1189 return(__regDACR);
group-onsemi 0:098463de4c5d 1190 }
group-onsemi 0:098463de4c5d 1191
group-onsemi 0:098463de4c5d 1192 /** \brief Set DACR
group-onsemi 0:098463de4c5d 1193
group-onsemi 0:098463de4c5d 1194 This function assigns the given value to the Domain Access Control Register.
group-onsemi 0:098463de4c5d 1195
group-onsemi 0:098463de4c5d 1196 \param [in] dacr Domain Access Control Register value to set
group-onsemi 0:098463de4c5d 1197 */
group-onsemi 0:098463de4c5d 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
group-onsemi 0:098463de4c5d 1199 #if 1
group-onsemi 0:098463de4c5d 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
group-onsemi 0:098463de4c5d 1201 #else
group-onsemi 0:098463de4c5d 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
group-onsemi 0:098463de4c5d 1203 __regDACR = dacr;
group-onsemi 0:098463de4c5d 1204 #endif
group-onsemi 0:098463de4c5d 1205 __ISB();
group-onsemi 0:098463de4c5d 1206 }
group-onsemi 0:098463de4c5d 1207
group-onsemi 0:098463de4c5d 1208 /******************************** Cache and BTAC enable ****************************************************/
group-onsemi 0:098463de4c5d 1209
group-onsemi 0:098463de4c5d 1210 /** \brief Set SCTLR
group-onsemi 0:098463de4c5d 1211
group-onsemi 0:098463de4c5d 1212 This function assigns the given value to the System Control Register.
group-onsemi 0:098463de4c5d 1213
group-onsemi 0:098463de4c5d 1214 \param [in] sctlr System Control Register value to set
group-onsemi 0:098463de4c5d 1215 */
group-onsemi 0:098463de4c5d 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
group-onsemi 0:098463de4c5d 1217 {
group-onsemi 0:098463de4c5d 1218 #if 1
group-onsemi 0:098463de4c5d 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
group-onsemi 0:098463de4c5d 1220 #else
group-onsemi 0:098463de4c5d 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
group-onsemi 0:098463de4c5d 1222 __regSCTLR = sctlr;
group-onsemi 0:098463de4c5d 1223 #endif
group-onsemi 0:098463de4c5d 1224 }
group-onsemi 0:098463de4c5d 1225
group-onsemi 0:098463de4c5d 1226 /** \brief Get SCTLR
group-onsemi 0:098463de4c5d 1227
group-onsemi 0:098463de4c5d 1228 This function returns the value of the System Control Register.
group-onsemi 0:098463de4c5d 1229
group-onsemi 0:098463de4c5d 1230 \return System Control Register value
group-onsemi 0:098463de4c5d 1231 */
group-onsemi 0:098463de4c5d 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
group-onsemi 0:098463de4c5d 1233 #if 1
group-onsemi 0:098463de4c5d 1234 register uint32_t __regSCTLR;
group-onsemi 0:098463de4c5d 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
group-onsemi 0:098463de4c5d 1236 #else
group-onsemi 0:098463de4c5d 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
group-onsemi 0:098463de4c5d 1238 #endif
group-onsemi 0:098463de4c5d 1239 return(__regSCTLR);
group-onsemi 0:098463de4c5d 1240 }
group-onsemi 0:098463de4c5d 1241
group-onsemi 0:098463de4c5d 1242 /** \brief Enable Caches
group-onsemi 0:098463de4c5d 1243
group-onsemi 0:098463de4c5d 1244 Enable Caches
group-onsemi 0:098463de4c5d 1245 */
group-onsemi 0:098463de4c5d 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
group-onsemi 0:098463de4c5d 1247 // Set I bit 12 to enable I Cache
group-onsemi 0:098463de4c5d 1248 // Set C bit 2 to enable D Cache
group-onsemi 0:098463de4c5d 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
group-onsemi 0:098463de4c5d 1250 }
group-onsemi 0:098463de4c5d 1251
group-onsemi 0:098463de4c5d 1252 /** \brief Disable Caches
group-onsemi 0:098463de4c5d 1253
group-onsemi 0:098463de4c5d 1254 Disable Caches
group-onsemi 0:098463de4c5d 1255 */
group-onsemi 0:098463de4c5d 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
group-onsemi 0:098463de4c5d 1257 // Clear I bit 12 to disable I Cache
group-onsemi 0:098463de4c5d 1258 // Clear C bit 2 to disable D Cache
group-onsemi 0:098463de4c5d 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
group-onsemi 0:098463de4c5d 1260 __ISB();
group-onsemi 0:098463de4c5d 1261 }
group-onsemi 0:098463de4c5d 1262
group-onsemi 0:098463de4c5d 1263 /** \brief Enable BTAC
group-onsemi 0:098463de4c5d 1264
group-onsemi 0:098463de4c5d 1265 Enable BTAC
group-onsemi 0:098463de4c5d 1266 */
group-onsemi 0:098463de4c5d 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
group-onsemi 0:098463de4c5d 1268 // Set Z bit 11 to enable branch prediction
group-onsemi 0:098463de4c5d 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
group-onsemi 0:098463de4c5d 1270 __ISB();
group-onsemi 0:098463de4c5d 1271 }
group-onsemi 0:098463de4c5d 1272
group-onsemi 0:098463de4c5d 1273 /** \brief Disable BTAC
group-onsemi 0:098463de4c5d 1274
group-onsemi 0:098463de4c5d 1275 Disable BTAC
group-onsemi 0:098463de4c5d 1276 */
group-onsemi 0:098463de4c5d 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
group-onsemi 0:098463de4c5d 1278 // Clear Z bit 11 to disable branch prediction
group-onsemi 0:098463de4c5d 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
group-onsemi 0:098463de4c5d 1280 }
group-onsemi 0:098463de4c5d 1281
group-onsemi 0:098463de4c5d 1282
group-onsemi 0:098463de4c5d 1283 /** \brief Enable MMU
group-onsemi 0:098463de4c5d 1284
group-onsemi 0:098463de4c5d 1285 Enable MMU
group-onsemi 0:098463de4c5d 1286 */
group-onsemi 0:098463de4c5d 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
group-onsemi 0:098463de4c5d 1288 // Set M bit 0 to enable the MMU
group-onsemi 0:098463de4c5d 1289 // Set AFE bit to enable simplified access permissions model
group-onsemi 0:098463de4c5d 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
group-onsemi 0:098463de4c5d 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
group-onsemi 0:098463de4c5d 1292 __ISB();
group-onsemi 0:098463de4c5d 1293 }
group-onsemi 0:098463de4c5d 1294
group-onsemi 0:098463de4c5d 1295 /** \brief Disable MMU
group-onsemi 0:098463de4c5d 1296
group-onsemi 0:098463de4c5d 1297 Disable MMU
group-onsemi 0:098463de4c5d 1298 */
group-onsemi 0:098463de4c5d 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
group-onsemi 0:098463de4c5d 1300 // Clear M bit 0 to disable the MMU
group-onsemi 0:098463de4c5d 1301 __set_SCTLR( __get_SCTLR() & ~1);
group-onsemi 0:098463de4c5d 1302 __ISB();
group-onsemi 0:098463de4c5d 1303 }
group-onsemi 0:098463de4c5d 1304
group-onsemi 0:098463de4c5d 1305 /******************************** TLB maintenance operations ************************************************/
group-onsemi 0:098463de4c5d 1306 /** \brief Invalidate the whole tlb
group-onsemi 0:098463de4c5d 1307
group-onsemi 0:098463de4c5d 1308 TLBIALL. Invalidate the whole tlb
group-onsemi 0:098463de4c5d 1309 */
group-onsemi 0:098463de4c5d 1310
group-onsemi 0:098463de4c5d 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
group-onsemi 0:098463de4c5d 1312 #if 1
group-onsemi 0:098463de4c5d 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
group-onsemi 0:098463de4c5d 1314 #else
group-onsemi 0:098463de4c5d 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
group-onsemi 0:098463de4c5d 1316 __TLBIALL = 0;
group-onsemi 0:098463de4c5d 1317 #endif
group-onsemi 0:098463de4c5d 1318 __DSB();
group-onsemi 0:098463de4c5d 1319 __ISB();
group-onsemi 0:098463de4c5d 1320 }
group-onsemi 0:098463de4c5d 1321
group-onsemi 0:098463de4c5d 1322 /******************************** BTB maintenance operations ************************************************/
group-onsemi 0:098463de4c5d 1323 /** \brief Invalidate entire branch predictor array
group-onsemi 0:098463de4c5d 1324
group-onsemi 0:098463de4c5d 1325 BPIALL. Branch Predictor Invalidate All.
group-onsemi 0:098463de4c5d 1326 */
group-onsemi 0:098463de4c5d 1327
group-onsemi 0:098463de4c5d 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
group-onsemi 0:098463de4c5d 1329 #if 1
group-onsemi 0:098463de4c5d 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
group-onsemi 0:098463de4c5d 1331 #else
group-onsemi 0:098463de4c5d 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
group-onsemi 0:098463de4c5d 1333 __BPIALL = 0;
group-onsemi 0:098463de4c5d 1334 #endif
group-onsemi 0:098463de4c5d 1335 __DSB(); //ensure completion of the invalidation
group-onsemi 0:098463de4c5d 1336 __ISB(); //ensure instruction fetch path sees new state
group-onsemi 0:098463de4c5d 1337 }
group-onsemi 0:098463de4c5d 1338
group-onsemi 0:098463de4c5d 1339
group-onsemi 0:098463de4c5d 1340 /******************************** L1 cache operations ******************************************************/
group-onsemi 0:098463de4c5d 1341
group-onsemi 0:098463de4c5d 1342 /** \brief Invalidate the whole I$
group-onsemi 0:098463de4c5d 1343
group-onsemi 0:098463de4c5d 1344 ICIALLU. Instruction Cache Invalidate All to PoU
group-onsemi 0:098463de4c5d 1345 */
group-onsemi 0:098463de4c5d 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
group-onsemi 0:098463de4c5d 1347 #if 1
group-onsemi 0:098463de4c5d 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
group-onsemi 0:098463de4c5d 1349 #else
group-onsemi 0:098463de4c5d 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
group-onsemi 0:098463de4c5d 1351 __ICIALLU = 0;
group-onsemi 0:098463de4c5d 1352 #endif
group-onsemi 0:098463de4c5d 1353 __DSB(); //ensure completion of the invalidation
group-onsemi 0:098463de4c5d 1354 __ISB(); //ensure instruction fetch path sees new I cache state
group-onsemi 0:098463de4c5d 1355 }
group-onsemi 0:098463de4c5d 1356
group-onsemi 0:098463de4c5d 1357 /** \brief Clean D$ by MVA
group-onsemi 0:098463de4c5d 1358
group-onsemi 0:098463de4c5d 1359 DCCMVAC. Data cache clean by MVA to PoC
group-onsemi 0:098463de4c5d 1360 */
group-onsemi 0:098463de4c5d 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 1362 #if 1
group-onsemi 0:098463de4c5d 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
group-onsemi 0:098463de4c5d 1364 #else
group-onsemi 0:098463de4c5d 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
group-onsemi 0:098463de4c5d 1366 __DCCMVAC = (uint32_t)va;
group-onsemi 0:098463de4c5d 1367 #endif
group-onsemi 0:098463de4c5d 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
group-onsemi 0:098463de4c5d 1369 }
group-onsemi 0:098463de4c5d 1370
group-onsemi 0:098463de4c5d 1371 /** \brief Invalidate D$ by MVA
group-onsemi 0:098463de4c5d 1372
group-onsemi 0:098463de4c5d 1373 DCIMVAC. Data cache invalidate by MVA to PoC
group-onsemi 0:098463de4c5d 1374 */
group-onsemi 0:098463de4c5d 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 1376 #if 1
group-onsemi 0:098463de4c5d 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
group-onsemi 0:098463de4c5d 1378 #else
group-onsemi 0:098463de4c5d 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
group-onsemi 0:098463de4c5d 1380 __DCIMVAC = (uint32_t)va;
group-onsemi 0:098463de4c5d 1381 #endif
group-onsemi 0:098463de4c5d 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
group-onsemi 0:098463de4c5d 1383 }
group-onsemi 0:098463de4c5d 1384
group-onsemi 0:098463de4c5d 1385 /** \brief Clean and Invalidate D$ by MVA
group-onsemi 0:098463de4c5d 1386
group-onsemi 0:098463de4c5d 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
group-onsemi 0:098463de4c5d 1388 */
group-onsemi 0:098463de4c5d 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
group-onsemi 0:098463de4c5d 1390 #if 1
group-onsemi 0:098463de4c5d 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
group-onsemi 0:098463de4c5d 1392 #else
group-onsemi 0:098463de4c5d 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
group-onsemi 0:098463de4c5d 1394 __DCCIMVAC = (uint32_t)va;
group-onsemi 0:098463de4c5d 1395 #endif
group-onsemi 0:098463de4c5d 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
group-onsemi 0:098463de4c5d 1397 }
group-onsemi 0:098463de4c5d 1398
group-onsemi 0:098463de4c5d 1399 /** \brief Clean and Invalidate the entire data or unified cache
group-onsemi 0:098463de4c5d 1400
group-onsemi 0:098463de4c5d 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
group-onsemi 0:098463de4c5d 1402 */
group-onsemi 0:098463de4c5d 1403 extern void __v7_all_cache(uint32_t op);
group-onsemi 0:098463de4c5d 1404
group-onsemi 0:098463de4c5d 1405
group-onsemi 0:098463de4c5d 1406 /** \brief Invalidate the whole D$
group-onsemi 0:098463de4c5d 1407
group-onsemi 0:098463de4c5d 1408 DCISW. Invalidate by Set/Way
group-onsemi 0:098463de4c5d 1409 */
group-onsemi 0:098463de4c5d 1410
group-onsemi 0:098463de4c5d 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
group-onsemi 0:098463de4c5d 1412 __v7_all_cache(0);
group-onsemi 0:098463de4c5d 1413 }
group-onsemi 0:098463de4c5d 1414
group-onsemi 0:098463de4c5d 1415 /** \brief Clean the whole D$
group-onsemi 0:098463de4c5d 1416
group-onsemi 0:098463de4c5d 1417 DCCSW. Clean by Set/Way
group-onsemi 0:098463de4c5d 1418 */
group-onsemi 0:098463de4c5d 1419
group-onsemi 0:098463de4c5d 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
group-onsemi 0:098463de4c5d 1421 __v7_all_cache(1);
group-onsemi 0:098463de4c5d 1422 }
group-onsemi 0:098463de4c5d 1423
group-onsemi 0:098463de4c5d 1424 /** \brief Clean and invalidate the whole D$
group-onsemi 0:098463de4c5d 1425
group-onsemi 0:098463de4c5d 1426 DCCISW. Clean and Invalidate by Set/Way
group-onsemi 0:098463de4c5d 1427 */
group-onsemi 0:098463de4c5d 1428
group-onsemi 0:098463de4c5d 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
group-onsemi 0:098463de4c5d 1430 __v7_all_cache(2);
group-onsemi 0:098463de4c5d 1431 }
group-onsemi 0:098463de4c5d 1432
group-onsemi 0:098463de4c5d 1433 #include "core_ca_mmu.h"
group-onsemi 0:098463de4c5d 1434
group-onsemi 0:098463de4c5d 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
group-onsemi 0:098463de4c5d 1436
group-onsemi 0:098463de4c5d 1437 #error TASKING Compiler support not implemented for Cortex-A
group-onsemi 0:098463de4c5d 1438
group-onsemi 0:098463de4c5d 1439 #endif
group-onsemi 0:098463de4c5d 1440
group-onsemi 0:098463de4c5d 1441 /*@} end of CMSIS_Core_RegAccFunctions */
group-onsemi 0:098463de4c5d 1442
group-onsemi 0:098463de4c5d 1443
group-onsemi 0:098463de4c5d 1444 #endif /* __CORE_CAFUNC_H__ */