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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:: group-onsemi
Date:: Wed Jan 25 20:34:15 2017 +0000
Revision:: 0:098463de4c5d

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
group-onsemi	0:098463de4c5d	1	/**
group-onsemi	0:098463de4c5d	2	******************************************************************************
group-onsemi	0:098463de4c5d	3	* @file stm32f4xx_hal_dma2d.c
group-onsemi	0:098463de4c5d	4	* @author MCD Application Team
group-onsemi	0:098463de4c5d	5	* @version V1.5.0
group-onsemi	0:098463de4c5d	6	* @date 06-May-2016
group-onsemi	0:098463de4c5d	7	* @brief DMA2D HAL module driver.
group-onsemi	0:098463de4c5d	8	* This file provides firmware functions to manage the following
group-onsemi	0:098463de4c5d	9	* functionalities of the DMA2D peripheral:
group-onsemi	0:098463de4c5d	10	* + Initialization and de-initialization functions
group-onsemi	0:098463de4c5d	11	* + IO operation functions
group-onsemi	0:098463de4c5d	12	* + Peripheral Control functions
group-onsemi	0:098463de4c5d	13	* + Peripheral State and Errors functions
group-onsemi	0:098463de4c5d	14	*
group-onsemi	0:098463de4c5d	15	@verbatim
group-onsemi	0:098463de4c5d	16	==============================================================================
group-onsemi	0:098463de4c5d	17	##### How to use this driver #####
group-onsemi	0:098463de4c5d	18	==============================================================================
group-onsemi	0:098463de4c5d	19	[..]
group-onsemi	0:098463de4c5d	20	(#) Program the required configuration through the following parameters:
group-onsemi	0:098463de4c5d	21	the transfer mode, the output color mode and the output offset using
group-onsemi	0:098463de4c5d	22	HAL_DMA2D_Init() function.
group-onsemi	0:098463de4c5d	23
group-onsemi	0:098463de4c5d	24	(#) Program the required configuration through the following parameters:
group-onsemi	0:098463de4c5d	25	the input color mode, the input color, the input alpha value, the alpha mode,
group-onsemi	0:098463de4c5d	26	and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
group-onsemi	0:098463de4c5d	27	or/and background layer.
group-onsemi	0:098463de4c5d	28
group-onsemi	0:098463de4c5d	29	* Polling mode IO operation *
group-onsemi	0:098463de4c5d	30	=================================
group-onsemi	0:098463de4c5d	31	[..]
group-onsemi	0:098463de4c5d	32	(#) Configure pdata parameter (explained hereafter), destination and data length
group-onsemi	0:098463de4c5d	33	and enable the transfer using HAL_DMA2D_Start().
group-onsemi	0:098463de4c5d	34	(#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
group-onsemi	0:098463de4c5d	35	user can specify the value of timeout according to his end application.
group-onsemi	0:098463de4c5d	36
group-onsemi	0:098463de4c5d	37	* Interrupt mode IO operation *
group-onsemi	0:098463de4c5d	38	===================================
group-onsemi	0:098463de4c5d	39	[..]
group-onsemi	0:098463de4c5d	40	(#) Configure pdata parameter, destination and data length and enable
group-onsemi	0:098463de4c5d	41	the transfer using HAL_DMA2D_Start_IT().
group-onsemi	0:098463de4c5d	42	(#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
group-onsemi	0:098463de4c5d	43	(#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
group-onsemi	0:098463de4c5d	44	add his own function by customization of function pointer XferCpltCallback (member
group-onsemi	0:098463de4c5d	45	of DMA2D handle structure).
group-onsemi	0:098463de4c5d	46	(#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
group-onsemi	0:098463de4c5d	47	XferErrorCallback.
group-onsemi	0:098463de4c5d	48
group-onsemi	0:098463de4c5d	49	-@- In Register-to-Memory transfer mode, pdata parameter is the register
group-onsemi	0:098463de4c5d	50	color, in Memory-to-memory or Memory-to-Memory with pixel format
group-onsemi	0:098463de4c5d	51	conversion pdata is the source address.
group-onsemi	0:098463de4c5d	52
group-onsemi	0:098463de4c5d	53	-@- Configure the foreground source address, the background source address,
group-onsemi	0:098463de4c5d	54	the destination and data length then Enable the transfer using
group-onsemi	0:098463de4c5d	55	HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
group-onsemi	0:098463de4c5d	56	in interrupt mode
group-onsemi	0:098463de4c5d	57
group-onsemi	0:098463de4c5d	58	-@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
group-onsemi	0:098463de4c5d	59	are used if the memory to memory with blending transfer mode is selected.
group-onsemi	0:098463de4c5d	60
group-onsemi	0:098463de4c5d	61	(#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
group-onsemi	0:098463de4c5d	62	mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
group-onsemi	0:098463de4c5d	63
group-onsemi	0:098463de4c5d	64	(#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
group-onsemi	0:098463de4c5d	65
group-onsemi	0:098463de4c5d	66	(#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
group-onsemi	0:098463de4c5d	67	consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
group-onsemi	0:098463de4c5d	68	and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
group-onsemi	0:098463de4c5d	69	HAL_DMA2D_DisableDeadTime().
group-onsemi	0:098463de4c5d	70
group-onsemi	0:098463de4c5d	71	(#) The transfer can be suspended, resumed and aborted using the following
group-onsemi	0:098463de4c5d	72	functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
group-onsemi	0:098463de4c5d	73
group-onsemi	0:098463de4c5d	74	(#) The CLUT loading can be suspended, resumed and aborted using the following
group-onsemi	0:098463de4c5d	75	functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
group-onsemi	0:098463de4c5d	76	HAL_DMA2D_CLUTLoading_Abort().
group-onsemi	0:098463de4c5d	77
group-onsemi	0:098463de4c5d	78	(#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
group-onsemi	0:098463de4c5d	79
group-onsemi	0:098463de4c5d	80	(#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
group-onsemi	0:098463de4c5d	81
group-onsemi	0:098463de4c5d	82	* DMA2D HAL driver macros list *
group-onsemi	0:098463de4c5d	83	=============================================
group-onsemi	0:098463de4c5d	84	[..]
group-onsemi	0:098463de4c5d	85	Below the list of most used macros in DMA2D HAL driver :
group-onsemi	0:098463de4c5d	86
group-onsemi	0:098463de4c5d	87	(+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
group-onsemi	0:098463de4c5d	88	(+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
group-onsemi	0:098463de4c5d	89	(+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
group-onsemi	0:098463de4c5d	90	(+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
group-onsemi	0:098463de4c5d	91	(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
group-onsemi	0:098463de4c5d	92	(+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
group-onsemi	0:098463de4c5d	93
group-onsemi	0:098463de4c5d	94	[..]
group-onsemi	0:098463de4c5d	95	(@) You can refer to the DMA2D HAL driver header file for more useful macros
group-onsemi	0:098463de4c5d	96
group-onsemi	0:098463de4c5d	97	@endverbatim
group-onsemi	0:098463de4c5d	98	******************************************************************************
group-onsemi	0:098463de4c5d	99	* @attention
group-onsemi	0:098463de4c5d	100	*
group-onsemi	0:098463de4c5d	101	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
group-onsemi	0:098463de4c5d	102	*
group-onsemi	0:098463de4c5d	103	* Redistribution and use in source and binary forms, with or without modification,
group-onsemi	0:098463de4c5d	104	* are permitted provided that the following conditions are met:
group-onsemi	0:098463de4c5d	105	* 1. Redistributions of source code must retain the above copyright notice,
group-onsemi	0:098463de4c5d	106	* this list of conditions and the following disclaimer.
group-onsemi	0:098463de4c5d	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi	0:098463de4c5d	108	* this list of conditions and the following disclaimer in the documentation
group-onsemi	0:098463de4c5d	109	* and/or other materials provided with the distribution.
group-onsemi	0:098463de4c5d	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi	0:098463de4c5d	111	* may be used to endorse or promote products derived from this software
group-onsemi	0:098463de4c5d	112	* without specific prior written permission.
group-onsemi	0:098463de4c5d	113	*
group-onsemi	0:098463de4c5d	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi	0:098463de4c5d	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi	0:098463de4c5d	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi	0:098463de4c5d	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi	0:098463de4c5d	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi	0:098463de4c5d	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi	0:098463de4c5d	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi	0:098463de4c5d	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi	0:098463de4c5d	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi	0:098463de4c5d	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi	0:098463de4c5d	124	*
group-onsemi	0:098463de4c5d	125	******************************************************************************
group-onsemi	0:098463de4c5d	126	*/
group-onsemi	0:098463de4c5d	127
group-onsemi	0:098463de4c5d	128	/* Includes ------------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	129	#include "stm32f4xx_hal.h"
group-onsemi	0:098463de4c5d	130
group-onsemi	0:098463de4c5d	131	/** @addtogroup STM32F4xx_HAL_Driver
group-onsemi	0:098463de4c5d	132	* @{
group-onsemi	0:098463de4c5d	133	*/
group-onsemi	0:098463de4c5d	134
group-onsemi	0:098463de4c5d	135	/** @defgroup DMA2D DMA2D
group-onsemi	0:098463de4c5d	136	* @brief DMA2D HAL module driver
group-onsemi	0:098463de4c5d	137	* @{
group-onsemi	0:098463de4c5d	138	*/
group-onsemi	0:098463de4c5d	139
group-onsemi	0:098463de4c5d	140	#ifdef HAL_DMA2D_MODULE_ENABLED
group-onsemi	0:098463de4c5d	141
group-onsemi	0:098463de4c5d	142	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
group-onsemi	0:098463de4c5d	143
group-onsemi	0:098463de4c5d	144	/* Private types -------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	145	/* Private define ------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	146	/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
group-onsemi	0:098463de4c5d	147	* @{
group-onsemi	0:098463de4c5d	148	*/
group-onsemi	0:098463de4c5d	149
group-onsemi	0:098463de4c5d	150	/** @defgroup DMA2D_TimeOut DMA2D Time Out
group-onsemi	0:098463de4c5d	151	* @{
group-onsemi	0:098463de4c5d	152	*/
group-onsemi	0:098463de4c5d	153	#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000U) /!< 1s /
group-onsemi	0:098463de4c5d	154	#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000U) /!< 1s /
group-onsemi	0:098463de4c5d	155	/**
group-onsemi	0:098463de4c5d	156	* @}
group-onsemi	0:098463de4c5d	157	*/
group-onsemi	0:098463de4c5d	158
group-onsemi	0:098463de4c5d	159	/** @defgroup DMA2D_Shifts DMA2D Shifts
group-onsemi	0:098463de4c5d	160	* @{
group-onsemi	0:098463de4c5d	161	*/
group-onsemi	0:098463de4c5d	162	#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /!< Required left shift to set foreground CLUT size /
group-onsemi	0:098463de4c5d	163	#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /!< Required left shift to set background CLUT size /
group-onsemi	0:098463de4c5d	164
group-onsemi	0:098463de4c5d	165	#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /!< Required left shift to set foreground CLUT color mode /
group-onsemi	0:098463de4c5d	166	#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /!< Required left shift to set background CLUT color mode /
group-onsemi	0:098463de4c5d	167
group-onsemi	0:098463de4c5d	168	#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /!< Required left shift to set deadtime value /
group-onsemi	0:098463de4c5d	169
group-onsemi	0:098463de4c5d	170	#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /!< Required left shift to set foreground alpha mode /
group-onsemi	0:098463de4c5d	171	#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /!< Required left shift to set background alpha mode /
group-onsemi	0:098463de4c5d	172
group-onsemi	0:098463de4c5d	173	#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /!< Required left shift to set foreground alpha value /
group-onsemi	0:098463de4c5d	174	#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /!< Required left shift to set background alpha value /
group-onsemi	0:098463de4c5d	175
group-onsemi	0:098463de4c5d	176	#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /!< Required left shift to set pixels per lines value /
group-onsemi	0:098463de4c5d	177	/**
group-onsemi	0:098463de4c5d	178	* @}
group-onsemi	0:098463de4c5d	179	*/
group-onsemi	0:098463de4c5d	180
group-onsemi	0:098463de4c5d	181	/**
group-onsemi	0:098463de4c5d	182	* @}
group-onsemi	0:098463de4c5d	183	*/
group-onsemi	0:098463de4c5d	184
group-onsemi	0:098463de4c5d	185	/* Private variables ---------------------------------------------------------*/
group-onsemi	0:098463de4c5d	186	/* Private constants ---------------------------------------------------------*/
group-onsemi	0:098463de4c5d	187	/* Private macro -------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	188	/* Private function prototypes -----------------------------------------------*/
group-onsemi	0:098463de4c5d	189	/** @addtogroup DMA2D_Private_Functions_Prototypes
group-onsemi	0:098463de4c5d	190	* @{
group-onsemi	0:098463de4c5d	191	*/
group-onsemi	0:098463de4c5d	192	static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
group-onsemi	0:098463de4c5d	193	/**
group-onsemi	0:098463de4c5d	194	* @}
group-onsemi	0:098463de4c5d	195	*/
group-onsemi	0:098463de4c5d	196
group-onsemi	0:098463de4c5d	197	/* Private functions ---------------------------------------------------------*/
group-onsemi	0:098463de4c5d	198	/* Exported functions --------------------------------------------------------*/
group-onsemi	0:098463de4c5d	199	/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
group-onsemi	0:098463de4c5d	200	* @{
group-onsemi	0:098463de4c5d	201	*/
group-onsemi	0:098463de4c5d	202
group-onsemi	0:098463de4c5d	203	/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
group-onsemi	0:098463de4c5d	204	* @brief Initialization and Configuration functions
group-onsemi	0:098463de4c5d	205	*
group-onsemi	0:098463de4c5d	206	@verbatim
group-onsemi	0:098463de4c5d	207	===============================================================================
group-onsemi	0:098463de4c5d	208	##### Initialization and Configuration functions #####
group-onsemi	0:098463de4c5d	209	===============================================================================
group-onsemi	0:098463de4c5d	210	[..] This section provides functions allowing to:
group-onsemi	0:098463de4c5d	211	(+) Initialize and configure the DMA2D
group-onsemi	0:098463de4c5d	212	(+) De-initialize the DMA2D
group-onsemi	0:098463de4c5d	213
group-onsemi	0:098463de4c5d	214	@endverbatim
group-onsemi	0:098463de4c5d	215	* @{
group-onsemi	0:098463de4c5d	216	*/
group-onsemi	0:098463de4c5d	217
group-onsemi	0:098463de4c5d	218	/**
group-onsemi	0:098463de4c5d	219	* @brief Initialize the DMA2D according to the specified
group-onsemi	0:098463de4c5d	220	* parameters in the DMA2D_InitTypeDef and create the associated handle.
group-onsemi	0:098463de4c5d	221	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	222	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	223	* @retval HAL status
group-onsemi	0:098463de4c5d	224	*/
group-onsemi	0:098463de4c5d	225	HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	226	{
group-onsemi	0:098463de4c5d	227	/* Check the DMA2D peripheral state */
group-onsemi	0:098463de4c5d	228	if(hdma2d == NULL)
group-onsemi	0:098463de4c5d	229	{
group-onsemi	0:098463de4c5d	230	return HAL_ERROR;
group-onsemi	0:098463de4c5d	231	}
group-onsemi	0:098463de4c5d	232
group-onsemi	0:098463de4c5d	233	/* Check the parameters */
group-onsemi	0:098463de4c5d	234	assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
group-onsemi	0:098463de4c5d	235	assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
group-onsemi	0:098463de4c5d	236	assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
group-onsemi	0:098463de4c5d	237	assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
group-onsemi	0:098463de4c5d	238
group-onsemi	0:098463de4c5d	239	if(hdma2d->State == HAL_DMA2D_STATE_RESET)
group-onsemi	0:098463de4c5d	240	{
group-onsemi	0:098463de4c5d	241	/* Allocate lock resource and initialize it */
group-onsemi	0:098463de4c5d	242	hdma2d->Lock = HAL_UNLOCKED;
group-onsemi	0:098463de4c5d	243	/* Init the low level hardware */
group-onsemi	0:098463de4c5d	244	HAL_DMA2D_MspInit(hdma2d);
group-onsemi	0:098463de4c5d	245	}
group-onsemi	0:098463de4c5d	246
group-onsemi	0:098463de4c5d	247	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	248	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	249
group-onsemi	0:098463de4c5d	250	/* DMA2D CR register configuration -------------------------------------------*/
group-onsemi	0:098463de4c5d	251	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
group-onsemi	0:098463de4c5d	252
group-onsemi	0:098463de4c5d	253	/* DMA2D OPFCCR register configuration ---------------------------------------*/
group-onsemi	0:098463de4c5d	254	MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
group-onsemi	0:098463de4c5d	255
group-onsemi	0:098463de4c5d	256	/* DMA2D OOR register configuration ------------------------------------------*/
group-onsemi	0:098463de4c5d	257	MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
group-onsemi	0:098463de4c5d	258
group-onsemi	0:098463de4c5d	259	/* Update error code */
group-onsemi	0:098463de4c5d	260	hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
group-onsemi	0:098463de4c5d	261
group-onsemi	0:098463de4c5d	262	/* Initialize the DMA2D state*/
group-onsemi	0:098463de4c5d	263	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	264
group-onsemi	0:098463de4c5d	265	return HAL_OK;
group-onsemi	0:098463de4c5d	266	}
group-onsemi	0:098463de4c5d	267
group-onsemi	0:098463de4c5d	268	/**
group-onsemi	0:098463de4c5d	269	* @brief Deinitializes the DMA2D peripheral registers to their default reset
group-onsemi	0:098463de4c5d	270	* values.
group-onsemi	0:098463de4c5d	271	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	272	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	273	* @retval None
group-onsemi	0:098463de4c5d	274	*/
group-onsemi	0:098463de4c5d	275
group-onsemi	0:098463de4c5d	276	HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	277	{
group-onsemi	0:098463de4c5d	278	/* Check the DMA2D peripheral state */
group-onsemi	0:098463de4c5d	279	if(hdma2d == NULL)
group-onsemi	0:098463de4c5d	280	{
group-onsemi	0:098463de4c5d	281	return HAL_ERROR;
group-onsemi	0:098463de4c5d	282	}
group-onsemi	0:098463de4c5d	283
group-onsemi	0:098463de4c5d	284	/* Before aborting any DMA2D transfer or CLUT loading, check
group-onsemi	0:098463de4c5d	285	first whether or not DMA2D clock is enabled */
group-onsemi	0:098463de4c5d	286	if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
group-onsemi	0:098463de4c5d	287	{
group-onsemi	0:098463de4c5d	288	/* Abort DMA2D transfer if any */
group-onsemi	0:098463de4c5d	289	if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
group-onsemi	0:098463de4c5d	290	{
group-onsemi	0:098463de4c5d	291	if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
group-onsemi	0:098463de4c5d	292	{
group-onsemi	0:098463de4c5d	293	/* Issue when aborting DMA2D transfer */
group-onsemi	0:098463de4c5d	294	return HAL_ERROR;
group-onsemi	0:098463de4c5d	295	}
group-onsemi	0:098463de4c5d	296	}
group-onsemi	0:098463de4c5d	297	else
group-onsemi	0:098463de4c5d	298	{
group-onsemi	0:098463de4c5d	299	/* Abort background CLUT loading if any */
group-onsemi	0:098463de4c5d	300	if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
group-onsemi	0:098463de4c5d	301	{
group-onsemi	0:098463de4c5d	302	if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
group-onsemi	0:098463de4c5d	303	{
group-onsemi	0:098463de4c5d	304	/* Issue when aborting background CLUT loading */
group-onsemi	0:098463de4c5d	305	return HAL_ERROR;
group-onsemi	0:098463de4c5d	306	}
group-onsemi	0:098463de4c5d	307	}
group-onsemi	0:098463de4c5d	308	else
group-onsemi	0:098463de4c5d	309	{
group-onsemi	0:098463de4c5d	310	/* Abort foreground CLUT loading if any */
group-onsemi	0:098463de4c5d	311	if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
group-onsemi	0:098463de4c5d	312	{
group-onsemi	0:098463de4c5d	313	if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
group-onsemi	0:098463de4c5d	314	{
group-onsemi	0:098463de4c5d	315	/* Issue when aborting foreground CLUT loading */
group-onsemi	0:098463de4c5d	316	return HAL_ERROR;
group-onsemi	0:098463de4c5d	317	}
group-onsemi	0:098463de4c5d	318	}
group-onsemi	0:098463de4c5d	319	}
group-onsemi	0:098463de4c5d	320	}
group-onsemi	0:098463de4c5d	321	}
group-onsemi	0:098463de4c5d	322
group-onsemi	0:098463de4c5d	323	/* Carry on with de-initialization of low level hardware */
group-onsemi	0:098463de4c5d	324	HAL_DMA2D_MspDeInit(hdma2d);
group-onsemi	0:098463de4c5d	325
group-onsemi	0:098463de4c5d	326	/* Reset DMA2D control registers*/
group-onsemi	0:098463de4c5d	327	hdma2d->Instance->CR = 0U;
group-onsemi	0:098463de4c5d	328	hdma2d->Instance->FGOR = 0U;
group-onsemi	0:098463de4c5d	329	hdma2d->Instance->BGOR = 0U;
group-onsemi	0:098463de4c5d	330	hdma2d->Instance->FGPFCCR = 0U;
group-onsemi	0:098463de4c5d	331	hdma2d->Instance->BGPFCCR = 0U;
group-onsemi	0:098463de4c5d	332	hdma2d->Instance->OPFCCR = 0U;
group-onsemi	0:098463de4c5d	333
group-onsemi	0:098463de4c5d	334	/* Update error code */
group-onsemi	0:098463de4c5d	335	hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
group-onsemi	0:098463de4c5d	336
group-onsemi	0:098463de4c5d	337	/* Initialize the DMA2D state*/
group-onsemi	0:098463de4c5d	338	hdma2d->State = HAL_DMA2D_STATE_RESET;
group-onsemi	0:098463de4c5d	339
group-onsemi	0:098463de4c5d	340	/* Release Lock */
group-onsemi	0:098463de4c5d	341	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	342
group-onsemi	0:098463de4c5d	343	return HAL_OK;
group-onsemi	0:098463de4c5d	344	}
group-onsemi	0:098463de4c5d	345
group-onsemi	0:098463de4c5d	346	/**
group-onsemi	0:098463de4c5d	347	* @brief Initializes the DMA2D MSP.
group-onsemi	0:098463de4c5d	348	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	349	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	350	* @retval None
group-onsemi	0:098463de4c5d	351	*/
group-onsemi	0:098463de4c5d	352	__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
group-onsemi	0:098463de4c5d	353	{
group-onsemi	0:098463de4c5d	354	/* Prevent unused argument(s) compilation warning */
group-onsemi	0:098463de4c5d	355	UNUSED(hdma2d);
group-onsemi	0:098463de4c5d	356
group-onsemi	0:098463de4c5d	357	/* NOTE : This function should not be modified; when the callback is needed,
group-onsemi	0:098463de4c5d	358	the HAL_DMA2D_MspInit can be implemented in the user file.
group-onsemi	0:098463de4c5d	359	*/
group-onsemi	0:098463de4c5d	360	}
group-onsemi	0:098463de4c5d	361
group-onsemi	0:098463de4c5d	362	/**
group-onsemi	0:098463de4c5d	363	* @brief DeInitializes the DMA2D MSP.
group-onsemi	0:098463de4c5d	364	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	365	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	366	* @retval None
group-onsemi	0:098463de4c5d	367	*/
group-onsemi	0:098463de4c5d	368	__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
group-onsemi	0:098463de4c5d	369	{
group-onsemi	0:098463de4c5d	370	/* Prevent unused argument(s) compilation warning */
group-onsemi	0:098463de4c5d	371	UNUSED(hdma2d);
group-onsemi	0:098463de4c5d	372
group-onsemi	0:098463de4c5d	373	/* NOTE : This function should not be modified; when the callback is needed,
group-onsemi	0:098463de4c5d	374	the HAL_DMA2D_MspDeInit can be implemented in the user file.
group-onsemi	0:098463de4c5d	375	*/
group-onsemi	0:098463de4c5d	376	}
group-onsemi	0:098463de4c5d	377
group-onsemi	0:098463de4c5d	378	/**
group-onsemi	0:098463de4c5d	379	* @}
group-onsemi	0:098463de4c5d	380	*/
group-onsemi	0:098463de4c5d	381
group-onsemi	0:098463de4c5d	382	/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
group-onsemi	0:098463de4c5d	383	* @brief IO operation functions
group-onsemi	0:098463de4c5d	384	*
group-onsemi	0:098463de4c5d	385	@verbatim
group-onsemi	0:098463de4c5d	386	===============================================================================
group-onsemi	0:098463de4c5d	387	##### IO operation functions #####
group-onsemi	0:098463de4c5d	388	===============================================================================
group-onsemi	0:098463de4c5d	389	[..] This section provides functions allowing to:
group-onsemi	0:098463de4c5d	390	(+) Configure the pdata, destination address and data size then
group-onsemi	0:098463de4c5d	391	start the DMA2D transfer.
group-onsemi	0:098463de4c5d	392	(+) Configure the source for foreground and background, destination address
group-onsemi	0:098463de4c5d	393	and data size then start a MultiBuffer DMA2D transfer.
group-onsemi	0:098463de4c5d	394	(+) Configure the pdata, destination address and data size then
group-onsemi	0:098463de4c5d	395	start the DMA2D transfer with interrupt.
group-onsemi	0:098463de4c5d	396	(+) Configure the source for foreground and background, destination address
group-onsemi	0:098463de4c5d	397	and data size then start a MultiBuffer DMA2D transfer with interrupt.
group-onsemi	0:098463de4c5d	398	(+) Abort DMA2D transfer.
group-onsemi	0:098463de4c5d	399	(+) Suspend DMA2D transfer.
group-onsemi	0:098463de4c5d	400	(+) Resume DMA2D transfer.
group-onsemi	0:098463de4c5d	401	(+) Enable CLUT transfer.
group-onsemi	0:098463de4c5d	402	(+) Configure CLUT loading then start transfer in polling mode.
group-onsemi	0:098463de4c5d	403	(+) Configure CLUT loading then start transfer in interrupt mode.
group-onsemi	0:098463de4c5d	404	(+) Abort DMA2D CLUT loading.
group-onsemi	0:098463de4c5d	405	(+) Suspend DMA2D CLUT loading.
group-onsemi	0:098463de4c5d	406	(+) Resume DMA2D CLUT loading.
group-onsemi	0:098463de4c5d	407	(+) Poll for transfer complete.
group-onsemi	0:098463de4c5d	408	(+) handle DMA2D interrupt request.
group-onsemi	0:098463de4c5d	409	(+) Transfer watermark callback.
group-onsemi	0:098463de4c5d	410	(+) CLUT Transfer Complete callback.
group-onsemi	0:098463de4c5d	411
group-onsemi	0:098463de4c5d	412	@endverbatim
group-onsemi	0:098463de4c5d	413	* @{
group-onsemi	0:098463de4c5d	414	*/
group-onsemi	0:098463de4c5d	415
group-onsemi	0:098463de4c5d	416	/**
group-onsemi	0:098463de4c5d	417	* @brief Start the DMA2D Transfer.
group-onsemi	0:098463de4c5d	418	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	419	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	420	* @param pdata: Configure the source memory Buffer address if
group-onsemi	0:098463de4c5d	421	* Memory-to-Memory or Memory-to-Memory with pixel format
group-onsemi	0:098463de4c5d	422	* conversion mode is selected, or configure
group-onsemi	0:098463de4c5d	423	* the color value if Register-to-Memory mode is selected.
group-onsemi	0:098463de4c5d	424	* @param DstAddress: The destination memory Buffer address.
group-onsemi	0:098463de4c5d	425	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
group-onsemi	0:098463de4c5d	426	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
group-onsemi	0:098463de4c5d	427	* @retval HAL status
group-onsemi	0:098463de4c5d	428	*/
group-onsemi	0:098463de4c5d	429	HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
group-onsemi	0:098463de4c5d	430	{
group-onsemi	0:098463de4c5d	431	/* Check the parameters */
group-onsemi	0:098463de4c5d	432	assert_param(IS_DMA2D_LINE(Height));
group-onsemi	0:098463de4c5d	433	assert_param(IS_DMA2D_PIXEL(Width));
group-onsemi	0:098463de4c5d	434
group-onsemi	0:098463de4c5d	435	/* Process locked */
group-onsemi	0:098463de4c5d	436	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	437
group-onsemi	0:098463de4c5d	438	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	439	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	440
group-onsemi	0:098463de4c5d	441	/* Configure the source, destination address and the data size */
group-onsemi	0:098463de4c5d	442	DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
group-onsemi	0:098463de4c5d	443
group-onsemi	0:098463de4c5d	444	/* Enable the Peripheral */
group-onsemi	0:098463de4c5d	445	__HAL_DMA2D_ENABLE(hdma2d);
group-onsemi	0:098463de4c5d	446
group-onsemi	0:098463de4c5d	447	return HAL_OK;
group-onsemi	0:098463de4c5d	448	}
group-onsemi	0:098463de4c5d	449
group-onsemi	0:098463de4c5d	450	/**
group-onsemi	0:098463de4c5d	451	* @brief Start the DMA2D Transfer with interrupt enabled.
group-onsemi	0:098463de4c5d	452	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	453	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	454	* @param pdata: Configure the source memory Buffer address if
group-onsemi	0:098463de4c5d	455	* the Memory-to-Memory or Memory-to-Memory with pixel format
group-onsemi	0:098463de4c5d	456	* conversion mode is selected, or configure
group-onsemi	0:098463de4c5d	457	* the color value if Register-to-Memory mode is selected.
group-onsemi	0:098463de4c5d	458	* @param DstAddress: The destination memory Buffer address.
group-onsemi	0:098463de4c5d	459	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
group-onsemi	0:098463de4c5d	460	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
group-onsemi	0:098463de4c5d	461	* @retval HAL status
group-onsemi	0:098463de4c5d	462	*/
group-onsemi	0:098463de4c5d	463	HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
group-onsemi	0:098463de4c5d	464	{
group-onsemi	0:098463de4c5d	465	/* Check the parameters */
group-onsemi	0:098463de4c5d	466	assert_param(IS_DMA2D_LINE(Height));
group-onsemi	0:098463de4c5d	467	assert_param(IS_DMA2D_PIXEL(Width));
group-onsemi	0:098463de4c5d	468
group-onsemi	0:098463de4c5d	469	/* Process locked */
group-onsemi	0:098463de4c5d	470	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	471
group-onsemi	0:098463de4c5d	472	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	473	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	474
group-onsemi	0:098463de4c5d	475	/* Configure the source, destination address and the data size */
group-onsemi	0:098463de4c5d	476	DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
group-onsemi	0:098463de4c5d	477
group-onsemi	0:098463de4c5d	478	/* Enable the transfer complete, transfer error and configuration error interrupts */
group-onsemi	0:098463de4c5d	479	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
group-onsemi	0:098463de4c5d	480
group-onsemi	0:098463de4c5d	481	/* Enable the Peripheral */
group-onsemi	0:098463de4c5d	482	__HAL_DMA2D_ENABLE(hdma2d);
group-onsemi	0:098463de4c5d	483
group-onsemi	0:098463de4c5d	484	return HAL_OK;
group-onsemi	0:098463de4c5d	485	}
group-onsemi	0:098463de4c5d	486
group-onsemi	0:098463de4c5d	487	/**
group-onsemi	0:098463de4c5d	488	* @brief Start the multi-source DMA2D Transfer.
group-onsemi	0:098463de4c5d	489	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	490	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	491	* @param SrcAddress1: The source memory Buffer address for the foreground layer.
group-onsemi	0:098463de4c5d	492	* @param SrcAddress2: The source memory Buffer address for the background layer.
group-onsemi	0:098463de4c5d	493	* @param DstAddress: The destination memory Buffer address.
group-onsemi	0:098463de4c5d	494	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
group-onsemi	0:098463de4c5d	495	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
group-onsemi	0:098463de4c5d	496	* @retval HAL status
group-onsemi	0:098463de4c5d	497	*/
group-onsemi	0:098463de4c5d	498	HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
group-onsemi	0:098463de4c5d	499	{
group-onsemi	0:098463de4c5d	500	/* Check the parameters */
group-onsemi	0:098463de4c5d	501	assert_param(IS_DMA2D_LINE(Height));
group-onsemi	0:098463de4c5d	502	assert_param(IS_DMA2D_PIXEL(Width));
group-onsemi	0:098463de4c5d	503
group-onsemi	0:098463de4c5d	504	/* Process locked */
group-onsemi	0:098463de4c5d	505	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	506
group-onsemi	0:098463de4c5d	507	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	508	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	509
group-onsemi	0:098463de4c5d	510	/* Configure DMA2D Stream source2 address */
group-onsemi	0:098463de4c5d	511	WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
group-onsemi	0:098463de4c5d	512
group-onsemi	0:098463de4c5d	513	/* Configure the source, destination address and the data size */
group-onsemi	0:098463de4c5d	514	DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
group-onsemi	0:098463de4c5d	515
group-onsemi	0:098463de4c5d	516	/* Enable the Peripheral */
group-onsemi	0:098463de4c5d	517	__HAL_DMA2D_ENABLE(hdma2d);
group-onsemi	0:098463de4c5d	518
group-onsemi	0:098463de4c5d	519	return HAL_OK;
group-onsemi	0:098463de4c5d	520	}
group-onsemi	0:098463de4c5d	521
group-onsemi	0:098463de4c5d	522	/**
group-onsemi	0:098463de4c5d	523	* @brief Start the multi-source DMA2D Transfer with interrupt enabled.
group-onsemi	0:098463de4c5d	524	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	525	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	526	* @param SrcAddress1: The source memory Buffer address for the foreground layer.
group-onsemi	0:098463de4c5d	527	* @param SrcAddress2: The source memory Buffer address for the background layer.
group-onsemi	0:098463de4c5d	528	* @param DstAddress: The destination memory Buffer address.
group-onsemi	0:098463de4c5d	529	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
group-onsemi	0:098463de4c5d	530	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
group-onsemi	0:098463de4c5d	531	* @retval HAL status
group-onsemi	0:098463de4c5d	532	*/
group-onsemi	0:098463de4c5d	533	HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
group-onsemi	0:098463de4c5d	534	{
group-onsemi	0:098463de4c5d	535	/* Check the parameters */
group-onsemi	0:098463de4c5d	536	assert_param(IS_DMA2D_LINE(Height));
group-onsemi	0:098463de4c5d	537	assert_param(IS_DMA2D_PIXEL(Width));
group-onsemi	0:098463de4c5d	538
group-onsemi	0:098463de4c5d	539	/* Process locked */
group-onsemi	0:098463de4c5d	540	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	541
group-onsemi	0:098463de4c5d	542	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	543	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	544
group-onsemi	0:098463de4c5d	545	/* Configure DMA2D Stream source2 address */
group-onsemi	0:098463de4c5d	546	WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
group-onsemi	0:098463de4c5d	547
group-onsemi	0:098463de4c5d	548	/* Configure the source, destination address and the data size */
group-onsemi	0:098463de4c5d	549	DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
group-onsemi	0:098463de4c5d	550
group-onsemi	0:098463de4c5d	551	/* Enable the transfer complete, transfer error and configuration error interrupts */
group-onsemi	0:098463de4c5d	552	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
group-onsemi	0:098463de4c5d	553
group-onsemi	0:098463de4c5d	554	/* Enable the Peripheral */
group-onsemi	0:098463de4c5d	555	__HAL_DMA2D_ENABLE(hdma2d);
group-onsemi	0:098463de4c5d	556
group-onsemi	0:098463de4c5d	557	return HAL_OK;
group-onsemi	0:098463de4c5d	558	}
group-onsemi	0:098463de4c5d	559
group-onsemi	0:098463de4c5d	560	/**
group-onsemi	0:098463de4c5d	561	* @brief Abort the DMA2D Transfer.
group-onsemi	0:098463de4c5d	562	* @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	563	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	564	* @retval HAL status
group-onsemi	0:098463de4c5d	565	*/
group-onsemi	0:098463de4c5d	566	HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	567	{
group-onsemi	0:098463de4c5d	568	uint32_t tickstart = 0U;
group-onsemi	0:098463de4c5d	569
group-onsemi	0:098463de4c5d	570	/* Abort the DMA2D transfer */
group-onsemi	0:098463de4c5d	571	/* START bit is reset to make sure not to set it again, in the event the HW clears it
group-onsemi	0:098463de4c5d	572	between the register read and the register write by the CPU (writing 0 has no
group-onsemi	0:098463de4c5d	573	effect on START bitvalue). */
group-onsemi	0:098463de4c5d	574	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT\|DMA2D_CR_START, DMA2D_CR_ABORT);
group-onsemi	0:098463de4c5d	575
group-onsemi	0:098463de4c5d	576	/* Get tick */
group-onsemi	0:098463de4c5d	577	tickstart = HAL_GetTick();
group-onsemi	0:098463de4c5d	578
group-onsemi	0:098463de4c5d	579	/* Check if the DMA2D is effectively disabled */
group-onsemi	0:098463de4c5d	580	while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
group-onsemi	0:098463de4c5d	581	{
group-onsemi	0:098463de4c5d	582	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
group-onsemi	0:098463de4c5d	583	{
group-onsemi	0:098463de4c5d	584	/* Update error code */
group-onsemi	0:098463de4c5d	585	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
group-onsemi	0:098463de4c5d	586
group-onsemi	0:098463de4c5d	587	/* Change the DMA2D state */
group-onsemi	0:098463de4c5d	588	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
group-onsemi	0:098463de4c5d	589
group-onsemi	0:098463de4c5d	590	/* Process Unlocked */
group-onsemi	0:098463de4c5d	591	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	592
group-onsemi	0:098463de4c5d	593	return HAL_TIMEOUT;
group-onsemi	0:098463de4c5d	594	}
group-onsemi	0:098463de4c5d	595	}
group-onsemi	0:098463de4c5d	596
group-onsemi	0:098463de4c5d	597	/* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
group-onsemi	0:098463de4c5d	598	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
group-onsemi	0:098463de4c5d	599
group-onsemi	0:098463de4c5d	600	/* Change the DMA2D state*/
group-onsemi	0:098463de4c5d	601	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	602
group-onsemi	0:098463de4c5d	603	/* Process Unlocked */
group-onsemi	0:098463de4c5d	604	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	605
group-onsemi	0:098463de4c5d	606	return HAL_OK;
group-onsemi	0:098463de4c5d	607	}
group-onsemi	0:098463de4c5d	608
group-onsemi	0:098463de4c5d	609	/**
group-onsemi	0:098463de4c5d	610	* @brief Suspend the DMA2D Transfer.
group-onsemi	0:098463de4c5d	611	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	612	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	613	* @retval HAL status
group-onsemi	0:098463de4c5d	614	*/
group-onsemi	0:098463de4c5d	615	HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	616	{
group-onsemi	0:098463de4c5d	617	uint32_t tickstart = 0U;
group-onsemi	0:098463de4c5d	618
group-onsemi	0:098463de4c5d	619	/* Suspend the DMA2D transfer */
group-onsemi	0:098463de4c5d	620	/* START bit is reset to make sure not to set it again, in the event the HW clears it
group-onsemi	0:098463de4c5d	621	between the register read and the register write by the CPU (writing 0 has no
group-onsemi	0:098463de4c5d	622	effect on START bitvalue). */
group-onsemi	0:098463de4c5d	623	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP\|DMA2D_CR_START, DMA2D_CR_SUSP);
group-onsemi	0:098463de4c5d	624
group-onsemi	0:098463de4c5d	625	/* Get tick */
group-onsemi	0:098463de4c5d	626	tickstart = HAL_GetTick();
group-onsemi	0:098463de4c5d	627
group-onsemi	0:098463de4c5d	628	/* Check if the DMA2D is effectively suspended */
group-onsemi	0:098463de4c5d	629	while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
group-onsemi	0:098463de4c5d	630	&& ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
group-onsemi	0:098463de4c5d	631	{
group-onsemi	0:098463de4c5d	632	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
group-onsemi	0:098463de4c5d	633	{
group-onsemi	0:098463de4c5d	634	/* Update error code */
group-onsemi	0:098463de4c5d	635	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
group-onsemi	0:098463de4c5d	636
group-onsemi	0:098463de4c5d	637	/* Change the DMA2D state */
group-onsemi	0:098463de4c5d	638	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
group-onsemi	0:098463de4c5d	639
group-onsemi	0:098463de4c5d	640	return HAL_TIMEOUT;
group-onsemi	0:098463de4c5d	641	}
group-onsemi	0:098463de4c5d	642	}
group-onsemi	0:098463de4c5d	643
group-onsemi	0:098463de4c5d	644	/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
group-onsemi	0:098463de4c5d	645	if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
group-onsemi	0:098463de4c5d	646	{
group-onsemi	0:098463de4c5d	647	hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
group-onsemi	0:098463de4c5d	648	}
group-onsemi	0:098463de4c5d	649	else
group-onsemi	0:098463de4c5d	650	{
group-onsemi	0:098463de4c5d	651	/* Make sure SUSP bit is cleared since it is meaningless
group-onsemi	0:098463de4c5d	652	when no tranfer is on-going */
group-onsemi	0:098463de4c5d	653	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
group-onsemi	0:098463de4c5d	654	}
group-onsemi	0:098463de4c5d	655
group-onsemi	0:098463de4c5d	656	return HAL_OK;
group-onsemi	0:098463de4c5d	657	}
group-onsemi	0:098463de4c5d	658
group-onsemi	0:098463de4c5d	659	/**
group-onsemi	0:098463de4c5d	660	* @brief Resume the DMA2D Transfer.
group-onsemi	0:098463de4c5d	661	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	662	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	663	* @retval HAL status
group-onsemi	0:098463de4c5d	664	*/
group-onsemi	0:098463de4c5d	665	HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	666	{
group-onsemi	0:098463de4c5d	667	/* Check the SUSP and START bits */
group-onsemi	0:098463de4c5d	668	if((hdma2d->Instance->CR & (DMA2D_CR_SUSP \| DMA2D_CR_START)) == (DMA2D_CR_SUSP \| DMA2D_CR_START))
group-onsemi	0:098463de4c5d	669	{
group-onsemi	0:098463de4c5d	670	/* Ongoing transfer is suspended: change the DMA2D state before resuming */
group-onsemi	0:098463de4c5d	671	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	672	}
group-onsemi	0:098463de4c5d	673
group-onsemi	0:098463de4c5d	674	/* Resume the DMA2D transfer */
group-onsemi	0:098463de4c5d	675	/* START bit is reset to make sure not to set it again, in the event the HW clears it
group-onsemi	0:098463de4c5d	676	between the register read and the register write by the CPU (writing 0 has no
group-onsemi	0:098463de4c5d	677	effect on START bitvalue). */
group-onsemi	0:098463de4c5d	678	CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP\|DMA2D_CR_START));
group-onsemi	0:098463de4c5d	679
group-onsemi	0:098463de4c5d	680	return HAL_OK;
group-onsemi	0:098463de4c5d	681	}
group-onsemi	0:098463de4c5d	682
group-onsemi	0:098463de4c5d	683	/**
group-onsemi	0:098463de4c5d	684	* @brief Enable the DMA2D CLUT Transfer.
group-onsemi	0:098463de4c5d	685	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	686	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	687	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	688	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	689	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	690	* @retval HAL status
group-onsemi	0:098463de4c5d	691	*/
group-onsemi	0:098463de4c5d	692	HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	693	{
group-onsemi	0:098463de4c5d	694	/* Check the parameters */
group-onsemi	0:098463de4c5d	695	assert_param(IS_DMA2D_LAYER(LayerIdx));
group-onsemi	0:098463de4c5d	696
group-onsemi	0:098463de4c5d	697	/* Process locked */
group-onsemi	0:098463de4c5d	698	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	699
group-onsemi	0:098463de4c5d	700	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	701	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	702
group-onsemi	0:098463de4c5d	703	if(LayerIdx == 0U)
group-onsemi	0:098463de4c5d	704	{
group-onsemi	0:098463de4c5d	705	/* Enable the background CLUT loading */
group-onsemi	0:098463de4c5d	706	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
group-onsemi	0:098463de4c5d	707	}
group-onsemi	0:098463de4c5d	708	else
group-onsemi	0:098463de4c5d	709	{
group-onsemi	0:098463de4c5d	710	/* Enable the foreground CLUT loading */
group-onsemi	0:098463de4c5d	711	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
group-onsemi	0:098463de4c5d	712	}
group-onsemi	0:098463de4c5d	713
group-onsemi	0:098463de4c5d	714	return HAL_OK;
group-onsemi	0:098463de4c5d	715	}
group-onsemi	0:098463de4c5d	716
group-onsemi	0:098463de4c5d	717	/**
group-onsemi	0:098463de4c5d	718	* @brief Start DMA2D CLUT Loading.
group-onsemi	0:098463de4c5d	719	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	720	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	721	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
group-onsemi	0:098463de4c5d	722	* the configuration information for the color look up table.
group-onsemi	0:098463de4c5d	723	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	724	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	725	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	726	* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
group-onsemi	0:098463de4c5d	727	* @retval HAL status
group-onsemi	0:098463de4c5d	728	*/
group-onsemi	0:098463de4c5d	729	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	730	{
group-onsemi	0:098463de4c5d	731	/* Check the parameters */
group-onsemi	0:098463de4c5d	732	assert_param(IS_DMA2D_LAYER(LayerIdx));
group-onsemi	0:098463de4c5d	733	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
group-onsemi	0:098463de4c5d	734	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
group-onsemi	0:098463de4c5d	735
group-onsemi	0:098463de4c5d	736	/* Process locked */
group-onsemi	0:098463de4c5d	737	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	738
group-onsemi	0:098463de4c5d	739	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	740	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	741
group-onsemi	0:098463de4c5d	742	/* Configure the CLUT of the background DMA2D layer */
group-onsemi	0:098463de4c5d	743	if(LayerIdx == 0U)
group-onsemi	0:098463de4c5d	744	{
group-onsemi	0:098463de4c5d	745	/* Write background CLUT memory address */
group-onsemi	0:098463de4c5d	746	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
group-onsemi	0:098463de4c5d	747
group-onsemi	0:098463de4c5d	748	/* Write background CLUT size and CLUT color mode */
group-onsemi	0:098463de4c5d	749	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
group-onsemi	0:098463de4c5d	750	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
group-onsemi	0:098463de4c5d	751
group-onsemi	0:098463de4c5d	752	/* Enable the CLUT loading for the background */
group-onsemi	0:098463de4c5d	753	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
group-onsemi	0:098463de4c5d	754	}
group-onsemi	0:098463de4c5d	755	/* Configure the CLUT of the foreground DMA2D layer */
group-onsemi	0:098463de4c5d	756	else
group-onsemi	0:098463de4c5d	757	{
group-onsemi	0:098463de4c5d	758	/* Write foreground CLUT memory address */
group-onsemi	0:098463de4c5d	759	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
group-onsemi	0:098463de4c5d	760
group-onsemi	0:098463de4c5d	761	/* Write foreground CLUT size and CLUT color mode */
group-onsemi	0:098463de4c5d	762	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
group-onsemi	0:098463de4c5d	763	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
group-onsemi	0:098463de4c5d	764
group-onsemi	0:098463de4c5d	765	/* Enable the CLUT loading for the foreground */
group-onsemi	0:098463de4c5d	766	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
group-onsemi	0:098463de4c5d	767	}
group-onsemi	0:098463de4c5d	768
group-onsemi	0:098463de4c5d	769	return HAL_OK;
group-onsemi	0:098463de4c5d	770	}
group-onsemi	0:098463de4c5d	771
group-onsemi	0:098463de4c5d	772	/**
group-onsemi	0:098463de4c5d	773	* @brief Start DMA2D CLUT Loading with interrupt enabled.
group-onsemi	0:098463de4c5d	774	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	775	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	776	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
group-onsemi	0:098463de4c5d	777	* the configuration information for the color look up table.
group-onsemi	0:098463de4c5d	778	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	779	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	780	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	781	* @retval HAL status
group-onsemi	0:098463de4c5d	782	*/
group-onsemi	0:098463de4c5d	783	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	784	{
group-onsemi	0:098463de4c5d	785	/* Check the parameters */
group-onsemi	0:098463de4c5d	786	assert_param(IS_DMA2D_LAYER(LayerIdx));
group-onsemi	0:098463de4c5d	787	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
group-onsemi	0:098463de4c5d	788	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
group-onsemi	0:098463de4c5d	789
group-onsemi	0:098463de4c5d	790	/* Process locked */
group-onsemi	0:098463de4c5d	791	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	792
group-onsemi	0:098463de4c5d	793	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	794	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	795
group-onsemi	0:098463de4c5d	796	/* Configure the CLUT of the background DMA2D layer */
group-onsemi	0:098463de4c5d	797	if(LayerIdx == 0U)
group-onsemi	0:098463de4c5d	798	{
group-onsemi	0:098463de4c5d	799	/* Write background CLUT memory address */
group-onsemi	0:098463de4c5d	800	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
group-onsemi	0:098463de4c5d	801
group-onsemi	0:098463de4c5d	802	/* Write background CLUT size and CLUT color mode */
group-onsemi	0:098463de4c5d	803	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
group-onsemi	0:098463de4c5d	804	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
group-onsemi	0:098463de4c5d	805
group-onsemi	0:098463de4c5d	806	/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
group-onsemi	0:098463de4c5d	807	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
group-onsemi	0:098463de4c5d	808
group-onsemi	0:098463de4c5d	809	/* Enable the CLUT loading for the background */
group-onsemi	0:098463de4c5d	810	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
group-onsemi	0:098463de4c5d	811	}
group-onsemi	0:098463de4c5d	812	/* Configure the CLUT of the foreground DMA2D layer */
group-onsemi	0:098463de4c5d	813	else
group-onsemi	0:098463de4c5d	814	{
group-onsemi	0:098463de4c5d	815	/* Write foreground CLUT memory address */
group-onsemi	0:098463de4c5d	816	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
group-onsemi	0:098463de4c5d	817
group-onsemi	0:098463de4c5d	818	/* Write foreground CLUT size and CLUT color mode */
group-onsemi	0:098463de4c5d	819	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
group-onsemi	0:098463de4c5d	820	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
group-onsemi	0:098463de4c5d	821
group-onsemi	0:098463de4c5d	822	/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
group-onsemi	0:098463de4c5d	823	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
group-onsemi	0:098463de4c5d	824
group-onsemi	0:098463de4c5d	825	/* Enable the CLUT loading for the foreground */
group-onsemi	0:098463de4c5d	826	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
group-onsemi	0:098463de4c5d	827	}
group-onsemi	0:098463de4c5d	828
group-onsemi	0:098463de4c5d	829	return HAL_OK;
group-onsemi	0:098463de4c5d	830	}
group-onsemi	0:098463de4c5d	831
group-onsemi	0:098463de4c5d	832	/**
group-onsemi	0:098463de4c5d	833	* @brief Abort the DMA2D CLUT loading.
group-onsemi	0:098463de4c5d	834	* @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	835	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	836	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	837	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	838	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	839	* @retval HAL status
group-onsemi	0:098463de4c5d	840	*/
group-onsemi	0:098463de4c5d	841	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	842	{
group-onsemi	0:098463de4c5d	843	uint32_t tickstart = 0U;
group-onsemi	0:098463de4c5d	844	__IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
group-onsemi	0:098463de4c5d	845
group-onsemi	0:098463de4c5d	846	/* Abort the CLUT loading */
group-onsemi	0:098463de4c5d	847	SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
group-onsemi	0:098463de4c5d	848
group-onsemi	0:098463de4c5d	849	/* If foreground CLUT loading is considered, update local variables */
group-onsemi	0:098463de4c5d	850	if(LayerIdx == 1)
group-onsemi	0:098463de4c5d	851	{
group-onsemi	0:098463de4c5d	852	reg = &(hdma2d->Instance->FGPFCCR);
group-onsemi	0:098463de4c5d	853	}
group-onsemi	0:098463de4c5d	854
group-onsemi	0:098463de4c5d	855	/* Get tick */
group-onsemi	0:098463de4c5d	856	tickstart = HAL_GetTick();
group-onsemi	0:098463de4c5d	857
group-onsemi	0:098463de4c5d	858	/* Check if the CLUT loading is aborted */
group-onsemi	0:098463de4c5d	859	while((*reg & DMA2D_BGPFCCR_START) != RESET)
group-onsemi	0:098463de4c5d	860	{
group-onsemi	0:098463de4c5d	861	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
group-onsemi	0:098463de4c5d	862	{
group-onsemi	0:098463de4c5d	863	/* Update error code */
group-onsemi	0:098463de4c5d	864	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
group-onsemi	0:098463de4c5d	865
group-onsemi	0:098463de4c5d	866	/* Change the DMA2D state */
group-onsemi	0:098463de4c5d	867	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
group-onsemi	0:098463de4c5d	868
group-onsemi	0:098463de4c5d	869	/* Process Unlocked */
group-onsemi	0:098463de4c5d	870	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	871
group-onsemi	0:098463de4c5d	872	return HAL_TIMEOUT;
group-onsemi	0:098463de4c5d	873	}
group-onsemi	0:098463de4c5d	874	}
group-onsemi	0:098463de4c5d	875
group-onsemi	0:098463de4c5d	876	/* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
group-onsemi	0:098463de4c5d	877	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
group-onsemi	0:098463de4c5d	878
group-onsemi	0:098463de4c5d	879	/* Change the DMA2D state*/
group-onsemi	0:098463de4c5d	880	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	881
group-onsemi	0:098463de4c5d	882	/* Process Unlocked */
group-onsemi	0:098463de4c5d	883	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	884
group-onsemi	0:098463de4c5d	885	return HAL_OK;
group-onsemi	0:098463de4c5d	886	}
group-onsemi	0:098463de4c5d	887
group-onsemi	0:098463de4c5d	888	/**
group-onsemi	0:098463de4c5d	889	* @brief Suspend the DMA2D CLUT loading.
group-onsemi	0:098463de4c5d	890	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	891	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	892	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	893	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	894	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	895	* @retval HAL status
group-onsemi	0:098463de4c5d	896	*/
group-onsemi	0:098463de4c5d	897	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	898	{
group-onsemi	0:098463de4c5d	899	uint32_t tickstart = 0U;
group-onsemi	0:098463de4c5d	900	__IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
group-onsemi	0:098463de4c5d	901
group-onsemi	0:098463de4c5d	902	/* Suspend the CLUT loading */
group-onsemi	0:098463de4c5d	903	SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
group-onsemi	0:098463de4c5d	904
group-onsemi	0:098463de4c5d	905	/* If foreground CLUT loading is considered, update local variables */
group-onsemi	0:098463de4c5d	906	if(LayerIdx == 1U)
group-onsemi	0:098463de4c5d	907	{
group-onsemi	0:098463de4c5d	908	reg = &(hdma2d->Instance->FGPFCCR);
group-onsemi	0:098463de4c5d	909	}
group-onsemi	0:098463de4c5d	910
group-onsemi	0:098463de4c5d	911	/* Get tick */
group-onsemi	0:098463de4c5d	912	tickstart = HAL_GetTick();
group-onsemi	0:098463de4c5d	913
group-onsemi	0:098463de4c5d	914	/* Check if the CLUT loading is suspended */
group-onsemi	0:098463de4c5d	915	while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
group-onsemi	0:098463de4c5d	916	&& ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
group-onsemi	0:098463de4c5d	917	{
group-onsemi	0:098463de4c5d	918	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
group-onsemi	0:098463de4c5d	919	{
group-onsemi	0:098463de4c5d	920	/* Update error code */
group-onsemi	0:098463de4c5d	921	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
group-onsemi	0:098463de4c5d	922
group-onsemi	0:098463de4c5d	923	/* Change the DMA2D state */
group-onsemi	0:098463de4c5d	924	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
group-onsemi	0:098463de4c5d	925
group-onsemi	0:098463de4c5d	926	return HAL_TIMEOUT;
group-onsemi	0:098463de4c5d	927	}
group-onsemi	0:098463de4c5d	928	}
group-onsemi	0:098463de4c5d	929
group-onsemi	0:098463de4c5d	930	/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
group-onsemi	0:098463de4c5d	931	if ((*reg & DMA2D_BGPFCCR_START) != RESET)
group-onsemi	0:098463de4c5d	932	{
group-onsemi	0:098463de4c5d	933	hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
group-onsemi	0:098463de4c5d	934	}
group-onsemi	0:098463de4c5d	935	else
group-onsemi	0:098463de4c5d	936	{
group-onsemi	0:098463de4c5d	937	/* Make sure SUSP bit is cleared since it is meaningless
group-onsemi	0:098463de4c5d	938	when no tranfer is on-going */
group-onsemi	0:098463de4c5d	939	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
group-onsemi	0:098463de4c5d	940	}
group-onsemi	0:098463de4c5d	941
group-onsemi	0:098463de4c5d	942	return HAL_OK;
group-onsemi	0:098463de4c5d	943	}
group-onsemi	0:098463de4c5d	944
group-onsemi	0:098463de4c5d	945	/**
group-onsemi	0:098463de4c5d	946	* @brief Resume the DMA2D CLUT loading.
group-onsemi	0:098463de4c5d	947	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	948	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	949	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	950	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	951	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	952	* @retval HAL status
group-onsemi	0:098463de4c5d	953	*/
group-onsemi	0:098463de4c5d	954	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	955	{
group-onsemi	0:098463de4c5d	956	/* Check the SUSP and START bits for background or foreground CLUT loading */
group-onsemi	0:098463de4c5d	957	if(LayerIdx == 0U)
group-onsemi	0:098463de4c5d	958	{
group-onsemi	0:098463de4c5d	959	/* Background CLUT loading suspension check */
group-onsemi	0:098463de4c5d	960	if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
group-onsemi	0:098463de4c5d	961	&& ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
group-onsemi	0:098463de4c5d	962	{
group-onsemi	0:098463de4c5d	963	/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
group-onsemi	0:098463de4c5d	964	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	965	}
group-onsemi	0:098463de4c5d	966	}
group-onsemi	0:098463de4c5d	967	else
group-onsemi	0:098463de4c5d	968	{
group-onsemi	0:098463de4c5d	969	/* Foreground CLUT loading suspension check */
group-onsemi	0:098463de4c5d	970	if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
group-onsemi	0:098463de4c5d	971	&& ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
group-onsemi	0:098463de4c5d	972	{
group-onsemi	0:098463de4c5d	973	/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
group-onsemi	0:098463de4c5d	974	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	975	}
group-onsemi	0:098463de4c5d	976	}
group-onsemi	0:098463de4c5d	977
group-onsemi	0:098463de4c5d	978	/* Resume the CLUT loading */
group-onsemi	0:098463de4c5d	979	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
group-onsemi	0:098463de4c5d	980
group-onsemi	0:098463de4c5d	981	return HAL_OK;
group-onsemi	0:098463de4c5d	982	}
group-onsemi	0:098463de4c5d	983
group-onsemi	0:098463de4c5d	984	/**
group-onsemi	0:098463de4c5d	985	* @brief Polling for transfer complete or CLUT loading.
group-onsemi	0:098463de4c5d	986	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	987	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	988	* @param Timeout: Timeout duration
group-onsemi	0:098463de4c5d	989	* @retval HAL status
group-onsemi	0:098463de4c5d	990	*/
group-onsemi	0:098463de4c5d	991	HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
group-onsemi	0:098463de4c5d	992	{
group-onsemi	0:098463de4c5d	993	uint32_t tickstart = 0U;
group-onsemi	0:098463de4c5d	994	__IO uint32_t isrflags = 0x0U;
group-onsemi	0:098463de4c5d	995
group-onsemi	0:098463de4c5d	996	/* Polling for DMA2D transfer */
group-onsemi	0:098463de4c5d	997	if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
group-onsemi	0:098463de4c5d	998	{
group-onsemi	0:098463de4c5d	999	/* Get tick */
group-onsemi	0:098463de4c5d	1000	tickstart = HAL_GetTick();
group-onsemi	0:098463de4c5d	1001
group-onsemi	0:098463de4c5d	1002	while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
group-onsemi	0:098463de4c5d	1003	{
group-onsemi	0:098463de4c5d	1004	isrflags = READ_REG(hdma2d->Instance->ISR);
group-onsemi	0:098463de4c5d	1005	if ((isrflags & (DMA2D_FLAG_CE\|DMA2D_FLAG_TE)) != RESET)
group-onsemi	0:098463de4c5d	1006	{
group-onsemi	0:098463de4c5d	1007	if ((isrflags & DMA2D_FLAG_CE) != RESET)
group-onsemi	0:098463de4c5d	1008	{
group-onsemi	0:098463de4c5d	1009	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
group-onsemi	0:098463de4c5d	1010	}
group-onsemi	0:098463de4c5d	1011	if ((isrflags & DMA2D_FLAG_TE) != RESET)
group-onsemi	0:098463de4c5d	1012	{
group-onsemi	0:098463de4c5d	1013	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
group-onsemi	0:098463de4c5d	1014	}
group-onsemi	0:098463de4c5d	1015	/* Clear the transfer and configuration error flags */
group-onsemi	0:098463de4c5d	1016	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE \| DMA2D_FLAG_TE);
group-onsemi	0:098463de4c5d	1017
group-onsemi	0:098463de4c5d	1018	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1019	hdma2d->State = HAL_DMA2D_STATE_ERROR;
group-onsemi	0:098463de4c5d	1020
group-onsemi	0:098463de4c5d	1021	/* Process unlocked */
group-onsemi	0:098463de4c5d	1022	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1023
group-onsemi	0:098463de4c5d	1024	return HAL_ERROR;
group-onsemi	0:098463de4c5d	1025	}
group-onsemi	0:098463de4c5d	1026	/* Check for the Timeout */
group-onsemi	0:098463de4c5d	1027	if(Timeout != HAL_MAX_DELAY)
group-onsemi	0:098463de4c5d	1028	{
group-onsemi	0:098463de4c5d	1029	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
group-onsemi	0:098463de4c5d	1030	{
group-onsemi	0:098463de4c5d	1031	/* Update error code */
group-onsemi	0:098463de4c5d	1032	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
group-onsemi	0:098463de4c5d	1033
group-onsemi	0:098463de4c5d	1034	/* Change the DMA2D state */
group-onsemi	0:098463de4c5d	1035	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
group-onsemi	0:098463de4c5d	1036
group-onsemi	0:098463de4c5d	1037	/* Process unlocked */
group-onsemi	0:098463de4c5d	1038	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1039
group-onsemi	0:098463de4c5d	1040	return HAL_TIMEOUT;
group-onsemi	0:098463de4c5d	1041	}
group-onsemi	0:098463de4c5d	1042	}
group-onsemi	0:098463de4c5d	1043	}
group-onsemi	0:098463de4c5d	1044	}
group-onsemi	0:098463de4c5d	1045	/* Polling for CLUT loading (foreground or background) */
group-onsemi	0:098463de4c5d	1046	if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) \|\|
group-onsemi	0:098463de4c5d	1047	((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
group-onsemi	0:098463de4c5d	1048	{
group-onsemi	0:098463de4c5d	1049	/* Get tick */
group-onsemi	0:098463de4c5d	1050	tickstart = HAL_GetTick();
group-onsemi	0:098463de4c5d	1051
group-onsemi	0:098463de4c5d	1052	while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
group-onsemi	0:098463de4c5d	1053	{
group-onsemi	0:098463de4c5d	1054	isrflags = READ_REG(hdma2d->Instance->ISR);
group-onsemi	0:098463de4c5d	1055	if ((isrflags & (DMA2D_FLAG_CAE\|DMA2D_FLAG_CE\|DMA2D_FLAG_TE)) != RESET)
group-onsemi	0:098463de4c5d	1056	{
group-onsemi	0:098463de4c5d	1057	if ((isrflags & DMA2D_FLAG_CAE) != RESET)
group-onsemi	0:098463de4c5d	1058	{
group-onsemi	0:098463de4c5d	1059	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CAE;
group-onsemi	0:098463de4c5d	1060	}
group-onsemi	0:098463de4c5d	1061	if ((isrflags & DMA2D_FLAG_CE) != RESET)
group-onsemi	0:098463de4c5d	1062	{
group-onsemi	0:098463de4c5d	1063	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
group-onsemi	0:098463de4c5d	1064	}
group-onsemi	0:098463de4c5d	1065	if ((isrflags & DMA2D_FLAG_TE) != RESET)
group-onsemi	0:098463de4c5d	1066	{
group-onsemi	0:098463de4c5d	1067	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
group-onsemi	0:098463de4c5d	1068	}
group-onsemi	0:098463de4c5d	1069	/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
group-onsemi	0:098463de4c5d	1070	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE \| DMA2D_FLAG_CE \| DMA2D_FLAG_TE);
group-onsemi	0:098463de4c5d	1071
group-onsemi	0:098463de4c5d	1072	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1073	hdma2d->State= HAL_DMA2D_STATE_ERROR;
group-onsemi	0:098463de4c5d	1074
group-onsemi	0:098463de4c5d	1075	/* Process unlocked */
group-onsemi	0:098463de4c5d	1076	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1077
group-onsemi	0:098463de4c5d	1078	return HAL_ERROR;
group-onsemi	0:098463de4c5d	1079	}
group-onsemi	0:098463de4c5d	1080	/* Check for the Timeout */
group-onsemi	0:098463de4c5d	1081	if(Timeout != HAL_MAX_DELAY)
group-onsemi	0:098463de4c5d	1082	{
group-onsemi	0:098463de4c5d	1083	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
group-onsemi	0:098463de4c5d	1084	{
group-onsemi	0:098463de4c5d	1085	/* Update error code */
group-onsemi	0:098463de4c5d	1086	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
group-onsemi	0:098463de4c5d	1087
group-onsemi	0:098463de4c5d	1088	/* Change the DMA2D state */
group-onsemi	0:098463de4c5d	1089	hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
group-onsemi	0:098463de4c5d	1090
group-onsemi	0:098463de4c5d	1091	/* Process unlocked */
group-onsemi	0:098463de4c5d	1092	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1093
group-onsemi	0:098463de4c5d	1094	return HAL_TIMEOUT;
group-onsemi	0:098463de4c5d	1095	}
group-onsemi	0:098463de4c5d	1096	}
group-onsemi	0:098463de4c5d	1097	}
group-onsemi	0:098463de4c5d	1098	}
group-onsemi	0:098463de4c5d	1099
group-onsemi	0:098463de4c5d	1100	/* Clear the transfer complete and CLUT loading flags */
group-onsemi	0:098463de4c5d	1101	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC\|DMA2D_FLAG_CTC);
group-onsemi	0:098463de4c5d	1102
group-onsemi	0:098463de4c5d	1103	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1104	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1105
group-onsemi	0:098463de4c5d	1106	/* Process unlocked */
group-onsemi	0:098463de4c5d	1107	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1108
group-onsemi	0:098463de4c5d	1109	return HAL_OK;
group-onsemi	0:098463de4c5d	1110	}
group-onsemi	0:098463de4c5d	1111	/**
group-onsemi	0:098463de4c5d	1112	* @brief Handle DMA2D interrupt request.
group-onsemi	0:098463de4c5d	1113	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1114	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1115	* @retval HAL status
group-onsemi	0:098463de4c5d	1116	*/
group-onsemi	0:098463de4c5d	1117	void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1118	{
group-onsemi	0:098463de4c5d	1119	uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
group-onsemi	0:098463de4c5d	1120	uint32_t crflags = READ_REG(hdma2d->Instance->CR);
group-onsemi	0:098463de4c5d	1121
group-onsemi	0:098463de4c5d	1122	/* Transfer Error Interrupt management ***************************************/
group-onsemi	0:098463de4c5d	1123	if ((isrflags & DMA2D_FLAG_TE) != RESET)
group-onsemi	0:098463de4c5d	1124	{
group-onsemi	0:098463de4c5d	1125	if ((crflags & DMA2D_IT_TE) != RESET)
group-onsemi	0:098463de4c5d	1126	{
group-onsemi	0:098463de4c5d	1127	/* Disable the transfer Error interrupt */
group-onsemi	0:098463de4c5d	1128	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
group-onsemi	0:098463de4c5d	1129
group-onsemi	0:098463de4c5d	1130	/* Update error code */
group-onsemi	0:098463de4c5d	1131	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
group-onsemi	0:098463de4c5d	1132
group-onsemi	0:098463de4c5d	1133	/* Clear the transfer error flag */
group-onsemi	0:098463de4c5d	1134	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
group-onsemi	0:098463de4c5d	1135
group-onsemi	0:098463de4c5d	1136	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1137	hdma2d->State = HAL_DMA2D_STATE_ERROR;
group-onsemi	0:098463de4c5d	1138
group-onsemi	0:098463de4c5d	1139	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1140	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1141
group-onsemi	0:098463de4c5d	1142	if(hdma2d->XferErrorCallback != NULL)
group-onsemi	0:098463de4c5d	1143	{
group-onsemi	0:098463de4c5d	1144	/* Transfer error Callback */
group-onsemi	0:098463de4c5d	1145	hdma2d->XferErrorCallback(hdma2d);
group-onsemi	0:098463de4c5d	1146	}
group-onsemi	0:098463de4c5d	1147	}
group-onsemi	0:098463de4c5d	1148	}
group-onsemi	0:098463de4c5d	1149	/* Configuration Error Interrupt management **********************************/
group-onsemi	0:098463de4c5d	1150	if ((isrflags & DMA2D_FLAG_CE) != RESET)
group-onsemi	0:098463de4c5d	1151	{
group-onsemi	0:098463de4c5d	1152	if ((crflags & DMA2D_IT_CE) != RESET)
group-onsemi	0:098463de4c5d	1153	{
group-onsemi	0:098463de4c5d	1154	/* Disable the Configuration Error interrupt */
group-onsemi	0:098463de4c5d	1155	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
group-onsemi	0:098463de4c5d	1156
group-onsemi	0:098463de4c5d	1157	/* Clear the Configuration error flag */
group-onsemi	0:098463de4c5d	1158	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
group-onsemi	0:098463de4c5d	1159
group-onsemi	0:098463de4c5d	1160	/* Update error code */
group-onsemi	0:098463de4c5d	1161	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
group-onsemi	0:098463de4c5d	1162
group-onsemi	0:098463de4c5d	1163	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1164	hdma2d->State = HAL_DMA2D_STATE_ERROR;
group-onsemi	0:098463de4c5d	1165
group-onsemi	0:098463de4c5d	1166	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1167	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1168
group-onsemi	0:098463de4c5d	1169	if(hdma2d->XferErrorCallback != NULL)
group-onsemi	0:098463de4c5d	1170	{
group-onsemi	0:098463de4c5d	1171	/* Transfer error Callback */
group-onsemi	0:098463de4c5d	1172	hdma2d->XferErrorCallback(hdma2d);
group-onsemi	0:098463de4c5d	1173	}
group-onsemi	0:098463de4c5d	1174	}
group-onsemi	0:098463de4c5d	1175	}
group-onsemi	0:098463de4c5d	1176	/* CLUT access Error Interrupt management ***********************************/
group-onsemi	0:098463de4c5d	1177	if ((isrflags & DMA2D_FLAG_CAE) != RESET)
group-onsemi	0:098463de4c5d	1178	{
group-onsemi	0:098463de4c5d	1179	if ((crflags & DMA2D_IT_CAE) != RESET)
group-onsemi	0:098463de4c5d	1180	{
group-onsemi	0:098463de4c5d	1181	/* Disable the CLUT access error interrupt */
group-onsemi	0:098463de4c5d	1182	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
group-onsemi	0:098463de4c5d	1183
group-onsemi	0:098463de4c5d	1184	/* Clear the CLUT access error flag */
group-onsemi	0:098463de4c5d	1185	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
group-onsemi	0:098463de4c5d	1186
group-onsemi	0:098463de4c5d	1187	/* Update error code */
group-onsemi	0:098463de4c5d	1188	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CAE;
group-onsemi	0:098463de4c5d	1189
group-onsemi	0:098463de4c5d	1190	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1191	hdma2d->State = HAL_DMA2D_STATE_ERROR;
group-onsemi	0:098463de4c5d	1192
group-onsemi	0:098463de4c5d	1193	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1194	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1195
group-onsemi	0:098463de4c5d	1196	if(hdma2d->XferErrorCallback != NULL)
group-onsemi	0:098463de4c5d	1197	{
group-onsemi	0:098463de4c5d	1198	/* Transfer error Callback */
group-onsemi	0:098463de4c5d	1199	hdma2d->XferErrorCallback(hdma2d);
group-onsemi	0:098463de4c5d	1200	}
group-onsemi	0:098463de4c5d	1201	}
group-onsemi	0:098463de4c5d	1202	}
group-onsemi	0:098463de4c5d	1203	/* Transfer watermark Interrupt management **********************************/
group-onsemi	0:098463de4c5d	1204	if ((isrflags & DMA2D_FLAG_TW) != RESET)
group-onsemi	0:098463de4c5d	1205	{
group-onsemi	0:098463de4c5d	1206	if ((crflags & DMA2D_IT_TW) != RESET)
group-onsemi	0:098463de4c5d	1207	{
group-onsemi	0:098463de4c5d	1208	/* Disable the transfer watermark interrupt */
group-onsemi	0:098463de4c5d	1209	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
group-onsemi	0:098463de4c5d	1210
group-onsemi	0:098463de4c5d	1211	/* Clear the transfer watermark flag */
group-onsemi	0:098463de4c5d	1212	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
group-onsemi	0:098463de4c5d	1213
group-onsemi	0:098463de4c5d	1214	/* Transfer watermark Callback */
group-onsemi	0:098463de4c5d	1215	HAL_DMA2D_LineEventCallback(hdma2d);
group-onsemi	0:098463de4c5d	1216	}
group-onsemi	0:098463de4c5d	1217	}
group-onsemi	0:098463de4c5d	1218	/* Transfer Complete Interrupt management ************************************/
group-onsemi	0:098463de4c5d	1219	if ((isrflags & DMA2D_FLAG_TC) != RESET)
group-onsemi	0:098463de4c5d	1220	{
group-onsemi	0:098463de4c5d	1221	if ((crflags & DMA2D_IT_TC) != RESET)
group-onsemi	0:098463de4c5d	1222	{
group-onsemi	0:098463de4c5d	1223	/* Disable the transfer complete interrupt */
group-onsemi	0:098463de4c5d	1224	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
group-onsemi	0:098463de4c5d	1225
group-onsemi	0:098463de4c5d	1226	/* Clear the transfer complete flag */
group-onsemi	0:098463de4c5d	1227	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
group-onsemi	0:098463de4c5d	1228
group-onsemi	0:098463de4c5d	1229	/* Update error code */
group-onsemi	0:098463de4c5d	1230	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_NONE;
group-onsemi	0:098463de4c5d	1231
group-onsemi	0:098463de4c5d	1232	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1233	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1234
group-onsemi	0:098463de4c5d	1235	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1236	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1237
group-onsemi	0:098463de4c5d	1238	if(hdma2d->XferCpltCallback != NULL)
group-onsemi	0:098463de4c5d	1239	{
group-onsemi	0:098463de4c5d	1240	/* Transfer complete Callback */
group-onsemi	0:098463de4c5d	1241	hdma2d->XferCpltCallback(hdma2d);
group-onsemi	0:098463de4c5d	1242	}
group-onsemi	0:098463de4c5d	1243	}
group-onsemi	0:098463de4c5d	1244	}
group-onsemi	0:098463de4c5d	1245	/* CLUT Transfer Complete Interrupt management ******************************/
group-onsemi	0:098463de4c5d	1246	if ((isrflags & DMA2D_FLAG_CTC) != RESET)
group-onsemi	0:098463de4c5d	1247	{
group-onsemi	0:098463de4c5d	1248	if ((crflags & DMA2D_IT_CTC) != RESET)
group-onsemi	0:098463de4c5d	1249	{
group-onsemi	0:098463de4c5d	1250	/* Disable the CLUT transfer complete interrupt */
group-onsemi	0:098463de4c5d	1251	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
group-onsemi	0:098463de4c5d	1252
group-onsemi	0:098463de4c5d	1253	/* Clear the CLUT transfer complete flag */
group-onsemi	0:098463de4c5d	1254	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
group-onsemi	0:098463de4c5d	1255
group-onsemi	0:098463de4c5d	1256	/* Update error code */
group-onsemi	0:098463de4c5d	1257	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_NONE;
group-onsemi	0:098463de4c5d	1258
group-onsemi	0:098463de4c5d	1259	/* Change DMA2D state */
group-onsemi	0:098463de4c5d	1260	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1261
group-onsemi	0:098463de4c5d	1262	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1263	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1264
group-onsemi	0:098463de4c5d	1265	/* CLUT Transfer complete Callback */
group-onsemi	0:098463de4c5d	1266	HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
group-onsemi	0:098463de4c5d	1267	}
group-onsemi	0:098463de4c5d	1268	}
group-onsemi	0:098463de4c5d	1269	}
group-onsemi	0:098463de4c5d	1270
group-onsemi	0:098463de4c5d	1271	/**
group-onsemi	0:098463de4c5d	1272	* @brief Transfer watermark callback.
group-onsemi	0:098463de4c5d	1273	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1274	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1275	* @retval None
group-onsemi	0:098463de4c5d	1276	*/
group-onsemi	0:098463de4c5d	1277	__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1278	{
group-onsemi	0:098463de4c5d	1279	/* Prevent unused argument(s) compilation warning */
group-onsemi	0:098463de4c5d	1280	UNUSED(hdma2d);
group-onsemi	0:098463de4c5d	1281
group-onsemi	0:098463de4c5d	1282	/* NOTE : This function should not be modified; when the callback is needed,
group-onsemi	0:098463de4c5d	1283	the HAL_DMA2D_LineEventCallback can be implemented in the user file.
group-onsemi	0:098463de4c5d	1284	*/
group-onsemi	0:098463de4c5d	1285	}
group-onsemi	0:098463de4c5d	1286
group-onsemi	0:098463de4c5d	1287	/**
group-onsemi	0:098463de4c5d	1288	* @brief CLUT Transfer Complete callback.
group-onsemi	0:098463de4c5d	1289	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1290	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1291	* @retval None
group-onsemi	0:098463de4c5d	1292	*/
group-onsemi	0:098463de4c5d	1293	__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1294	{
group-onsemi	0:098463de4c5d	1295	/* Prevent unused argument(s) compilation warning */
group-onsemi	0:098463de4c5d	1296	UNUSED(hdma2d);
group-onsemi	0:098463de4c5d	1297
group-onsemi	0:098463de4c5d	1298	/* NOTE : This function should not be modified; when the callback is needed,
group-onsemi	0:098463de4c5d	1299	the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
group-onsemi	0:098463de4c5d	1300	*/
group-onsemi	0:098463de4c5d	1301	}
group-onsemi	0:098463de4c5d	1302
group-onsemi	0:098463de4c5d	1303	/**
group-onsemi	0:098463de4c5d	1304	* @}
group-onsemi	0:098463de4c5d	1305	*/
group-onsemi	0:098463de4c5d	1306
group-onsemi	0:098463de4c5d	1307	/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
group-onsemi	0:098463de4c5d	1308	* @brief Peripheral Control functions
group-onsemi	0:098463de4c5d	1309	*
group-onsemi	0:098463de4c5d	1310	@verbatim
group-onsemi	0:098463de4c5d	1311	===============================================================================
group-onsemi	0:098463de4c5d	1312	##### Peripheral Control functions #####
group-onsemi	0:098463de4c5d	1313	===============================================================================
group-onsemi	0:098463de4c5d	1314	[..] This section provides functions allowing to:
group-onsemi	0:098463de4c5d	1315	(+) Configure the DMA2D foreground or background layer parameters.
group-onsemi	0:098463de4c5d	1316	(+) Configure the DMA2D CLUT transfer.
group-onsemi	0:098463de4c5d	1317	(+) Configure the line watermark
group-onsemi	0:098463de4c5d	1318	(+) Configure the dead time value.
group-onsemi	0:098463de4c5d	1319	(+) Enable or disable the dead time value functionality.
group-onsemi	0:098463de4c5d	1320
group-onsemi	0:098463de4c5d	1321	@endverbatim
group-onsemi	0:098463de4c5d	1322	* @{
group-onsemi	0:098463de4c5d	1323	*/
group-onsemi	0:098463de4c5d	1324
group-onsemi	0:098463de4c5d	1325	/**
group-onsemi	0:098463de4c5d	1326	* @brief Configure the DMA2D Layer according to the specified
group-onsemi	0:098463de4c5d	1327	* parameters in the DMA2D_InitTypeDef and create the associated handle.
group-onsemi	0:098463de4c5d	1328	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1329	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1330	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	1331	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	1332	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	1333	* @retval HAL status
group-onsemi	0:098463de4c5d	1334	*/
group-onsemi	0:098463de4c5d	1335	HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	1336	{
group-onsemi	0:098463de4c5d	1337	DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
group-onsemi	0:098463de4c5d	1338	uint32_t regValue = 0U;
group-onsemi	0:098463de4c5d	1339
group-onsemi	0:098463de4c5d	1340	/* Check the parameters */
group-onsemi	0:098463de4c5d	1341	assert_param(IS_DMA2D_LAYER(LayerIdx));
group-onsemi	0:098463de4c5d	1342	assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
group-onsemi	0:098463de4c5d	1343	if(hdma2d->Init.Mode != DMA2D_R2M)
group-onsemi	0:098463de4c5d	1344	{
group-onsemi	0:098463de4c5d	1345	assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
group-onsemi	0:098463de4c5d	1346	if(hdma2d->Init.Mode != DMA2D_M2M)
group-onsemi	0:098463de4c5d	1347	{
group-onsemi	0:098463de4c5d	1348	assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
group-onsemi	0:098463de4c5d	1349	}
group-onsemi	0:098463de4c5d	1350	}
group-onsemi	0:098463de4c5d	1351
group-onsemi	0:098463de4c5d	1352	/* Process locked */
group-onsemi	0:098463de4c5d	1353	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	1354
group-onsemi	0:098463de4c5d	1355	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	1356	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	1357
group-onsemi	0:098463de4c5d	1358	/* DMA2D BGPFCR register configuration -----------------------------------*/
group-onsemi	0:098463de4c5d	1359	/* Prepare the value to be written to the BGPFCCR register */
group-onsemi	0:098463de4c5d	1360
group-onsemi	0:098463de4c5d	1361	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
group-onsemi	0:098463de4c5d	1362	{
group-onsemi	0:098463de4c5d	1363	regValue = pLayerCfg->InputColorMode \| (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) \| (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
group-onsemi	0:098463de4c5d	1364	}
group-onsemi	0:098463de4c5d	1365	else
group-onsemi	0:098463de4c5d	1366	{
group-onsemi	0:098463de4c5d	1367	regValue = pLayerCfg->InputColorMode \| (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) \| (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
group-onsemi	0:098463de4c5d	1368	}
group-onsemi	0:098463de4c5d	1369
group-onsemi	0:098463de4c5d	1370	/* Configure the background DMA2D layer */
group-onsemi	0:098463de4c5d	1371	if(LayerIdx == 0)
group-onsemi	0:098463de4c5d	1372	{
group-onsemi	0:098463de4c5d	1373	/* Write DMA2D BGPFCCR register */
group-onsemi	0:098463de4c5d	1374	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM \| DMA2D_BGPFCCR_AM \| DMA2D_BGPFCCR_ALPHA), regValue);
group-onsemi	0:098463de4c5d	1375
group-onsemi	0:098463de4c5d	1376	/* DMA2D BGOR register configuration -------------------------------------*/
group-onsemi	0:098463de4c5d	1377	WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
group-onsemi	0:098463de4c5d	1378
group-onsemi	0:098463de4c5d	1379	/* DMA2D BGCOLR register configuration -------------------------------------*/
group-onsemi	0:098463de4c5d	1380	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
group-onsemi	0:098463de4c5d	1381	{
group-onsemi	0:098463de4c5d	1382	WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE\|DMA2D_BGCOLR_GREEN\|DMA2D_BGCOLR_RED));
group-onsemi	0:098463de4c5d	1383	}
group-onsemi	0:098463de4c5d	1384	}
group-onsemi	0:098463de4c5d	1385	/* Configure the foreground DMA2D layer */
group-onsemi	0:098463de4c5d	1386	else
group-onsemi	0:098463de4c5d	1387	{
group-onsemi	0:098463de4c5d	1388	/* Write DMA2D FGPFCCR register */
group-onsemi	0:098463de4c5d	1389	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM \| DMA2D_BGPFCCR_AM \| DMA2D_BGPFCCR_ALPHA), regValue);
group-onsemi	0:098463de4c5d	1390
group-onsemi	0:098463de4c5d	1391	/* DMA2D FGOR register configuration -------------------------------------*/
group-onsemi	0:098463de4c5d	1392	WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
group-onsemi	0:098463de4c5d	1393
group-onsemi	0:098463de4c5d	1394	/* DMA2D FGCOLR register configuration -------------------------------------*/
group-onsemi	0:098463de4c5d	1395	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
group-onsemi	0:098463de4c5d	1396	{
group-onsemi	0:098463de4c5d	1397	WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE\|DMA2D_FGCOLR_GREEN\|DMA2D_FGCOLR_RED));
group-onsemi	0:098463de4c5d	1398	}
group-onsemi	0:098463de4c5d	1399	}
group-onsemi	0:098463de4c5d	1400	/* Initialize the DMA2D state*/
group-onsemi	0:098463de4c5d	1401	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1402
group-onsemi	0:098463de4c5d	1403	/* Process unlocked */
group-onsemi	0:098463de4c5d	1404	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1405
group-onsemi	0:098463de4c5d	1406	return HAL_OK;
group-onsemi	0:098463de4c5d	1407	}
group-onsemi	0:098463de4c5d	1408
group-onsemi	0:098463de4c5d	1409	/**
group-onsemi	0:098463de4c5d	1410	* @brief Configure the DMA2D CLUT Transfer.
group-onsemi	0:098463de4c5d	1411	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1412	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1413	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
group-onsemi	0:098463de4c5d	1414	* the configuration information for the color look up table.
group-onsemi	0:098463de4c5d	1415	* @param LayerIdx: DMA2D Layer index.
group-onsemi	0:098463de4c5d	1416	* This parameter can be one of the following values:
group-onsemi	0:098463de4c5d	1417	* 0(background) / 1(foreground)
group-onsemi	0:098463de4c5d	1418	* @retval HAL status
group-onsemi	0:098463de4c5d	1419	*/
group-onsemi	0:098463de4c5d	1420	HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
group-onsemi	0:098463de4c5d	1421	{
group-onsemi	0:098463de4c5d	1422	/* Check the parameters */
group-onsemi	0:098463de4c5d	1423	assert_param(IS_DMA2D_LAYER(LayerIdx));
group-onsemi	0:098463de4c5d	1424	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
group-onsemi	0:098463de4c5d	1425	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
group-onsemi	0:098463de4c5d	1426
group-onsemi	0:098463de4c5d	1427	/* Process locked */
group-onsemi	0:098463de4c5d	1428	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	1429
group-onsemi	0:098463de4c5d	1430	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	1431	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	1432
group-onsemi	0:098463de4c5d	1433	/* Configure the CLUT of the background DMA2D layer */
group-onsemi	0:098463de4c5d	1434	if(LayerIdx == 0U)
group-onsemi	0:098463de4c5d	1435	{
group-onsemi	0:098463de4c5d	1436	/* Write background CLUT memory address */
group-onsemi	0:098463de4c5d	1437	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
group-onsemi	0:098463de4c5d	1438
group-onsemi	0:098463de4c5d	1439	/* Write background CLUT size and CLUT color mode */
group-onsemi	0:098463de4c5d	1440	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
group-onsemi	0:098463de4c5d	1441	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
group-onsemi	0:098463de4c5d	1442	}
group-onsemi	0:098463de4c5d	1443	/* Configure the CLUT of the foreground DMA2D layer */
group-onsemi	0:098463de4c5d	1444	else
group-onsemi	0:098463de4c5d	1445	{
group-onsemi	0:098463de4c5d	1446	/* Write foreground CLUT memory address */
group-onsemi	0:098463de4c5d	1447	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
group-onsemi	0:098463de4c5d	1448
group-onsemi	0:098463de4c5d	1449	/* Write foreground CLUT size and CLUT color mode */
group-onsemi	0:098463de4c5d	1450	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
group-onsemi	0:098463de4c5d	1451	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
group-onsemi	0:098463de4c5d	1452	}
group-onsemi	0:098463de4c5d	1453
group-onsemi	0:098463de4c5d	1454	/* Set the DMA2D state to Ready */
group-onsemi	0:098463de4c5d	1455	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1456
group-onsemi	0:098463de4c5d	1457	/* Process unlocked */
group-onsemi	0:098463de4c5d	1458	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1459
group-onsemi	0:098463de4c5d	1460	return HAL_OK;
group-onsemi	0:098463de4c5d	1461	}
group-onsemi	0:098463de4c5d	1462
group-onsemi	0:098463de4c5d	1463	/**
group-onsemi	0:098463de4c5d	1464	* @brief Configure the line watermark.
group-onsemi	0:098463de4c5d	1465	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1466	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1467	* @param Line: Line Watermark configuration (maximum 16-bit long value expected).
group-onsemi	0:098463de4c5d	1468	* @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
group-onsemi	0:098463de4c5d	1469	* @note The transfer watermark interrupt is disabled once it has occurred.
group-onsemi	0:098463de4c5d	1470	* @retval HAL status
group-onsemi	0:098463de4c5d	1471	*/
group-onsemi	0:098463de4c5d	1472
group-onsemi	0:098463de4c5d	1473	HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
group-onsemi	0:098463de4c5d	1474	{
group-onsemi	0:098463de4c5d	1475	/* Check the parameters */
group-onsemi	0:098463de4c5d	1476	assert_param(IS_DMA2D_LINEWATERMARK(Line));
group-onsemi	0:098463de4c5d	1477
group-onsemi	0:098463de4c5d	1478	if (Line > DMA2D_LWR_LW)
group-onsemi	0:098463de4c5d	1479	{
group-onsemi	0:098463de4c5d	1480	return HAL_ERROR;
group-onsemi	0:098463de4c5d	1481	}
group-onsemi	0:098463de4c5d	1482	else
group-onsemi	0:098463de4c5d	1483	{
group-onsemi	0:098463de4c5d	1484	/* Process locked */
group-onsemi	0:098463de4c5d	1485	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	1486
group-onsemi	0:098463de4c5d	1487	/* Change DMA2D peripheral state */
group-onsemi	0:098463de4c5d	1488	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	1489
group-onsemi	0:098463de4c5d	1490	/* Sets the Line watermark configuration */
group-onsemi	0:098463de4c5d	1491	WRITE_REG(hdma2d->Instance->LWR, Line);
group-onsemi	0:098463de4c5d	1492
group-onsemi	0:098463de4c5d	1493	/* Enable the Line interrupt */
group-onsemi	0:098463de4c5d	1494	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
group-onsemi	0:098463de4c5d	1495
group-onsemi	0:098463de4c5d	1496	/* Initialize the DMA2D state */
group-onsemi	0:098463de4c5d	1497	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1498
group-onsemi	0:098463de4c5d	1499	/* Process unlocked */
group-onsemi	0:098463de4c5d	1500	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1501
group-onsemi	0:098463de4c5d	1502	return HAL_OK;
group-onsemi	0:098463de4c5d	1503	}
group-onsemi	0:098463de4c5d	1504	}
group-onsemi	0:098463de4c5d	1505
group-onsemi	0:098463de4c5d	1506	/**
group-onsemi	0:098463de4c5d	1507	* @brief Enable DMA2D dead time feature.
group-onsemi	0:098463de4c5d	1508	* @param hdma2d: DMA2D handle.
group-onsemi	0:098463de4c5d	1509	* @retval HAL status
group-onsemi	0:098463de4c5d	1510	*/
group-onsemi	0:098463de4c5d	1511	HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1512	{
group-onsemi	0:098463de4c5d	1513	/* Process Locked */
group-onsemi	0:098463de4c5d	1514	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	1515
group-onsemi	0:098463de4c5d	1516	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	1517
group-onsemi	0:098463de4c5d	1518	/* Set DMA2D_AMTCR EN bit */
group-onsemi	0:098463de4c5d	1519	SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
group-onsemi	0:098463de4c5d	1520
group-onsemi	0:098463de4c5d	1521	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1522
group-onsemi	0:098463de4c5d	1523	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1524	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1525
group-onsemi	0:098463de4c5d	1526	return HAL_OK;
group-onsemi	0:098463de4c5d	1527	}
group-onsemi	0:098463de4c5d	1528
group-onsemi	0:098463de4c5d	1529	/**
group-onsemi	0:098463de4c5d	1530	* @brief Disable DMA2D dead time feature.
group-onsemi	0:098463de4c5d	1531	* @param hdma2d: DMA2D handle.
group-onsemi	0:098463de4c5d	1532	* @retval HAL status
group-onsemi	0:098463de4c5d	1533	*/
group-onsemi	0:098463de4c5d	1534	HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1535	{
group-onsemi	0:098463de4c5d	1536	/* Process Locked */
group-onsemi	0:098463de4c5d	1537	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	1538
group-onsemi	0:098463de4c5d	1539	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	1540
group-onsemi	0:098463de4c5d	1541	/* Clear DMA2D_AMTCR EN bit */
group-onsemi	0:098463de4c5d	1542	CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
group-onsemi	0:098463de4c5d	1543
group-onsemi	0:098463de4c5d	1544	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1545
group-onsemi	0:098463de4c5d	1546	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1547	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1548
group-onsemi	0:098463de4c5d	1549	return HAL_OK;
group-onsemi	0:098463de4c5d	1550	}
group-onsemi	0:098463de4c5d	1551
group-onsemi	0:098463de4c5d	1552	/**
group-onsemi	0:098463de4c5d	1553	* @brief Configure dead time.
group-onsemi	0:098463de4c5d	1554	* @note The dead time value represents the guaranteed minimum number of cycles between
group-onsemi	0:098463de4c5d	1555	* two consecutive transactions on the AHB bus.
group-onsemi	0:098463de4c5d	1556	* @param hdma2d: DMA2D handle.
group-onsemi	0:098463de4c5d	1557	* @param DeadTime: dead time value.
group-onsemi	0:098463de4c5d	1558	* @retval HAL status
group-onsemi	0:098463de4c5d	1559	*/
group-onsemi	0:098463de4c5d	1560	HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
group-onsemi	0:098463de4c5d	1561	{
group-onsemi	0:098463de4c5d	1562	/* Process Locked */
group-onsemi	0:098463de4c5d	1563	__HAL_LOCK(hdma2d);
group-onsemi	0:098463de4c5d	1564
group-onsemi	0:098463de4c5d	1565	hdma2d->State = HAL_DMA2D_STATE_BUSY;
group-onsemi	0:098463de4c5d	1566
group-onsemi	0:098463de4c5d	1567	/* Set DMA2D_AMTCR DT field */
group-onsemi	0:098463de4c5d	1568	MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
group-onsemi	0:098463de4c5d	1569
group-onsemi	0:098463de4c5d	1570	hdma2d->State = HAL_DMA2D_STATE_READY;
group-onsemi	0:098463de4c5d	1571
group-onsemi	0:098463de4c5d	1572	/* Process Unlocked */
group-onsemi	0:098463de4c5d	1573	__HAL_UNLOCK(hdma2d);
group-onsemi	0:098463de4c5d	1574
group-onsemi	0:098463de4c5d	1575	return HAL_OK;
group-onsemi	0:098463de4c5d	1576	}
group-onsemi	0:098463de4c5d	1577
group-onsemi	0:098463de4c5d	1578	/**
group-onsemi	0:098463de4c5d	1579	* @}
group-onsemi	0:098463de4c5d	1580	*/
group-onsemi	0:098463de4c5d	1581
group-onsemi	0:098463de4c5d	1582	/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
group-onsemi	0:098463de4c5d	1583	* @brief Peripheral State functions
group-onsemi	0:098463de4c5d	1584	*
group-onsemi	0:098463de4c5d	1585	@verbatim
group-onsemi	0:098463de4c5d	1586	===============================================================================
group-onsemi	0:098463de4c5d	1587	##### Peripheral State and Errors functions #####
group-onsemi	0:098463de4c5d	1588	===============================================================================
group-onsemi	0:098463de4c5d	1589	[..]
group-onsemi	0:098463de4c5d	1590	This subsection provides functions allowing to :
group-onsemi	0:098463de4c5d	1591	(+) Get the DMA2D state
group-onsemi	0:098463de4c5d	1592	(+) Get the DMA2D error code
group-onsemi	0:098463de4c5d	1593
group-onsemi	0:098463de4c5d	1594	@endverbatim
group-onsemi	0:098463de4c5d	1595	* @{
group-onsemi	0:098463de4c5d	1596	*/
group-onsemi	0:098463de4c5d	1597
group-onsemi	0:098463de4c5d	1598	/**
group-onsemi	0:098463de4c5d	1599	* @brief Return the DMA2D state
group-onsemi	0:098463de4c5d	1600	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1601	* the configuration information for the DMA2D.
group-onsemi	0:098463de4c5d	1602	* @retval HAL state
group-onsemi	0:098463de4c5d	1603	*/
group-onsemi	0:098463de4c5d	1604	HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1605	{
group-onsemi	0:098463de4c5d	1606	return hdma2d->State;
group-onsemi	0:098463de4c5d	1607	}
group-onsemi	0:098463de4c5d	1608
group-onsemi	0:098463de4c5d	1609	/**
group-onsemi	0:098463de4c5d	1610	* @brief Return the DMA2D error code
group-onsemi	0:098463de4c5d	1611	* @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1612	* the configuration information for DMA2D.
group-onsemi	0:098463de4c5d	1613	* @retval DMA2D Error Code
group-onsemi	0:098463de4c5d	1614	*/
group-onsemi	0:098463de4c5d	1615	uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
group-onsemi	0:098463de4c5d	1616	{
group-onsemi	0:098463de4c5d	1617	return hdma2d->ErrorCode;
group-onsemi	0:098463de4c5d	1618	}
group-onsemi	0:098463de4c5d	1619
group-onsemi	0:098463de4c5d	1620	/**
group-onsemi	0:098463de4c5d	1621	* @}
group-onsemi	0:098463de4c5d	1622	*/
group-onsemi	0:098463de4c5d	1623
group-onsemi	0:098463de4c5d	1624	/**
group-onsemi	0:098463de4c5d	1625	* @}
group-onsemi	0:098463de4c5d	1626	*/
group-onsemi	0:098463de4c5d	1627
group-onsemi	0:098463de4c5d	1628	/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
group-onsemi	0:098463de4c5d	1629	* @{
group-onsemi	0:098463de4c5d	1630	*/
group-onsemi	0:098463de4c5d	1631
group-onsemi	0:098463de4c5d	1632	/**
group-onsemi	0:098463de4c5d	1633	* @brief Set the DMA2D transfer parameters.
group-onsemi	0:098463de4c5d	1634	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
group-onsemi	0:098463de4c5d	1635	* the configuration information for the specified DMA2D.
group-onsemi	0:098463de4c5d	1636	* @param pdata: The source memory Buffer address
group-onsemi	0:098463de4c5d	1637	* @param DstAddress: The destination memory Buffer address
group-onsemi	0:098463de4c5d	1638	* @param Width: The width of data to be transferred from source to destination.
group-onsemi	0:098463de4c5d	1639	* @param Height: The height of data to be transferred from source to destination.
group-onsemi	0:098463de4c5d	1640	* @retval HAL status
group-onsemi	0:098463de4c5d	1641	*/
group-onsemi	0:098463de4c5d	1642	static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
group-onsemi	0:098463de4c5d	1643	{
group-onsemi	0:098463de4c5d	1644	uint32_t tmp = 0U;
group-onsemi	0:098463de4c5d	1645	uint32_t tmp1 = 0U;
group-onsemi	0:098463de4c5d	1646	uint32_t tmp2 = 0U;
group-onsemi	0:098463de4c5d	1647	uint32_t tmp3 = 0U;
group-onsemi	0:098463de4c5d	1648	uint32_t tmp4 = 0U;
group-onsemi	0:098463de4c5d	1649
group-onsemi	0:098463de4c5d	1650	/* Configure DMA2D data size */
group-onsemi	0:098463de4c5d	1651	MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL\|DMA2D_NLR_PL), (Height\| (Width << DMA2D_POSITION_NLR_PL)));
group-onsemi	0:098463de4c5d	1652
group-onsemi	0:098463de4c5d	1653	/* Configure DMA2D destination address */
group-onsemi	0:098463de4c5d	1654	WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
group-onsemi	0:098463de4c5d	1655
group-onsemi	0:098463de4c5d	1656	/* Register to memory DMA2D mode selected */
group-onsemi	0:098463de4c5d	1657	if (hdma2d->Init.Mode == DMA2D_R2M)
group-onsemi	0:098463de4c5d	1658	{
group-onsemi	0:098463de4c5d	1659	tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
group-onsemi	0:098463de4c5d	1660	tmp2 = pdata & DMA2D_OCOLR_RED_1;
group-onsemi	0:098463de4c5d	1661	tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
group-onsemi	0:098463de4c5d	1662	tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
group-onsemi	0:098463de4c5d	1663
group-onsemi	0:098463de4c5d	1664	/* Prepare the value to be written to the OCOLR register according to the color mode */
group-onsemi	0:098463de4c5d	1665	if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
group-onsemi	0:098463de4c5d	1666	{
group-onsemi	0:098463de4c5d	1667	tmp = (tmp3 \| tmp2 \| tmp1\| tmp4);
group-onsemi	0:098463de4c5d	1668	}
group-onsemi	0:098463de4c5d	1669	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
group-onsemi	0:098463de4c5d	1670	{
group-onsemi	0:098463de4c5d	1671	tmp = (tmp3 \| tmp2 \| tmp4);
group-onsemi	0:098463de4c5d	1672	}
group-onsemi	0:098463de4c5d	1673	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
group-onsemi	0:098463de4c5d	1674	{
group-onsemi	0:098463de4c5d	1675	tmp2 = (tmp2 >> 19U);
group-onsemi	0:098463de4c5d	1676	tmp3 = (tmp3 >> 10U);
group-onsemi	0:098463de4c5d	1677	tmp4 = (tmp4 >> 3U);
group-onsemi	0:098463de4c5d	1678	tmp = ((tmp3 << 5U) \| (tmp2 << 11U) \| tmp4);
group-onsemi	0:098463de4c5d	1679	}
group-onsemi	0:098463de4c5d	1680	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
group-onsemi	0:098463de4c5d	1681	{
group-onsemi	0:098463de4c5d	1682	tmp1 = (tmp1 >> 31U);
group-onsemi	0:098463de4c5d	1683	tmp2 = (tmp2 >> 19U);
group-onsemi	0:098463de4c5d	1684	tmp3 = (tmp3 >> 11U);
group-onsemi	0:098463de4c5d	1685	tmp4 = (tmp4 >> 3U);
group-onsemi	0:098463de4c5d	1686	tmp = ((tmp3 << 5U) \| (tmp2 << 10U) \| (tmp1 << 15U) \| tmp4);
group-onsemi	0:098463de4c5d	1687	}
group-onsemi	0:098463de4c5d	1688	else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
group-onsemi	0:098463de4c5d	1689	{
group-onsemi	0:098463de4c5d	1690	tmp1 = (tmp1 >> 28U);
group-onsemi	0:098463de4c5d	1691	tmp2 = (tmp2 >> 20U);
group-onsemi	0:098463de4c5d	1692	tmp3 = (tmp3 >> 12U);
group-onsemi	0:098463de4c5d	1693	tmp4 = (tmp4 >> 4U);
group-onsemi	0:098463de4c5d	1694	tmp = ((tmp3 << 4U) \| (tmp2 << 8U) \| (tmp1 << 12U) \| tmp4);
group-onsemi	0:098463de4c5d	1695	}
group-onsemi	0:098463de4c5d	1696	/* Write to DMA2D OCOLR register */
group-onsemi	0:098463de4c5d	1697	WRITE_REG(hdma2d->Instance->OCOLR, tmp);
group-onsemi	0:098463de4c5d	1698	}
group-onsemi	0:098463de4c5d	1699	else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
group-onsemi	0:098463de4c5d	1700	{
group-onsemi	0:098463de4c5d	1701	/* Configure DMA2D source address */
group-onsemi	0:098463de4c5d	1702	WRITE_REG(hdma2d->Instance->FGMAR, pdata);
group-onsemi	0:098463de4c5d	1703	}
group-onsemi	0:098463de4c5d	1704	}
group-onsemi	0:098463de4c5d	1705
group-onsemi	0:098463de4c5d	1706	/**
group-onsemi	0:098463de4c5d	1707	* @}
group-onsemi	0:098463de4c5d	1708	*/
group-onsemi	0:098463de4c5d	1709	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
group-onsemi	0:098463de4c5d	1710	#endif /* HAL_DMA2D_MODULE_ENABLED */
group-onsemi	0:098463de4c5d	1711	/**
group-onsemi	0:098463de4c5d	1712	* @}
group-onsemi	0:098463de4c5d	1713	*/
group-onsemi	0:098463de4c5d	1714
group-onsemi	0:098463de4c5d	1715	/**
group-onsemi	0:098463de4c5d	1716	* @}
group-onsemi	0:098463de4c5d	1717	*/
group-onsemi	0:098463de4c5d	1718
group-onsemi	0:098463de4c5d	1719	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	25 Jan 2017
Imports:	32
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