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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************/
group-onsemi 0:098463de4c5d 2 /**
group-onsemi 0:098463de4c5d 3 * @file NCS36510.h
group-onsemi 0:098463de4c5d 4 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
group-onsemi 0:098463de4c5d 5 * for CM3 Device Series
group-onsemi 0:098463de4c5d 6 * @version V1.05
group-onsemi 0:098463de4c5d 7 * @date 26. July 2011
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 * @note
group-onsemi 0:098463de4c5d 10 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
group-onsemi 0:098463de4c5d 11 *
group-onsemi 0:098463de4c5d 12 * @par
group-onsemi 0:098463de4c5d 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
group-onsemi 0:098463de4c5d 14 * processor based microcontrollers. This file can be freely distributed
group-onsemi 0:098463de4c5d 15 * within development tools that are supporting such ARM based processors.
group-onsemi 0:098463de4c5d 16 *
group-onsemi 0:098463de4c5d 17 * @par
group-onsemi 0:098463de4c5d 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
group-onsemi 0:098463de4c5d 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
group-onsemi 0:098463de4c5d 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
group-onsemi 0:098463de4c5d 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
group-onsemi 0:098463de4c5d 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 ******************************************************************************/
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 #ifndef ARMCM3_H
group-onsemi 0:098463de4c5d 27 #define ARMCM3_H
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 /**
group-onsemi 0:098463de4c5d 30 * ==========================================================================
group-onsemi 0:098463de4c5d 31 * ---------- Interrupt Number Definition -----------------------------------
group-onsemi 0:098463de4c5d 32 * ==========================================================================
group-onsemi 0:098463de4c5d 33 */
group-onsemi 0:098463de4c5d 34 typedef enum IRQn {
group-onsemi 0:098463de4c5d 35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
group-onsemi 0:098463de4c5d 36 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
group-onsemi 0:098463de4c5d 37 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
group-onsemi 0:098463de4c5d 38 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
group-onsemi 0:098463de4c5d 39 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
group-onsemi 0:098463de4c5d 40 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
group-onsemi 0:098463de4c5d 41 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
group-onsemi 0:098463de4c5d 42 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
group-onsemi 0:098463de4c5d 43 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
group-onsemi 0:098463de4c5d 44 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /****** ARMCM3 specific Interrupt Numbers ********************************************************/
group-onsemi 0:098463de4c5d 47 Tim0_IRQn = 0,
group-onsemi 0:098463de4c5d 48 Tim1_IRQn = 1,
group-onsemi 0:098463de4c5d 49 Tim2_IRQn = 2,
group-onsemi 0:098463de4c5d 50 Uart1_IRQn = 3,
group-onsemi 0:098463de4c5d 51 Spi_IRQn = 4,
group-onsemi 0:098463de4c5d 52 I2C_IRQn = 5,
group-onsemi 0:098463de4c5d 53 Gpio_IRQn = 6,
group-onsemi 0:098463de4c5d 54 Rtc_IRQn = 7,
group-onsemi 0:098463de4c5d 55 Flash_IRQn = 8,
group-onsemi 0:098463de4c5d 56 MacHw_IRQn = 9,
group-onsemi 0:098463de4c5d 57 Aes_IRQn = 10,
group-onsemi 0:098463de4c5d 58 Adc_IRQn = 11,
group-onsemi 0:098463de4c5d 59 ClockCal_IRQn = 12,
group-onsemi 0:098463de4c5d 60 Uart2_IRQn = 13,
group-onsemi 0:098463de4c5d 61 Uvi_IRQn = 14,
group-onsemi 0:098463de4c5d 62 Dma_IRQn = 15,
group-onsemi 0:098463de4c5d 63 DbgPwrUp_IRQn = 16,
group-onsemi 0:098463de4c5d 64 Spi2_IRQn = 17,
group-onsemi 0:098463de4c5d 65 I2C2_IRQn = 18,
group-onsemi 0:098463de4c5d 66 FVDDHComp_IRQn = 19
group-onsemi 0:098463de4c5d 67 } IRQn_Type;
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 /**
group-onsemi 0:098463de4c5d 70 * ==========================================================================
group-onsemi 0:098463de4c5d 71 * ----------- Processor and Core Peripheral Section ------------------------
group-onsemi 0:098463de4c5d 72 * ==========================================================================
group-onsemi 0:098463de4c5d 73 */
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 /** Configuration of the Cortex-M3 Processor and Core Peripherals */
group-onsemi 0:098463de4c5d 76 #define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
group-onsemi 0:098463de4c5d 77 #define __MPU_PRESENT 1 /*!< MPU present or not */
group-onsemi 0:098463de4c5d 78 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
group-onsemi 0:098463de4c5d 79 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
group-onsemi 0:098463de4c5d 82 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
group-onsemi 0:098463de4c5d 83 //#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 //#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
group-onsemi 0:098463de4c5d 86 //#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
group-onsemi 0:098463de4c5d 89 #include "system_NCS36510.h" /* System Header */
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 #endif /* ARMCM3_H */