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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file clock_map.h
group-onsemi 0:098463de4c5d 4 * @brief CLOCK hw module register map
group-onsemi 0:098463de4c5d 5 * @internal
group-onsemi 0:098463de4c5d 6 * @author ON Semiconductor
group-onsemi 0:098463de4c5d 7 * $Rev: 2848 $
group-onsemi 0:098463de4c5d 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
group-onsemi 0:098463de4c5d 9 ******************************************************************************
group-onsemi 0:098463de4c5d 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
group-onsemi 0:098463de4c5d 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
group-onsemi 0:098463de4c5d 12 * under limited terms and conditions. The terms and conditions pertaining to the software
group-onsemi 0:098463de4c5d 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
group-onsemi 0:098463de4c5d 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
group-onsemi 0:098463de4c5d 15 * if applicable the software license agreement. Do not use this software and/or
group-onsemi 0:098463de4c5d 16 * documentation unless you have carefully read and you agree to the limited terms and
group-onsemi 0:098463de4c5d 17 * conditions. By using this software and/or documentation, you agree to the limited
group-onsemi 0:098463de4c5d 18 * terms and conditions.
group-onsemi 0:098463de4c5d 19 *
group-onsemi 0:098463de4c5d 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
group-onsemi 0:098463de4c5d 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
group-onsemi 0:098463de4c5d 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
group-onsemi 0:098463de4c5d 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
group-onsemi 0:098463de4c5d 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
group-onsemi 0:098463de4c5d 25 * @endinternal
group-onsemi 0:098463de4c5d 26 *
group-onsemi 0:098463de4c5d 27 * @ingroup clock
group-onsemi 0:098463de4c5d 28 *
group-onsemi 0:098463de4c5d 29 * @details
group-onsemi 0:098463de4c5d 30 */
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 #ifndef CLOCK_MAP_H_
group-onsemi 0:098463de4c5d 33 #define CLOCK_MAP_H_
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 /*************************************************************************************************
group-onsemi 0:098463de4c5d 36 * *
group-onsemi 0:098463de4c5d 37 * Header files *
group-onsemi 0:098463de4c5d 38 * *
group-onsemi 0:098463de4c5d 39 *************************************************************************************************/
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include "architecture.h"
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /**************************************************************************************************
group-onsemi 0:098463de4c5d 44 * *
group-onsemi 0:098463de4c5d 45 * Type definitions *
group-onsemi 0:098463de4c5d 46 * *
group-onsemi 0:098463de4c5d 47 **************************************************************************************************/
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /** Clock control HW structure overlay */
group-onsemi 0:098463de4c5d 50 typedef struct {
group-onsemi 0:098463de4c5d 51 union {
group-onsemi 0:098463de4c5d 52 struct {
group-onsemi 0:098463de4c5d 53 __IO uint32_t OSC_SEL:1;
group-onsemi 0:098463de4c5d 54 __IO uint32_t PAD0:1;
group-onsemi 0:098463de4c5d 55 __IO uint32_t CAL32K:1;
group-onsemi 0:098463de4c5d 56 __IO uint32_t CAL32M:1;
group-onsemi 0:098463de4c5d 57 __IO uint32_t RTCEN:1;
group-onsemi 0:098463de4c5d 58 } BITS;
group-onsemi 0:098463de4c5d 59 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 60 } CCR; /**< 0x4001B000 Clock control register */
group-onsemi 0:098463de4c5d 61 union {
group-onsemi 0:098463de4c5d 62 struct {
group-onsemi 0:098463de4c5d 63 __I uint32_t XTAL32M:1;
group-onsemi 0:098463de4c5d 64 __I uint32_t XTAL32K:1;
group-onsemi 0:098463de4c5d 65 __I uint32_t CAL32K:1;
group-onsemi 0:098463de4c5d 66 __I uint32_t DONE32K:1;
group-onsemi 0:098463de4c5d 67 __I uint32_t CAL32MFAIL:1;
group-onsemi 0:098463de4c5d 68 __I uint32_t CAL32MDONE:1;
group-onsemi 0:098463de4c5d 69 } BITS;
group-onsemi 0:098463de4c5d 70 __I uint32_t WORD;
group-onsemi 0:098463de4c5d 71 } CSR; /**< 0x4001B004 Clock status register */
group-onsemi 0:098463de4c5d 72 union {
group-onsemi 0:098463de4c5d 73 struct {
group-onsemi 0:098463de4c5d 74 __IO uint32_t IE32K:1;
group-onsemi 0:098463de4c5d 75 __IO uint32_t IE32M:1;
group-onsemi 0:098463de4c5d 76 } BITS;
group-onsemi 0:098463de4c5d 77 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 78 } IER; /**< 0x4001B008 Interrup enable register */
group-onsemi 0:098463de4c5d 79 __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
group-onsemi 0:098463de4c5d 80 union {
group-onsemi 0:098463de4c5d 81 struct {
group-onsemi 0:098463de4c5d 82 __IO uint32_t TIMER0:1;
group-onsemi 0:098463de4c5d 83 __IO uint32_t TIMER1:1;
group-onsemi 0:098463de4c5d 84 __IO uint32_t TIMER2:1;
group-onsemi 0:098463de4c5d 85 __IO uint32_t PAD0:2;
group-onsemi 0:098463de4c5d 86 __IO uint32_t UART1:1;
group-onsemi 0:098463de4c5d 87 __IO uint32_t SPI:1;
group-onsemi 0:098463de4c5d 88 __IO uint32_t I2C:1;
group-onsemi 0:098463de4c5d 89 __IO uint32_t UART2:1;
group-onsemi 0:098463de4c5d 90 __IO uint32_t PAD1:1;
group-onsemi 0:098463de4c5d 91 __IO uint32_t WDOG:1;
group-onsemi 0:098463de4c5d 92 __IO uint32_t PWM:1;
group-onsemi 0:098463de4c5d 93 __IO uint32_t GPIO:1;
group-onsemi 0:098463de4c5d 94 __IO uint32_t PAD2:2;
group-onsemi 0:098463de4c5d 95 __IO uint32_t RTC:1;
group-onsemi 0:098463de4c5d 96 __IO uint32_t XBAR:1;
group-onsemi 0:098463de4c5d 97 __IO uint32_t RAND:1;
group-onsemi 0:098463de4c5d 98 __IO uint32_t PAD3:2;
group-onsemi 0:098463de4c5d 99 __IO uint32_t MACHW:1;
group-onsemi 0:098463de4c5d 100 __IO uint32_t ADC:1;
group-onsemi 0:098463de4c5d 101 __IO uint32_t AES:1;
group-onsemi 0:098463de4c5d 102 __IO uint32_t FLASH:1;
group-onsemi 0:098463de4c5d 103 __IO uint32_t PAD4:1;
group-onsemi 0:098463de4c5d 104 __IO uint32_t RFANA:1;
group-onsemi 0:098463de4c5d 105 __IO uint32_t IO:1;
group-onsemi 0:098463de4c5d 106 __IO uint32_t PAD5:1;
group-onsemi 0:098463de4c5d 107 __IO uint32_t PAD:1;
group-onsemi 0:098463de4c5d 108 __IO uint32_t PMU:1;
group-onsemi 0:098463de4c5d 109 __IO uint32_t PAD6:1;
group-onsemi 0:098463de4c5d 110 __IO uint32_t TEST:1;
group-onsemi 0:098463de4c5d 111 } BITS;
group-onsemi 0:098463de4c5d 112 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 113 } PDIS; /**< 0x4001B010 Periphery disable */
group-onsemi 0:098463de4c5d 114 __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
group-onsemi 0:098463de4c5d 115 __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
group-onsemi 0:098463de4c5d 116 __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
group-onsemi 0:098463de4c5d 117 __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
group-onsemi 0:098463de4c5d 118 __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
group-onsemi 0:098463de4c5d 119 union {
group-onsemi 0:098463de4c5d 120 struct {
group-onsemi 0:098463de4c5d 121 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
group-onsemi 0:098463de4c5d 122 __IO uint32_t BOOST :2; /* Boost done signal tap control */
group-onsemi 0:098463de4c5d 123 __IO uint32_t READY :2; /* Ready signal tap control */
group-onsemi 0:098463de4c5d 124 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
group-onsemi 0:098463de4c5d 125 __IO uint32_t PAD :20; /* Unused bits */
group-onsemi 0:098463de4c5d 126 } BITS;
group-onsemi 0:098463de4c5d 127 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 128 } TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 union {
group-onsemi 0:098463de4c5d 131 struct {
group-onsemi 0:098463de4c5d 132 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
group-onsemi 0:098463de4c5d 133 __IO uint32_t BOOST :2; /* Boost done signal tap control */
group-onsemi 0:098463de4c5d 134 __IO uint32_t READY :2; /* Ready signal tap control */
group-onsemi 0:098463de4c5d 135 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
group-onsemi 0:098463de4c5d 136 __IO uint32_t PAD :20; /* Unused bits */
group-onsemi 0:098463de4c5d 137 } BITS;
group-onsemi 0:098463de4c5d 138 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 139 } TRIM_32K_EXT;
group-onsemi 0:098463de4c5d 140 union {
group-onsemi 0:098463de4c5d 141 struct {
group-onsemi 0:098463de4c5d 142 __IO uint32_t OV32M;
group-onsemi 0:098463de4c5d 143 __IO uint32_t EN32M;
group-onsemi 0:098463de4c5d 144 __IO uint32_t OV32K;
group-onsemi 0:098463de4c5d 145 __IO uint32_t EN32K;
group-onsemi 0:098463de4c5d 146 } BITS;
group-onsemi 0:098463de4c5d 147 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 148 } CER; /**< 0x4001B038 clock enable register*/
group-onsemi 0:098463de4c5d 149 } ClockReg_t, *ClockReg_pt;
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 #endif /* CLOCK_MAP_H_ */