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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC81X/pinmap.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include "pinmap.h"
group-onsemi 0:098463de4c5d 18 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 __IO uint32_t* IOCON_REGISTERS[18] = {
group-onsemi 0:098463de4c5d 21 &LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 ,
group-onsemi 0:098463de4c5d 22 &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 ,
group-onsemi 0:098463de4c5d 23 &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 ,
group-onsemi 0:098463de4c5d 24 &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11,
group-onsemi 0:098463de4c5d 25 &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14,
group-onsemi 0:098463de4c5d 26 &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17,
group-onsemi 0:098463de4c5d 27 };
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 void pin_function(PinName pin, int function) {
group-onsemi 0:098463de4c5d 30 if (function == 0) {
group-onsemi 0:098463de4c5d 31 // Disable initial fixed function for P0_2, P0_3 and P0_5
group-onsemi 0:098463de4c5d 32 uint32_t enable = 0;
group-onsemi 0:098463de4c5d 33 if (pin == P0_2)
group-onsemi 0:098463de4c5d 34 enable = 1 << 3;
group-onsemi 0:098463de4c5d 35 else if (pin == P0_3)
group-onsemi 0:098463de4c5d 36 enable = 1 << 2;
group-onsemi 0:098463de4c5d 37 else if (pin == P0_5)
group-onsemi 0:098463de4c5d 38 enable = 1 << 6;
group-onsemi 0:098463de4c5d 39 LPC_SWM->PINENABLE0 |= enable;
group-onsemi 0:098463de4c5d 40 }
group-onsemi 0:098463de4c5d 41 }
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 void pin_mode(PinName pin, PinMode mode) {
group-onsemi 0:098463de4c5d 44 MBED_ASSERT(pin != (PinName)NC);
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 if ((pin == 10) || (pin == 11)) {
group-onsemi 0:098463de4c5d 47 // True open-drain pins can be configured for different I2C-bus speeds
group-onsemi 0:098463de4c5d 48 return;
group-onsemi 0:098463de4c5d 49 }
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 __IO uint32_t *reg = IOCON_REGISTERS[pin];
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 if (mode == OpenDrain) {
group-onsemi 0:098463de4c5d 54 *reg |= (1 << 10);
group-onsemi 0:098463de4c5d 55 } else {
group-onsemi 0:098463de4c5d 56 uint32_t tmp = *reg;
group-onsemi 0:098463de4c5d 57 tmp &= ~(0x3 << 3);
group-onsemi 0:098463de4c5d 58 tmp |= (mode & 0x3) << 3;
group-onsemi 0:098463de4c5d 59 *reg = tmp;
group-onsemi 0:098463de4c5d 60 }
group-onsemi 0:098463de4c5d 61 }