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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC23XX/spi_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include <math.h>
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #include "spi_api.h"
group-onsemi 0:098463de4c5d 20 #include "cmsis.h"
group-onsemi 0:098463de4c5d 21 #include "pinmap.h"
group-onsemi 0:098463de4c5d 22 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 static const PinMap PinMap_SPI_SCLK[] = {
group-onsemi 0:098463de4c5d 25 {P0_7 , SPI_1, 2},
group-onsemi 0:098463de4c5d 26 {P0_15, SPI_0, 2},
group-onsemi 0:098463de4c5d 27 {P1_20, SPI_0, 3},
group-onsemi 0:098463de4c5d 28 {P1_31, SPI_1, 2},
group-onsemi 0:098463de4c5d 29 {NC , NC , 0}
group-onsemi 0:098463de4c5d 30 };
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 static const PinMap PinMap_SPI_MOSI[] = {
group-onsemi 0:098463de4c5d 33 {P0_9 , SPI_1, 2},
group-onsemi 0:098463de4c5d 34 {P0_13, SPI_1, 2},
group-onsemi 0:098463de4c5d 35 {P0_18, SPI_0, 2},
group-onsemi 0:098463de4c5d 36 {P1_24, SPI_0, 3},
group-onsemi 0:098463de4c5d 37 {NC , NC , 0}
group-onsemi 0:098463de4c5d 38 };
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 static const PinMap PinMap_SPI_MISO[] = {
group-onsemi 0:098463de4c5d 41 {P0_8 , SPI_1, 2},
group-onsemi 0:098463de4c5d 42 {P0_12, SPI_1, 2},
group-onsemi 0:098463de4c5d 43 {P0_17, SPI_0, 2},
group-onsemi 0:098463de4c5d 44 {P1_23, SPI_0, 3},
group-onsemi 0:098463de4c5d 45 {NC , NC , 0}
group-onsemi 0:098463de4c5d 46 };
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 static const PinMap PinMap_SPI_SSEL[] = {
group-onsemi 0:098463de4c5d 49 {P0_6 , SPI_1, 2},
group-onsemi 0:098463de4c5d 50 {P0_11, SPI_1, 2},
group-onsemi 0:098463de4c5d 51 {P0_16, SPI_0, 2},
group-onsemi 0:098463de4c5d 52 {P1_21, SPI_0, 3},
group-onsemi 0:098463de4c5d 53 {NC , NC , 0}
group-onsemi 0:098463de4c5d 54 };
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 static inline int ssp_disable(spi_t *obj);
group-onsemi 0:098463de4c5d 57 static inline int ssp_enable(spi_t *obj);
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
group-onsemi 0:098463de4c5d 60 // determine the SPI to use
group-onsemi 0:098463de4c5d 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 65 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
group-onsemi 0:098463de4c5d 66 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
group-onsemi 0:098463de4c5d 67 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
group-onsemi 0:098463de4c5d 68 MBED_ASSERT((int)obj->spi != NC);
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 // enable power and clocking
group-onsemi 0:098463de4c5d 71 switch ((int)obj->spi) {
group-onsemi 0:098463de4c5d 72 case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
group-onsemi 0:098463de4c5d 73 case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
group-onsemi 0:098463de4c5d 74 }
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 // pin out the spi pins
group-onsemi 0:098463de4c5d 77 pinmap_pinout(mosi, PinMap_SPI_MOSI);
group-onsemi 0:098463de4c5d 78 pinmap_pinout(miso, PinMap_SPI_MISO);
group-onsemi 0:098463de4c5d 79 pinmap_pinout(sclk, PinMap_SPI_SCLK);
group-onsemi 0:098463de4c5d 80 if (ssel != NC) {
group-onsemi 0:098463de4c5d 81 pinmap_pinout(ssel, PinMap_SPI_SSEL);
group-onsemi 0:098463de4c5d 82 }
group-onsemi 0:098463de4c5d 83 }
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 void spi_free(spi_t *obj) {}
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 void spi_format(spi_t *obj, int bits, int mode, int slave) {
group-onsemi 0:098463de4c5d 88 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
group-onsemi 0:098463de4c5d 89 ssp_disable(obj);
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 int polarity = (mode & 0x2) ? 1 : 0;
group-onsemi 0:098463de4c5d 92 int phase = (mode & 0x1) ? 1 : 0;
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 // set it up
group-onsemi 0:098463de4c5d 95 int DSS = bits - 1; // DSS (data select size)
group-onsemi 0:098463de4c5d 96 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
group-onsemi 0:098463de4c5d 97 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 int FRF = 0; // FRF (frame format) = SPI
group-onsemi 0:098463de4c5d 100 uint32_t tmp = obj->spi->CR0;
group-onsemi 0:098463de4c5d 101 tmp &= ~(0xFFFF);
group-onsemi 0:098463de4c5d 102 tmp |= DSS << 0
group-onsemi 0:098463de4c5d 103 | FRF << 4
group-onsemi 0:098463de4c5d 104 | SPO << 6
group-onsemi 0:098463de4c5d 105 | SPH << 7;
group-onsemi 0:098463de4c5d 106 obj->spi->CR0 = tmp;
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 tmp = obj->spi->CR1;
group-onsemi 0:098463de4c5d 109 tmp &= ~(0xD);
group-onsemi 0:098463de4c5d 110 tmp |= 0 << 0 // LBM - loop back mode - off
group-onsemi 0:098463de4c5d 111 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
group-onsemi 0:098463de4c5d 112 | 0 << 3; // SOD - slave output disable - na
group-onsemi 0:098463de4c5d 113 obj->spi->CR1 = tmp;
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 ssp_enable(obj);
group-onsemi 0:098463de4c5d 116 }
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 void spi_frequency(spi_t *obj, int hz) {
group-onsemi 0:098463de4c5d 119 ssp_disable(obj);
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 // setup the spi clock diveder to /1
group-onsemi 0:098463de4c5d 122 switch ((int)obj->spi) {
group-onsemi 0:098463de4c5d 123 case SPI_0:
group-onsemi 0:098463de4c5d 124 LPC_SC->PCLKSEL1 &= ~(3 << 10);
group-onsemi 0:098463de4c5d 125 LPC_SC->PCLKSEL1 |= (1 << 10);
group-onsemi 0:098463de4c5d 126 break;
group-onsemi 0:098463de4c5d 127 case SPI_1:
group-onsemi 0:098463de4c5d 128 LPC_SC->PCLKSEL0 &= ~(3 << 20);
group-onsemi 0:098463de4c5d 129 LPC_SC->PCLKSEL0 |= (1 << 20);
group-onsemi 0:098463de4c5d 130 break;
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133 uint32_t PCLK = SystemCoreClock;
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 int prescaler;
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
group-onsemi 0:098463de4c5d 138 int prescale_hz = PCLK / prescaler;
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 // calculate the divider
group-onsemi 0:098463de4c5d 141 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 // check we can support the divider
group-onsemi 0:098463de4c5d 144 if (divider < 256) {
group-onsemi 0:098463de4c5d 145 // prescaler
group-onsemi 0:098463de4c5d 146 obj->spi->CPSR = prescaler;
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 // divider
group-onsemi 0:098463de4c5d 149 obj->spi->CR0 &= ~(0xFFFF << 8);
group-onsemi 0:098463de4c5d 150 obj->spi->CR0 |= (divider - 1) << 8;
group-onsemi 0:098463de4c5d 151 ssp_enable(obj);
group-onsemi 0:098463de4c5d 152 return;
group-onsemi 0:098463de4c5d 153 }
group-onsemi 0:098463de4c5d 154 }
group-onsemi 0:098463de4c5d 155 error("Couldn't setup requested SPI frequency");
group-onsemi 0:098463de4c5d 156 }
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 static inline int ssp_disable(spi_t *obj) {
group-onsemi 0:098463de4c5d 159 return obj->spi->CR1 &= ~(1 << 1);
group-onsemi 0:098463de4c5d 160 }
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 static inline int ssp_enable(spi_t *obj) {
group-onsemi 0:098463de4c5d 163 return obj->spi->CR1 |= (1 << 1);
group-onsemi 0:098463de4c5d 164 }
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 static inline int ssp_readable(spi_t *obj) {
group-onsemi 0:098463de4c5d 167 return obj->spi->SR & (1 << 2);
group-onsemi 0:098463de4c5d 168 }
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 static inline int ssp_writeable(spi_t *obj) {
group-onsemi 0:098463de4c5d 171 return obj->spi->SR & (1 << 1);
group-onsemi 0:098463de4c5d 172 }
group-onsemi 0:098463de4c5d 173
group-onsemi 0:098463de4c5d 174 static inline void ssp_write(spi_t *obj, int value) {
group-onsemi 0:098463de4c5d 175 while (!ssp_writeable(obj));
group-onsemi 0:098463de4c5d 176 obj->spi->DR = value;
group-onsemi 0:098463de4c5d 177 }
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 static inline int ssp_read(spi_t *obj) {
group-onsemi 0:098463de4c5d 180 while (!ssp_readable(obj));
group-onsemi 0:098463de4c5d 181 return obj->spi->DR;
group-onsemi 0:098463de4c5d 182 }
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 static inline int ssp_busy(spi_t *obj) {
group-onsemi 0:098463de4c5d 185 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
group-onsemi 0:098463de4c5d 186 }
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 int spi_master_write(spi_t *obj, int value) {
group-onsemi 0:098463de4c5d 189 ssp_write(obj, value);
group-onsemi 0:098463de4c5d 190 return ssp_read(obj);
group-onsemi 0:098463de4c5d 191 }
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 int spi_slave_receive(spi_t *obj) {
group-onsemi 0:098463de4c5d 194 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
group-onsemi 0:098463de4c5d 195 }
group-onsemi 0:098463de4c5d 196
group-onsemi 0:098463de4c5d 197 int spi_slave_read(spi_t *obj) {
group-onsemi 0:098463de4c5d 198 return obj->spi->DR;
group-onsemi 0:098463de4c5d 199 }
group-onsemi 0:098463de4c5d 200
group-onsemi 0:098463de4c5d 201 void spi_slave_write(spi_t *obj, int value) {
group-onsemi 0:098463de4c5d 202 while (ssp_writeable(obj) == 0) ;
group-onsemi 0:098463de4c5d 203 obj->spi->DR = value;
group-onsemi 0:098463de4c5d 204 }
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 int spi_busy(spi_t *obj) {
group-onsemi 0:098463de4c5d 207 return ssp_busy(obj);
group-onsemi 0:098463de4c5d 208 }