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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include "i2c_api.h"
group-onsemi 0:098463de4c5d 18 #include "cmsis.h"
group-onsemi 0:098463de4c5d 19 #include "pinmap.h"
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 static const PinMap PinMap_I2C_SDA[] = {
group-onsemi 0:098463de4c5d 22 {P0_0 , I2C_1, 3},
group-onsemi 0:098463de4c5d 23 {P0_10, I2C_2, 2},
group-onsemi 0:098463de4c5d 24 {P0_19, I2C_1, 3},
group-onsemi 0:098463de4c5d 25 {P0_27, I2C_0, 1},
group-onsemi 0:098463de4c5d 26 {NC , NC , 0}
group-onsemi 0:098463de4c5d 27 };
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 static const PinMap PinMap_I2C_SCL[] = {
group-onsemi 0:098463de4c5d 30 {P0_1 , I2C_1, 3},
group-onsemi 0:098463de4c5d 31 {P0_11, I2C_2, 2},
group-onsemi 0:098463de4c5d 32 {P0_20, I2C_1, 3},
group-onsemi 0:098463de4c5d 33 {P0_28, I2C_0, 1},
group-onsemi 0:098463de4c5d 34 {NC , NC, 0}
group-onsemi 0:098463de4c5d 35 };
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #define I2C_CONSET(x) (x->i2c->I2CONSET)
group-onsemi 0:098463de4c5d 38 #define I2C_CONCLR(x) (x->i2c->I2CONCLR)
group-onsemi 0:098463de4c5d 39 #define I2C_STAT(x) (x->i2c->I2STAT)
group-onsemi 0:098463de4c5d 40 #define I2C_DAT(x) (x->i2c->I2DAT)
group-onsemi 0:098463de4c5d 41 #define I2C_SCLL(x, val) (x->i2c->I2SCLL = val)
group-onsemi 0:098463de4c5d 42 #define I2C_SCLH(x, val) (x->i2c->I2SCLH = val)
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 static const uint32_t I2C_addr_offset[2][4] = {
group-onsemi 0:098463de4c5d 45 {0x0C, 0x20, 0x24, 0x28},
group-onsemi 0:098463de4c5d 46 {0x30, 0x34, 0x38, 0x3C}
group-onsemi 0:098463de4c5d 47 };
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
group-onsemi 0:098463de4c5d 50 I2C_CONCLR(obj) = (start << 5)
group-onsemi 0:098463de4c5d 51 | (stop << 4)
group-onsemi 0:098463de4c5d 52 | (interrupt << 3)
group-onsemi 0:098463de4c5d 53 | (acknowledge << 2);
group-onsemi 0:098463de4c5d 54 }
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
group-onsemi 0:098463de4c5d 57 I2C_CONSET(obj) = (start << 5)
group-onsemi 0:098463de4c5d 58 | (stop << 4)
group-onsemi 0:098463de4c5d 59 | (interrupt << 3)
group-onsemi 0:098463de4c5d 60 | (acknowledge << 2);
group-onsemi 0:098463de4c5d 61 }
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 // Clear the Serial Interrupt (SI)
group-onsemi 0:098463de4c5d 64 static inline void i2c_clear_SI(i2c_t *obj) {
group-onsemi 0:098463de4c5d 65 i2c_conclr(obj, 0, 0, 1, 0);
group-onsemi 0:098463de4c5d 66 }
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 static inline int i2c_status(i2c_t *obj) {
group-onsemi 0:098463de4c5d 69 return I2C_STAT(obj);
group-onsemi 0:098463de4c5d 70 }
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 // Wait until the Serial Interrupt (SI) is set
group-onsemi 0:098463de4c5d 73 static int i2c_wait_SI(i2c_t *obj) {
group-onsemi 0:098463de4c5d 74 int timeout = 0;
group-onsemi 0:098463de4c5d 75 while (!(I2C_CONSET(obj) & (1 << 3))) {
group-onsemi 0:098463de4c5d 76 timeout++;
group-onsemi 0:098463de4c5d 77 if (timeout > 100000) return -1;
group-onsemi 0:098463de4c5d 78 }
group-onsemi 0:098463de4c5d 79 return 0;
group-onsemi 0:098463de4c5d 80 }
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 static inline void i2c_interface_enable(i2c_t *obj) {
group-onsemi 0:098463de4c5d 83 I2C_CONSET(obj) = 0x40;
group-onsemi 0:098463de4c5d 84 }
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 static inline void i2c_power_enable(i2c_t *obj) {
group-onsemi 0:098463de4c5d 87 switch ((int)obj->i2c) {
group-onsemi 0:098463de4c5d 88 case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
group-onsemi 0:098463de4c5d 89 case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
group-onsemi 0:098463de4c5d 90 case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
group-onsemi 0:098463de4c5d 91 }
group-onsemi 0:098463de4c5d 92 }
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
group-onsemi 0:098463de4c5d 95 // determine the SPI to use
group-onsemi 0:098463de4c5d 96 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
group-onsemi 0:098463de4c5d 97 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
group-onsemi 0:098463de4c5d 98 obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
group-onsemi 0:098463de4c5d 99 MBED_ASSERT((int)obj->i2c != NC);
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 // enable power
group-onsemi 0:098463de4c5d 102 i2c_power_enable(obj);
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 // set default frequency at 100k
group-onsemi 0:098463de4c5d 105 i2c_frequency(obj, 100000);
group-onsemi 0:098463de4c5d 106 i2c_conclr(obj, 1, 1, 1, 1);
group-onsemi 0:098463de4c5d 107 i2c_interface_enable(obj);
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 pinmap_pinout(sda, PinMap_I2C_SDA);
group-onsemi 0:098463de4c5d 110 pinmap_pinout(scl, PinMap_I2C_SCL);
group-onsemi 0:098463de4c5d 111 }
group-onsemi 0:098463de4c5d 112
group-onsemi 0:098463de4c5d 113 inline int i2c_start(i2c_t *obj) {
group-onsemi 0:098463de4c5d 114 int status = 0;
group-onsemi 0:098463de4c5d 115 int isInterrupted = I2C_CONSET(obj) & (1 << 3);
group-onsemi 0:098463de4c5d 116
group-onsemi 0:098463de4c5d 117 // 8.1 Before master mode can be entered, I2CON must be initialised to:
group-onsemi 0:098463de4c5d 118 // - I2EN STA STO SI AA - -
group-onsemi 0:098463de4c5d 119 // - 1 0 0 x x - -
group-onsemi 0:098463de4c5d 120 // if AA = 0, it can't enter slave mode
group-onsemi 0:098463de4c5d 121 i2c_conclr(obj, 1, 1, 0, 1);
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 // The master mode may now be entered by setting the STA bit
group-onsemi 0:098463de4c5d 124 // this will generate a start condition when the bus becomes free
group-onsemi 0:098463de4c5d 125 i2c_conset(obj, 1, 0, 0, 1);
group-onsemi 0:098463de4c5d 126 // Clearing SI bit when it wasn't set on entry can jump past state
group-onsemi 0:098463de4c5d 127 // 0x10 or 0x08 and erroneously send uninitialized slave address.
group-onsemi 0:098463de4c5d 128 if (isInterrupted)
group-onsemi 0:098463de4c5d 129 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 i2c_wait_SI(obj);
group-onsemi 0:098463de4c5d 132 status = i2c_status(obj);
group-onsemi 0:098463de4c5d 133
group-onsemi 0:098463de4c5d 134 // Clear start bit now that it's transmitted
group-onsemi 0:098463de4c5d 135 i2c_conclr(obj, 1, 0, 0, 0);
group-onsemi 0:098463de4c5d 136 return status;
group-onsemi 0:098463de4c5d 137 }
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 inline int i2c_stop(i2c_t *obj) {
group-onsemi 0:098463de4c5d 140 int timeout = 0;
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 // write the stop bit
group-onsemi 0:098463de4c5d 143 i2c_conset(obj, 0, 1, 0, 0);
group-onsemi 0:098463de4c5d 144 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 145
group-onsemi 0:098463de4c5d 146 // wait for STO bit to reset
group-onsemi 0:098463de4c5d 147 while(I2C_CONSET(obj) & (1 << 4)) {
group-onsemi 0:098463de4c5d 148 timeout ++;
group-onsemi 0:098463de4c5d 149 if (timeout > 100000) return 1;
group-onsemi 0:098463de4c5d 150 }
group-onsemi 0:098463de4c5d 151
group-onsemi 0:098463de4c5d 152 return 0;
group-onsemi 0:098463de4c5d 153 }
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
group-onsemi 0:098463de4c5d 156 // write the data
group-onsemi 0:098463de4c5d 157 I2C_DAT(obj) = value;
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 // clear SI to init a send
group-onsemi 0:098463de4c5d 160 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 // wait and return status
group-onsemi 0:098463de4c5d 163 i2c_wait_SI(obj);
group-onsemi 0:098463de4c5d 164 return i2c_status(obj);
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 static inline int i2c_do_read(i2c_t *obj, int last) {
group-onsemi 0:098463de4c5d 168 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
group-onsemi 0:098463de4c5d 169 if(last) {
group-onsemi 0:098463de4c5d 170 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
group-onsemi 0:098463de4c5d 171 } else {
group-onsemi 0:098463de4c5d 172 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 // accept byte
group-onsemi 0:098463de4c5d 176 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 // wait for it to arrive
group-onsemi 0:098463de4c5d 179 i2c_wait_SI(obj);
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 // return the data
group-onsemi 0:098463de4c5d 182 return (I2C_DAT(obj) & 0xFF);
group-onsemi 0:098463de4c5d 183 }
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 void i2c_frequency(i2c_t *obj, int hz) {
group-onsemi 0:098463de4c5d 186 // [TODO] set pclk to /4
group-onsemi 0:098463de4c5d 187 uint32_t PCLK = SystemCoreClock / 4;
group-onsemi 0:098463de4c5d 188
group-onsemi 0:098463de4c5d 189 uint32_t pulse = PCLK / (hz * 2);
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 // I2C Rate
group-onsemi 0:098463de4c5d 192 I2C_SCLL(obj, pulse);
group-onsemi 0:098463de4c5d 193 I2C_SCLH(obj, pulse);
group-onsemi 0:098463de4c5d 194 }
group-onsemi 0:098463de4c5d 195
group-onsemi 0:098463de4c5d 196 // The I2C does a read or a write as a whole operation
group-onsemi 0:098463de4c5d 197 // There are two types of error conditions it can encounter
group-onsemi 0:098463de4c5d 198 // 1) it can not obtain the bus
group-onsemi 0:098463de4c5d 199 // 2) it gets error responses at part of the transmission
group-onsemi 0:098463de4c5d 200 //
group-onsemi 0:098463de4c5d 201 // We tackle them as follows:
group-onsemi 0:098463de4c5d 202 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
group-onsemi 0:098463de4c5d 203 // which basically turns it in to a 2)
group-onsemi 0:098463de4c5d 204 // 2) on error, we use the standard error mechanisms to report/debug
group-onsemi 0:098463de4c5d 205 //
group-onsemi 0:098463de4c5d 206 // Therefore an I2C transaction should always complete. If it doesn't it is usually
group-onsemi 0:098463de4c5d 207 // because something is setup wrong (e.g. wiring), and we don't need to programatically
group-onsemi 0:098463de4c5d 208 // check for that
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
group-onsemi 0:098463de4c5d 211 int count, status;
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 status = i2c_start(obj);
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 if ((status != 0x10) && (status != 0x08)) {
group-onsemi 0:098463de4c5d 216 i2c_stop(obj);
group-onsemi 0:098463de4c5d 217 return I2C_ERROR_BUS_BUSY;
group-onsemi 0:098463de4c5d 218 }
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 status = i2c_do_write(obj, (address | 0x01), 1);
group-onsemi 0:098463de4c5d 221 if (status != 0x40) {
group-onsemi 0:098463de4c5d 222 i2c_stop(obj);
group-onsemi 0:098463de4c5d 223 return I2C_ERROR_NO_SLAVE;
group-onsemi 0:098463de4c5d 224 }
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 // Read in all except last byte
group-onsemi 0:098463de4c5d 227 for (count = 0; count < (length - 1); count++) {
group-onsemi 0:098463de4c5d 228 int value = i2c_do_read(obj, 0);
group-onsemi 0:098463de4c5d 229 status = i2c_status(obj);
group-onsemi 0:098463de4c5d 230 if (status != 0x50) {
group-onsemi 0:098463de4c5d 231 i2c_stop(obj);
group-onsemi 0:098463de4c5d 232 return count;
group-onsemi 0:098463de4c5d 233 }
group-onsemi 0:098463de4c5d 234 data[count] = (char) value;
group-onsemi 0:098463de4c5d 235 }
group-onsemi 0:098463de4c5d 236
group-onsemi 0:098463de4c5d 237 // read in last byte
group-onsemi 0:098463de4c5d 238 int value = i2c_do_read(obj, 1);
group-onsemi 0:098463de4c5d 239 status = i2c_status(obj);
group-onsemi 0:098463de4c5d 240 if (status != 0x58) {
group-onsemi 0:098463de4c5d 241 i2c_stop(obj);
group-onsemi 0:098463de4c5d 242 return length - 1;
group-onsemi 0:098463de4c5d 243 }
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 data[count] = (char) value;
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 // If not repeated start, send stop.
group-onsemi 0:098463de4c5d 248 if (stop) {
group-onsemi 0:098463de4c5d 249 i2c_stop(obj);
group-onsemi 0:098463de4c5d 250 }
group-onsemi 0:098463de4c5d 251
group-onsemi 0:098463de4c5d 252 return length;
group-onsemi 0:098463de4c5d 253 }
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
group-onsemi 0:098463de4c5d 256 int i, status;
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 status = i2c_start(obj);
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 if ((status != 0x10) && (status != 0x08)) {
group-onsemi 0:098463de4c5d 261 i2c_stop(obj);
group-onsemi 0:098463de4c5d 262 return I2C_ERROR_BUS_BUSY;
group-onsemi 0:098463de4c5d 263 }
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 status = i2c_do_write(obj, (address & 0xFE), 1);
group-onsemi 0:098463de4c5d 266 if (status != 0x18) {
group-onsemi 0:098463de4c5d 267 i2c_stop(obj);
group-onsemi 0:098463de4c5d 268 return I2C_ERROR_NO_SLAVE;
group-onsemi 0:098463de4c5d 269 }
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271 for (i=0; i<length; i++) {
group-onsemi 0:098463de4c5d 272 status = i2c_do_write(obj, data[i], 0);
group-onsemi 0:098463de4c5d 273 if(status != 0x28) {
group-onsemi 0:098463de4c5d 274 i2c_stop(obj);
group-onsemi 0:098463de4c5d 275 return i;
group-onsemi 0:098463de4c5d 276 }
group-onsemi 0:098463de4c5d 277 }
group-onsemi 0:098463de4c5d 278
group-onsemi 0:098463de4c5d 279 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
group-onsemi 0:098463de4c5d 280 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
group-onsemi 0:098463de4c5d 281 // i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 282
group-onsemi 0:098463de4c5d 283 // If not repeated start, send stop.
group-onsemi 0:098463de4c5d 284 if (stop) {
group-onsemi 0:098463de4c5d 285 i2c_stop(obj);
group-onsemi 0:098463de4c5d 286 }
group-onsemi 0:098463de4c5d 287
group-onsemi 0:098463de4c5d 288 return length;
group-onsemi 0:098463de4c5d 289 }
group-onsemi 0:098463de4c5d 290
group-onsemi 0:098463de4c5d 291 void i2c_reset(i2c_t *obj) {
group-onsemi 0:098463de4c5d 292 i2c_stop(obj);
group-onsemi 0:098463de4c5d 293 }
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 int i2c_byte_read(i2c_t *obj, int last) {
group-onsemi 0:098463de4c5d 296 return (i2c_do_read(obj, last) & 0xFF);
group-onsemi 0:098463de4c5d 297 }
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 int i2c_byte_write(i2c_t *obj, int data) {
group-onsemi 0:098463de4c5d 300 int ack;
group-onsemi 0:098463de4c5d 301 int status = i2c_do_write(obj, (data & 0xFF), 0);
group-onsemi 0:098463de4c5d 302
group-onsemi 0:098463de4c5d 303 switch(status) {
group-onsemi 0:098463de4c5d 304 case 0x18: case 0x28: // Master transmit ACKs
group-onsemi 0:098463de4c5d 305 ack = 1;
group-onsemi 0:098463de4c5d 306 break;
group-onsemi 0:098463de4c5d 307 case 0x40: // Master receive address transmitted ACK
group-onsemi 0:098463de4c5d 308 ack = 1;
group-onsemi 0:098463de4c5d 309 break;
group-onsemi 0:098463de4c5d 310 case 0xB8: // Slave transmit ACK
group-onsemi 0:098463de4c5d 311 ack = 1;
group-onsemi 0:098463de4c5d 312 break;
group-onsemi 0:098463de4c5d 313 default:
group-onsemi 0:098463de4c5d 314 ack = 0;
group-onsemi 0:098463de4c5d 315 break;
group-onsemi 0:098463de4c5d 316 }
group-onsemi 0:098463de4c5d 317
group-onsemi 0:098463de4c5d 318 return ack;
group-onsemi 0:098463de4c5d 319 }
group-onsemi 0:098463de4c5d 320
group-onsemi 0:098463de4c5d 321 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
group-onsemi 0:098463de4c5d 322 if (enable_slave != 0) {
group-onsemi 0:098463de4c5d 323 i2c_conclr(obj, 1, 1, 1, 0);
group-onsemi 0:098463de4c5d 324 i2c_conset(obj, 0, 0, 0, 1);
group-onsemi 0:098463de4c5d 325 } else {
group-onsemi 0:098463de4c5d 326 i2c_conclr(obj, 1, 1, 1, 1);
group-onsemi 0:098463de4c5d 327 }
group-onsemi 0:098463de4c5d 328 }
group-onsemi 0:098463de4c5d 329
group-onsemi 0:098463de4c5d 330 int i2c_slave_receive(i2c_t *obj) {
group-onsemi 0:098463de4c5d 331 int status;
group-onsemi 0:098463de4c5d 332 int retval;
group-onsemi 0:098463de4c5d 333
group-onsemi 0:098463de4c5d 334 status = i2c_status(obj);
group-onsemi 0:098463de4c5d 335 switch(status) {
group-onsemi 0:098463de4c5d 336 case 0x60: retval = 3; break;
group-onsemi 0:098463de4c5d 337 case 0x70: retval = 2; break;
group-onsemi 0:098463de4c5d 338 case 0xA8: retval = 1; break;
group-onsemi 0:098463de4c5d 339 default : retval = 0; break;
group-onsemi 0:098463de4c5d 340 }
group-onsemi 0:098463de4c5d 341
group-onsemi 0:098463de4c5d 342 return(retval);
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 int i2c_slave_read(i2c_t *obj, char *data, int length) {
group-onsemi 0:098463de4c5d 346 int count = 0;
group-onsemi 0:098463de4c5d 347 int status;
group-onsemi 0:098463de4c5d 348
group-onsemi 0:098463de4c5d 349 do {
group-onsemi 0:098463de4c5d 350 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 351 i2c_wait_SI(obj);
group-onsemi 0:098463de4c5d 352 status = i2c_status(obj);
group-onsemi 0:098463de4c5d 353 if((status == 0x80) || (status == 0x90)) {
group-onsemi 0:098463de4c5d 354 data[count] = I2C_DAT(obj) & 0xFF;
group-onsemi 0:098463de4c5d 355 }
group-onsemi 0:098463de4c5d 356 count++;
group-onsemi 0:098463de4c5d 357 } while (((status == 0x80) || (status == 0x90) ||
group-onsemi 0:098463de4c5d 358 (status == 0x060) || (status == 0x70)) && (count < length));
group-onsemi 0:098463de4c5d 359
group-onsemi 0:098463de4c5d 360 // Clear old status and wait for Serial Interrupt.
group-onsemi 0:098463de4c5d 361 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 362 i2c_wait_SI(obj);
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364 // Obtain new status.
group-onsemi 0:098463de4c5d 365 status = i2c_status(obj);
group-onsemi 0:098463de4c5d 366
group-onsemi 0:098463de4c5d 367 if(status != 0xA0) {
group-onsemi 0:098463de4c5d 368 i2c_stop(obj);
group-onsemi 0:098463de4c5d 369 }
group-onsemi 0:098463de4c5d 370
group-onsemi 0:098463de4c5d 371 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 372
group-onsemi 0:098463de4c5d 373 return count;
group-onsemi 0:098463de4c5d 374 }
group-onsemi 0:098463de4c5d 375
group-onsemi 0:098463de4c5d 376 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
group-onsemi 0:098463de4c5d 377 int count = 0;
group-onsemi 0:098463de4c5d 378 int status;
group-onsemi 0:098463de4c5d 379
group-onsemi 0:098463de4c5d 380 if(length <= 0) {
group-onsemi 0:098463de4c5d 381 return(0);
group-onsemi 0:098463de4c5d 382 }
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 do {
group-onsemi 0:098463de4c5d 385 status = i2c_do_write(obj, data[count], 0);
group-onsemi 0:098463de4c5d 386 count++;
group-onsemi 0:098463de4c5d 387 } while ((count < length) && (status == 0xB8));
group-onsemi 0:098463de4c5d 388
group-onsemi 0:098463de4c5d 389 if ((status != 0xC0) && (status != 0xC8)) {
group-onsemi 0:098463de4c5d 390 i2c_stop(obj);
group-onsemi 0:098463de4c5d 391 }
group-onsemi 0:098463de4c5d 392
group-onsemi 0:098463de4c5d 393 i2c_clear_SI(obj);
group-onsemi 0:098463de4c5d 394
group-onsemi 0:098463de4c5d 395 return(count);
group-onsemi 0:098463de4c5d 396 }
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
group-onsemi 0:098463de4c5d 399 uint32_t addr;
group-onsemi 0:098463de4c5d 400
group-onsemi 0:098463de4c5d 401 if ((idx >= 0) && (idx <= 3)) {
group-onsemi 0:098463de4c5d 402 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
group-onsemi 0:098463de4c5d 403 *((uint32_t *) addr) = address & 0xFF;
group-onsemi 0:098463de4c5d 404 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
group-onsemi 0:098463de4c5d 405 *((uint32_t *) addr) = mask & 0xFE;
group-onsemi 0:098463de4c5d 406 }
group-onsemi 0:098463de4c5d 407 }