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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC15XX/spi_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include <math.h>
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #include "spi_api.h"
group-onsemi 0:098463de4c5d 20 #include "cmsis.h"
group-onsemi 0:098463de4c5d 21 #include "pinmap.h"
group-onsemi 0:098463de4c5d 22 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 static const SWM_Map SWM_SPI_SSEL[] = {
group-onsemi 0:098463de4c5d 25 {4, 0},
group-onsemi 0:098463de4c5d 26 {5, 24},
group-onsemi 0:098463de4c5d 27 };
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 static const SWM_Map SWM_SPI_SCLK[] = {
group-onsemi 0:098463de4c5d 30 {3, 8},
group-onsemi 0:098463de4c5d 31 {5, 0},
group-onsemi 0:098463de4c5d 32 };
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 static const SWM_Map SWM_SPI_MOSI[] = {
group-onsemi 0:098463de4c5d 35 {3, 16},
group-onsemi 0:098463de4c5d 36 {5, 8},
group-onsemi 0:098463de4c5d 37 };
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39 static const SWM_Map SWM_SPI_MISO[] = {
group-onsemi 0:098463de4c5d 40 {3, 24},
group-onsemi 0:098463de4c5d 41 {5, 16},
group-onsemi 0:098463de4c5d 42 };
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 // bit flags for used SPIs
group-onsemi 0:098463de4c5d 45 static unsigned char spi_used = 0;
group-onsemi 0:098463de4c5d 46 static int get_available_spi(PinName mosi, PinName miso, PinName sclk, PinName ssel)
group-onsemi 0:098463de4c5d 47 {
group-onsemi 0:098463de4c5d 48 if (spi_used == 0) {
group-onsemi 0:098463de4c5d 49 return 0; // The first user
group-onsemi 0:098463de4c5d 50 }
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 const SWM_Map *swm;
group-onsemi 0:098463de4c5d 53 uint32_t regVal;
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 // Investigate if same pins as the used SPI0/1 - to be able to reuse it
group-onsemi 0:098463de4c5d 56 for (int spi_n = 0; spi_n < 2; spi_n++) {
group-onsemi 0:098463de4c5d 57 if (spi_used & (1<<spi_n)) {
group-onsemi 0:098463de4c5d 58 if (sclk != NC) {
group-onsemi 0:098463de4c5d 59 swm = &SWM_SPI_SCLK[spi_n];
group-onsemi 0:098463de4c5d 60 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
group-onsemi 0:098463de4c5d 61 if (regVal != (sclk << swm->offset)) {
group-onsemi 0:098463de4c5d 62 // Existing pin is not the same as the one we want
group-onsemi 0:098463de4c5d 63 continue;
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65 }
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 if (mosi != NC) {
group-onsemi 0:098463de4c5d 68 swm = &SWM_SPI_MOSI[spi_n];
group-onsemi 0:098463de4c5d 69 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
group-onsemi 0:098463de4c5d 70 if (regVal != (mosi << swm->offset)) {
group-onsemi 0:098463de4c5d 71 // Existing pin is not the same as the one we want
group-onsemi 0:098463de4c5d 72 continue;
group-onsemi 0:098463de4c5d 73 }
group-onsemi 0:098463de4c5d 74 }
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 if (miso != NC) {
group-onsemi 0:098463de4c5d 77 swm = &SWM_SPI_MISO[spi_n];
group-onsemi 0:098463de4c5d 78 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
group-onsemi 0:098463de4c5d 79 if (regVal != (miso << swm->offset)) {
group-onsemi 0:098463de4c5d 80 // Existing pin is not the same as the one we want
group-onsemi 0:098463de4c5d 81 continue;
group-onsemi 0:098463de4c5d 82 }
group-onsemi 0:098463de4c5d 83 }
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 if (ssel != NC) {
group-onsemi 0:098463de4c5d 86 swm = &SWM_SPI_SSEL[spi_n];
group-onsemi 0:098463de4c5d 87 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
group-onsemi 0:098463de4c5d 88 if (regVal != (ssel << swm->offset)) {
group-onsemi 0:098463de4c5d 89 // Existing pin is not the same as the one we want
group-onsemi 0:098463de4c5d 90 continue;
group-onsemi 0:098463de4c5d 91 }
group-onsemi 0:098463de4c5d 92 }
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 // The pins for the currently used SPIx are the same as the
group-onsemi 0:098463de4c5d 95 // ones we want so we will reuse it
group-onsemi 0:098463de4c5d 96 return spi_n;
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98 }
group-onsemi 0:098463de4c5d 99
group-onsemi 0:098463de4c5d 100 // None of the existing SPIx pin setups match the pins we want
group-onsemi 0:098463de4c5d 101 // so the last hope is to select one unused SPIx
group-onsemi 0:098463de4c5d 102 if ((spi_used & 1) == 0) {
group-onsemi 0:098463de4c5d 103 return 0;
group-onsemi 0:098463de4c5d 104 } else if ((spi_used & 2) == 0) {
group-onsemi 0:098463de4c5d 105 return 1;
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 // No matching setup and no free SPIx
group-onsemi 0:098463de4c5d 109 return -1;
group-onsemi 0:098463de4c5d 110 }
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 static inline void spi_disable(spi_t *obj);
group-onsemi 0:098463de4c5d 113 static inline void spi_enable(spi_t *obj);
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
group-onsemi 0:098463de4c5d 116 {
group-onsemi 0:098463de4c5d 117 int spi_n = get_available_spi(mosi, miso, sclk, ssel);
group-onsemi 0:098463de4c5d 118 if (spi_n == -1) {
group-onsemi 0:098463de4c5d 119 error("No available SPI");
group-onsemi 0:098463de4c5d 120 }
group-onsemi 0:098463de4c5d 121
group-onsemi 0:098463de4c5d 122 obj->spi_n = spi_n;
group-onsemi 0:098463de4c5d 123 spi_used |= (1 << spi_n);
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 const SWM_Map *swm;
group-onsemi 0:098463de4c5d 128 uint32_t regVal;
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 if (sclk != NC) {
group-onsemi 0:098463de4c5d 131 swm = &SWM_SPI_SCLK[obj->spi_n];
group-onsemi 0:098463de4c5d 132 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 133 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
group-onsemi 0:098463de4c5d 134 }
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 if (mosi != NC) {
group-onsemi 0:098463de4c5d 137 swm = &SWM_SPI_MOSI[obj->spi_n];
group-onsemi 0:098463de4c5d 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 139 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
group-onsemi 0:098463de4c5d 140 }
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 if (miso != NC) {
group-onsemi 0:098463de4c5d 143 swm = &SWM_SPI_MISO[obj->spi_n];
group-onsemi 0:098463de4c5d 144 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 145 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
group-onsemi 0:098463de4c5d 146 }
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 if (ssel != NC) {
group-onsemi 0:098463de4c5d 149 swm = &SWM_SPI_SSEL[obj->spi_n];
group-onsemi 0:098463de4c5d 150 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 151 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
group-onsemi 0:098463de4c5d 152 }
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 // clear interrupts
group-onsemi 0:098463de4c5d 155 obj->spi->INTENCLR = 0x3f;
group-onsemi 0:098463de4c5d 156
group-onsemi 0:098463de4c5d 157 // enable power and clocking
group-onsemi 0:098463de4c5d 158 LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1 << (obj->spi_n + 9));
group-onsemi 0:098463de4c5d 159 LPC_SYSCON->PRESETCTRL1 |= (0x1 << (obj->spi_n + 9));
group-onsemi 0:098463de4c5d 160 LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (obj->spi_n + 9));
group-onsemi 0:098463de4c5d 161 }
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 void spi_free(spi_t *obj)
group-onsemi 0:098463de4c5d 164 {
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 void spi_format(spi_t *obj, int bits, int mode, int slave)
group-onsemi 0:098463de4c5d 168 {
group-onsemi 0:098463de4c5d 169 spi_disable(obj);
group-onsemi 0:098463de4c5d 170 MBED_ASSERT((bits >= 1 && bits <= 16) && (mode >= 0 && mode <= 3));
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 int polarity = (mode & 0x2) ? 1 : 0;
group-onsemi 0:098463de4c5d 173 int phase = (mode & 0x1) ? 1 : 0;
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 // set it up
group-onsemi 0:098463de4c5d 176 int LEN = bits - 1; // LEN - Data Length
group-onsemi 0:098463de4c5d 177 int CPOL = (polarity) ? 1 : 0; // CPOL - Clock Polarity select
group-onsemi 0:098463de4c5d 178 int CPHA = (phase) ? 1 : 0; // CPHA - Clock Phase select
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 uint32_t tmp = obj->spi->CFG;
group-onsemi 0:098463de4c5d 181 tmp &= ~((1 << 5) | (1 << 4) | (1 << 2));
group-onsemi 0:098463de4c5d 182 tmp |= (CPOL << 5) | (CPHA << 4) | ((slave ? 0 : 1) << 2);
group-onsemi 0:098463de4c5d 183 obj->spi->CFG = tmp;
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 // select frame length
group-onsemi 0:098463de4c5d 186 tmp = obj->spi->TXCTL;
group-onsemi 0:098463de4c5d 187 tmp &= ~(0xf << 24);
group-onsemi 0:098463de4c5d 188 tmp |= (LEN << 24);
group-onsemi 0:098463de4c5d 189 obj->spi->TXCTL = tmp;
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 spi_enable(obj);
group-onsemi 0:098463de4c5d 192 }
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 void spi_frequency(spi_t *obj, int hz)
group-onsemi 0:098463de4c5d 195 {
group-onsemi 0:098463de4c5d 196 spi_disable(obj);
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 // rise DIV value if it cannot be divided
group-onsemi 0:098463de4c5d 199 obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
group-onsemi 0:098463de4c5d 200 obj->spi->DLY = 0;
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 spi_enable(obj);
group-onsemi 0:098463de4c5d 203 }
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 static inline void spi_disable(spi_t *obj)
group-onsemi 0:098463de4c5d 206 {
group-onsemi 0:098463de4c5d 207 obj->spi->CFG &= ~(1 << 0);
group-onsemi 0:098463de4c5d 208 }
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 static inline void spi_enable(spi_t *obj)
group-onsemi 0:098463de4c5d 211 {
group-onsemi 0:098463de4c5d 212 obj->spi->CFG |= (1 << 0);
group-onsemi 0:098463de4c5d 213 }
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 static inline int spi_readable(spi_t *obj)
group-onsemi 0:098463de4c5d 216 {
group-onsemi 0:098463de4c5d 217 return obj->spi->STAT & (1 << 0);
group-onsemi 0:098463de4c5d 218 }
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 static inline int spi_writeable(spi_t *obj)
group-onsemi 0:098463de4c5d 221 {
group-onsemi 0:098463de4c5d 222 return obj->spi->STAT & (1 << 1);
group-onsemi 0:098463de4c5d 223 }
group-onsemi 0:098463de4c5d 224
group-onsemi 0:098463de4c5d 225 static inline void spi_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 226 {
group-onsemi 0:098463de4c5d 227 while (!spi_writeable(obj));
group-onsemi 0:098463de4c5d 228 // end of transfer
group-onsemi 0:098463de4c5d 229 obj->spi->TXCTL |= (1 << 20);
group-onsemi 0:098463de4c5d 230 obj->spi->TXDAT = (value & 0xffff);
group-onsemi 0:098463de4c5d 231 }
group-onsemi 0:098463de4c5d 232
group-onsemi 0:098463de4c5d 233 static inline int spi_read(spi_t *obj)
group-onsemi 0:098463de4c5d 234 {
group-onsemi 0:098463de4c5d 235 while (!spi_readable(obj));
group-onsemi 0:098463de4c5d 236 return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
group-onsemi 0:098463de4c5d 237 }
group-onsemi 0:098463de4c5d 238
group-onsemi 0:098463de4c5d 239 int spi_busy(spi_t *obj)
group-onsemi 0:098463de4c5d 240 {
group-onsemi 0:098463de4c5d 241 // checking RXOV(Receiver Overrun interrupt flag)
group-onsemi 0:098463de4c5d 242 return obj->spi->STAT & (1 << 2);
group-onsemi 0:098463de4c5d 243 }
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 int spi_master_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 246 {
group-onsemi 0:098463de4c5d 247 spi_write(obj, value);
group-onsemi 0:098463de4c5d 248 return spi_read(obj);
group-onsemi 0:098463de4c5d 249 }
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 int spi_slave_receive(spi_t *obj)
group-onsemi 0:098463de4c5d 252 {
group-onsemi 0:098463de4c5d 253 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
group-onsemi 0:098463de4c5d 254 }
group-onsemi 0:098463de4c5d 255
group-onsemi 0:098463de4c5d 256 int spi_slave_read(spi_t *obj)
group-onsemi 0:098463de4c5d 257 {
group-onsemi 0:098463de4c5d 258 return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
group-onsemi 0:098463de4c5d 259 }
group-onsemi 0:098463de4c5d 260
group-onsemi 0:098463de4c5d 261 void spi_slave_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 262 {
group-onsemi 0:098463de4c5d 263 while (spi_writeable(obj) == 0) ;
group-onsemi 0:098463de4c5d 264 obj->spi->TXDAT = value;
group-onsemi 0:098463de4c5d 265 }