ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NUVOTON/TARGET_M451/dma_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

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group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2015-2016 Nuvoton
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #include "dma_api.h"
group-onsemi 0:098463de4c5d 18 #include "string.h"
group-onsemi 0:098463de4c5d 19 #include "cmsis.h"
group-onsemi 0:098463de4c5d 20 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 21 #include "PeripheralNames.h"
group-onsemi 0:098463de4c5d 22 #include "nu_modutil.h"
group-onsemi 0:098463de4c5d 23 #include "nu_bitutil.h"
group-onsemi 0:098463de4c5d 24 #include "dma.h"
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 struct nu_dma_chn_s {
group-onsemi 0:098463de4c5d 27 void (*handler)(uint32_t, uint32_t);
group-onsemi 0:098463de4c5d 28 uint32_t id;
group-onsemi 0:098463de4c5d 29 uint32_t event;
group-onsemi 0:098463de4c5d 30 };
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 static int dma_inited = 0;
group-onsemi 0:098463de4c5d 33 static uint32_t dma_chn_mask = 0;
group-onsemi 0:098463de4c5d 34 static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX];
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 static void pdma_vec(void);
group-onsemi 0:098463de4c5d 37 static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 void dma_init(void)
group-onsemi 0:098463de4c5d 41 {
group-onsemi 0:098463de4c5d 42 if (dma_inited) {
group-onsemi 0:098463de4c5d 43 return;
group-onsemi 0:098463de4c5d 44 }
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 dma_inited = 1;
group-onsemi 0:098463de4c5d 47 dma_chn_mask = 0;
group-onsemi 0:098463de4c5d 48 memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 // Reset this module
group-onsemi 0:098463de4c5d 51 SYS_ResetModule(dma_modinit.rsetidx);
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 // Enable IP clock
group-onsemi 0:098463de4c5d 54 CLK_EnableModuleClock(dma_modinit.clkidx);
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 PDMA_Open(0);
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
group-onsemi 0:098463de4c5d 59 NVIC_EnableIRQ(dma_modinit.irq_n);
group-onsemi 0:098463de4c5d 60 }
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 int dma_channel_allocate(uint32_t capabilities)
group-onsemi 0:098463de4c5d 63 {
group-onsemi 0:098463de4c5d 64 if (! dma_inited) {
group-onsemi 0:098463de4c5d 65 dma_init();
group-onsemi 0:098463de4c5d 66 }
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 #if 1
group-onsemi 0:098463de4c5d 69 int i = nu_cto(dma_chn_mask);
group-onsemi 0:098463de4c5d 70 if (i != 32) {
group-onsemi 0:098463de4c5d 71 dma_chn_mask |= 1 << i;
group-onsemi 0:098463de4c5d 72 memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
group-onsemi 0:098463de4c5d 73 return i;
group-onsemi 0:098463de4c5d 74 }
group-onsemi 0:098463de4c5d 75 #else
group-onsemi 0:098463de4c5d 76 int i;
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 for (i = 0; i < PDMA_CH_MAX; i ++) {
group-onsemi 0:098463de4c5d 79 if ((dma_chn_mask & (1 << i)) == 0) {
group-onsemi 0:098463de4c5d 80 // Channel available
group-onsemi 0:098463de4c5d 81 dma_chn_mask |= 1 << i;
group-onsemi 0:098463de4c5d 82 memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
group-onsemi 0:098463de4c5d 83 return i;
group-onsemi 0:098463de4c5d 84 }
group-onsemi 0:098463de4c5d 85 }
group-onsemi 0:098463de4c5d 86 #endif
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 // No channel available
group-onsemi 0:098463de4c5d 89 return DMA_ERROR_OUT_OF_CHANNELS;
group-onsemi 0:098463de4c5d 90 }
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 int dma_channel_free(int channelid)
group-onsemi 0:098463de4c5d 93 {
group-onsemi 0:098463de4c5d 94 if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
group-onsemi 0:098463de4c5d 95 dma_chn_mask &= ~(1 << channelid);
group-onsemi 0:098463de4c5d 96 }
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 return 0;
group-onsemi 0:098463de4c5d 99 }
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
group-onsemi 0:098463de4c5d 102 {
group-onsemi 0:098463de4c5d 103 MBED_ASSERT(dma_chn_mask & (1 << channelid));
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler;
group-onsemi 0:098463de4c5d 106 dma_chn_arr[channelid].id = id;
group-onsemi 0:098463de4c5d 107 dma_chn_arr[channelid].event = event;
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 // Set interrupt vector if someone has removed it.
group-onsemi 0:098463de4c5d 110 NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
group-onsemi 0:098463de4c5d 111 NVIC_EnableIRQ(dma_modinit.irq_n);
group-onsemi 0:098463de4c5d 112 }
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 static void pdma_vec(void)
group-onsemi 0:098463de4c5d 115 {
group-onsemi 0:098463de4c5d 116 uint32_t intsts = PDMA_GET_INT_STATUS();
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 // Abort
group-onsemi 0:098463de4c5d 119 if (intsts & PDMA_INTSTS_ABTIF_Msk) {
group-onsemi 0:098463de4c5d 120 uint32_t abtsts = PDMA_GET_ABORT_STS();
group-onsemi 0:098463de4c5d 121 // Clear all Abort flags
group-onsemi 0:098463de4c5d 122 PDMA_CLR_ABORT_FLAG(abtsts);
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 while (abtsts) {
group-onsemi 0:098463de4c5d 125 int chn_id = nu_ctz(abtsts);
group-onsemi 0:098463de4c5d 126 if (dma_chn_mask & (1 << chn_id)) {
group-onsemi 0:098463de4c5d 127 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
group-onsemi 0:098463de4c5d 128 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
group-onsemi 0:098463de4c5d 129 dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
group-onsemi 0:098463de4c5d 130 }
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132 abtsts &= ~(1 << chn_id);
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134 }
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 // Transfer done
group-onsemi 0:098463de4c5d 137 if (intsts & PDMA_INTSTS_TDIF_Msk) {
group-onsemi 0:098463de4c5d 138 uint32_t tdsts = PDMA_GET_TD_STS();
group-onsemi 0:098463de4c5d 139 // Clear all transfer done flags
group-onsemi 0:098463de4c5d 140 PDMA_CLR_TD_FLAG(tdsts);
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 while (tdsts) {
group-onsemi 0:098463de4c5d 143 int chn_id = nu_ctz(tdsts);
group-onsemi 0:098463de4c5d 144 if (dma_chn_mask & (1 << chn_id)) {
group-onsemi 0:098463de4c5d 145 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
group-onsemi 0:098463de4c5d 146 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
group-onsemi 0:098463de4c5d 147 dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
group-onsemi 0:098463de4c5d 148 }
group-onsemi 0:098463de4c5d 149 }
group-onsemi 0:098463de4c5d 150 tdsts &= ~(1 << chn_id);
group-onsemi 0:098463de4c5d 151 }
group-onsemi 0:098463de4c5d 152 }
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 // Table empty
group-onsemi 0:098463de4c5d 155 if (intsts & PDMA_INTSTS_TEIF_Msk) {
group-onsemi 0:098463de4c5d 156 uint32_t scatsts = PDMA_GET_EMPTY_STS();
group-onsemi 0:098463de4c5d 157 // Clear all table empty flags
group-onsemi 0:098463de4c5d 158 PDMA_CLR_EMPTY_FLAG(scatsts);
group-onsemi 0:098463de4c5d 159 }
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 // Timeout
group-onsemi 0:098463de4c5d 162 uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk;
group-onsemi 0:098463de4c5d 163 if (reqto) {
group-onsemi 0:098463de4c5d 164 // Clear all Timeout flags
group-onsemi 0:098463de4c5d 165 PDMA->INTSTS = reqto;
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 while (reqto) {
group-onsemi 0:098463de4c5d 168 int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFn_Pos;
group-onsemi 0:098463de4c5d 169 if (dma_chn_mask & (1 << chn_id)) {
group-onsemi 0:098463de4c5d 170 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
group-onsemi 0:098463de4c5d 171 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
group-onsemi 0:098463de4c5d 172 dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174 }
group-onsemi 0:098463de4c5d 175 reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos));
group-onsemi 0:098463de4c5d 176 }
group-onsemi 0:098463de4c5d 177 }
group-onsemi 0:098463de4c5d 178 }