ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "device.h"
group-onsemi 0:098463de4c5d 35 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 36 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 /*
group-onsemi 0:098463de4c5d 39 * To select a peripheral function on Maxim microcontrollers, multiple
group-onsemi 0:098463de4c5d 40 * configurations must be made. The mbed PinMap structure only includes one
group-onsemi 0:098463de4c5d 41 * data member to hold this information. To extend the configuration storage,
group-onsemi 0:098463de4c5d 42 * the "function" data member is used as a pointer to a pin_function_t
group-onsemi 0:098463de4c5d 43 * structure. This structure is defined in objects.h. The definitions below
group-onsemi 0:098463de4c5d 44 * include the creation of the pin_function_t structures and the assignment of
group-onsemi 0:098463de4c5d 45 * the pointers to the "function" data members.
group-onsemi 0:098463de4c5d 46 */
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 #ifdef TOOLCHAIN_ARM_STD
group-onsemi 0:098463de4c5d 49 #pragma diag_suppress 1296
group-onsemi 0:098463de4c5d 50 #endif
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 /************I2C***************/
group-onsemi 0:098463de4c5d 53 const PinMap PinMap_I2C_SDA[] = {
group-onsemi 0:098463de4c5d 54 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
group-onsemi 0:098463de4c5d 55 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
group-onsemi 0:098463de4c5d 56 { NC, NC, 0 }
group-onsemi 0:098463de4c5d 57 };
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 const PinMap PinMap_I2C_SCL[] = {
group-onsemi 0:098463de4c5d 60 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
group-onsemi 0:098463de4c5d 61 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
group-onsemi 0:098463de4c5d 62 { NC, NC, 0 }
group-onsemi 0:098463de4c5d 63 };
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 /************UART***************/
group-onsemi 0:098463de4c5d 66 const PinMap PinMap_UART_TX[] = {
group-onsemi 0:098463de4c5d 67 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 68 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 69 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 70 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 71 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 72 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 73 { NC, NC, 0 }
group-onsemi 0:098463de4c5d 74 };
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 const PinMap PinMap_UART_RX[] = {
group-onsemi 0:098463de4c5d 77 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 78 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 79 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 80 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 81 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 82 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
group-onsemi 0:098463de4c5d 83 { NC, NC, 0 }
group-onsemi 0:098463de4c5d 84 };
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 const PinMap PinMap_UART_CTS[] = {
group-onsemi 0:098463de4c5d 87 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
group-onsemi 0:098463de4c5d 88 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
group-onsemi 0:098463de4c5d 89 { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
group-onsemi 0:098463de4c5d 90 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
group-onsemi 0:098463de4c5d 91 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
group-onsemi 0:098463de4c5d 92 { NC, NC, 0 }
group-onsemi 0:098463de4c5d 93 };
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 const PinMap PinMap_UART_RTS[] = {
group-onsemi 0:098463de4c5d 96 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
group-onsemi 0:098463de4c5d 97 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
group-onsemi 0:098463de4c5d 98 { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
group-onsemi 0:098463de4c5d 99 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
group-onsemi 0:098463de4c5d 100 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
group-onsemi 0:098463de4c5d 101 { NC, NC, 0 }
group-onsemi 0:098463de4c5d 102 };
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 /************SPI***************/
group-onsemi 0:098463de4c5d 105 const PinMap PinMap_SPI_SCLK[] = {
group-onsemi 0:098463de4c5d 106 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
group-onsemi 0:098463de4c5d 107 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
group-onsemi 0:098463de4c5d 108 { NC, NC, 0}
group-onsemi 0:098463de4c5d 109 };
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 const PinMap PinMap_SPI_MOSI[] = {
group-onsemi 0:098463de4c5d 112 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
group-onsemi 0:098463de4c5d 113 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
group-onsemi 0:098463de4c5d 114 { NC, NC, 0}
group-onsemi 0:098463de4c5d 115 };
group-onsemi 0:098463de4c5d 116
group-onsemi 0:098463de4c5d 117 const PinMap PinMap_SPI_MISO[] = {
group-onsemi 0:098463de4c5d 118 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
group-onsemi 0:098463de4c5d 119 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
group-onsemi 0:098463de4c5d 120 { NC, NC, 0}
group-onsemi 0:098463de4c5d 121 };
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 const PinMap PinMap_SPI_SSEL[] = {
group-onsemi 0:098463de4c5d 124 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
group-onsemi 0:098463de4c5d 125 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
group-onsemi 0:098463de4c5d 126 { NC, NC, 0}
group-onsemi 0:098463de4c5d 127 };
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 /************PWM***************/
group-onsemi 0:098463de4c5d 130 const PinMap PinMap_PWM[] = {
group-onsemi 0:098463de4c5d 131 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
group-onsemi 0:098463de4c5d 132 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
group-onsemi 0:098463de4c5d 133 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
group-onsemi 0:098463de4c5d 134 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
group-onsemi 0:098463de4c5d 135 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
group-onsemi 0:098463de4c5d 136 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
group-onsemi 0:098463de4c5d 137 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
group-onsemi 0:098463de4c5d 138 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
group-onsemi 0:098463de4c5d 141 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
group-onsemi 0:098463de4c5d 142 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
group-onsemi 0:098463de4c5d 143 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
group-onsemi 0:098463de4c5d 144 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
group-onsemi 0:098463de4c5d 145 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
group-onsemi 0:098463de4c5d 146 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
group-onsemi 0:098463de4c5d 147 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
group-onsemi 0:098463de4c5d 150 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
group-onsemi 0:098463de4c5d 151 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
group-onsemi 0:098463de4c5d 152 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
group-onsemi 0:098463de4c5d 153 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
group-onsemi 0:098463de4c5d 154 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
group-onsemi 0:098463de4c5d 155 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
group-onsemi 0:098463de4c5d 156 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 {NC, NC, 0}
group-onsemi 0:098463de4c5d 159 };
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 /************ADC***************/
group-onsemi 0:098463de4c5d 162 const PinMap PinMap_ADC[] = {
group-onsemi 0:098463de4c5d 163 {AIN_0P, ADC, 0},
group-onsemi 0:098463de4c5d 164 {AIN_1P, ADC, 0},
group-onsemi 0:098463de4c5d 165 {AIN_2P, ADC, 0},
group-onsemi 0:098463de4c5d 166 {AIN_3P, ADC, 0},
group-onsemi 0:098463de4c5d 167 {AIN_4P, ADC, 0},
group-onsemi 0:098463de4c5d 168 {AIN_5P, ADC, 0},
group-onsemi 0:098463de4c5d 169 {AIN_0N, ADC, 0},
group-onsemi 0:098463de4c5d 170 {AIN_1N, ADC, 0},
group-onsemi 0:098463de4c5d 171 {AIN_2N, ADC, 0},
group-onsemi 0:098463de4c5d 172 {AIN_3N, ADC, 0},
group-onsemi 0:098463de4c5d 173 {AIN_4N, ADC, 0},
group-onsemi 0:098463de4c5d 174 {AIN_5N, ADC, 0},
group-onsemi 0:098463de4c5d 175 {AIN_0D, ADC, 1},
group-onsemi 0:098463de4c5d 176 {AIN_1D, ADC, 1},
group-onsemi 0:098463de4c5d 177 {AIN_2D, ADC, 1},
group-onsemi 0:098463de4c5d 178 {AIN_3D, ADC, 1},
group-onsemi 0:098463de4c5d 179 {AIN_4D, ADC, 1},
group-onsemi 0:098463de4c5d 180 {AIN_5D, ADC, 1},
group-onsemi 0:098463de4c5d 181 {NC, NC, 0}
group-onsemi 0:098463de4c5d 182 };
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 /************DAC***************/
group-onsemi 0:098463de4c5d 185 const PinMap PinMap_DAC[] = {
group-onsemi 0:098463de4c5d 186 {AOUT_AO, DAC0, 0},
group-onsemi 0:098463de4c5d 187 {AOUT_BO, DAC1, 0},
group-onsemi 0:098463de4c5d 188 {AOUT_CO, DAC2, 0},
group-onsemi 0:098463de4c5d 189 {AOUT_DO, DAC3, 0},
group-onsemi 0:098463de4c5d 190 {NC, NC, 0}
group-onsemi 0:098463de4c5d 191 };