5.2.1 - Updated I2C files
Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510
cmsis/core_sc000.h@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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group-onsemi | 0:098463de4c5d | 1 | /**************************************************************************//** |
group-onsemi | 0:098463de4c5d | 2 | * @file core_sc000.h |
group-onsemi | 0:098463de4c5d | 3 | * @brief CMSIS SC000 Core Peripheral Access Layer Header File |
group-onsemi | 0:098463de4c5d | 4 | * @version V4.10 |
group-onsemi | 0:098463de4c5d | 5 | * @date 18. March 2015 |
group-onsemi | 0:098463de4c5d | 6 | * |
group-onsemi | 0:098463de4c5d | 7 | * @note |
group-onsemi | 0:098463de4c5d | 8 | * |
group-onsemi | 0:098463de4c5d | 9 | ******************************************************************************/ |
group-onsemi | 0:098463de4c5d | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
group-onsemi | 0:098463de4c5d | 11 | |
group-onsemi | 0:098463de4c5d | 12 | All rights reserved. |
group-onsemi | 0:098463de4c5d | 13 | Redistribution and use in source and binary forms, with or without |
group-onsemi | 0:098463de4c5d | 14 | modification, are permitted provided that the following conditions are met: |
group-onsemi | 0:098463de4c5d | 15 | - Redistributions of source code must retain the above copyright |
group-onsemi | 0:098463de4c5d | 16 | notice, this list of conditions and the following disclaimer. |
group-onsemi | 0:098463de4c5d | 17 | - Redistributions in binary form must reproduce the above copyright |
group-onsemi | 0:098463de4c5d | 18 | notice, this list of conditions and the following disclaimer in the |
group-onsemi | 0:098463de4c5d | 19 | documentation and/or other materials provided with the distribution. |
group-onsemi | 0:098463de4c5d | 20 | - Neither the name of ARM nor the names of its contributors may be used |
group-onsemi | 0:098463de4c5d | 21 | to endorse or promote products derived from this software without |
group-onsemi | 0:098463de4c5d | 22 | specific prior written permission. |
group-onsemi | 0:098463de4c5d | 23 | * |
group-onsemi | 0:098463de4c5d | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
group-onsemi | 0:098463de4c5d | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
group-onsemi | 0:098463de4c5d | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
group-onsemi | 0:098463de4c5d | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
group-onsemi | 0:098463de4c5d | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
group-onsemi | 0:098463de4c5d | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
group-onsemi | 0:098463de4c5d | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
group-onsemi | 0:098463de4c5d | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
group-onsemi | 0:098463de4c5d | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
group-onsemi | 0:098463de4c5d | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
group-onsemi | 0:098463de4c5d | 34 | POSSIBILITY OF SUCH DAMAGE. |
group-onsemi | 0:098463de4c5d | 35 | ---------------------------------------------------------------------------*/ |
group-onsemi | 0:098463de4c5d | 36 | |
group-onsemi | 0:098463de4c5d | 37 | |
group-onsemi | 0:098463de4c5d | 38 | #if defined ( __ICCARM__ ) |
group-onsemi | 0:098463de4c5d | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
group-onsemi | 0:098463de4c5d | 40 | #endif |
group-onsemi | 0:098463de4c5d | 41 | |
group-onsemi | 0:098463de4c5d | 42 | #ifndef __CORE_SC000_H_GENERIC |
group-onsemi | 0:098463de4c5d | 43 | #define __CORE_SC000_H_GENERIC |
group-onsemi | 0:098463de4c5d | 44 | |
group-onsemi | 0:098463de4c5d | 45 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 46 | extern "C" { |
group-onsemi | 0:098463de4c5d | 47 | #endif |
group-onsemi | 0:098463de4c5d | 48 | |
group-onsemi | 0:098463de4c5d | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
group-onsemi | 0:098463de4c5d | 50 | CMSIS violates the following MISRA-C:2004 rules: |
group-onsemi | 0:098463de4c5d | 51 | |
group-onsemi | 0:098463de4c5d | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
group-onsemi | 0:098463de4c5d | 53 | Function definitions in header files are used to allow 'inlining'. |
group-onsemi | 0:098463de4c5d | 54 | |
group-onsemi | 0:098463de4c5d | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
group-onsemi | 0:098463de4c5d | 56 | Unions are used for effective representation of core registers. |
group-onsemi | 0:098463de4c5d | 57 | |
group-onsemi | 0:098463de4c5d | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
group-onsemi | 0:098463de4c5d | 59 | Function-like macros are used to allow more efficient code. |
group-onsemi | 0:098463de4c5d | 60 | */ |
group-onsemi | 0:098463de4c5d | 61 | |
group-onsemi | 0:098463de4c5d | 62 | |
group-onsemi | 0:098463de4c5d | 63 | /******************************************************************************* |
group-onsemi | 0:098463de4c5d | 64 | * CMSIS definitions |
group-onsemi | 0:098463de4c5d | 65 | ******************************************************************************/ |
group-onsemi | 0:098463de4c5d | 66 | /** \ingroup SC000 |
group-onsemi | 0:098463de4c5d | 67 | @{ |
group-onsemi | 0:098463de4c5d | 68 | */ |
group-onsemi | 0:098463de4c5d | 69 | |
group-onsemi | 0:098463de4c5d | 70 | /* CMSIS SC000 definitions */ |
group-onsemi | 0:098463de4c5d | 71 | #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
group-onsemi | 0:098463de4c5d | 72 | #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
group-onsemi | 0:098463de4c5d | 73 | #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ |
group-onsemi | 0:098463de4c5d | 74 | __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
group-onsemi | 0:098463de4c5d | 75 | |
group-onsemi | 0:098463de4c5d | 76 | #define __CORTEX_SC (000) /*!< Cortex secure core */ |
group-onsemi | 0:098463de4c5d | 77 | |
group-onsemi | 0:098463de4c5d | 78 | |
group-onsemi | 0:098463de4c5d | 79 | #if defined ( __CC_ARM ) |
group-onsemi | 0:098463de4c5d | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
group-onsemi | 0:098463de4c5d | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
group-onsemi | 0:098463de4c5d | 82 | #define __STATIC_INLINE static __inline |
group-onsemi | 0:098463de4c5d | 83 | |
group-onsemi | 0:098463de4c5d | 84 | #elif defined ( __GNUC__ ) |
group-onsemi | 0:098463de4c5d | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
group-onsemi | 0:098463de4c5d | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
group-onsemi | 0:098463de4c5d | 87 | #define __STATIC_INLINE static inline |
group-onsemi | 0:098463de4c5d | 88 | |
group-onsemi | 0:098463de4c5d | 89 | #elif defined ( __ICCARM__ ) |
group-onsemi | 0:098463de4c5d | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
group-onsemi | 0:098463de4c5d | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
group-onsemi | 0:098463de4c5d | 92 | #define __STATIC_INLINE static inline |
group-onsemi | 0:098463de4c5d | 93 | |
group-onsemi | 0:098463de4c5d | 94 | #elif defined ( __TMS470__ ) |
group-onsemi | 0:098463de4c5d | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
group-onsemi | 0:098463de4c5d | 96 | #define __STATIC_INLINE static inline |
group-onsemi | 0:098463de4c5d | 97 | |
group-onsemi | 0:098463de4c5d | 98 | #elif defined ( __TASKING__ ) |
group-onsemi | 0:098463de4c5d | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
group-onsemi | 0:098463de4c5d | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
group-onsemi | 0:098463de4c5d | 101 | #define __STATIC_INLINE static inline |
group-onsemi | 0:098463de4c5d | 102 | |
group-onsemi | 0:098463de4c5d | 103 | #elif defined ( __CSMC__ ) |
group-onsemi | 0:098463de4c5d | 104 | #define __packed |
group-onsemi | 0:098463de4c5d | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
group-onsemi | 0:098463de4c5d | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
group-onsemi | 0:098463de4c5d | 107 | #define __STATIC_INLINE static inline |
group-onsemi | 0:098463de4c5d | 108 | |
group-onsemi | 0:098463de4c5d | 109 | #endif |
group-onsemi | 0:098463de4c5d | 110 | |
group-onsemi | 0:098463de4c5d | 111 | /** __FPU_USED indicates whether an FPU is used or not. |
group-onsemi | 0:098463de4c5d | 112 | This core does not support an FPU at all |
group-onsemi | 0:098463de4c5d | 113 | */ |
group-onsemi | 0:098463de4c5d | 114 | #define __FPU_USED 0 |
group-onsemi | 0:098463de4c5d | 115 | |
group-onsemi | 0:098463de4c5d | 116 | #if defined ( __CC_ARM ) |
group-onsemi | 0:098463de4c5d | 117 | #if defined __TARGET_FPU_VFP |
group-onsemi | 0:098463de4c5d | 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
group-onsemi | 0:098463de4c5d | 119 | #endif |
group-onsemi | 0:098463de4c5d | 120 | |
group-onsemi | 0:098463de4c5d | 121 | #elif defined ( __GNUC__ ) |
group-onsemi | 0:098463de4c5d | 122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
group-onsemi | 0:098463de4c5d | 123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
group-onsemi | 0:098463de4c5d | 124 | #endif |
group-onsemi | 0:098463de4c5d | 125 | |
group-onsemi | 0:098463de4c5d | 126 | #elif defined ( __ICCARM__ ) |
group-onsemi | 0:098463de4c5d | 127 | #if defined __ARMVFP__ |
group-onsemi | 0:098463de4c5d | 128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
group-onsemi | 0:098463de4c5d | 129 | #endif |
group-onsemi | 0:098463de4c5d | 130 | |
group-onsemi | 0:098463de4c5d | 131 | #elif defined ( __TMS470__ ) |
group-onsemi | 0:098463de4c5d | 132 | #if defined __TI__VFP_SUPPORT____ |
group-onsemi | 0:098463de4c5d | 133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
group-onsemi | 0:098463de4c5d | 134 | #endif |
group-onsemi | 0:098463de4c5d | 135 | |
group-onsemi | 0:098463de4c5d | 136 | #elif defined ( __TASKING__ ) |
group-onsemi | 0:098463de4c5d | 137 | #if defined __FPU_VFP__ |
group-onsemi | 0:098463de4c5d | 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
group-onsemi | 0:098463de4c5d | 139 | #endif |
group-onsemi | 0:098463de4c5d | 140 | |
group-onsemi | 0:098463de4c5d | 141 | #elif defined ( __CSMC__ ) /* Cosmic */ |
group-onsemi | 0:098463de4c5d | 142 | #if ( __CSMC__ & 0x400) // FPU present for parser |
group-onsemi | 0:098463de4c5d | 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
group-onsemi | 0:098463de4c5d | 144 | #endif |
group-onsemi | 0:098463de4c5d | 145 | #endif |
group-onsemi | 0:098463de4c5d | 146 | |
group-onsemi | 0:098463de4c5d | 147 | #include <stdint.h> /* standard types definitions */ |
group-onsemi | 0:098463de4c5d | 148 | #include <core_cmInstr.h> /* Core Instruction Access */ |
group-onsemi | 0:098463de4c5d | 149 | #include <core_cmFunc.h> /* Core Function Access */ |
group-onsemi | 0:098463de4c5d | 150 | |
group-onsemi | 0:098463de4c5d | 151 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 152 | } |
group-onsemi | 0:098463de4c5d | 153 | #endif |
group-onsemi | 0:098463de4c5d | 154 | |
group-onsemi | 0:098463de4c5d | 155 | #endif /* __CORE_SC000_H_GENERIC */ |
group-onsemi | 0:098463de4c5d | 156 | |
group-onsemi | 0:098463de4c5d | 157 | #ifndef __CMSIS_GENERIC |
group-onsemi | 0:098463de4c5d | 158 | |
group-onsemi | 0:098463de4c5d | 159 | #ifndef __CORE_SC000_H_DEPENDANT |
group-onsemi | 0:098463de4c5d | 160 | #define __CORE_SC000_H_DEPENDANT |
group-onsemi | 0:098463de4c5d | 161 | |
group-onsemi | 0:098463de4c5d | 162 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 163 | extern "C" { |
group-onsemi | 0:098463de4c5d | 164 | #endif |
group-onsemi | 0:098463de4c5d | 165 | |
group-onsemi | 0:098463de4c5d | 166 | /* check device defines and use defaults */ |
group-onsemi | 0:098463de4c5d | 167 | #if defined __CHECK_DEVICE_DEFINES |
group-onsemi | 0:098463de4c5d | 168 | #ifndef __SC000_REV |
group-onsemi | 0:098463de4c5d | 169 | #define __SC000_REV 0x0000 |
group-onsemi | 0:098463de4c5d | 170 | #warning "__SC000_REV not defined in device header file; using default!" |
group-onsemi | 0:098463de4c5d | 171 | #endif |
group-onsemi | 0:098463de4c5d | 172 | |
group-onsemi | 0:098463de4c5d | 173 | #ifndef __MPU_PRESENT |
group-onsemi | 0:098463de4c5d | 174 | #define __MPU_PRESENT 0 |
group-onsemi | 0:098463de4c5d | 175 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
group-onsemi | 0:098463de4c5d | 176 | #endif |
group-onsemi | 0:098463de4c5d | 177 | |
group-onsemi | 0:098463de4c5d | 178 | #ifndef __NVIC_PRIO_BITS |
group-onsemi | 0:098463de4c5d | 179 | #define __NVIC_PRIO_BITS 2 |
group-onsemi | 0:098463de4c5d | 180 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
group-onsemi | 0:098463de4c5d | 181 | #endif |
group-onsemi | 0:098463de4c5d | 182 | |
group-onsemi | 0:098463de4c5d | 183 | #ifndef __Vendor_SysTickConfig |
group-onsemi | 0:098463de4c5d | 184 | #define __Vendor_SysTickConfig 0 |
group-onsemi | 0:098463de4c5d | 185 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
group-onsemi | 0:098463de4c5d | 186 | #endif |
group-onsemi | 0:098463de4c5d | 187 | #endif |
group-onsemi | 0:098463de4c5d | 188 | |
group-onsemi | 0:098463de4c5d | 189 | /* IO definitions (access restrictions to peripheral registers) */ |
group-onsemi | 0:098463de4c5d | 190 | /** |
group-onsemi | 0:098463de4c5d | 191 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
group-onsemi | 0:098463de4c5d | 192 | |
group-onsemi | 0:098463de4c5d | 193 | <strong>IO Type Qualifiers</strong> are used |
group-onsemi | 0:098463de4c5d | 194 | \li to specify the access to peripheral variables. |
group-onsemi | 0:098463de4c5d | 195 | \li for automatic generation of peripheral register debug information. |
group-onsemi | 0:098463de4c5d | 196 | */ |
group-onsemi | 0:098463de4c5d | 197 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 198 | #define __I volatile /*!< Defines 'read only' permissions */ |
group-onsemi | 0:098463de4c5d | 199 | #else |
group-onsemi | 0:098463de4c5d | 200 | #define __I volatile const /*!< Defines 'read only' permissions */ |
group-onsemi | 0:098463de4c5d | 201 | #endif |
group-onsemi | 0:098463de4c5d | 202 | #define __O volatile /*!< Defines 'write only' permissions */ |
group-onsemi | 0:098463de4c5d | 203 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
group-onsemi | 0:098463de4c5d | 204 | |
group-onsemi | 0:098463de4c5d | 205 | /*@} end of group SC000 */ |
group-onsemi | 0:098463de4c5d | 206 | |
group-onsemi | 0:098463de4c5d | 207 | |
group-onsemi | 0:098463de4c5d | 208 | |
group-onsemi | 0:098463de4c5d | 209 | /******************************************************************************* |
group-onsemi | 0:098463de4c5d | 210 | * Register Abstraction |
group-onsemi | 0:098463de4c5d | 211 | Core Register contain: |
group-onsemi | 0:098463de4c5d | 212 | - Core Register |
group-onsemi | 0:098463de4c5d | 213 | - Core NVIC Register |
group-onsemi | 0:098463de4c5d | 214 | - Core SCB Register |
group-onsemi | 0:098463de4c5d | 215 | - Core SysTick Register |
group-onsemi | 0:098463de4c5d | 216 | - Core MPU Register |
group-onsemi | 0:098463de4c5d | 217 | ******************************************************************************/ |
group-onsemi | 0:098463de4c5d | 218 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
group-onsemi | 0:098463de4c5d | 219 | \brief Type definitions and defines for Cortex-M processor based devices. |
group-onsemi | 0:098463de4c5d | 220 | */ |
group-onsemi | 0:098463de4c5d | 221 | |
group-onsemi | 0:098463de4c5d | 222 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 223 | \defgroup CMSIS_CORE Status and Control Registers |
group-onsemi | 0:098463de4c5d | 224 | \brief Core Register type definitions. |
group-onsemi | 0:098463de4c5d | 225 | @{ |
group-onsemi | 0:098463de4c5d | 226 | */ |
group-onsemi | 0:098463de4c5d | 227 | |
group-onsemi | 0:098463de4c5d | 228 | /** \brief Union type to access the Application Program Status Register (APSR). |
group-onsemi | 0:098463de4c5d | 229 | */ |
group-onsemi | 0:098463de4c5d | 230 | typedef union |
group-onsemi | 0:098463de4c5d | 231 | { |
group-onsemi | 0:098463de4c5d | 232 | struct |
group-onsemi | 0:098463de4c5d | 233 | { |
group-onsemi | 0:098463de4c5d | 234 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
group-onsemi | 0:098463de4c5d | 235 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
group-onsemi | 0:098463de4c5d | 236 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
group-onsemi | 0:098463de4c5d | 237 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
group-onsemi | 0:098463de4c5d | 238 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
group-onsemi | 0:098463de4c5d | 239 | } b; /*!< Structure used for bit access */ |
group-onsemi | 0:098463de4c5d | 240 | uint32_t w; /*!< Type used for word access */ |
group-onsemi | 0:098463de4c5d | 241 | } APSR_Type; |
group-onsemi | 0:098463de4c5d | 242 | |
group-onsemi | 0:098463de4c5d | 243 | /* APSR Register Definitions */ |
group-onsemi | 0:098463de4c5d | 244 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
group-onsemi | 0:098463de4c5d | 245 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
group-onsemi | 0:098463de4c5d | 246 | |
group-onsemi | 0:098463de4c5d | 247 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
group-onsemi | 0:098463de4c5d | 248 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
group-onsemi | 0:098463de4c5d | 249 | |
group-onsemi | 0:098463de4c5d | 250 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
group-onsemi | 0:098463de4c5d | 251 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
group-onsemi | 0:098463de4c5d | 252 | |
group-onsemi | 0:098463de4c5d | 253 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
group-onsemi | 0:098463de4c5d | 254 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
group-onsemi | 0:098463de4c5d | 255 | |
group-onsemi | 0:098463de4c5d | 256 | |
group-onsemi | 0:098463de4c5d | 257 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
group-onsemi | 0:098463de4c5d | 258 | */ |
group-onsemi | 0:098463de4c5d | 259 | typedef union |
group-onsemi | 0:098463de4c5d | 260 | { |
group-onsemi | 0:098463de4c5d | 261 | struct |
group-onsemi | 0:098463de4c5d | 262 | { |
group-onsemi | 0:098463de4c5d | 263 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
group-onsemi | 0:098463de4c5d | 264 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
group-onsemi | 0:098463de4c5d | 265 | } b; /*!< Structure used for bit access */ |
group-onsemi | 0:098463de4c5d | 266 | uint32_t w; /*!< Type used for word access */ |
group-onsemi | 0:098463de4c5d | 267 | } IPSR_Type; |
group-onsemi | 0:098463de4c5d | 268 | |
group-onsemi | 0:098463de4c5d | 269 | /* IPSR Register Definitions */ |
group-onsemi | 0:098463de4c5d | 270 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
group-onsemi | 0:098463de4c5d | 271 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
group-onsemi | 0:098463de4c5d | 272 | |
group-onsemi | 0:098463de4c5d | 273 | |
group-onsemi | 0:098463de4c5d | 274 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
group-onsemi | 0:098463de4c5d | 275 | */ |
group-onsemi | 0:098463de4c5d | 276 | typedef union |
group-onsemi | 0:098463de4c5d | 277 | { |
group-onsemi | 0:098463de4c5d | 278 | struct |
group-onsemi | 0:098463de4c5d | 279 | { |
group-onsemi | 0:098463de4c5d | 280 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
group-onsemi | 0:098463de4c5d | 281 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
group-onsemi | 0:098463de4c5d | 282 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
group-onsemi | 0:098463de4c5d | 283 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
group-onsemi | 0:098463de4c5d | 284 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
group-onsemi | 0:098463de4c5d | 285 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
group-onsemi | 0:098463de4c5d | 286 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
group-onsemi | 0:098463de4c5d | 287 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
group-onsemi | 0:098463de4c5d | 288 | } b; /*!< Structure used for bit access */ |
group-onsemi | 0:098463de4c5d | 289 | uint32_t w; /*!< Type used for word access */ |
group-onsemi | 0:098463de4c5d | 290 | } xPSR_Type; |
group-onsemi | 0:098463de4c5d | 291 | |
group-onsemi | 0:098463de4c5d | 292 | /* xPSR Register Definitions */ |
group-onsemi | 0:098463de4c5d | 293 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
group-onsemi | 0:098463de4c5d | 294 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
group-onsemi | 0:098463de4c5d | 295 | |
group-onsemi | 0:098463de4c5d | 296 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
group-onsemi | 0:098463de4c5d | 297 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
group-onsemi | 0:098463de4c5d | 298 | |
group-onsemi | 0:098463de4c5d | 299 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
group-onsemi | 0:098463de4c5d | 300 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
group-onsemi | 0:098463de4c5d | 301 | |
group-onsemi | 0:098463de4c5d | 302 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
group-onsemi | 0:098463de4c5d | 303 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
group-onsemi | 0:098463de4c5d | 304 | |
group-onsemi | 0:098463de4c5d | 305 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
group-onsemi | 0:098463de4c5d | 306 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
group-onsemi | 0:098463de4c5d | 307 | |
group-onsemi | 0:098463de4c5d | 308 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
group-onsemi | 0:098463de4c5d | 309 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
group-onsemi | 0:098463de4c5d | 310 | |
group-onsemi | 0:098463de4c5d | 311 | |
group-onsemi | 0:098463de4c5d | 312 | /** \brief Union type to access the Control Registers (CONTROL). |
group-onsemi | 0:098463de4c5d | 313 | */ |
group-onsemi | 0:098463de4c5d | 314 | typedef union |
group-onsemi | 0:098463de4c5d | 315 | { |
group-onsemi | 0:098463de4c5d | 316 | struct |
group-onsemi | 0:098463de4c5d | 317 | { |
group-onsemi | 0:098463de4c5d | 318 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
group-onsemi | 0:098463de4c5d | 319 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
group-onsemi | 0:098463de4c5d | 320 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
group-onsemi | 0:098463de4c5d | 321 | } b; /*!< Structure used for bit access */ |
group-onsemi | 0:098463de4c5d | 322 | uint32_t w; /*!< Type used for word access */ |
group-onsemi | 0:098463de4c5d | 323 | } CONTROL_Type; |
group-onsemi | 0:098463de4c5d | 324 | |
group-onsemi | 0:098463de4c5d | 325 | /* CONTROL Register Definitions */ |
group-onsemi | 0:098463de4c5d | 326 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
group-onsemi | 0:098463de4c5d | 327 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
group-onsemi | 0:098463de4c5d | 328 | |
group-onsemi | 0:098463de4c5d | 329 | /*@} end of group CMSIS_CORE */ |
group-onsemi | 0:098463de4c5d | 330 | |
group-onsemi | 0:098463de4c5d | 331 | |
group-onsemi | 0:098463de4c5d | 332 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 333 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
group-onsemi | 0:098463de4c5d | 334 | \brief Type definitions for the NVIC Registers |
group-onsemi | 0:098463de4c5d | 335 | @{ |
group-onsemi | 0:098463de4c5d | 336 | */ |
group-onsemi | 0:098463de4c5d | 337 | |
group-onsemi | 0:098463de4c5d | 338 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
group-onsemi | 0:098463de4c5d | 339 | */ |
group-onsemi | 0:098463de4c5d | 340 | typedef struct |
group-onsemi | 0:098463de4c5d | 341 | { |
group-onsemi | 0:098463de4c5d | 342 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
group-onsemi | 0:098463de4c5d | 343 | uint32_t RESERVED0[31]; |
group-onsemi | 0:098463de4c5d | 344 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
group-onsemi | 0:098463de4c5d | 345 | uint32_t RSERVED1[31]; |
group-onsemi | 0:098463de4c5d | 346 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
group-onsemi | 0:098463de4c5d | 347 | uint32_t RESERVED2[31]; |
group-onsemi | 0:098463de4c5d | 348 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
group-onsemi | 0:098463de4c5d | 349 | uint32_t RESERVED3[31]; |
group-onsemi | 0:098463de4c5d | 350 | uint32_t RESERVED4[64]; |
group-onsemi | 0:098463de4c5d | 351 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
group-onsemi | 0:098463de4c5d | 352 | } NVIC_Type; |
group-onsemi | 0:098463de4c5d | 353 | |
group-onsemi | 0:098463de4c5d | 354 | /*@} end of group CMSIS_NVIC */ |
group-onsemi | 0:098463de4c5d | 355 | |
group-onsemi | 0:098463de4c5d | 356 | |
group-onsemi | 0:098463de4c5d | 357 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 358 | \defgroup CMSIS_SCB System Control Block (SCB) |
group-onsemi | 0:098463de4c5d | 359 | \brief Type definitions for the System Control Block Registers |
group-onsemi | 0:098463de4c5d | 360 | @{ |
group-onsemi | 0:098463de4c5d | 361 | */ |
group-onsemi | 0:098463de4c5d | 362 | |
group-onsemi | 0:098463de4c5d | 363 | /** \brief Structure type to access the System Control Block (SCB). |
group-onsemi | 0:098463de4c5d | 364 | */ |
group-onsemi | 0:098463de4c5d | 365 | typedef struct |
group-onsemi | 0:098463de4c5d | 366 | { |
group-onsemi | 0:098463de4c5d | 367 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
group-onsemi | 0:098463de4c5d | 368 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
group-onsemi | 0:098463de4c5d | 369 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
group-onsemi | 0:098463de4c5d | 370 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
group-onsemi | 0:098463de4c5d | 371 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
group-onsemi | 0:098463de4c5d | 372 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
group-onsemi | 0:098463de4c5d | 373 | uint32_t RESERVED0[1]; |
group-onsemi | 0:098463de4c5d | 374 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
group-onsemi | 0:098463de4c5d | 375 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
group-onsemi | 0:098463de4c5d | 376 | uint32_t RESERVED1[154]; |
group-onsemi | 0:098463de4c5d | 377 | __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ |
group-onsemi | 0:098463de4c5d | 378 | } SCB_Type; |
group-onsemi | 0:098463de4c5d | 379 | |
group-onsemi | 0:098463de4c5d | 380 | /* SCB CPUID Register Definitions */ |
group-onsemi | 0:098463de4c5d | 381 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
group-onsemi | 0:098463de4c5d | 382 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
group-onsemi | 0:098463de4c5d | 383 | |
group-onsemi | 0:098463de4c5d | 384 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
group-onsemi | 0:098463de4c5d | 385 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
group-onsemi | 0:098463de4c5d | 386 | |
group-onsemi | 0:098463de4c5d | 387 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
group-onsemi | 0:098463de4c5d | 388 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
group-onsemi | 0:098463de4c5d | 389 | |
group-onsemi | 0:098463de4c5d | 390 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
group-onsemi | 0:098463de4c5d | 391 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
group-onsemi | 0:098463de4c5d | 392 | |
group-onsemi | 0:098463de4c5d | 393 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
group-onsemi | 0:098463de4c5d | 394 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
group-onsemi | 0:098463de4c5d | 395 | |
group-onsemi | 0:098463de4c5d | 396 | /* SCB Interrupt Control State Register Definitions */ |
group-onsemi | 0:098463de4c5d | 397 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
group-onsemi | 0:098463de4c5d | 398 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
group-onsemi | 0:098463de4c5d | 399 | |
group-onsemi | 0:098463de4c5d | 400 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
group-onsemi | 0:098463de4c5d | 401 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
group-onsemi | 0:098463de4c5d | 402 | |
group-onsemi | 0:098463de4c5d | 403 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
group-onsemi | 0:098463de4c5d | 404 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
group-onsemi | 0:098463de4c5d | 405 | |
group-onsemi | 0:098463de4c5d | 406 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
group-onsemi | 0:098463de4c5d | 407 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
group-onsemi | 0:098463de4c5d | 408 | |
group-onsemi | 0:098463de4c5d | 409 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
group-onsemi | 0:098463de4c5d | 410 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
group-onsemi | 0:098463de4c5d | 411 | |
group-onsemi | 0:098463de4c5d | 412 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
group-onsemi | 0:098463de4c5d | 413 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
group-onsemi | 0:098463de4c5d | 414 | |
group-onsemi | 0:098463de4c5d | 415 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
group-onsemi | 0:098463de4c5d | 416 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
group-onsemi | 0:098463de4c5d | 417 | |
group-onsemi | 0:098463de4c5d | 418 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
group-onsemi | 0:098463de4c5d | 419 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
group-onsemi | 0:098463de4c5d | 420 | |
group-onsemi | 0:098463de4c5d | 421 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
group-onsemi | 0:098463de4c5d | 422 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
group-onsemi | 0:098463de4c5d | 423 | |
group-onsemi | 0:098463de4c5d | 424 | /* SCB Interrupt Control State Register Definitions */ |
group-onsemi | 0:098463de4c5d | 425 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
group-onsemi | 0:098463de4c5d | 426 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
group-onsemi | 0:098463de4c5d | 427 | |
group-onsemi | 0:098463de4c5d | 428 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
group-onsemi | 0:098463de4c5d | 429 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
group-onsemi | 0:098463de4c5d | 430 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
group-onsemi | 0:098463de4c5d | 431 | |
group-onsemi | 0:098463de4c5d | 432 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
group-onsemi | 0:098463de4c5d | 433 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
group-onsemi | 0:098463de4c5d | 434 | |
group-onsemi | 0:098463de4c5d | 435 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
group-onsemi | 0:098463de4c5d | 436 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
group-onsemi | 0:098463de4c5d | 437 | |
group-onsemi | 0:098463de4c5d | 438 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
group-onsemi | 0:098463de4c5d | 439 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
group-onsemi | 0:098463de4c5d | 440 | |
group-onsemi | 0:098463de4c5d | 441 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
group-onsemi | 0:098463de4c5d | 442 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
group-onsemi | 0:098463de4c5d | 443 | |
group-onsemi | 0:098463de4c5d | 444 | /* SCB System Control Register Definitions */ |
group-onsemi | 0:098463de4c5d | 445 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
group-onsemi | 0:098463de4c5d | 446 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
group-onsemi | 0:098463de4c5d | 447 | |
group-onsemi | 0:098463de4c5d | 448 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
group-onsemi | 0:098463de4c5d | 449 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
group-onsemi | 0:098463de4c5d | 450 | |
group-onsemi | 0:098463de4c5d | 451 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
group-onsemi | 0:098463de4c5d | 452 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
group-onsemi | 0:098463de4c5d | 453 | |
group-onsemi | 0:098463de4c5d | 454 | /* SCB Configuration Control Register Definitions */ |
group-onsemi | 0:098463de4c5d | 455 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
group-onsemi | 0:098463de4c5d | 456 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
group-onsemi | 0:098463de4c5d | 457 | |
group-onsemi | 0:098463de4c5d | 458 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
group-onsemi | 0:098463de4c5d | 459 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
group-onsemi | 0:098463de4c5d | 460 | |
group-onsemi | 0:098463de4c5d | 461 | /* SCB System Handler Control and State Register Definitions */ |
group-onsemi | 0:098463de4c5d | 462 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
group-onsemi | 0:098463de4c5d | 463 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
group-onsemi | 0:098463de4c5d | 464 | |
group-onsemi | 0:098463de4c5d | 465 | /*@} end of group CMSIS_SCB */ |
group-onsemi | 0:098463de4c5d | 466 | |
group-onsemi | 0:098463de4c5d | 467 | |
group-onsemi | 0:098463de4c5d | 468 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 469 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
group-onsemi | 0:098463de4c5d | 470 | \brief Type definitions for the System Control and ID Register not in the SCB |
group-onsemi | 0:098463de4c5d | 471 | @{ |
group-onsemi | 0:098463de4c5d | 472 | */ |
group-onsemi | 0:098463de4c5d | 473 | |
group-onsemi | 0:098463de4c5d | 474 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
group-onsemi | 0:098463de4c5d | 475 | */ |
group-onsemi | 0:098463de4c5d | 476 | typedef struct |
group-onsemi | 0:098463de4c5d | 477 | { |
group-onsemi | 0:098463de4c5d | 478 | uint32_t RESERVED0[2]; |
group-onsemi | 0:098463de4c5d | 479 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
group-onsemi | 0:098463de4c5d | 480 | } SCnSCB_Type; |
group-onsemi | 0:098463de4c5d | 481 | |
group-onsemi | 0:098463de4c5d | 482 | /* Auxiliary Control Register Definitions */ |
group-onsemi | 0:098463de4c5d | 483 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
group-onsemi | 0:098463de4c5d | 484 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
group-onsemi | 0:098463de4c5d | 485 | |
group-onsemi | 0:098463de4c5d | 486 | /*@} end of group CMSIS_SCnotSCB */ |
group-onsemi | 0:098463de4c5d | 487 | |
group-onsemi | 0:098463de4c5d | 488 | |
group-onsemi | 0:098463de4c5d | 489 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 490 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
group-onsemi | 0:098463de4c5d | 491 | \brief Type definitions for the System Timer Registers. |
group-onsemi | 0:098463de4c5d | 492 | @{ |
group-onsemi | 0:098463de4c5d | 493 | */ |
group-onsemi | 0:098463de4c5d | 494 | |
group-onsemi | 0:098463de4c5d | 495 | /** \brief Structure type to access the System Timer (SysTick). |
group-onsemi | 0:098463de4c5d | 496 | */ |
group-onsemi | 0:098463de4c5d | 497 | typedef struct |
group-onsemi | 0:098463de4c5d | 498 | { |
group-onsemi | 0:098463de4c5d | 499 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
group-onsemi | 0:098463de4c5d | 500 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
group-onsemi | 0:098463de4c5d | 501 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
group-onsemi | 0:098463de4c5d | 502 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
group-onsemi | 0:098463de4c5d | 503 | } SysTick_Type; |
group-onsemi | 0:098463de4c5d | 504 | |
group-onsemi | 0:098463de4c5d | 505 | /* SysTick Control / Status Register Definitions */ |
group-onsemi | 0:098463de4c5d | 506 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
group-onsemi | 0:098463de4c5d | 507 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
group-onsemi | 0:098463de4c5d | 508 | |
group-onsemi | 0:098463de4c5d | 509 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
group-onsemi | 0:098463de4c5d | 510 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
group-onsemi | 0:098463de4c5d | 511 | |
group-onsemi | 0:098463de4c5d | 512 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
group-onsemi | 0:098463de4c5d | 513 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
group-onsemi | 0:098463de4c5d | 514 | |
group-onsemi | 0:098463de4c5d | 515 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
group-onsemi | 0:098463de4c5d | 516 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
group-onsemi | 0:098463de4c5d | 517 | |
group-onsemi | 0:098463de4c5d | 518 | /* SysTick Reload Register Definitions */ |
group-onsemi | 0:098463de4c5d | 519 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
group-onsemi | 0:098463de4c5d | 520 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
group-onsemi | 0:098463de4c5d | 521 | |
group-onsemi | 0:098463de4c5d | 522 | /* SysTick Current Register Definitions */ |
group-onsemi | 0:098463de4c5d | 523 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
group-onsemi | 0:098463de4c5d | 524 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
group-onsemi | 0:098463de4c5d | 525 | |
group-onsemi | 0:098463de4c5d | 526 | /* SysTick Calibration Register Definitions */ |
group-onsemi | 0:098463de4c5d | 527 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
group-onsemi | 0:098463de4c5d | 528 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
group-onsemi | 0:098463de4c5d | 529 | |
group-onsemi | 0:098463de4c5d | 530 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
group-onsemi | 0:098463de4c5d | 531 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
group-onsemi | 0:098463de4c5d | 532 | |
group-onsemi | 0:098463de4c5d | 533 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
group-onsemi | 0:098463de4c5d | 534 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
group-onsemi | 0:098463de4c5d | 535 | |
group-onsemi | 0:098463de4c5d | 536 | /*@} end of group CMSIS_SysTick */ |
group-onsemi | 0:098463de4c5d | 537 | |
group-onsemi | 0:098463de4c5d | 538 | #if (__MPU_PRESENT == 1) |
group-onsemi | 0:098463de4c5d | 539 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 540 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
group-onsemi | 0:098463de4c5d | 541 | \brief Type definitions for the Memory Protection Unit (MPU) |
group-onsemi | 0:098463de4c5d | 542 | @{ |
group-onsemi | 0:098463de4c5d | 543 | */ |
group-onsemi | 0:098463de4c5d | 544 | |
group-onsemi | 0:098463de4c5d | 545 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
group-onsemi | 0:098463de4c5d | 546 | */ |
group-onsemi | 0:098463de4c5d | 547 | typedef struct |
group-onsemi | 0:098463de4c5d | 548 | { |
group-onsemi | 0:098463de4c5d | 549 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
group-onsemi | 0:098463de4c5d | 550 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
group-onsemi | 0:098463de4c5d | 551 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
group-onsemi | 0:098463de4c5d | 552 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
group-onsemi | 0:098463de4c5d | 553 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
group-onsemi | 0:098463de4c5d | 554 | } MPU_Type; |
group-onsemi | 0:098463de4c5d | 555 | |
group-onsemi | 0:098463de4c5d | 556 | /* MPU Type Register */ |
group-onsemi | 0:098463de4c5d | 557 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
group-onsemi | 0:098463de4c5d | 558 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
group-onsemi | 0:098463de4c5d | 559 | |
group-onsemi | 0:098463de4c5d | 560 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
group-onsemi | 0:098463de4c5d | 561 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
group-onsemi | 0:098463de4c5d | 562 | |
group-onsemi | 0:098463de4c5d | 563 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
group-onsemi | 0:098463de4c5d | 564 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
group-onsemi | 0:098463de4c5d | 565 | |
group-onsemi | 0:098463de4c5d | 566 | /* MPU Control Register */ |
group-onsemi | 0:098463de4c5d | 567 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
group-onsemi | 0:098463de4c5d | 568 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
group-onsemi | 0:098463de4c5d | 569 | |
group-onsemi | 0:098463de4c5d | 570 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
group-onsemi | 0:098463de4c5d | 571 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
group-onsemi | 0:098463de4c5d | 572 | |
group-onsemi | 0:098463de4c5d | 573 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
group-onsemi | 0:098463de4c5d | 574 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
group-onsemi | 0:098463de4c5d | 575 | |
group-onsemi | 0:098463de4c5d | 576 | /* MPU Region Number Register */ |
group-onsemi | 0:098463de4c5d | 577 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
group-onsemi | 0:098463de4c5d | 578 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
group-onsemi | 0:098463de4c5d | 579 | |
group-onsemi | 0:098463de4c5d | 580 | /* MPU Region Base Address Register */ |
group-onsemi | 0:098463de4c5d | 581 | #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ |
group-onsemi | 0:098463de4c5d | 582 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
group-onsemi | 0:098463de4c5d | 583 | |
group-onsemi | 0:098463de4c5d | 584 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
group-onsemi | 0:098463de4c5d | 585 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
group-onsemi | 0:098463de4c5d | 586 | |
group-onsemi | 0:098463de4c5d | 587 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
group-onsemi | 0:098463de4c5d | 588 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
group-onsemi | 0:098463de4c5d | 589 | |
group-onsemi | 0:098463de4c5d | 590 | /* MPU Region Attribute and Size Register */ |
group-onsemi | 0:098463de4c5d | 591 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
group-onsemi | 0:098463de4c5d | 592 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
group-onsemi | 0:098463de4c5d | 593 | |
group-onsemi | 0:098463de4c5d | 594 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
group-onsemi | 0:098463de4c5d | 595 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
group-onsemi | 0:098463de4c5d | 596 | |
group-onsemi | 0:098463de4c5d | 597 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
group-onsemi | 0:098463de4c5d | 598 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
group-onsemi | 0:098463de4c5d | 599 | |
group-onsemi | 0:098463de4c5d | 600 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
group-onsemi | 0:098463de4c5d | 601 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
group-onsemi | 0:098463de4c5d | 602 | |
group-onsemi | 0:098463de4c5d | 603 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
group-onsemi | 0:098463de4c5d | 604 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
group-onsemi | 0:098463de4c5d | 605 | |
group-onsemi | 0:098463de4c5d | 606 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
group-onsemi | 0:098463de4c5d | 607 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
group-onsemi | 0:098463de4c5d | 608 | |
group-onsemi | 0:098463de4c5d | 609 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
group-onsemi | 0:098463de4c5d | 610 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
group-onsemi | 0:098463de4c5d | 611 | |
group-onsemi | 0:098463de4c5d | 612 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
group-onsemi | 0:098463de4c5d | 613 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
group-onsemi | 0:098463de4c5d | 614 | |
group-onsemi | 0:098463de4c5d | 615 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
group-onsemi | 0:098463de4c5d | 616 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
group-onsemi | 0:098463de4c5d | 617 | |
group-onsemi | 0:098463de4c5d | 618 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
group-onsemi | 0:098463de4c5d | 619 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
group-onsemi | 0:098463de4c5d | 620 | |
group-onsemi | 0:098463de4c5d | 621 | /*@} end of group CMSIS_MPU */ |
group-onsemi | 0:098463de4c5d | 622 | #endif |
group-onsemi | 0:098463de4c5d | 623 | |
group-onsemi | 0:098463de4c5d | 624 | |
group-onsemi | 0:098463de4c5d | 625 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 626 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
group-onsemi | 0:098463de4c5d | 627 | \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) |
group-onsemi | 0:098463de4c5d | 628 | are only accessible over DAP and not via processor. Therefore |
group-onsemi | 0:098463de4c5d | 629 | they are not covered by the Cortex-M0 header file. |
group-onsemi | 0:098463de4c5d | 630 | @{ |
group-onsemi | 0:098463de4c5d | 631 | */ |
group-onsemi | 0:098463de4c5d | 632 | /*@} end of group CMSIS_CoreDebug */ |
group-onsemi | 0:098463de4c5d | 633 | |
group-onsemi | 0:098463de4c5d | 634 | |
group-onsemi | 0:098463de4c5d | 635 | /** \ingroup CMSIS_core_register |
group-onsemi | 0:098463de4c5d | 636 | \defgroup CMSIS_core_base Core Definitions |
group-onsemi | 0:098463de4c5d | 637 | \brief Definitions for base addresses, unions, and structures. |
group-onsemi | 0:098463de4c5d | 638 | @{ |
group-onsemi | 0:098463de4c5d | 639 | */ |
group-onsemi | 0:098463de4c5d | 640 | |
group-onsemi | 0:098463de4c5d | 641 | /* Memory mapping of SC000 Hardware */ |
group-onsemi | 0:098463de4c5d | 642 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
group-onsemi | 0:098463de4c5d | 643 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
group-onsemi | 0:098463de4c5d | 644 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
group-onsemi | 0:098463de4c5d | 645 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
group-onsemi | 0:098463de4c5d | 646 | |
group-onsemi | 0:098463de4c5d | 647 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
group-onsemi | 0:098463de4c5d | 648 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
group-onsemi | 0:098463de4c5d | 649 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
group-onsemi | 0:098463de4c5d | 650 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
group-onsemi | 0:098463de4c5d | 651 | |
group-onsemi | 0:098463de4c5d | 652 | #if (__MPU_PRESENT == 1) |
group-onsemi | 0:098463de4c5d | 653 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
group-onsemi | 0:098463de4c5d | 654 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
group-onsemi | 0:098463de4c5d | 655 | #endif |
group-onsemi | 0:098463de4c5d | 656 | |
group-onsemi | 0:098463de4c5d | 657 | /*@} */ |
group-onsemi | 0:098463de4c5d | 658 | |
group-onsemi | 0:098463de4c5d | 659 | |
group-onsemi | 0:098463de4c5d | 660 | |
group-onsemi | 0:098463de4c5d | 661 | /******************************************************************************* |
group-onsemi | 0:098463de4c5d | 662 | * Hardware Abstraction Layer |
group-onsemi | 0:098463de4c5d | 663 | Core Function Interface contains: |
group-onsemi | 0:098463de4c5d | 664 | - Core NVIC Functions |
group-onsemi | 0:098463de4c5d | 665 | - Core SysTick Functions |
group-onsemi | 0:098463de4c5d | 666 | - Core Register Access Functions |
group-onsemi | 0:098463de4c5d | 667 | ******************************************************************************/ |
group-onsemi | 0:098463de4c5d | 668 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
group-onsemi | 0:098463de4c5d | 669 | */ |
group-onsemi | 0:098463de4c5d | 670 | |
group-onsemi | 0:098463de4c5d | 671 | |
group-onsemi | 0:098463de4c5d | 672 | |
group-onsemi | 0:098463de4c5d | 673 | /* ########################## NVIC functions #################################### */ |
group-onsemi | 0:098463de4c5d | 674 | /** \ingroup CMSIS_Core_FunctionInterface |
group-onsemi | 0:098463de4c5d | 675 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
group-onsemi | 0:098463de4c5d | 676 | \brief Functions that manage interrupts and exceptions via the NVIC. |
group-onsemi | 0:098463de4c5d | 677 | @{ |
group-onsemi | 0:098463de4c5d | 678 | */ |
group-onsemi | 0:098463de4c5d | 679 | |
group-onsemi | 0:098463de4c5d | 680 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
group-onsemi | 0:098463de4c5d | 681 | /* The following MACROS handle generation of the register offset and byte masks */ |
group-onsemi | 0:098463de4c5d | 682 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
group-onsemi | 0:098463de4c5d | 683 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
group-onsemi | 0:098463de4c5d | 684 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
group-onsemi | 0:098463de4c5d | 685 | |
group-onsemi | 0:098463de4c5d | 686 | |
group-onsemi | 0:098463de4c5d | 687 | /** \brief Enable External Interrupt |
group-onsemi | 0:098463de4c5d | 688 | |
group-onsemi | 0:098463de4c5d | 689 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
group-onsemi | 0:098463de4c5d | 690 | |
group-onsemi | 0:098463de4c5d | 691 | \param [in] IRQn External interrupt number. Value cannot be negative. |
group-onsemi | 0:098463de4c5d | 692 | */ |
group-onsemi | 0:098463de4c5d | 693 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
group-onsemi | 0:098463de4c5d | 694 | { |
group-onsemi | 0:098463de4c5d | 695 | NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
group-onsemi | 0:098463de4c5d | 696 | } |
group-onsemi | 0:098463de4c5d | 697 | |
group-onsemi | 0:098463de4c5d | 698 | |
group-onsemi | 0:098463de4c5d | 699 | /** \brief Disable External Interrupt |
group-onsemi | 0:098463de4c5d | 700 | |
group-onsemi | 0:098463de4c5d | 701 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
group-onsemi | 0:098463de4c5d | 702 | |
group-onsemi | 0:098463de4c5d | 703 | \param [in] IRQn External interrupt number. Value cannot be negative. |
group-onsemi | 0:098463de4c5d | 704 | */ |
group-onsemi | 0:098463de4c5d | 705 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
group-onsemi | 0:098463de4c5d | 706 | { |
group-onsemi | 0:098463de4c5d | 707 | NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
group-onsemi | 0:098463de4c5d | 708 | __DSB(); |
group-onsemi | 0:098463de4c5d | 709 | __ISB(); |
group-onsemi | 0:098463de4c5d | 710 | } |
group-onsemi | 0:098463de4c5d | 711 | |
group-onsemi | 0:098463de4c5d | 712 | |
group-onsemi | 0:098463de4c5d | 713 | /** \brief Get Pending Interrupt |
group-onsemi | 0:098463de4c5d | 714 | |
group-onsemi | 0:098463de4c5d | 715 | The function reads the pending register in the NVIC and returns the pending bit |
group-onsemi | 0:098463de4c5d | 716 | for the specified interrupt. |
group-onsemi | 0:098463de4c5d | 717 | |
group-onsemi | 0:098463de4c5d | 718 | \param [in] IRQn Interrupt number. |
group-onsemi | 0:098463de4c5d | 719 | |
group-onsemi | 0:098463de4c5d | 720 | \return 0 Interrupt status is not pending. |
group-onsemi | 0:098463de4c5d | 721 | \return 1 Interrupt status is pending. |
group-onsemi | 0:098463de4c5d | 722 | */ |
group-onsemi | 0:098463de4c5d | 723 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
group-onsemi | 0:098463de4c5d | 724 | { |
group-onsemi | 0:098463de4c5d | 725 | return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
group-onsemi | 0:098463de4c5d | 726 | } |
group-onsemi | 0:098463de4c5d | 727 | |
group-onsemi | 0:098463de4c5d | 728 | |
group-onsemi | 0:098463de4c5d | 729 | /** \brief Set Pending Interrupt |
group-onsemi | 0:098463de4c5d | 730 | |
group-onsemi | 0:098463de4c5d | 731 | The function sets the pending bit of an external interrupt. |
group-onsemi | 0:098463de4c5d | 732 | |
group-onsemi | 0:098463de4c5d | 733 | \param [in] IRQn Interrupt number. Value cannot be negative. |
group-onsemi | 0:098463de4c5d | 734 | */ |
group-onsemi | 0:098463de4c5d | 735 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
group-onsemi | 0:098463de4c5d | 736 | { |
group-onsemi | 0:098463de4c5d | 737 | NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
group-onsemi | 0:098463de4c5d | 738 | } |
group-onsemi | 0:098463de4c5d | 739 | |
group-onsemi | 0:098463de4c5d | 740 | |
group-onsemi | 0:098463de4c5d | 741 | /** \brief Clear Pending Interrupt |
group-onsemi | 0:098463de4c5d | 742 | |
group-onsemi | 0:098463de4c5d | 743 | The function clears the pending bit of an external interrupt. |
group-onsemi | 0:098463de4c5d | 744 | |
group-onsemi | 0:098463de4c5d | 745 | \param [in] IRQn External interrupt number. Value cannot be negative. |
group-onsemi | 0:098463de4c5d | 746 | */ |
group-onsemi | 0:098463de4c5d | 747 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
group-onsemi | 0:098463de4c5d | 748 | { |
group-onsemi | 0:098463de4c5d | 749 | NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
group-onsemi | 0:098463de4c5d | 750 | } |
group-onsemi | 0:098463de4c5d | 751 | |
group-onsemi | 0:098463de4c5d | 752 | |
group-onsemi | 0:098463de4c5d | 753 | /** \brief Set Interrupt Priority |
group-onsemi | 0:098463de4c5d | 754 | |
group-onsemi | 0:098463de4c5d | 755 | The function sets the priority of an interrupt. |
group-onsemi | 0:098463de4c5d | 756 | |
group-onsemi | 0:098463de4c5d | 757 | \note The priority cannot be set for every core interrupt. |
group-onsemi | 0:098463de4c5d | 758 | |
group-onsemi | 0:098463de4c5d | 759 | \param [in] IRQn Interrupt number. |
group-onsemi | 0:098463de4c5d | 760 | \param [in] priority Priority to set. |
group-onsemi | 0:098463de4c5d | 761 | */ |
group-onsemi | 0:098463de4c5d | 762 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
group-onsemi | 0:098463de4c5d | 763 | { |
group-onsemi | 0:098463de4c5d | 764 | if((int32_t)(IRQn) < 0) { |
group-onsemi | 0:098463de4c5d | 765 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
group-onsemi | 0:098463de4c5d | 766 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
group-onsemi | 0:098463de4c5d | 767 | } |
group-onsemi | 0:098463de4c5d | 768 | else { |
group-onsemi | 0:098463de4c5d | 769 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
group-onsemi | 0:098463de4c5d | 770 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
group-onsemi | 0:098463de4c5d | 771 | } |
group-onsemi | 0:098463de4c5d | 772 | } |
group-onsemi | 0:098463de4c5d | 773 | |
group-onsemi | 0:098463de4c5d | 774 | |
group-onsemi | 0:098463de4c5d | 775 | /** \brief Get Interrupt Priority |
group-onsemi | 0:098463de4c5d | 776 | |
group-onsemi | 0:098463de4c5d | 777 | The function reads the priority of an interrupt. The interrupt |
group-onsemi | 0:098463de4c5d | 778 | number can be positive to specify an external (device specific) |
group-onsemi | 0:098463de4c5d | 779 | interrupt, or negative to specify an internal (core) interrupt. |
group-onsemi | 0:098463de4c5d | 780 | |
group-onsemi | 0:098463de4c5d | 781 | |
group-onsemi | 0:098463de4c5d | 782 | \param [in] IRQn Interrupt number. |
group-onsemi | 0:098463de4c5d | 783 | \return Interrupt Priority. Value is aligned automatically to the implemented |
group-onsemi | 0:098463de4c5d | 784 | priority bits of the microcontroller. |
group-onsemi | 0:098463de4c5d | 785 | */ |
group-onsemi | 0:098463de4c5d | 786 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
group-onsemi | 0:098463de4c5d | 787 | { |
group-onsemi | 0:098463de4c5d | 788 | |
group-onsemi | 0:098463de4c5d | 789 | if((int32_t)(IRQn) < 0) { |
group-onsemi | 0:098463de4c5d | 790 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
group-onsemi | 0:098463de4c5d | 791 | } |
group-onsemi | 0:098463de4c5d | 792 | else { |
group-onsemi | 0:098463de4c5d | 793 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
group-onsemi | 0:098463de4c5d | 794 | } |
group-onsemi | 0:098463de4c5d | 795 | } |
group-onsemi | 0:098463de4c5d | 796 | |
group-onsemi | 0:098463de4c5d | 797 | |
group-onsemi | 0:098463de4c5d | 798 | /** \brief System Reset |
group-onsemi | 0:098463de4c5d | 799 | |
group-onsemi | 0:098463de4c5d | 800 | The function initiates a system reset request to reset the MCU. |
group-onsemi | 0:098463de4c5d | 801 | */ |
group-onsemi | 0:098463de4c5d | 802 | __STATIC_INLINE void NVIC_SystemReset(void) |
group-onsemi | 0:098463de4c5d | 803 | { |
group-onsemi | 0:098463de4c5d | 804 | __DSB(); /* Ensure all outstanding memory accesses included |
group-onsemi | 0:098463de4c5d | 805 | buffered write are completed before reset */ |
group-onsemi | 0:098463de4c5d | 806 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
group-onsemi | 0:098463de4c5d | 807 | SCB_AIRCR_SYSRESETREQ_Msk); |
group-onsemi | 0:098463de4c5d | 808 | __DSB(); /* Ensure completion of memory access */ |
group-onsemi | 0:098463de4c5d | 809 | while(1) { __NOP(); } /* wait until reset */ |
group-onsemi | 0:098463de4c5d | 810 | } |
group-onsemi | 0:098463de4c5d | 811 | |
group-onsemi | 0:098463de4c5d | 812 | /*@} end of CMSIS_Core_NVICFunctions */ |
group-onsemi | 0:098463de4c5d | 813 | |
group-onsemi | 0:098463de4c5d | 814 | |
group-onsemi | 0:098463de4c5d | 815 | |
group-onsemi | 0:098463de4c5d | 816 | /* ################################## SysTick function ############################################ */ |
group-onsemi | 0:098463de4c5d | 817 | /** \ingroup CMSIS_Core_FunctionInterface |
group-onsemi | 0:098463de4c5d | 818 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
group-onsemi | 0:098463de4c5d | 819 | \brief Functions that configure the System. |
group-onsemi | 0:098463de4c5d | 820 | @{ |
group-onsemi | 0:098463de4c5d | 821 | */ |
group-onsemi | 0:098463de4c5d | 822 | |
group-onsemi | 0:098463de4c5d | 823 | #if (__Vendor_SysTickConfig == 0) |
group-onsemi | 0:098463de4c5d | 824 | |
group-onsemi | 0:098463de4c5d | 825 | /** \brief System Tick Configuration |
group-onsemi | 0:098463de4c5d | 826 | |
group-onsemi | 0:098463de4c5d | 827 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
group-onsemi | 0:098463de4c5d | 828 | Counter is in free running mode to generate periodic interrupts. |
group-onsemi | 0:098463de4c5d | 829 | |
group-onsemi | 0:098463de4c5d | 830 | \param [in] ticks Number of ticks between two interrupts. |
group-onsemi | 0:098463de4c5d | 831 | |
group-onsemi | 0:098463de4c5d | 832 | \return 0 Function succeeded. |
group-onsemi | 0:098463de4c5d | 833 | \return 1 Function failed. |
group-onsemi | 0:098463de4c5d | 834 | |
group-onsemi | 0:098463de4c5d | 835 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
group-onsemi | 0:098463de4c5d | 836 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
group-onsemi | 0:098463de4c5d | 837 | must contain a vendor-specific implementation of this function. |
group-onsemi | 0:098463de4c5d | 838 | |
group-onsemi | 0:098463de4c5d | 839 | */ |
group-onsemi | 0:098463de4c5d | 840 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
group-onsemi | 0:098463de4c5d | 841 | { |
group-onsemi | 0:098463de4c5d | 842 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ |
group-onsemi | 0:098463de4c5d | 843 | |
group-onsemi | 0:098463de4c5d | 844 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
group-onsemi | 0:098463de4c5d | 845 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
group-onsemi | 0:098463de4c5d | 846 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
group-onsemi | 0:098463de4c5d | 847 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
group-onsemi | 0:098463de4c5d | 848 | SysTick_CTRL_TICKINT_Msk | |
group-onsemi | 0:098463de4c5d | 849 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
group-onsemi | 0:098463de4c5d | 850 | return (0UL); /* Function successful */ |
group-onsemi | 0:098463de4c5d | 851 | } |
group-onsemi | 0:098463de4c5d | 852 | |
group-onsemi | 0:098463de4c5d | 853 | #endif |
group-onsemi | 0:098463de4c5d | 854 | |
group-onsemi | 0:098463de4c5d | 855 | /*@} end of CMSIS_Core_SysTickFunctions */ |
group-onsemi | 0:098463de4c5d | 856 | |
group-onsemi | 0:098463de4c5d | 857 | |
group-onsemi | 0:098463de4c5d | 858 | |
group-onsemi | 0:098463de4c5d | 859 | |
group-onsemi | 0:098463de4c5d | 860 | #ifdef __cplusplus |
group-onsemi | 0:098463de4c5d | 861 | } |
group-onsemi | 0:098463de4c5d | 862 | #endif |
group-onsemi | 0:098463de4c5d | 863 | |
group-onsemi | 0:098463de4c5d | 864 | #endif /* __CORE_SC000_H_DEPENDANT */ |
group-onsemi | 0:098463de4c5d | 865 | |
group-onsemi | 0:098463de4c5d | 866 | #endif /* __CMSIS_GENERIC */ |