ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_cmSimd.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file core_cmSimd.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-M SIMD Header File
group-onsemi 0:098463de4c5d 4 * @version V4.10
group-onsemi 0:098463de4c5d 5 * @date 18. March 2015
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @note
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 ******************************************************************************/
group-onsemi 0:098463de4c5d 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 All rights reserved.
group-onsemi 0:098463de4c5d 13 Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 14 modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 - Redistributions of source code must retain the above copyright
group-onsemi 0:098463de4c5d 16 notice, this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 - Redistributions in binary form must reproduce the above copyright
group-onsemi 0:098463de4c5d 18 notice, this list of conditions and the following disclaimer in the
group-onsemi 0:098463de4c5d 19 documentation and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 - Neither the name of ARM nor the names of its contributors may be used
group-onsemi 0:098463de4c5d 21 to endorse or promote products derived from this software without
group-onsemi 0:098463de4c5d 22 specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi 0:098463de4c5d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi 0:098463de4c5d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi 0:098463de4c5d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi 0:098463de4c5d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi 0:098463de4c5d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi 0:098463de4c5d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi 0:098463de4c5d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi 0:098463de4c5d 34 POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 35 ---------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #if defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 39 #pragma system_include /* treat file as system include file for MISRA check */
group-onsemi 0:098463de4c5d 40 #endif
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #ifndef __CORE_CMSIMD_H
group-onsemi 0:098463de4c5d 43 #define __CORE_CMSIMD_H
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 46 extern "C" {
group-onsemi 0:098463de4c5d 47 #endif
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 /*******************************************************************************
group-onsemi 0:098463de4c5d 51 * Hardware Abstraction Layer
group-onsemi 0:098463de4c5d 52 ******************************************************************************/
group-onsemi 0:098463de4c5d 53
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 /* ################### Compiler specific Intrinsics ########################### */
group-onsemi 0:098463de4c5d 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
group-onsemi 0:098463de4c5d 57 Access to dedicated SIMD instructions
group-onsemi 0:098463de4c5d 58 @{
group-onsemi 0:098463de4c5d 59 */
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
group-onsemi 0:098463de4c5d 62 /* ARM armcc specific functions */
group-onsemi 0:098463de4c5d 63 #define __SADD8 __sadd8
group-onsemi 0:098463de4c5d 64 #define __QADD8 __qadd8
group-onsemi 0:098463de4c5d 65 #define __SHADD8 __shadd8
group-onsemi 0:098463de4c5d 66 #define __UADD8 __uadd8
group-onsemi 0:098463de4c5d 67 #define __UQADD8 __uqadd8
group-onsemi 0:098463de4c5d 68 #define __UHADD8 __uhadd8
group-onsemi 0:098463de4c5d 69 #define __SSUB8 __ssub8
group-onsemi 0:098463de4c5d 70 #define __QSUB8 __qsub8
group-onsemi 0:098463de4c5d 71 #define __SHSUB8 __shsub8
group-onsemi 0:098463de4c5d 72 #define __USUB8 __usub8
group-onsemi 0:098463de4c5d 73 #define __UQSUB8 __uqsub8
group-onsemi 0:098463de4c5d 74 #define __UHSUB8 __uhsub8
group-onsemi 0:098463de4c5d 75 #define __SADD16 __sadd16
group-onsemi 0:098463de4c5d 76 #define __QADD16 __qadd16
group-onsemi 0:098463de4c5d 77 #define __SHADD16 __shadd16
group-onsemi 0:098463de4c5d 78 #define __UADD16 __uadd16
group-onsemi 0:098463de4c5d 79 #define __UQADD16 __uqadd16
group-onsemi 0:098463de4c5d 80 #define __UHADD16 __uhadd16
group-onsemi 0:098463de4c5d 81 #define __SSUB16 __ssub16
group-onsemi 0:098463de4c5d 82 #define __QSUB16 __qsub16
group-onsemi 0:098463de4c5d 83 #define __SHSUB16 __shsub16
group-onsemi 0:098463de4c5d 84 #define __USUB16 __usub16
group-onsemi 0:098463de4c5d 85 #define __UQSUB16 __uqsub16
group-onsemi 0:098463de4c5d 86 #define __UHSUB16 __uhsub16
group-onsemi 0:098463de4c5d 87 #define __SASX __sasx
group-onsemi 0:098463de4c5d 88 #define __QASX __qasx
group-onsemi 0:098463de4c5d 89 #define __SHASX __shasx
group-onsemi 0:098463de4c5d 90 #define __UASX __uasx
group-onsemi 0:098463de4c5d 91 #define __UQASX __uqasx
group-onsemi 0:098463de4c5d 92 #define __UHASX __uhasx
group-onsemi 0:098463de4c5d 93 #define __SSAX __ssax
group-onsemi 0:098463de4c5d 94 #define __QSAX __qsax
group-onsemi 0:098463de4c5d 95 #define __SHSAX __shsax
group-onsemi 0:098463de4c5d 96 #define __USAX __usax
group-onsemi 0:098463de4c5d 97 #define __UQSAX __uqsax
group-onsemi 0:098463de4c5d 98 #define __UHSAX __uhsax
group-onsemi 0:098463de4c5d 99 #define __USAD8 __usad8
group-onsemi 0:098463de4c5d 100 #define __USADA8 __usada8
group-onsemi 0:098463de4c5d 101 #define __SSAT16 __ssat16
group-onsemi 0:098463de4c5d 102 #define __USAT16 __usat16
group-onsemi 0:098463de4c5d 103 #define __UXTB16 __uxtb16
group-onsemi 0:098463de4c5d 104 #define __UXTAB16 __uxtab16
group-onsemi 0:098463de4c5d 105 #define __SXTB16 __sxtb16
group-onsemi 0:098463de4c5d 106 #define __SXTAB16 __sxtab16
group-onsemi 0:098463de4c5d 107 #define __SMUAD __smuad
group-onsemi 0:098463de4c5d 108 #define __SMUADX __smuadx
group-onsemi 0:098463de4c5d 109 #define __SMLAD __smlad
group-onsemi 0:098463de4c5d 110 #define __SMLADX __smladx
group-onsemi 0:098463de4c5d 111 #define __SMLALD __smlald
group-onsemi 0:098463de4c5d 112 #define __SMLALDX __smlaldx
group-onsemi 0:098463de4c5d 113 #define __SMUSD __smusd
group-onsemi 0:098463de4c5d 114 #define __SMUSDX __smusdx
group-onsemi 0:098463de4c5d 115 #define __SMLSD __smlsd
group-onsemi 0:098463de4c5d 116 #define __SMLSDX __smlsdx
group-onsemi 0:098463de4c5d 117 #define __SMLSLD __smlsld
group-onsemi 0:098463de4c5d 118 #define __SMLSLDX __smlsldx
group-onsemi 0:098463de4c5d 119 #define __SEL __sel
group-onsemi 0:098463de4c5d 120 #define __QADD __qadd
group-onsemi 0:098463de4c5d 121 #define __QSUB __qsub
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
group-onsemi 0:098463de4c5d 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
group-onsemi 0:098463de4c5d 125
group-onsemi 0:098463de4c5d 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
group-onsemi 0:098463de4c5d 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
group-onsemi 0:098463de4c5d 130 ((int64_t)(ARG3) << 32) ) >> 32))
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
group-onsemi 0:098463de4c5d 134 /* GNU gcc specific functions */
group-onsemi 0:098463de4c5d 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 136 {
group-onsemi 0:098463de4c5d 137 uint32_t result;
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 140 return(result);
group-onsemi 0:098463de4c5d 141 }
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 144 {
group-onsemi 0:098463de4c5d 145 uint32_t result;
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 148 return(result);
group-onsemi 0:098463de4c5d 149 }
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 152 {
group-onsemi 0:098463de4c5d 153 uint32_t result;
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 156 return(result);
group-onsemi 0:098463de4c5d 157 }
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 160 {
group-onsemi 0:098463de4c5d 161 uint32_t result;
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 164 return(result);
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 168 {
group-onsemi 0:098463de4c5d 169 uint32_t result;
group-onsemi 0:098463de4c5d 170
group-onsemi 0:098463de4c5d 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 172 return(result);
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 176 {
group-onsemi 0:098463de4c5d 177 uint32_t result;
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 180 return(result);
group-onsemi 0:098463de4c5d 181 }
group-onsemi 0:098463de4c5d 182
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 185 {
group-onsemi 0:098463de4c5d 186 uint32_t result;
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 189 return(result);
group-onsemi 0:098463de4c5d 190 }
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 193 {
group-onsemi 0:098463de4c5d 194 uint32_t result;
group-onsemi 0:098463de4c5d 195
group-onsemi 0:098463de4c5d 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 197 return(result);
group-onsemi 0:098463de4c5d 198 }
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 201 {
group-onsemi 0:098463de4c5d 202 uint32_t result;
group-onsemi 0:098463de4c5d 203
group-onsemi 0:098463de4c5d 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 205 return(result);
group-onsemi 0:098463de4c5d 206 }
group-onsemi 0:098463de4c5d 207
group-onsemi 0:098463de4c5d 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 209 {
group-onsemi 0:098463de4c5d 210 uint32_t result;
group-onsemi 0:098463de4c5d 211
group-onsemi 0:098463de4c5d 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 213 return(result);
group-onsemi 0:098463de4c5d 214 }
group-onsemi 0:098463de4c5d 215
group-onsemi 0:098463de4c5d 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 217 {
group-onsemi 0:098463de4c5d 218 uint32_t result;
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 221 return(result);
group-onsemi 0:098463de4c5d 222 }
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 225 {
group-onsemi 0:098463de4c5d 226 uint32_t result;
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 229 return(result);
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232
group-onsemi 0:098463de4c5d 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 234 {
group-onsemi 0:098463de4c5d 235 uint32_t result;
group-onsemi 0:098463de4c5d 236
group-onsemi 0:098463de4c5d 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 238 return(result);
group-onsemi 0:098463de4c5d 239 }
group-onsemi 0:098463de4c5d 240
group-onsemi 0:098463de4c5d 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 242 {
group-onsemi 0:098463de4c5d 243 uint32_t result;
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 246 return(result);
group-onsemi 0:098463de4c5d 247 }
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 250 {
group-onsemi 0:098463de4c5d 251 uint32_t result;
group-onsemi 0:098463de4c5d 252
group-onsemi 0:098463de4c5d 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 254 return(result);
group-onsemi 0:098463de4c5d 255 }
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 258 {
group-onsemi 0:098463de4c5d 259 uint32_t result;
group-onsemi 0:098463de4c5d 260
group-onsemi 0:098463de4c5d 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 262 return(result);
group-onsemi 0:098463de4c5d 263 }
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 266 {
group-onsemi 0:098463de4c5d 267 uint32_t result;
group-onsemi 0:098463de4c5d 268
group-onsemi 0:098463de4c5d 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 270 return(result);
group-onsemi 0:098463de4c5d 271 }
group-onsemi 0:098463de4c5d 272
group-onsemi 0:098463de4c5d 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 274 {
group-onsemi 0:098463de4c5d 275 uint32_t result;
group-onsemi 0:098463de4c5d 276
group-onsemi 0:098463de4c5d 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 278 return(result);
group-onsemi 0:098463de4c5d 279 }
group-onsemi 0:098463de4c5d 280
group-onsemi 0:098463de4c5d 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 282 {
group-onsemi 0:098463de4c5d 283 uint32_t result;
group-onsemi 0:098463de4c5d 284
group-onsemi 0:098463de4c5d 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 286 return(result);
group-onsemi 0:098463de4c5d 287 }
group-onsemi 0:098463de4c5d 288
group-onsemi 0:098463de4c5d 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 290 {
group-onsemi 0:098463de4c5d 291 uint32_t result;
group-onsemi 0:098463de4c5d 292
group-onsemi 0:098463de4c5d 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 294 return(result);
group-onsemi 0:098463de4c5d 295 }
group-onsemi 0:098463de4c5d 296
group-onsemi 0:098463de4c5d 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 298 {
group-onsemi 0:098463de4c5d 299 uint32_t result;
group-onsemi 0:098463de4c5d 300
group-onsemi 0:098463de4c5d 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 302 return(result);
group-onsemi 0:098463de4c5d 303 }
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 306 {
group-onsemi 0:098463de4c5d 307 uint32_t result;
group-onsemi 0:098463de4c5d 308
group-onsemi 0:098463de4c5d 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 310 return(result);
group-onsemi 0:098463de4c5d 311 }
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 314 {
group-onsemi 0:098463de4c5d 315 uint32_t result;
group-onsemi 0:098463de4c5d 316
group-onsemi 0:098463de4c5d 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 318 return(result);
group-onsemi 0:098463de4c5d 319 }
group-onsemi 0:098463de4c5d 320
group-onsemi 0:098463de4c5d 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 322 {
group-onsemi 0:098463de4c5d 323 uint32_t result;
group-onsemi 0:098463de4c5d 324
group-onsemi 0:098463de4c5d 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 326 return(result);
group-onsemi 0:098463de4c5d 327 }
group-onsemi 0:098463de4c5d 328
group-onsemi 0:098463de4c5d 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 330 {
group-onsemi 0:098463de4c5d 331 uint32_t result;
group-onsemi 0:098463de4c5d 332
group-onsemi 0:098463de4c5d 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 334 return(result);
group-onsemi 0:098463de4c5d 335 }
group-onsemi 0:098463de4c5d 336
group-onsemi 0:098463de4c5d 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 338 {
group-onsemi 0:098463de4c5d 339 uint32_t result;
group-onsemi 0:098463de4c5d 340
group-onsemi 0:098463de4c5d 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 342 return(result);
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 346 {
group-onsemi 0:098463de4c5d 347 uint32_t result;
group-onsemi 0:098463de4c5d 348
group-onsemi 0:098463de4c5d 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 350 return(result);
group-onsemi 0:098463de4c5d 351 }
group-onsemi 0:098463de4c5d 352
group-onsemi 0:098463de4c5d 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 354 {
group-onsemi 0:098463de4c5d 355 uint32_t result;
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 358 return(result);
group-onsemi 0:098463de4c5d 359 }
group-onsemi 0:098463de4c5d 360
group-onsemi 0:098463de4c5d 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 362 {
group-onsemi 0:098463de4c5d 363 uint32_t result;
group-onsemi 0:098463de4c5d 364
group-onsemi 0:098463de4c5d 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 366 return(result);
group-onsemi 0:098463de4c5d 367 }
group-onsemi 0:098463de4c5d 368
group-onsemi 0:098463de4c5d 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 370 {
group-onsemi 0:098463de4c5d 371 uint32_t result;
group-onsemi 0:098463de4c5d 372
group-onsemi 0:098463de4c5d 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 374 return(result);
group-onsemi 0:098463de4c5d 375 }
group-onsemi 0:098463de4c5d 376
group-onsemi 0:098463de4c5d 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 378 {
group-onsemi 0:098463de4c5d 379 uint32_t result;
group-onsemi 0:098463de4c5d 380
group-onsemi 0:098463de4c5d 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 382 return(result);
group-onsemi 0:098463de4c5d 383 }
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 386 {
group-onsemi 0:098463de4c5d 387 uint32_t result;
group-onsemi 0:098463de4c5d 388
group-onsemi 0:098463de4c5d 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 390 return(result);
group-onsemi 0:098463de4c5d 391 }
group-onsemi 0:098463de4c5d 392
group-onsemi 0:098463de4c5d 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 394 {
group-onsemi 0:098463de4c5d 395 uint32_t result;
group-onsemi 0:098463de4c5d 396
group-onsemi 0:098463de4c5d 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 398 return(result);
group-onsemi 0:098463de4c5d 399 }
group-onsemi 0:098463de4c5d 400
group-onsemi 0:098463de4c5d 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 402 {
group-onsemi 0:098463de4c5d 403 uint32_t result;
group-onsemi 0:098463de4c5d 404
group-onsemi 0:098463de4c5d 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 406 return(result);
group-onsemi 0:098463de4c5d 407 }
group-onsemi 0:098463de4c5d 408
group-onsemi 0:098463de4c5d 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 410 {
group-onsemi 0:098463de4c5d 411 uint32_t result;
group-onsemi 0:098463de4c5d 412
group-onsemi 0:098463de4c5d 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 414 return(result);
group-onsemi 0:098463de4c5d 415 }
group-onsemi 0:098463de4c5d 416
group-onsemi 0:098463de4c5d 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 418 {
group-onsemi 0:098463de4c5d 419 uint32_t result;
group-onsemi 0:098463de4c5d 420
group-onsemi 0:098463de4c5d 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 422 return(result);
group-onsemi 0:098463de4c5d 423 }
group-onsemi 0:098463de4c5d 424
group-onsemi 0:098463de4c5d 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 426 {
group-onsemi 0:098463de4c5d 427 uint32_t result;
group-onsemi 0:098463de4c5d 428
group-onsemi 0:098463de4c5d 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 430 return(result);
group-onsemi 0:098463de4c5d 431 }
group-onsemi 0:098463de4c5d 432
group-onsemi 0:098463de4c5d 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 434 {
group-onsemi 0:098463de4c5d 435 uint32_t result;
group-onsemi 0:098463de4c5d 436
group-onsemi 0:098463de4c5d 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 438 return(result);
group-onsemi 0:098463de4c5d 439 }
group-onsemi 0:098463de4c5d 440
group-onsemi 0:098463de4c5d 441 #define __SSAT16(ARG1,ARG2) \
group-onsemi 0:098463de4c5d 442 ({ \
group-onsemi 0:098463de4c5d 443 uint32_t __RES, __ARG1 = (ARG1); \
group-onsemi 0:098463de4c5d 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
group-onsemi 0:098463de4c5d 445 __RES; \
group-onsemi 0:098463de4c5d 446 })
group-onsemi 0:098463de4c5d 447
group-onsemi 0:098463de4c5d 448 #define __USAT16(ARG1,ARG2) \
group-onsemi 0:098463de4c5d 449 ({ \
group-onsemi 0:098463de4c5d 450 uint32_t __RES, __ARG1 = (ARG1); \
group-onsemi 0:098463de4c5d 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
group-onsemi 0:098463de4c5d 452 __RES; \
group-onsemi 0:098463de4c5d 453 })
group-onsemi 0:098463de4c5d 454
group-onsemi 0:098463de4c5d 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
group-onsemi 0:098463de4c5d 456 {
group-onsemi 0:098463de4c5d 457 uint32_t result;
group-onsemi 0:098463de4c5d 458
group-onsemi 0:098463de4c5d 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
group-onsemi 0:098463de4c5d 460 return(result);
group-onsemi 0:098463de4c5d 461 }
group-onsemi 0:098463de4c5d 462
group-onsemi 0:098463de4c5d 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 464 {
group-onsemi 0:098463de4c5d 465 uint32_t result;
group-onsemi 0:098463de4c5d 466
group-onsemi 0:098463de4c5d 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 468 return(result);
group-onsemi 0:098463de4c5d 469 }
group-onsemi 0:098463de4c5d 470
group-onsemi 0:098463de4c5d 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
group-onsemi 0:098463de4c5d 472 {
group-onsemi 0:098463de4c5d 473 uint32_t result;
group-onsemi 0:098463de4c5d 474
group-onsemi 0:098463de4c5d 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
group-onsemi 0:098463de4c5d 476 return(result);
group-onsemi 0:098463de4c5d 477 }
group-onsemi 0:098463de4c5d 478
group-onsemi 0:098463de4c5d 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 480 {
group-onsemi 0:098463de4c5d 481 uint32_t result;
group-onsemi 0:098463de4c5d 482
group-onsemi 0:098463de4c5d 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 484 return(result);
group-onsemi 0:098463de4c5d 485 }
group-onsemi 0:098463de4c5d 486
group-onsemi 0:098463de4c5d 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 488 {
group-onsemi 0:098463de4c5d 489 uint32_t result;
group-onsemi 0:098463de4c5d 490
group-onsemi 0:098463de4c5d 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 492 return(result);
group-onsemi 0:098463de4c5d 493 }
group-onsemi 0:098463de4c5d 494
group-onsemi 0:098463de4c5d 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 496 {
group-onsemi 0:098463de4c5d 497 uint32_t result;
group-onsemi 0:098463de4c5d 498
group-onsemi 0:098463de4c5d 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 500 return(result);
group-onsemi 0:098463de4c5d 501 }
group-onsemi 0:098463de4c5d 502
group-onsemi 0:098463de4c5d 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 504 {
group-onsemi 0:098463de4c5d 505 uint32_t result;
group-onsemi 0:098463de4c5d 506
group-onsemi 0:098463de4c5d 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 508 return(result);
group-onsemi 0:098463de4c5d 509 }
group-onsemi 0:098463de4c5d 510
group-onsemi 0:098463de4c5d 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 512 {
group-onsemi 0:098463de4c5d 513 uint32_t result;
group-onsemi 0:098463de4c5d 514
group-onsemi 0:098463de4c5d 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 516 return(result);
group-onsemi 0:098463de4c5d 517 }
group-onsemi 0:098463de4c5d 518
group-onsemi 0:098463de4c5d 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
group-onsemi 0:098463de4c5d 520 {
group-onsemi 0:098463de4c5d 521 union llreg_u{
group-onsemi 0:098463de4c5d 522 uint32_t w32[2];
group-onsemi 0:098463de4c5d 523 uint64_t w64;
group-onsemi 0:098463de4c5d 524 } llr;
group-onsemi 0:098463de4c5d 525 llr.w64 = acc;
group-onsemi 0:098463de4c5d 526
group-onsemi 0:098463de4c5d 527 #ifndef __ARMEB__ // Little endian
group-onsemi 0:098463de4c5d 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
group-onsemi 0:098463de4c5d 529 #else // Big endian
group-onsemi 0:098463de4c5d 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
group-onsemi 0:098463de4c5d 531 #endif
group-onsemi 0:098463de4c5d 532
group-onsemi 0:098463de4c5d 533 return(llr.w64);
group-onsemi 0:098463de4c5d 534 }
group-onsemi 0:098463de4c5d 535
group-onsemi 0:098463de4c5d 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
group-onsemi 0:098463de4c5d 537 {
group-onsemi 0:098463de4c5d 538 union llreg_u{
group-onsemi 0:098463de4c5d 539 uint32_t w32[2];
group-onsemi 0:098463de4c5d 540 uint64_t w64;
group-onsemi 0:098463de4c5d 541 } llr;
group-onsemi 0:098463de4c5d 542 llr.w64 = acc;
group-onsemi 0:098463de4c5d 543
group-onsemi 0:098463de4c5d 544 #ifndef __ARMEB__ // Little endian
group-onsemi 0:098463de4c5d 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
group-onsemi 0:098463de4c5d 546 #else // Big endian
group-onsemi 0:098463de4c5d 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
group-onsemi 0:098463de4c5d 548 #endif
group-onsemi 0:098463de4c5d 549
group-onsemi 0:098463de4c5d 550 return(llr.w64);
group-onsemi 0:098463de4c5d 551 }
group-onsemi 0:098463de4c5d 552
group-onsemi 0:098463de4c5d 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 554 {
group-onsemi 0:098463de4c5d 555 uint32_t result;
group-onsemi 0:098463de4c5d 556
group-onsemi 0:098463de4c5d 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 558 return(result);
group-onsemi 0:098463de4c5d 559 }
group-onsemi 0:098463de4c5d 560
group-onsemi 0:098463de4c5d 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 562 {
group-onsemi 0:098463de4c5d 563 uint32_t result;
group-onsemi 0:098463de4c5d 564
group-onsemi 0:098463de4c5d 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 566 return(result);
group-onsemi 0:098463de4c5d 567 }
group-onsemi 0:098463de4c5d 568
group-onsemi 0:098463de4c5d 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 570 {
group-onsemi 0:098463de4c5d 571 uint32_t result;
group-onsemi 0:098463de4c5d 572
group-onsemi 0:098463de4c5d 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 574 return(result);
group-onsemi 0:098463de4c5d 575 }
group-onsemi 0:098463de4c5d 576
group-onsemi 0:098463de4c5d 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 578 {
group-onsemi 0:098463de4c5d 579 uint32_t result;
group-onsemi 0:098463de4c5d 580
group-onsemi 0:098463de4c5d 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 582 return(result);
group-onsemi 0:098463de4c5d 583 }
group-onsemi 0:098463de4c5d 584
group-onsemi 0:098463de4c5d 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
group-onsemi 0:098463de4c5d 586 {
group-onsemi 0:098463de4c5d 587 union llreg_u{
group-onsemi 0:098463de4c5d 588 uint32_t w32[2];
group-onsemi 0:098463de4c5d 589 uint64_t w64;
group-onsemi 0:098463de4c5d 590 } llr;
group-onsemi 0:098463de4c5d 591 llr.w64 = acc;
group-onsemi 0:098463de4c5d 592
group-onsemi 0:098463de4c5d 593 #ifndef __ARMEB__ // Little endian
group-onsemi 0:098463de4c5d 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
group-onsemi 0:098463de4c5d 595 #else // Big endian
group-onsemi 0:098463de4c5d 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
group-onsemi 0:098463de4c5d 597 #endif
group-onsemi 0:098463de4c5d 598
group-onsemi 0:098463de4c5d 599 return(llr.w64);
group-onsemi 0:098463de4c5d 600 }
group-onsemi 0:098463de4c5d 601
group-onsemi 0:098463de4c5d 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
group-onsemi 0:098463de4c5d 603 {
group-onsemi 0:098463de4c5d 604 union llreg_u{
group-onsemi 0:098463de4c5d 605 uint32_t w32[2];
group-onsemi 0:098463de4c5d 606 uint64_t w64;
group-onsemi 0:098463de4c5d 607 } llr;
group-onsemi 0:098463de4c5d 608 llr.w64 = acc;
group-onsemi 0:098463de4c5d 609
group-onsemi 0:098463de4c5d 610 #ifndef __ARMEB__ // Little endian
group-onsemi 0:098463de4c5d 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
group-onsemi 0:098463de4c5d 612 #else // Big endian
group-onsemi 0:098463de4c5d 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
group-onsemi 0:098463de4c5d 614 #endif
group-onsemi 0:098463de4c5d 615
group-onsemi 0:098463de4c5d 616 return(llr.w64);
group-onsemi 0:098463de4c5d 617 }
group-onsemi 0:098463de4c5d 618
group-onsemi 0:098463de4c5d 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 620 {
group-onsemi 0:098463de4c5d 621 uint32_t result;
group-onsemi 0:098463de4c5d 622
group-onsemi 0:098463de4c5d 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 624 return(result);
group-onsemi 0:098463de4c5d 625 }
group-onsemi 0:098463de4c5d 626
group-onsemi 0:098463de4c5d 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 628 {
group-onsemi 0:098463de4c5d 629 uint32_t result;
group-onsemi 0:098463de4c5d 630
group-onsemi 0:098463de4c5d 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 632 return(result);
group-onsemi 0:098463de4c5d 633 }
group-onsemi 0:098463de4c5d 634
group-onsemi 0:098463de4c5d 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 636 {
group-onsemi 0:098463de4c5d 637 uint32_t result;
group-onsemi 0:098463de4c5d 638
group-onsemi 0:098463de4c5d 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 640 return(result);
group-onsemi 0:098463de4c5d 641 }
group-onsemi 0:098463de4c5d 642
group-onsemi 0:098463de4c5d 643 #define __PKHBT(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 644 ({ \
group-onsemi 0:098463de4c5d 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
group-onsemi 0:098463de4c5d 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
group-onsemi 0:098463de4c5d 647 __RES; \
group-onsemi 0:098463de4c5d 648 })
group-onsemi 0:098463de4c5d 649
group-onsemi 0:098463de4c5d 650 #define __PKHTB(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 651 ({ \
group-onsemi 0:098463de4c5d 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
group-onsemi 0:098463de4c5d 653 if (ARG3 == 0) \
group-onsemi 0:098463de4c5d 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
group-onsemi 0:098463de4c5d 655 else \
group-onsemi 0:098463de4c5d 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
group-onsemi 0:098463de4c5d 657 __RES; \
group-onsemi 0:098463de4c5d 658 })
group-onsemi 0:098463de4c5d 659
group-onsemi 0:098463de4c5d 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
group-onsemi 0:098463de4c5d 661 {
group-onsemi 0:098463de4c5d 662 int32_t result;
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 665 return(result);
group-onsemi 0:098463de4c5d 666 }
group-onsemi 0:098463de4c5d 667
group-onsemi 0:098463de4c5d 668
group-onsemi 0:098463de4c5d 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
group-onsemi 0:098463de4c5d 670 /* IAR iccarm specific functions */
group-onsemi 0:098463de4c5d 671 #include <cmsis_iar.h>
group-onsemi 0:098463de4c5d 672
group-onsemi 0:098463de4c5d 673
group-onsemi 0:098463de4c5d 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
group-onsemi 0:098463de4c5d 675 /* TI CCS specific functions */
group-onsemi 0:098463de4c5d 676 #include <cmsis_ccs.h>
group-onsemi 0:098463de4c5d 677
group-onsemi 0:098463de4c5d 678
group-onsemi 0:098463de4c5d 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
group-onsemi 0:098463de4c5d 680 /* TASKING carm specific functions */
group-onsemi 0:098463de4c5d 681 /* not yet supported */
group-onsemi 0:098463de4c5d 682
group-onsemi 0:098463de4c5d 683
group-onsemi 0:098463de4c5d 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
group-onsemi 0:098463de4c5d 685 /* Cosmic specific functions */
group-onsemi 0:098463de4c5d 686 #include <cmsis_csm.h>
group-onsemi 0:098463de4c5d 687
group-onsemi 0:098463de4c5d 688 #endif
group-onsemi 0:098463de4c5d 689
group-onsemi 0:098463de4c5d 690 /*@} end of group CMSIS_SIMD_intrinsics */
group-onsemi 0:098463de4c5d 691
group-onsemi 0:098463de4c5d 692
group-onsemi 0:098463de4c5d 693 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 694 }
group-onsemi 0:098463de4c5d 695 #endif
group-onsemi 0:098463de4c5d 696
group-onsemi 0:098463de4c5d 697 #endif /* __CORE_CMSIMD_H */