ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_cm4_simd.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

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group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file core_cm4_simd.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-M4 SIMD Header File
group-onsemi 0:098463de4c5d 4 * @version V3.20
group-onsemi 0:098463de4c5d 5 * @date 25. February 2013
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @note
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 ******************************************************************************/
group-onsemi 0:098463de4c5d 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 All rights reserved.
group-onsemi 0:098463de4c5d 13 Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 14 modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 - Redistributions of source code must retain the above copyright
group-onsemi 0:098463de4c5d 16 notice, this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 - Redistributions in binary form must reproduce the above copyright
group-onsemi 0:098463de4c5d 18 notice, this list of conditions and the following disclaimer in the
group-onsemi 0:098463de4c5d 19 documentation and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 - Neither the name of ARM nor the names of its contributors may be used
group-onsemi 0:098463de4c5d 21 to endorse or promote products derived from this software without
group-onsemi 0:098463de4c5d 22 specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi 0:098463de4c5d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi 0:098463de4c5d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi 0:098463de4c5d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi 0:098463de4c5d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi 0:098463de4c5d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi 0:098463de4c5d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi 0:098463de4c5d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi 0:098463de4c5d 34 POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 35 ---------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 39 extern "C" {
group-onsemi 0:098463de4c5d 40 #endif
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #ifndef __CORE_CM4_SIMD_H
group-onsemi 0:098463de4c5d 43 #define __CORE_CM4_SIMD_H
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /*******************************************************************************
group-onsemi 0:098463de4c5d 47 * Hardware Abstraction Layer
group-onsemi 0:098463de4c5d 48 ******************************************************************************/
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 /* ################### Compiler specific Intrinsics ########################### */
group-onsemi 0:098463de4c5d 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
group-onsemi 0:098463de4c5d 53 Access to dedicated SIMD instructions
group-onsemi 0:098463de4c5d 54 @{
group-onsemi 0:098463de4c5d 55 */
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
group-onsemi 0:098463de4c5d 58 /* ARM armcc specific functions */
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 61 #define __SADD8 __sadd8
group-onsemi 0:098463de4c5d 62 #define __QADD8 __qadd8
group-onsemi 0:098463de4c5d 63 #define __SHADD8 __shadd8
group-onsemi 0:098463de4c5d 64 #define __UADD8 __uadd8
group-onsemi 0:098463de4c5d 65 #define __UQADD8 __uqadd8
group-onsemi 0:098463de4c5d 66 #define __UHADD8 __uhadd8
group-onsemi 0:098463de4c5d 67 #define __SSUB8 __ssub8
group-onsemi 0:098463de4c5d 68 #define __QSUB8 __qsub8
group-onsemi 0:098463de4c5d 69 #define __SHSUB8 __shsub8
group-onsemi 0:098463de4c5d 70 #define __USUB8 __usub8
group-onsemi 0:098463de4c5d 71 #define __UQSUB8 __uqsub8
group-onsemi 0:098463de4c5d 72 #define __UHSUB8 __uhsub8
group-onsemi 0:098463de4c5d 73 #define __SADD16 __sadd16
group-onsemi 0:098463de4c5d 74 #define __QADD16 __qadd16
group-onsemi 0:098463de4c5d 75 #define __SHADD16 __shadd16
group-onsemi 0:098463de4c5d 76 #define __UADD16 __uadd16
group-onsemi 0:098463de4c5d 77 #define __UQADD16 __uqadd16
group-onsemi 0:098463de4c5d 78 #define __UHADD16 __uhadd16
group-onsemi 0:098463de4c5d 79 #define __SSUB16 __ssub16
group-onsemi 0:098463de4c5d 80 #define __QSUB16 __qsub16
group-onsemi 0:098463de4c5d 81 #define __SHSUB16 __shsub16
group-onsemi 0:098463de4c5d 82 #define __USUB16 __usub16
group-onsemi 0:098463de4c5d 83 #define __UQSUB16 __uqsub16
group-onsemi 0:098463de4c5d 84 #define __UHSUB16 __uhsub16
group-onsemi 0:098463de4c5d 85 #define __SASX __sasx
group-onsemi 0:098463de4c5d 86 #define __QASX __qasx
group-onsemi 0:098463de4c5d 87 #define __SHASX __shasx
group-onsemi 0:098463de4c5d 88 #define __UASX __uasx
group-onsemi 0:098463de4c5d 89 #define __UQASX __uqasx
group-onsemi 0:098463de4c5d 90 #define __UHASX __uhasx
group-onsemi 0:098463de4c5d 91 #define __SSAX __ssax
group-onsemi 0:098463de4c5d 92 #define __QSAX __qsax
group-onsemi 0:098463de4c5d 93 #define __SHSAX __shsax
group-onsemi 0:098463de4c5d 94 #define __USAX __usax
group-onsemi 0:098463de4c5d 95 #define __UQSAX __uqsax
group-onsemi 0:098463de4c5d 96 #define __UHSAX __uhsax
group-onsemi 0:098463de4c5d 97 #define __USAD8 __usad8
group-onsemi 0:098463de4c5d 98 #define __USADA8 __usada8
group-onsemi 0:098463de4c5d 99 #define __SSAT16 __ssat16
group-onsemi 0:098463de4c5d 100 #define __USAT16 __usat16
group-onsemi 0:098463de4c5d 101 #define __UXTB16 __uxtb16
group-onsemi 0:098463de4c5d 102 #define __UXTAB16 __uxtab16
group-onsemi 0:098463de4c5d 103 #define __SXTB16 __sxtb16
group-onsemi 0:098463de4c5d 104 #define __SXTAB16 __sxtab16
group-onsemi 0:098463de4c5d 105 #define __SMUAD __smuad
group-onsemi 0:098463de4c5d 106 #define __SMUADX __smuadx
group-onsemi 0:098463de4c5d 107 #define __SMLAD __smlad
group-onsemi 0:098463de4c5d 108 #define __SMLADX __smladx
group-onsemi 0:098463de4c5d 109 #define __SMLALD __smlald
group-onsemi 0:098463de4c5d 110 #define __SMLALDX __smlaldx
group-onsemi 0:098463de4c5d 111 #define __SMUSD __smusd
group-onsemi 0:098463de4c5d 112 #define __SMUSDX __smusdx
group-onsemi 0:098463de4c5d 113 #define __SMLSD __smlsd
group-onsemi 0:098463de4c5d 114 #define __SMLSDX __smlsdx
group-onsemi 0:098463de4c5d 115 #define __SMLSLD __smlsld
group-onsemi 0:098463de4c5d 116 #define __SMLSLDX __smlsldx
group-onsemi 0:098463de4c5d 117 #define __SEL __sel
group-onsemi 0:098463de4c5d 118 #define __QADD __qadd
group-onsemi 0:098463de4c5d 119 #define __QSUB __qsub
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
group-onsemi 0:098463de4c5d 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
group-onsemi 0:098463de4c5d 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
group-onsemi 0:098463de4c5d 128 ((int64_t)(ARG3) << 32) ) >> 32))
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133
group-onsemi 0:098463de4c5d 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
group-onsemi 0:098463de4c5d 135 /* IAR iccarm specific functions */
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 138 #include <cmsis_iar.h>
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
group-onsemi 0:098463de4c5d 145 /* TI CCS specific functions */
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 148 #include <cmsis_ccs.h>
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 151
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
group-onsemi 0:098463de4c5d 155 /* GNU gcc specific functions */
group-onsemi 0:098463de4c5d 156
group-onsemi 0:098463de4c5d 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 159 {
group-onsemi 0:098463de4c5d 160 uint32_t result;
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 163 return(result);
group-onsemi 0:098463de4c5d 164 }
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 167 {
group-onsemi 0:098463de4c5d 168 uint32_t result;
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 171 return(result);
group-onsemi 0:098463de4c5d 172 }
group-onsemi 0:098463de4c5d 173
group-onsemi 0:098463de4c5d 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 175 {
group-onsemi 0:098463de4c5d 176 uint32_t result;
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 179 return(result);
group-onsemi 0:098463de4c5d 180 }
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 183 {
group-onsemi 0:098463de4c5d 184 uint32_t result;
group-onsemi 0:098463de4c5d 185
group-onsemi 0:098463de4c5d 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 187 return(result);
group-onsemi 0:098463de4c5d 188 }
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 191 {
group-onsemi 0:098463de4c5d 192 uint32_t result;
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 195 return(result);
group-onsemi 0:098463de4c5d 196 }
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 199 {
group-onsemi 0:098463de4c5d 200 uint32_t result;
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 203 return(result);
group-onsemi 0:098463de4c5d 204 }
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206
group-onsemi 0:098463de4c5d 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 208 {
group-onsemi 0:098463de4c5d 209 uint32_t result;
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 212 return(result);
group-onsemi 0:098463de4c5d 213 }
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 216 {
group-onsemi 0:098463de4c5d 217 uint32_t result;
group-onsemi 0:098463de4c5d 218
group-onsemi 0:098463de4c5d 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 220 return(result);
group-onsemi 0:098463de4c5d 221 }
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 224 {
group-onsemi 0:098463de4c5d 225 uint32_t result;
group-onsemi 0:098463de4c5d 226
group-onsemi 0:098463de4c5d 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 228 return(result);
group-onsemi 0:098463de4c5d 229 }
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 232 {
group-onsemi 0:098463de4c5d 233 uint32_t result;
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 236 return(result);
group-onsemi 0:098463de4c5d 237 }
group-onsemi 0:098463de4c5d 238
group-onsemi 0:098463de4c5d 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 240 {
group-onsemi 0:098463de4c5d 241 uint32_t result;
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 244 return(result);
group-onsemi 0:098463de4c5d 245 }
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 248 {
group-onsemi 0:098463de4c5d 249 uint32_t result;
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 252 return(result);
group-onsemi 0:098463de4c5d 253 }
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255
group-onsemi 0:098463de4c5d 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 257 {
group-onsemi 0:098463de4c5d 258 uint32_t result;
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 261 return(result);
group-onsemi 0:098463de4c5d 262 }
group-onsemi 0:098463de4c5d 263
group-onsemi 0:098463de4c5d 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 265 {
group-onsemi 0:098463de4c5d 266 uint32_t result;
group-onsemi 0:098463de4c5d 267
group-onsemi 0:098463de4c5d 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 269 return(result);
group-onsemi 0:098463de4c5d 270 }
group-onsemi 0:098463de4c5d 271
group-onsemi 0:098463de4c5d 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 273 {
group-onsemi 0:098463de4c5d 274 uint32_t result;
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 277 return(result);
group-onsemi 0:098463de4c5d 278 }
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 281 {
group-onsemi 0:098463de4c5d 282 uint32_t result;
group-onsemi 0:098463de4c5d 283
group-onsemi 0:098463de4c5d 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 285 return(result);
group-onsemi 0:098463de4c5d 286 }
group-onsemi 0:098463de4c5d 287
group-onsemi 0:098463de4c5d 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 289 {
group-onsemi 0:098463de4c5d 290 uint32_t result;
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 293 return(result);
group-onsemi 0:098463de4c5d 294 }
group-onsemi 0:098463de4c5d 295
group-onsemi 0:098463de4c5d 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 297 {
group-onsemi 0:098463de4c5d 298 uint32_t result;
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 301 return(result);
group-onsemi 0:098463de4c5d 302 }
group-onsemi 0:098463de4c5d 303
group-onsemi 0:098463de4c5d 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 305 {
group-onsemi 0:098463de4c5d 306 uint32_t result;
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 309 return(result);
group-onsemi 0:098463de4c5d 310 }
group-onsemi 0:098463de4c5d 311
group-onsemi 0:098463de4c5d 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 313 {
group-onsemi 0:098463de4c5d 314 uint32_t result;
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 317 return(result);
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 321 {
group-onsemi 0:098463de4c5d 322 uint32_t result;
group-onsemi 0:098463de4c5d 323
group-onsemi 0:098463de4c5d 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 325 return(result);
group-onsemi 0:098463de4c5d 326 }
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 329 {
group-onsemi 0:098463de4c5d 330 uint32_t result;
group-onsemi 0:098463de4c5d 331
group-onsemi 0:098463de4c5d 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 333 return(result);
group-onsemi 0:098463de4c5d 334 }
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 337 {
group-onsemi 0:098463de4c5d 338 uint32_t result;
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 341 return(result);
group-onsemi 0:098463de4c5d 342 }
group-onsemi 0:098463de4c5d 343
group-onsemi 0:098463de4c5d 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 345 {
group-onsemi 0:098463de4c5d 346 uint32_t result;
group-onsemi 0:098463de4c5d 347
group-onsemi 0:098463de4c5d 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 349 return(result);
group-onsemi 0:098463de4c5d 350 }
group-onsemi 0:098463de4c5d 351
group-onsemi 0:098463de4c5d 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 353 {
group-onsemi 0:098463de4c5d 354 uint32_t result;
group-onsemi 0:098463de4c5d 355
group-onsemi 0:098463de4c5d 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 357 return(result);
group-onsemi 0:098463de4c5d 358 }
group-onsemi 0:098463de4c5d 359
group-onsemi 0:098463de4c5d 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 361 {
group-onsemi 0:098463de4c5d 362 uint32_t result;
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 365 return(result);
group-onsemi 0:098463de4c5d 366 }
group-onsemi 0:098463de4c5d 367
group-onsemi 0:098463de4c5d 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 369 {
group-onsemi 0:098463de4c5d 370 uint32_t result;
group-onsemi 0:098463de4c5d 371
group-onsemi 0:098463de4c5d 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 373 return(result);
group-onsemi 0:098463de4c5d 374 }
group-onsemi 0:098463de4c5d 375
group-onsemi 0:098463de4c5d 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 377 {
group-onsemi 0:098463de4c5d 378 uint32_t result;
group-onsemi 0:098463de4c5d 379
group-onsemi 0:098463de4c5d 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 381 return(result);
group-onsemi 0:098463de4c5d 382 }
group-onsemi 0:098463de4c5d 383
group-onsemi 0:098463de4c5d 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 385 {
group-onsemi 0:098463de4c5d 386 uint32_t result;
group-onsemi 0:098463de4c5d 387
group-onsemi 0:098463de4c5d 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 389 return(result);
group-onsemi 0:098463de4c5d 390 }
group-onsemi 0:098463de4c5d 391
group-onsemi 0:098463de4c5d 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 393 {
group-onsemi 0:098463de4c5d 394 uint32_t result;
group-onsemi 0:098463de4c5d 395
group-onsemi 0:098463de4c5d 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 397 return(result);
group-onsemi 0:098463de4c5d 398 }
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 401 {
group-onsemi 0:098463de4c5d 402 uint32_t result;
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 405 return(result);
group-onsemi 0:098463de4c5d 406 }
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 409 {
group-onsemi 0:098463de4c5d 410 uint32_t result;
group-onsemi 0:098463de4c5d 411
group-onsemi 0:098463de4c5d 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 413 return(result);
group-onsemi 0:098463de4c5d 414 }
group-onsemi 0:098463de4c5d 415
group-onsemi 0:098463de4c5d 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 417 {
group-onsemi 0:098463de4c5d 418 uint32_t result;
group-onsemi 0:098463de4c5d 419
group-onsemi 0:098463de4c5d 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 421 return(result);
group-onsemi 0:098463de4c5d 422 }
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 425 {
group-onsemi 0:098463de4c5d 426 uint32_t result;
group-onsemi 0:098463de4c5d 427
group-onsemi 0:098463de4c5d 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 429 return(result);
group-onsemi 0:098463de4c5d 430 }
group-onsemi 0:098463de4c5d 431
group-onsemi 0:098463de4c5d 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 433 {
group-onsemi 0:098463de4c5d 434 uint32_t result;
group-onsemi 0:098463de4c5d 435
group-onsemi 0:098463de4c5d 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 437 return(result);
group-onsemi 0:098463de4c5d 438 }
group-onsemi 0:098463de4c5d 439
group-onsemi 0:098463de4c5d 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 441 {
group-onsemi 0:098463de4c5d 442 uint32_t result;
group-onsemi 0:098463de4c5d 443
group-onsemi 0:098463de4c5d 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 445 return(result);
group-onsemi 0:098463de4c5d 446 }
group-onsemi 0:098463de4c5d 447
group-onsemi 0:098463de4c5d 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 449 {
group-onsemi 0:098463de4c5d 450 uint32_t result;
group-onsemi 0:098463de4c5d 451
group-onsemi 0:098463de4c5d 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 453 return(result);
group-onsemi 0:098463de4c5d 454 }
group-onsemi 0:098463de4c5d 455
group-onsemi 0:098463de4c5d 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 457 {
group-onsemi 0:098463de4c5d 458 uint32_t result;
group-onsemi 0:098463de4c5d 459
group-onsemi 0:098463de4c5d 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 461 return(result);
group-onsemi 0:098463de4c5d 462 }
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464 #define __SSAT16(ARG1,ARG2) \
group-onsemi 0:098463de4c5d 465 ({ \
group-onsemi 0:098463de4c5d 466 uint32_t __RES, __ARG1 = (ARG1); \
group-onsemi 0:098463de4c5d 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
group-onsemi 0:098463de4c5d 468 __RES; \
group-onsemi 0:098463de4c5d 469 })
group-onsemi 0:098463de4c5d 470
group-onsemi 0:098463de4c5d 471 #define __USAT16(ARG1,ARG2) \
group-onsemi 0:098463de4c5d 472 ({ \
group-onsemi 0:098463de4c5d 473 uint32_t __RES, __ARG1 = (ARG1); \
group-onsemi 0:098463de4c5d 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
group-onsemi 0:098463de4c5d 475 __RES; \
group-onsemi 0:098463de4c5d 476 })
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
group-onsemi 0:098463de4c5d 479 {
group-onsemi 0:098463de4c5d 480 uint32_t result;
group-onsemi 0:098463de4c5d 481
group-onsemi 0:098463de4c5d 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
group-onsemi 0:098463de4c5d 483 return(result);
group-onsemi 0:098463de4c5d 484 }
group-onsemi 0:098463de4c5d 485
group-onsemi 0:098463de4c5d 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 487 {
group-onsemi 0:098463de4c5d 488 uint32_t result;
group-onsemi 0:098463de4c5d 489
group-onsemi 0:098463de4c5d 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 491 return(result);
group-onsemi 0:098463de4c5d 492 }
group-onsemi 0:098463de4c5d 493
group-onsemi 0:098463de4c5d 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
group-onsemi 0:098463de4c5d 495 {
group-onsemi 0:098463de4c5d 496 uint32_t result;
group-onsemi 0:098463de4c5d 497
group-onsemi 0:098463de4c5d 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
group-onsemi 0:098463de4c5d 499 return(result);
group-onsemi 0:098463de4c5d 500 }
group-onsemi 0:098463de4c5d 501
group-onsemi 0:098463de4c5d 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 503 {
group-onsemi 0:098463de4c5d 504 uint32_t result;
group-onsemi 0:098463de4c5d 505
group-onsemi 0:098463de4c5d 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 507 return(result);
group-onsemi 0:098463de4c5d 508 }
group-onsemi 0:098463de4c5d 509
group-onsemi 0:098463de4c5d 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 511 {
group-onsemi 0:098463de4c5d 512 uint32_t result;
group-onsemi 0:098463de4c5d 513
group-onsemi 0:098463de4c5d 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 515 return(result);
group-onsemi 0:098463de4c5d 516 }
group-onsemi 0:098463de4c5d 517
group-onsemi 0:098463de4c5d 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 519 {
group-onsemi 0:098463de4c5d 520 uint32_t result;
group-onsemi 0:098463de4c5d 521
group-onsemi 0:098463de4c5d 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 523 return(result);
group-onsemi 0:098463de4c5d 524 }
group-onsemi 0:098463de4c5d 525
group-onsemi 0:098463de4c5d 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 527 {
group-onsemi 0:098463de4c5d 528 uint32_t result;
group-onsemi 0:098463de4c5d 529
group-onsemi 0:098463de4c5d 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 531 return(result);
group-onsemi 0:098463de4c5d 532 }
group-onsemi 0:098463de4c5d 533
group-onsemi 0:098463de4c5d 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 535 {
group-onsemi 0:098463de4c5d 536 uint32_t result;
group-onsemi 0:098463de4c5d 537
group-onsemi 0:098463de4c5d 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 539 return(result);
group-onsemi 0:098463de4c5d 540 }
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 #define __SMLALD(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 543 ({ \
group-onsemi 0:098463de4c5d 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
group-onsemi 0:098463de4c5d 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
group-onsemi 0:098463de4c5d 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
group-onsemi 0:098463de4c5d 547 })
group-onsemi 0:098463de4c5d 548
group-onsemi 0:098463de4c5d 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 550 ({ \
group-onsemi 0:098463de4c5d 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
group-onsemi 0:098463de4c5d 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
group-onsemi 0:098463de4c5d 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
group-onsemi 0:098463de4c5d 554 })
group-onsemi 0:098463de4c5d 555
group-onsemi 0:098463de4c5d 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 557 {
group-onsemi 0:098463de4c5d 558 uint32_t result;
group-onsemi 0:098463de4c5d 559
group-onsemi 0:098463de4c5d 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 561 return(result);
group-onsemi 0:098463de4c5d 562 }
group-onsemi 0:098463de4c5d 563
group-onsemi 0:098463de4c5d 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 565 {
group-onsemi 0:098463de4c5d 566 uint32_t result;
group-onsemi 0:098463de4c5d 567
group-onsemi 0:098463de4c5d 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 569 return(result);
group-onsemi 0:098463de4c5d 570 }
group-onsemi 0:098463de4c5d 571
group-onsemi 0:098463de4c5d 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 573 {
group-onsemi 0:098463de4c5d 574 uint32_t result;
group-onsemi 0:098463de4c5d 575
group-onsemi 0:098463de4c5d 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 577 return(result);
group-onsemi 0:098463de4c5d 578 }
group-onsemi 0:098463de4c5d 579
group-onsemi 0:098463de4c5d 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
group-onsemi 0:098463de4c5d 581 {
group-onsemi 0:098463de4c5d 582 uint32_t result;
group-onsemi 0:098463de4c5d 583
group-onsemi 0:098463de4c5d 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 585 return(result);
group-onsemi 0:098463de4c5d 586 }
group-onsemi 0:098463de4c5d 587
group-onsemi 0:098463de4c5d 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 589 ({ \
group-onsemi 0:098463de4c5d 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
group-onsemi 0:098463de4c5d 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
group-onsemi 0:098463de4c5d 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
group-onsemi 0:098463de4c5d 593 })
group-onsemi 0:098463de4c5d 594
group-onsemi 0:098463de4c5d 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 596 ({ \
group-onsemi 0:098463de4c5d 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
group-onsemi 0:098463de4c5d 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
group-onsemi 0:098463de4c5d 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
group-onsemi 0:098463de4c5d 600 })
group-onsemi 0:098463de4c5d 601
group-onsemi 0:098463de4c5d 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 603 {
group-onsemi 0:098463de4c5d 604 uint32_t result;
group-onsemi 0:098463de4c5d 605
group-onsemi 0:098463de4c5d 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 607 return(result);
group-onsemi 0:098463de4c5d 608 }
group-onsemi 0:098463de4c5d 609
group-onsemi 0:098463de4c5d 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 611 {
group-onsemi 0:098463de4c5d 612 uint32_t result;
group-onsemi 0:098463de4c5d 613
group-onsemi 0:098463de4c5d 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 615 return(result);
group-onsemi 0:098463de4c5d 616 }
group-onsemi 0:098463de4c5d 617
group-onsemi 0:098463de4c5d 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
group-onsemi 0:098463de4c5d 619 {
group-onsemi 0:098463de4c5d 620 uint32_t result;
group-onsemi 0:098463de4c5d 621
group-onsemi 0:098463de4c5d 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
group-onsemi 0:098463de4c5d 623 return(result);
group-onsemi 0:098463de4c5d 624 }
group-onsemi 0:098463de4c5d 625
group-onsemi 0:098463de4c5d 626 #define __PKHBT(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 627 ({ \
group-onsemi 0:098463de4c5d 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
group-onsemi 0:098463de4c5d 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
group-onsemi 0:098463de4c5d 630 __RES; \
group-onsemi 0:098463de4c5d 631 })
group-onsemi 0:098463de4c5d 632
group-onsemi 0:098463de4c5d 633 #define __PKHTB(ARG1,ARG2,ARG3) \
group-onsemi 0:098463de4c5d 634 ({ \
group-onsemi 0:098463de4c5d 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
group-onsemi 0:098463de4c5d 636 if (ARG3 == 0) \
group-onsemi 0:098463de4c5d 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
group-onsemi 0:098463de4c5d 638 else \
group-onsemi 0:098463de4c5d 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
group-onsemi 0:098463de4c5d 640 __RES; \
group-onsemi 0:098463de4c5d 641 })
group-onsemi 0:098463de4c5d 642
group-onsemi 0:098463de4c5d 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
group-onsemi 0:098463de4c5d 644 {
group-onsemi 0:098463de4c5d 645 int32_t result;
group-onsemi 0:098463de4c5d 646
group-onsemi 0:098463de4c5d 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
group-onsemi 0:098463de4c5d 648 return(result);
group-onsemi 0:098463de4c5d 649 }
group-onsemi 0:098463de4c5d 650
group-onsemi 0:098463de4c5d 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 652
group-onsemi 0:098463de4c5d 653
group-onsemi 0:098463de4c5d 654
group-onsemi 0:098463de4c5d 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
group-onsemi 0:098463de4c5d 656 /* TASKING carm specific functions */
group-onsemi 0:098463de4c5d 657
group-onsemi 0:098463de4c5d 658
group-onsemi 0:098463de4c5d 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 660 /* not yet supported */
group-onsemi 0:098463de4c5d 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
group-onsemi 0:098463de4c5d 662
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 #endif
group-onsemi 0:098463de4c5d 665
group-onsemi 0:098463de4c5d 666 /*@} end of group CMSIS_SIMD_intrinsics */
group-onsemi 0:098463de4c5d 667
group-onsemi 0:098463de4c5d 668
group-onsemi 0:098463de4c5d 669 #endif /* __CORE_CM4_SIMD_H */
group-onsemi 0:098463de4c5d 670
group-onsemi 0:098463de4c5d 671 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 672 }
group-onsemi 0:098463de4c5d 673 #endif