ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

cmsis/core_ca9.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file core_ca9.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
group-onsemi 0:098463de4c5d 4 * @version
group-onsemi 0:098463de4c5d 5 * @date 25 March 2013
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @note
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 ******************************************************************************/
group-onsemi 0:098463de4c5d 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 All rights reserved.
group-onsemi 0:098463de4c5d 13 Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 14 modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 - Redistributions of source code must retain the above copyright
group-onsemi 0:098463de4c5d 16 notice, this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 - Redistributions in binary form must reproduce the above copyright
group-onsemi 0:098463de4c5d 18 notice, this list of conditions and the following disclaimer in the
group-onsemi 0:098463de4c5d 19 documentation and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 - Neither the name of ARM nor the names of its contributors may be used
group-onsemi 0:098463de4c5d 21 to endorse or promote products derived from this software without
group-onsemi 0:098463de4c5d 22 specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
group-onsemi 0:098463de4c5d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
group-onsemi 0:098463de4c5d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
group-onsemi 0:098463de4c5d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
group-onsemi 0:098463de4c5d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
group-onsemi 0:098463de4c5d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
group-onsemi 0:098463de4c5d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
group-onsemi 0:098463de4c5d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
group-onsemi 0:098463de4c5d 34 POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 35 ---------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #if defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 39 #pragma system_include /* treat file as system include file for MISRA check */
group-onsemi 0:098463de4c5d 40 #endif
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 43 extern "C" {
group-onsemi 0:098463de4c5d 44 #endif
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 #ifndef __CORE_CA9_H_GENERIC
group-onsemi 0:098463de4c5d 47 #define __CORE_CA9_H_GENERIC
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
group-onsemi 0:098463de4c5d 51 CMSIS violates the following MISRA-C:2004 rules:
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 \li Required Rule 8.5, object/function definition in header file.<br>
group-onsemi 0:098463de4c5d 54 Function definitions in header files are used to allow 'inlining'.
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
group-onsemi 0:098463de4c5d 57 Unions are used for effective representation of core registers.
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
group-onsemi 0:098463de4c5d 60 Function-like macros are used to allow more efficient code.
group-onsemi 0:098463de4c5d 61 */
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 /*******************************************************************************
group-onsemi 0:098463de4c5d 65 * CMSIS definitions
group-onsemi 0:098463de4c5d 66 ******************************************************************************/
group-onsemi 0:098463de4c5d 67 /** \ingroup Cortex_A9
group-onsemi 0:098463de4c5d 68 @{
group-onsemi 0:098463de4c5d 69 */
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 /* CMSIS CA9 definitions */
group-onsemi 0:098463de4c5d 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
group-onsemi 0:098463de4c5d 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
group-onsemi 0:098463de4c5d 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
group-onsemi 0:098463de4c5d 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
group-onsemi 0:098463de4c5d 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
group-onsemi 0:098463de4c5d 83 #define __STATIC_INLINE static __inline
group-onsemi 0:098463de4c5d 84 #define __STATIC_ASM static __asm
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 #elif defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
group-onsemi 0:098463de4c5d 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
group-onsemi 0:098463de4c5d 89 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 90 #define __STATIC_ASM static __asm
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 #include <stdint.h>
group-onsemi 0:098463de4c5d 93 inline uint32_t __get_PSR(void) {
group-onsemi 0:098463de4c5d 94 __ASM("mrs r0, cpsr");
group-onsemi 0:098463de4c5d 95 }
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 #elif defined ( __TMS470__ )
group-onsemi 0:098463de4c5d 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
group-onsemi 0:098463de4c5d 99 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 100 #define __STATIC_ASM static __asm
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 #elif defined ( __GNUC__ )
group-onsemi 0:098463de4c5d 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
group-onsemi 0:098463de4c5d 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
group-onsemi 0:098463de4c5d 105 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 106 #define __STATIC_ASM static __asm
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 #elif defined ( __TASKING__ )
group-onsemi 0:098463de4c5d 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
group-onsemi 0:098463de4c5d 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
group-onsemi 0:098463de4c5d 111 #define __STATIC_INLINE static inline
group-onsemi 0:098463de4c5d 112 #define __STATIC_ASM static __asm
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 #endif
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
group-onsemi 0:098463de4c5d 117 */
group-onsemi 0:098463de4c5d 118 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 119 #if defined __TARGET_FPU_VFP
group-onsemi 0:098463de4c5d 120 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 121 #define __FPU_USED 1
group-onsemi 0:098463de4c5d 122 #else
group-onsemi 0:098463de4c5d 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 124 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 125 #endif
group-onsemi 0:098463de4c5d 126 #else
group-onsemi 0:098463de4c5d 127 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 128 #endif
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 #elif defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 131 #if defined __ARMVFP__
group-onsemi 0:098463de4c5d 132 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 133 #define __FPU_USED 1
group-onsemi 0:098463de4c5d 134 #else
group-onsemi 0:098463de4c5d 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 136 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 137 #endif
group-onsemi 0:098463de4c5d 138 #else
group-onsemi 0:098463de4c5d 139 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 140 #endif
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 #elif defined ( __TMS470__ )
group-onsemi 0:098463de4c5d 143 #if defined __TI_VFP_SUPPORT__
group-onsemi 0:098463de4c5d 144 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 145 #define __FPU_USED 1
group-onsemi 0:098463de4c5d 146 #else
group-onsemi 0:098463de4c5d 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 148 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 149 #endif
group-onsemi 0:098463de4c5d 150 #else
group-onsemi 0:098463de4c5d 151 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 152 #endif
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 #elif defined ( __GNUC__ )
group-onsemi 0:098463de4c5d 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
group-onsemi 0:098463de4c5d 156 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 157 #define __FPU_USED 1
group-onsemi 0:098463de4c5d 158 #else
group-onsemi 0:098463de4c5d 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 160 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 161 #endif
group-onsemi 0:098463de4c5d 162 #else
group-onsemi 0:098463de4c5d 163 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 164 #endif
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 #elif defined ( __TASKING__ )
group-onsemi 0:098463de4c5d 167 #if defined __FPU_VFP__
group-onsemi 0:098463de4c5d 168 #if (__FPU_PRESENT == 1)
group-onsemi 0:098463de4c5d 169 #define __FPU_USED 1
group-onsemi 0:098463de4c5d 170 #else
group-onsemi 0:098463de4c5d 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
group-onsemi 0:098463de4c5d 172 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 173 #endif
group-onsemi 0:098463de4c5d 174 #else
group-onsemi 0:098463de4c5d 175 #define __FPU_USED 0
group-onsemi 0:098463de4c5d 176 #endif
group-onsemi 0:098463de4c5d 177 #endif
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 #include <stdint.h> /*!< standard types definitions */
group-onsemi 0:098463de4c5d 180 #include "core_caInstr.h" /*!< Core Instruction Access */
group-onsemi 0:098463de4c5d 181 #include "core_caFunc.h" /*!< Core Function Access */
group-onsemi 0:098463de4c5d 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 #endif /* __CORE_CA9_H_GENERIC */
group-onsemi 0:098463de4c5d 185
group-onsemi 0:098463de4c5d 186 #ifndef __CMSIS_GENERIC
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 #ifndef __CORE_CA9_H_DEPENDANT
group-onsemi 0:098463de4c5d 189 #define __CORE_CA9_H_DEPENDANT
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 /* check device defines and use defaults */
group-onsemi 0:098463de4c5d 192 #if defined __CHECK_DEVICE_DEFINES
group-onsemi 0:098463de4c5d 193 #ifndef __CA9_REV
group-onsemi 0:098463de4c5d 194 #define __CA9_REV 0x0000
group-onsemi 0:098463de4c5d 195 #warning "__CA9_REV not defined in device header file; using default!"
group-onsemi 0:098463de4c5d 196 #endif
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 #ifndef __FPU_PRESENT
group-onsemi 0:098463de4c5d 199 #define __FPU_PRESENT 1
group-onsemi 0:098463de4c5d 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
group-onsemi 0:098463de4c5d 201 #endif
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 #ifndef __Vendor_SysTickConfig
group-onsemi 0:098463de4c5d 204 #define __Vendor_SysTickConfig 1
group-onsemi 0:098463de4c5d 205 #endif
group-onsemi 0:098463de4c5d 206
group-onsemi 0:098463de4c5d 207 #if __Vendor_SysTickConfig == 0
group-onsemi 0:098463de4c5d 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
group-onsemi 0:098463de4c5d 209 #endif
group-onsemi 0:098463de4c5d 210 #endif
group-onsemi 0:098463de4c5d 211
group-onsemi 0:098463de4c5d 212 /* IO definitions (access restrictions to peripheral registers) */
group-onsemi 0:098463de4c5d 213 /**
group-onsemi 0:098463de4c5d 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
group-onsemi 0:098463de4c5d 215
group-onsemi 0:098463de4c5d 216 <strong>IO Type Qualifiers</strong> are used
group-onsemi 0:098463de4c5d 217 \li to specify the access to peripheral variables.
group-onsemi 0:098463de4c5d 218 \li for automatic generation of peripheral register debug information.
group-onsemi 0:098463de4c5d 219 */
group-onsemi 0:098463de4c5d 220 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 221 #define __I volatile /*!< Defines 'read only' permissions */
group-onsemi 0:098463de4c5d 222 #else
group-onsemi 0:098463de4c5d 223 #define __I volatile const /*!< Defines 'read only' permissions */
group-onsemi 0:098463de4c5d 224 #endif
group-onsemi 0:098463de4c5d 225 #define __O volatile /*!< Defines 'write only' permissions */
group-onsemi 0:098463de4c5d 226 #define __IO volatile /*!< Defines 'read / write' permissions */
group-onsemi 0:098463de4c5d 227
group-onsemi 0:098463de4c5d 228 /*@} end of group Cortex_A9 */
group-onsemi 0:098463de4c5d 229
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 /*******************************************************************************
group-onsemi 0:098463de4c5d 232 * Register Abstraction
group-onsemi 0:098463de4c5d 233 ******************************************************************************/
group-onsemi 0:098463de4c5d 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
group-onsemi 0:098463de4c5d 235 \brief Type definitions and defines for Cortex-A processor based devices.
group-onsemi 0:098463de4c5d 236 */
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 /** \ingroup CMSIS_core_register
group-onsemi 0:098463de4c5d 239 \defgroup CMSIS_CORE Status and Control Registers
group-onsemi 0:098463de4c5d 240 \brief Core Register type definitions.
group-onsemi 0:098463de4c5d 241 @{
group-onsemi 0:098463de4c5d 242 */
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244 /** \brief Union type to access the Application Program Status Register (APSR).
group-onsemi 0:098463de4c5d 245 */
group-onsemi 0:098463de4c5d 246 typedef union
group-onsemi 0:098463de4c5d 247 {
group-onsemi 0:098463de4c5d 248 struct
group-onsemi 0:098463de4c5d 249 {
group-onsemi 0:098463de4c5d 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
group-onsemi 0:098463de4c5d 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
group-onsemi 0:098463de4c5d 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
group-onsemi 0:098463de4c5d 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
group-onsemi 0:098463de4c5d 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
group-onsemi 0:098463de4c5d 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
group-onsemi 0:098463de4c5d 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
group-onsemi 0:098463de4c5d 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
group-onsemi 0:098463de4c5d 258 } b; /*!< Structure used for bit access */
group-onsemi 0:098463de4c5d 259 uint32_t w; /*!< Type used for word access */
group-onsemi 0:098463de4c5d 260 } APSR_Type;
group-onsemi 0:098463de4c5d 261
group-onsemi 0:098463de4c5d 262
group-onsemi 0:098463de4c5d 263 /*@} end of group CMSIS_CORE */
group-onsemi 0:098463de4c5d 264
group-onsemi 0:098463de4c5d 265 /*@} end of CMSIS_Core_FPUFunctions */
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267
group-onsemi 0:098463de4c5d 268 #endif /* __CORE_CA9_H_GENERIC */
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 #endif /* __CMSIS_GENERIC */
group-onsemi 0:098463de4c5d 271
group-onsemi 0:098463de4c5d 272 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 273 }
group-onsemi 0:098463de4c5d 274
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 #endif