WizziLab / X_NUCLEO_IKS01A1

Suppressed conflicting destructor function.

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   D7A_1x_TRAINING D7_MLX_AND_BAT D7A_1x_demo_sensors_v3

Fork of X_NUCLEO_IKS01A1 by ST

Components/lsm303c/LSM303C_MAG_driver.h@99:5233cf5eb09d, 2017-02-09 (annotated)

Committer:
yordan
Date:
Thu Feb 09 16:10:33 2017 +0000
Revision:
99:5233cf5eb09d
Parent:
97:de5a5c00299a 
Fix regression with DEBUG_LED on NUCLEO-L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jeej 96:8cac3f3245b5 1 /**
Jeej 96:8cac3f3245b5 2 ******************************************************************************
Jeej 96:8cac3f3245b5 3 * @file LSM303C_MAG_driver.h
Jeej 96:8cac3f3245b5 4 * @author MEMS Application Team
Jeej 96:8cac3f3245b5 5 * @version V1.1
Jeej 96:8cac3f3245b5 6 * @date 25-February-2016
Jeej 96:8cac3f3245b5 7 * @brief LSM303C Magnetometer header driver file
Jeej 96:8cac3f3245b5 8 ******************************************************************************
Jeej 96:8cac3f3245b5 9 * @attention
Jeej 96:8cac3f3245b5 10 *
Jeej 96:8cac3f3245b5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Jeej 96:8cac3f3245b5 12 *
Jeej 96:8cac3f3245b5 13 * Redistribution and use in source and binary forms, with or without modification,
Jeej 96:8cac3f3245b5 14 * are permitted provided that the following conditions are met:
Jeej 96:8cac3f3245b5 15 * 1. Redistributions of source code must retain the above copyright notice,
Jeej 96:8cac3f3245b5 16 * this list of conditions and the following disclaimer.
Jeej 96:8cac3f3245b5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Jeej 96:8cac3f3245b5 18 * this list of conditions and the following disclaimer in the documentation
Jeej 96:8cac3f3245b5 19 * and/or other materials provided with the distribution.
Jeej 96:8cac3f3245b5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Jeej 96:8cac3f3245b5 21 * may be used to endorse or promote products derived from this software
Jeej 96:8cac3f3245b5 22 * without specific prior written permission.
Jeej 96:8cac3f3245b5 23 *
Jeej 96:8cac3f3245b5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Jeej 96:8cac3f3245b5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Jeej 96:8cac3f3245b5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jeej 96:8cac3f3245b5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Jeej 96:8cac3f3245b5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Jeej 96:8cac3f3245b5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Jeej 96:8cac3f3245b5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Jeej 96:8cac3f3245b5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Jeej 96:8cac3f3245b5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Jeej 96:8cac3f3245b5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jeej 96:8cac3f3245b5 34 *
Jeej 96:8cac3f3245b5 35 ******************************************************************************
Jeej 96:8cac3f3245b5 36 */
Jeej 96:8cac3f3245b5 37
Jeej 96:8cac3f3245b5 38 /* Define to prevent recursive inclusion -------------------------------------*/
Jeej 96:8cac3f3245b5 39 #ifndef __LSM303C_MAG_DRIVER__H
Jeej 96:8cac3f3245b5 40 #define __LSM303C_MAG_DRIVER__H
Jeej 96:8cac3f3245b5 41
Jeej 96:8cac3f3245b5 42 /* Includes ------------------------------------------------------------------*/
Jeej 96:8cac3f3245b5 43 #include <stdint.h>
Jeej 96:8cac3f3245b5 44
Jeej 96:8cac3f3245b5 45 /* Exported types ------------------------------------------------------------*/
Jeej 96:8cac3f3245b5 46
Jeej 96:8cac3f3245b5 47 #ifdef __cplusplus
Jeej 96:8cac3f3245b5 48 extern "C" {
Jeej 96:8cac3f3245b5 49 #endif
Jeej 96:8cac3f3245b5 50
Jeej 96:8cac3f3245b5 51 //these could change accordingly with the architecture
Jeej 96:8cac3f3245b5 52
Jeej 96:8cac3f3245b5 53 #ifndef __ARCHDEP__TYPES
Jeej 96:8cac3f3245b5 54 #define __ARCHDEP__TYPES
Jeej 96:8cac3f3245b5 55
Jeej 96:8cac3f3245b5 56 typedef unsigned char u8_t;
Jeej 96:8cac3f3245b5 57 typedef unsigned short int u16_t;
Jeej 96:8cac3f3245b5 58 typedef unsigned int u32_t;
Jeej 96:8cac3f3245b5 59 typedef int i32_t;
Jeej 96:8cac3f3245b5 60 typedef short int i16_t;
Jeej 96:8cac3f3245b5 61 typedef signed char i8_t;
Jeej 96:8cac3f3245b5 62
Jeej 96:8cac3f3245b5 63 #endif /*__ARCHDEP__TYPES*/
Jeej 96:8cac3f3245b5 64
Jeej 96:8cac3f3245b5 65 /* Exported common structure --------------------------------------------------------*/
Jeej 96:8cac3f3245b5 66
Jeej 96:8cac3f3245b5 67 #ifndef __SHARED__TYPES
Jeej 96:8cac3f3245b5 68 #define __SHARED__TYPES
Jeej 96:8cac3f3245b5 69
Jeej 96:8cac3f3245b5 70 typedef union{
Jeej 96:8cac3f3245b5 71 i16_t i16bit[3];
Jeej 96:8cac3f3245b5 72 u8_t u8bit[6];
Jeej 96:8cac3f3245b5 73 } Type3Axis16bit_U;
Jeej 96:8cac3f3245b5 74
Jeej 96:8cac3f3245b5 75 typedef union{
Jeej 96:8cac3f3245b5 76 i16_t i16bit;
Jeej 96:8cac3f3245b5 77 u8_t u8bit[2];
Jeej 96:8cac3f3245b5 78 } Type1Axis16bit_U;
Jeej 96:8cac3f3245b5 79
Jeej 96:8cac3f3245b5 80 typedef union{
Jeej 96:8cac3f3245b5 81 i32_t i32bit;
Jeej 96:8cac3f3245b5 82 u8_t u8bit[4];
Jeej 96:8cac3f3245b5 83 } Type1Axis32bit_U;
Jeej 96:8cac3f3245b5 84
Jeej 96:8cac3f3245b5 85 typedef enum {
Jeej 96:8cac3f3245b5 86 MEMS_SUCCESS = 0x01,
Jeej 96:8cac3f3245b5 87 MEMS_ERROR = 0x00
Jeej 96:8cac3f3245b5 88 } status_t;
Jeej 96:8cac3f3245b5 89
Jeej 96:8cac3f3245b5 90 #endif /*__SHARED__TYPES*/
Jeej 96:8cac3f3245b5 91
Jeej 96:8cac3f3245b5 92 /* Exported macro ------------------------------------------------------------*/
Jeej 96:8cac3f3245b5 93
Jeej 96:8cac3f3245b5 94 /* Exported constants --------------------------------------------------------*/
Jeej 96:8cac3f3245b5 95
Jeej 96:8cac3f3245b5 96 /************** I2C Address *****************/
Jeej 96:8cac3f3245b5 97
Jeej 96:8cac3f3245b5 98 #define LSM303C_MAG_I2C_ADDRESS 0x3C
Jeej 97:de5a5c00299a 99 #define I_AM_LSM303C_MAG 0x3D
Jeej 96:8cac3f3245b5 100
Jeej 96:8cac3f3245b5 101 /* Magnetic field Registers */
Jeej 96:8cac3f3245b5 102 #define LSM303C_WHO_AM_I_REG_M 0x0F /* device identification register */
Jeej 96:8cac3f3245b5 103 #define LSM303C_CTRL_REG1_M 0x20 /* Magnetic control register 1 */
Jeej 96:8cac3f3245b5 104 #define LSM303C_CTRL_REG2_M 0x21 /* Magnetic control register 2 */
Jeej 96:8cac3f3245b5 105 #define LSM303C_CTRL_REG3_M 0x22 /* Magnetic control register 3 */
Jeej 96:8cac3f3245b5 106 #define LSM303C_CTRL_REG4_M 0x23 /* Magnetic control register 4 */
Jeej 96:8cac3f3245b5 107 #define LSM303C_CTRL_REG5_M 0x24 /* Magnetic control register 5 */
Jeej 96:8cac3f3245b5 108
Jeej 96:8cac3f3245b5 109 #define LSM303C_STATUS_REG_M 0x27 /* Magnetic status register M */
Jeej 96:8cac3f3245b5 110
Jeej 96:8cac3f3245b5 111 #define LSM303C_OUT_X_L_M 0x28 /* Output Register X magnetic field */
Jeej 96:8cac3f3245b5 112 #define LSM303C_OUT_X_H_M 0x29 /* Output Register X magnetic field */
Jeej 96:8cac3f3245b5 113 #define LSM303C_OUT_Y_L_M 0x2A /* Output Register Y magnetic field */
Jeej 96:8cac3f3245b5 114 #define LSM303C_OUT_Y_H_M 0x2B /* Output Register Y magnetic field */
Jeej 96:8cac3f3245b5 115 #define LSM303C_OUT_Z_L_M 0x2C /* Output Register Z magnetic field */
Jeej 96:8cac3f3245b5 116 #define LSM303C_OUT_Z_H_M 0x2D /* Output Register Z magnetic field */
Jeej 96:8cac3f3245b5 117
Jeej 96:8cac3f3245b5 118 #define LSM303C_TEMP_OUT_L_M 0x2E /* Temperature Register magnetic field */
Jeej 96:8cac3f3245b5 119 #define LSM303C_TEMP_OUT_H_M 0x2F /* Temperature Register magnetic field */
Jeej 96:8cac3f3245b5 120
Jeej 96:8cac3f3245b5 121 #define LSM303C_INT_CFG_M 0x30 /* Axis interrupt configuration */
Jeej 96:8cac3f3245b5 122 #define LSM303C_INT_SRC_M 0x31 /* Axis interrupt source */
Jeej 96:8cac3f3245b5 123 #define LSM303C_INT_THS_L_M 0x32 /* Interrupt threshold L */
Jeej 96:8cac3f3245b5 124 #define LSM303C_INT_THS_H_M 0x33 /* Interrupt threshold M */
Jeej 96:8cac3f3245b5 125
Jeej 96:8cac3f3245b5 126 /* Private Function Prototype -------------------------------------------------------*/
Jeej 96:8cac3f3245b5 127
Jeej 96:8cac3f3245b5 128 void LSM303C_MAG_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension);
Jeej 96:8cac3f3245b5 129
Jeej 96:8cac3f3245b5 130 /* Public Function Prototypes -------------------------------------------------------*/
Jeej 96:8cac3f3245b5 131
Jeej 96:8cac3f3245b5 132 status_t LSM303C_MAG_ReadReg( void *handle, u8_t Reg, u8_t* Data );
Jeej 96:8cac3f3245b5 133 status_t LSM303C_MAG_WriteReg( void *handle, u8_t Reg, u8_t Data );
Jeej 96:8cac3f3245b5 134
Jeej 96:8cac3f3245b5 135 /*******************************************************************************
Jeej 96:8cac3f3245b5 136 * Register : WHO_AM_I_REG
Jeej 96:8cac3f3245b5 137 * Address : 0X4F
Jeej 96:8cac3f3245b5 138 * Bit Group Name: WHO_AM_I
Jeej 96:8cac3f3245b5 139 * Permission : RO
Jeej 96:8cac3f3245b5 140 *******************************************************************************/
Jeej 96:8cac3f3245b5 141 #define LSM303C_MAG_WHO_AM_I_MASK 0xFF
Jeej 96:8cac3f3245b5 142 #define LSM303C_MAG_WHO_AM_I_POSITION 0
Jeej 96:8cac3f3245b5 143 status_t LSM303C_MAG_R_WHO_AM_I(void *handle, u8_t *value);
Jeej 96:8cac3f3245b5 144
Jeej 96:8cac3f3245b5 145 /*******************************************************************************
Jeej 96:8cac3f3245b5 146 * Register : CFG_REG_A
Jeej 96:8cac3f3245b5 147 * Address : 0X60
Jeej 96:8cac3f3245b5 148 * Bit Group Name: MD
Jeej 96:8cac3f3245b5 149 * Permission : RW
Jeej 96:8cac3f3245b5 150 *******************************************************************************/
Jeej 96:8cac3f3245b5 151 typedef enum {
Jeej 96:8cac3f3245b5 152 LSM303C_MAG_MD_CONTINUOS_MODE =0x00,
Jeej 96:8cac3f3245b5 153 LSM303C_MAG_MD_SINGLE_MODE =0x01,
Jeej 96:8cac3f3245b5 154 LSM303C_MAG_MD_IDLE1_MODE =0x02,
Jeej 96:8cac3f3245b5 155 LSM303C_MAG_MD_IDLE2_MODE =0x03,
Jeej 96:8cac3f3245b5 156 } LSM303C_MAG_MD_t;
Jeej 96:8cac3f3245b5 157
Jeej 96:8cac3f3245b5 158 #define LSM303C_MAG_MD_MASK 0x03
Jeej 96:8cac3f3245b5 159 status_t LSM303C_MAG_W_MD(void *handle, LSM303C_MAG_MD_t newValue);
Jeej 96:8cac3f3245b5 160 status_t LSM303C_MAG_R_MD(void *handle, LSM303C_MAG_MD_t *value);
Jeej 96:8cac3f3245b5 161
Jeej 96:8cac3f3245b5 162 /*******************************************************************************
Jeej 96:8cac3f3245b5 163 * Register : CFG_REG_A
Jeej 96:8cac3f3245b5 164 * Address : 0X60
Jeej 96:8cac3f3245b5 165 * Bit Group Name: ODR
Jeej 96:8cac3f3245b5 166 * Permission : RW
Jeej 96:8cac3f3245b5 167 *******************************************************************************/
Jeej 96:8cac3f3245b5 168 typedef enum {
Jeej 96:8cac3f3245b5 169 LSM303C_MAG_ODR_0_625Hz =0x00,
Jeej 96:8cac3f3245b5 170 LSM303C_MAG_ODR_1_25Hz =0x04,
Jeej 96:8cac3f3245b5 171 LSM303C_MAG_ODR_2_5Hz =0x08,
Jeej 96:8cac3f3245b5 172 LSM303C_MAG_ODR_5Hz =0x0C,
Jeej 96:8cac3f3245b5 173 LSM303C_MAG_ODR_10Hz =0x10,
Jeej 96:8cac3f3245b5 174 LSM303C_MAG_ODR_20Hz =0x14,
Jeej 96:8cac3f3245b5 175 LSM303C_MAG_ODR_40Hz =0x18,
Jeej 96:8cac3f3245b5 176 LSM303C_MAG_ODR_80Hz =0x1C,
Jeej 96:8cac3f3245b5 177 } LSM303C_MAG_ODR_t;
Jeej 96:8cac3f3245b5 178
Jeej 96:8cac3f3245b5 179 #define LSM303C_MAG_ODR_MASK 0x1C
Jeej 96:8cac3f3245b5 180 status_t LSM303C_MAG_W_ODR(void *handle, LSM303C_MAG_ODR_t newValue);
Jeej 96:8cac3f3245b5 181 status_t LSM303C_MAG_R_ODR(void *handle, LSM303C_MAG_ODR_t *value);
Jeej 96:8cac3f3245b5 182
Jeej 96:8cac3f3245b5 183 /*******************************************************************************
Jeej 96:8cac3f3245b5 184 * Register : CFG_REG_A
Jeej 96:8cac3f3245b5 185 * Address : 0X60
Jeej 96:8cac3f3245b5 186 * Bit Group Name: LP
Jeej 96:8cac3f3245b5 187 * Permission : RW
Jeej 96:8cac3f3245b5 188 *******************************************************************************/
Jeej 96:8cac3f3245b5 189 typedef enum {
Jeej 96:8cac3f3245b5 190 LSM303C_MAG_HR_MODE =0x00,
Jeej 96:8cac3f3245b5 191 LSM303C_MAG_LP_MODE =0x20,
Jeej 96:8cac3f3245b5 192 } LSM303C_MAG_LP_t;
Jeej 96:8cac3f3245b5 193
Jeej 96:8cac3f3245b5 194 #define LSM303C_MAG_LP_MASK 0x20
Jeej 96:8cac3f3245b5 195 status_t LSM303C_MAG_W_LP(void *handle, LSM303C_MAG_LP_t newValue);
Jeej 96:8cac3f3245b5 196 status_t LSM303C_MAG_R_LP(void *handle, LSM303C_MAG_LP_t *value);
Jeej 96:8cac3f3245b5 197
Jeej 96:8cac3f3245b5 198 /*******************************************************************************
Jeej 96:8cac3f3245b5 199 * Register : CFG_REG_A
Jeej 96:8cac3f3245b5 200 * Address : 0X60
Jeej 96:8cac3f3245b5 201 * Bit Group Name: SOFT_RST
Jeej 96:8cac3f3245b5 202 * Permission : RW
Jeej 96:8cac3f3245b5 203 *******************************************************************************/
Jeej 96:8cac3f3245b5 204 typedef enum {
Jeej 96:8cac3f3245b5 205 LSM303C_MAG_SOFT_RST_DISABLED =0x00,
Jeej 96:8cac3f3245b5 206 LSM303C_MAG_SOFT_RST_ENABLED =0x04,
Jeej 96:8cac3f3245b5 207 } LSM303C_MAG_SOFT_RST_t;
Jeej 96:8cac3f3245b5 208
Jeej 96:8cac3f3245b5 209 #define LSM303C_MAG_SOFT_RST_MASK 0x04
Jeej 96:8cac3f3245b5 210 status_t LSM303C_MAG_W_SOFT_RST(void *handle, LSM303C_MAG_SOFT_RST_t newValue);
Jeej 96:8cac3f3245b5 211 status_t LSM303C_MAG_R_SOFT_RST(void *handle, LSM303C_MAG_SOFT_RST_t *value);
Jeej 96:8cac3f3245b5 212
Jeej 96:8cac3f3245b5 213 /*******************************************************************************
Jeej 96:8cac3f3245b5 214 * Register : CFG_REG_C
Jeej 96:8cac3f3245b5 215 * Address : 0X62
Jeej 96:8cac3f3245b5 216 * Bit Group Name: ST
Jeej 96:8cac3f3245b5 217 * Permission : RW
Jeej 96:8cac3f3245b5 218 *******************************************************************************/
Jeej 96:8cac3f3245b5 219 typedef enum {
Jeej 96:8cac3f3245b5 220 LSM303C_MAG_ST_DISABLED =0x00,
Jeej 96:8cac3f3245b5 221 LSM303C_MAG_ST_ENABLED =0x01,
Jeej 96:8cac3f3245b5 222 } LSM303C_MAG_ST_t;
Jeej 96:8cac3f3245b5 223
Jeej 96:8cac3f3245b5 224 #define LSM303C_MAG_ST_MASK 0x01
Jeej 96:8cac3f3245b5 225 status_t LSM303C_MAG_W_ST(void *handle, LSM303C_MAG_ST_t newValue);
Jeej 96:8cac3f3245b5 226 status_t LSM303C_MAG_R_ST(void *handle, LSM303C_MAG_ST_t *value);
Jeej 96:8cac3f3245b5 227
Jeej 96:8cac3f3245b5 228 /*******************************************************************************
Jeej 96:8cac3f3245b5 229 * Register : CFG_REG_C
Jeej 96:8cac3f3245b5 230 * Address : 0X62
Jeej 96:8cac3f3245b5 231 * Bit Group Name: BLE
Jeej 96:8cac3f3245b5 232 * Permission : RW
Jeej 96:8cac3f3245b5 233 *******************************************************************************/
Jeej 96:8cac3f3245b5 234 typedef enum {
Jeej 96:8cac3f3245b5 235 LSM303C_MAG_BLE_DISABLED =0x00,
Jeej 96:8cac3f3245b5 236 LSM303C_MAG_BLE_ENABLED =0x02,
Jeej 96:8cac3f3245b5 237 } LSM303C_MAG_BLE_t;
Jeej 96:8cac3f3245b5 238
Jeej 96:8cac3f3245b5 239 #define LSM303C_MAG_BLE_MASK 0x02
Jeej 96:8cac3f3245b5 240 status_t LSM303C_MAG_W_BLE(void *handle, LSM303C_MAG_BLE_t newValue);
Jeej 96:8cac3f3245b5 241 status_t LSM303C_MAG_R_BLE(void *handle, LSM303C_MAG_BLE_t *value);
Jeej 96:8cac3f3245b5 242
Jeej 96:8cac3f3245b5 243 /*******************************************************************************
Jeej 96:8cac3f3245b5 244 * Register : CFG_REG_C
Jeej 96:8cac3f3245b5 245 * Address : 0X62
Jeej 96:8cac3f3245b5 246 * Bit Group Name: BDU
Jeej 96:8cac3f3245b5 247 * Permission : RW
Jeej 96:8cac3f3245b5 248 *******************************************************************************/
Jeej 96:8cac3f3245b5 249 typedef enum {
Jeej 96:8cac3f3245b5 250 LSM303C_MAG_BDU_DISABLED =0x00,
Jeej 96:8cac3f3245b5 251 LSM303C_MAG_BDU_ENABLED =0x40,
Jeej 96:8cac3f3245b5 252 } LSM303C_MAG_BDU_t;
Jeej 96:8cac3f3245b5 253
Jeej 96:8cac3f3245b5 254 #define LSM303C_MAG_BDU_MASK 0x40
Jeej 96:8cac3f3245b5 255 status_t LSM303C_MAG_W_BDU(void *handle, LSM303C_MAG_BDU_t newValue);
Jeej 96:8cac3f3245b5 256 status_t LSM303C_MAG_R_BDU(void *handle, LSM303C_MAG_BDU_t *value);
Jeej 96:8cac3f3245b5 257
Jeej 96:8cac3f3245b5 258 /*******************************************************************************
Jeej 96:8cac3f3245b5 259 * Register : CFG_REG_C
Jeej 96:8cac3f3245b5 260 * Address : 0X62
Jeej 96:8cac3f3245b5 261 * Bit Group Name: I2C_DIS
Jeej 96:8cac3f3245b5 262 * Permission : RW
Jeej 96:8cac3f3245b5 263 *******************************************************************************/
Jeej 96:8cac3f3245b5 264 typedef enum {
Jeej 96:8cac3f3245b5 265 LSM303C_MAG_I2C_ENABLED =0x00,
Jeej 96:8cac3f3245b5 266 LSM303C_MAG_I2C_DISABLED =0x80,
Jeej 96:8cac3f3245b5 267 } LSM303C_MAG_I2C_DIS_t;
Jeej 96:8cac3f3245b5 268
Jeej 96:8cac3f3245b5 269 #define LSM303C_MAG_I2C_DIS_MASK 0x80
Jeej 96:8cac3f3245b5 270 status_t LSM303C_MAG_W_I2C_DIS(void *handle, LSM303C_MAG_I2C_DIS_t newValue);
Jeej 96:8cac3f3245b5 271 status_t LSM303C_MAG_R_I2C_DIS(void *handle, LSM303C_MAG_I2C_DIS_t *value);
Jeej 96:8cac3f3245b5 272
Jeej 96:8cac3f3245b5 273 /*******************************************************************************
Jeej 96:8cac3f3245b5 274 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 275 * Address : 0X67
Jeej 96:8cac3f3245b5 276 * Bit Group Name: XDA
Jeej 96:8cac3f3245b5 277 * Permission : RO
Jeej 96:8cac3f3245b5 278 *******************************************************************************/
Jeej 96:8cac3f3245b5 279 typedef enum {
Jeej 96:8cac3f3245b5 280 LSM303C_MAG_XDA_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 281 LSM303C_MAG_XDA_EV_ON =0x01,
Jeej 96:8cac3f3245b5 282 } LSM303C_MAG_XDA_t;
Jeej 96:8cac3f3245b5 283
Jeej 96:8cac3f3245b5 284 #define LSM303C_MAG_XDA_MASK 0x01
Jeej 96:8cac3f3245b5 285 status_t LSM303C_MAG_R_XDA(void *handle, LSM303C_MAG_XDA_t *value);
Jeej 96:8cac3f3245b5 286
Jeej 96:8cac3f3245b5 287 /*******************************************************************************
Jeej 96:8cac3f3245b5 288 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 289 * Address : 0X67
Jeej 96:8cac3f3245b5 290 * Bit Group Name: YDA
Jeej 96:8cac3f3245b5 291 * Permission : RO
Jeej 96:8cac3f3245b5 292 *******************************************************************************/
Jeej 96:8cac3f3245b5 293 typedef enum {
Jeej 96:8cac3f3245b5 294 LSM303C_MAG_YDA_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 295 LSM303C_MAG_YDA_EV_ON =0x02,
Jeej 96:8cac3f3245b5 296 } LSM303C_MAG_YDA_t;
Jeej 96:8cac3f3245b5 297
Jeej 96:8cac3f3245b5 298 #define LSM303C_MAG_YDA_MASK 0x02
Jeej 96:8cac3f3245b5 299 status_t LSM303C_MAG_R_YDA(void *handle, LSM303C_MAG_YDA_t *value);
Jeej 96:8cac3f3245b5 300
Jeej 96:8cac3f3245b5 301 /*******************************************************************************
Jeej 96:8cac3f3245b5 302 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 303 * Address : 0X67
Jeej 96:8cac3f3245b5 304 * Bit Group Name: ZDA
Jeej 96:8cac3f3245b5 305 * Permission : RO
Jeej 96:8cac3f3245b5 306 *******************************************************************************/
Jeej 96:8cac3f3245b5 307 typedef enum {
Jeej 96:8cac3f3245b5 308 LSM303C_MAG_ZDA_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 309 LSM303C_MAG_ZDA_EV_ON =0x04,
Jeej 96:8cac3f3245b5 310 } LSM303C_MAG_ZDA_t;
Jeej 96:8cac3f3245b5 311
Jeej 96:8cac3f3245b5 312 #define LSM303C_MAG_ZDA_MASK 0x04
Jeej 96:8cac3f3245b5 313 status_t LSM303C_MAG_R_ZDA(void *handle, LSM303C_MAG_ZDA_t *value);
Jeej 96:8cac3f3245b5 314
Jeej 96:8cac3f3245b5 315 /*******************************************************************************
Jeej 96:8cac3f3245b5 316 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 317 * Address : 0X67
Jeej 96:8cac3f3245b5 318 * Bit Group Name: ZYXDA
Jeej 96:8cac3f3245b5 319 * Permission : RO
Jeej 96:8cac3f3245b5 320 *******************************************************************************/
Jeej 96:8cac3f3245b5 321 typedef enum {
Jeej 96:8cac3f3245b5 322 LSM303C_MAG_ZYXDA_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 323 LSM303C_MAG_ZYXDA_EV_ON =0x08,
Jeej 96:8cac3f3245b5 324 } LSM303C_MAG_ZYXDA_t;
Jeej 96:8cac3f3245b5 325
Jeej 96:8cac3f3245b5 326 #define LSM303C_MAG_ZYXDA_MASK 0x08
Jeej 96:8cac3f3245b5 327 status_t LSM303C_MAG_R_ZYXDA(void *handle, LSM303C_MAG_ZYXDA_t *value);
Jeej 96:8cac3f3245b5 328
Jeej 96:8cac3f3245b5 329 /*******************************************************************************
Jeej 96:8cac3f3245b5 330 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 331 * Address : 0X67
Jeej 96:8cac3f3245b5 332 * Bit Group Name: XOR
Jeej 96:8cac3f3245b5 333 * Permission : RO
Jeej 96:8cac3f3245b5 334 *******************************************************************************/
Jeej 96:8cac3f3245b5 335 typedef enum {
Jeej 96:8cac3f3245b5 336 LSM303C_MAG_XOR_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 337 LSM303C_MAG_XOR_EV_ON =0x10,
Jeej 96:8cac3f3245b5 338 } LSM303C_MAG_XOR_t;
Jeej 96:8cac3f3245b5 339
Jeej 96:8cac3f3245b5 340 #define LSM303C_MAG_XOR_MASK 0x10
Jeej 96:8cac3f3245b5 341 status_t LSM303C_MAG_R_XOR(void *handle, LSM303C_MAG_XOR_t *value);
Jeej 96:8cac3f3245b5 342
Jeej 96:8cac3f3245b5 343 /*******************************************************************************
Jeej 96:8cac3f3245b5 344 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 345 * Address : 0X67
Jeej 96:8cac3f3245b5 346 * Bit Group Name: YOR
Jeej 96:8cac3f3245b5 347 * Permission : RO
Jeej 96:8cac3f3245b5 348 *******************************************************************************/
Jeej 96:8cac3f3245b5 349 typedef enum {
Jeej 96:8cac3f3245b5 350 LSM303C_MAG_YOR_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 351 LSM303C_MAG_YOR_EV_ON =0x20,
Jeej 96:8cac3f3245b5 352 } LSM303C_MAG_YOR_t;
Jeej 96:8cac3f3245b5 353
Jeej 96:8cac3f3245b5 354 #define LSM303C_MAG_YOR_MASK 0x20
Jeej 96:8cac3f3245b5 355 status_t LSM303C_MAG_R_YOR(void *handle, LSM303C_MAG_YOR_t *value);
Jeej 96:8cac3f3245b5 356
Jeej 96:8cac3f3245b5 357 /*******************************************************************************
Jeej 96:8cac3f3245b5 358 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 359 * Address : 0X67
Jeej 96:8cac3f3245b5 360 * Bit Group Name: ZOR
Jeej 96:8cac3f3245b5 361 * Permission : RO
Jeej 96:8cac3f3245b5 362 *******************************************************************************/
Jeej 96:8cac3f3245b5 363 typedef enum {
Jeej 96:8cac3f3245b5 364 LSM303C_MAG_ZOR_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 365 LSM303C_MAG_ZOR_EV_ON =0x40,
Jeej 96:8cac3f3245b5 366 } LSM303C_MAG_ZOR_t;
Jeej 96:8cac3f3245b5 367
Jeej 96:8cac3f3245b5 368 #define LSM303C_MAG_ZOR_MASK 0x40
Jeej 96:8cac3f3245b5 369 status_t LSM303C_MAG_R_ZOR(void *handle, LSM303C_MAG_ZOR_t *value);
Jeej 96:8cac3f3245b5 370
Jeej 96:8cac3f3245b5 371 /*******************************************************************************
Jeej 96:8cac3f3245b5 372 * Register : STATUS_REG
Jeej 96:8cac3f3245b5 373 * Address : 0X67
Jeej 96:8cac3f3245b5 374 * Bit Group Name: ZYXOR
Jeej 96:8cac3f3245b5 375 * Permission : RO
Jeej 96:8cac3f3245b5 376 *******************************************************************************/
Jeej 96:8cac3f3245b5 377 typedef enum {
Jeej 96:8cac3f3245b5 378 LSM303C_MAG_ZYXOR_EV_OFF =0x00,
Jeej 96:8cac3f3245b5 379 LSM303C_MAG_ZYXOR_EV_ON =0x80,
Jeej 96:8cac3f3245b5 380 } LSM303C_MAG_ZYXOR_t;
Jeej 96:8cac3f3245b5 381
Jeej 96:8cac3f3245b5 382 #define LSM303C_MAG_ZYXOR_MASK 0x80
Jeej 96:8cac3f3245b5 383 status_t LSM303C_MAG_R_ZYXOR(void *handle, LSM303C_MAG_ZYXOR_t *value);
Jeej 96:8cac3f3245b5 384 /*******************************************************************************
Jeej 96:8cac3f3245b5 385 * Register : <REGISTER_L> - <REGISTER_H>
Jeej 96:8cac3f3245b5 386 * Output Type : Magnetic
Jeej 96:8cac3f3245b5 387 * Permission : ro
Jeej 96:8cac3f3245b5 388 *******************************************************************************/
Jeej 96:8cac3f3245b5 389 status_t LSM303C_MAG_Get_Raw_Magnetic(void *handle, u8_t *buff);
Jeej 96:8cac3f3245b5 390 status_t LSM303C_MAG_Get_Magnetic(void *handle, int *buff);
Jeej 96:8cac3f3245b5 391
Jeej 96:8cac3f3245b5 392 /*******************************************************************************
Jeej 96:8cac3f3245b5 393 * Register : <REGISTER_L> - <REGISTER_H>
Jeej 96:8cac3f3245b5 394 * Output Type : IntThreshld
Jeej 96:8cac3f3245b5 395 * Permission : rw
Jeej 96:8cac3f3245b5 396 *******************************************************************************/
Jeej 96:8cac3f3245b5 397 status_t LSM303C_MAG_Get_IntThreshld(void *handle, u8_t *buff);
Jeej 96:8cac3f3245b5 398 status_t LSM303C_MAG_Set_IntThreshld(void *handle, u8_t *buff);
Jeej 96:8cac3f3245b5 399
Jeej 96:8cac3f3245b5 400 #ifdef __cplusplus
Jeej 96:8cac3f3245b5 401 }
Jeej 96:8cac3f3245b5 402 #endif
Jeej 96:8cac3f3245b5 403
Jeej 96:8cac3f3245b5 404 #endif