WizziLab / X_NUCLEO_IKS01A1

Suppressed conflicting destructor function.

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   D7A_1x_TRAINING D7_MLX_AND_BAT D7A_1x_demo_sensors_v3

Fork of X_NUCLEO_IKS01A1 by ST

Components/lsm303c/LSM303C_ACC_driver.h@99:5233cf5eb09d, 2017-02-09 (annotated)

Committer:
yordan
Date:
Thu Feb 09 16:10:33 2017 +0000
Revision:
99:5233cf5eb09d
Parent:
97:de5a5c00299a 
Fix regression with DEBUG_LED on NUCLEO-L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jeej 96:8cac3f3245b5 1 /**
Jeej 96:8cac3f3245b5 2 ******************************************************************************
Jeej 96:8cac3f3245b5 3 * @file LSM303C_ACC_driver.h
Jeej 96:8cac3f3245b5 4 * @author MEMS Application Team
Jeej 96:8cac3f3245b5 5 * @version V1.1
Jeej 96:8cac3f3245b5 6 * @date 24-February-2016
Jeej 96:8cac3f3245b5 7 * @brief LSM303C Accelerometer header driver file
Jeej 96:8cac3f3245b5 8 ******************************************************************************
Jeej 96:8cac3f3245b5 9 * @attention
Jeej 96:8cac3f3245b5 10 *
Jeej 96:8cac3f3245b5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Jeej 96:8cac3f3245b5 12 *
Jeej 96:8cac3f3245b5 13 * Redistribution and use in source and binary forms, with or without modification,
Jeej 96:8cac3f3245b5 14 * are permitted provided that the following conditions are met:
Jeej 96:8cac3f3245b5 15 * 1. Redistributions of source code must retain the above copyright notice,
Jeej 96:8cac3f3245b5 16 * this list of conditions and the following disclaimer.
Jeej 96:8cac3f3245b5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Jeej 96:8cac3f3245b5 18 * this list of conditions and the following disclaimer in the documentation
Jeej 96:8cac3f3245b5 19 * and/or other materials provided with the distribution.
Jeej 96:8cac3f3245b5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Jeej 96:8cac3f3245b5 21 * may be used to endorse or promote products derived from this software
Jeej 96:8cac3f3245b5 22 * without specific prior written permission.
Jeej 96:8cac3f3245b5 23 *
Jeej 96:8cac3f3245b5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Jeej 96:8cac3f3245b5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Jeej 96:8cac3f3245b5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jeej 96:8cac3f3245b5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Jeej 96:8cac3f3245b5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Jeej 96:8cac3f3245b5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Jeej 96:8cac3f3245b5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Jeej 96:8cac3f3245b5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Jeej 96:8cac3f3245b5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Jeej 96:8cac3f3245b5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jeej 96:8cac3f3245b5 34 *
Jeej 96:8cac3f3245b5 35 ******************************************************************************
Jeej 96:8cac3f3245b5 36 */
Jeej 96:8cac3f3245b5 37
Jeej 96:8cac3f3245b5 38 /* Define to prevent recursive inclusion -------------------------------------*/
Jeej 96:8cac3f3245b5 39 #ifndef __LSM303C_ACC_DRIVER__H
Jeej 96:8cac3f3245b5 40 #define __LSM303C_ACC_DRIVER__H
Jeej 96:8cac3f3245b5 41
Jeej 96:8cac3f3245b5 42 /* Includes ------------------------------------------------------------------*/
Jeej 96:8cac3f3245b5 43 #include <stdint.h>
Jeej 96:8cac3f3245b5 44
Jeej 96:8cac3f3245b5 45 /* Exported types ------------------------------------------------------------*/
Jeej 96:8cac3f3245b5 46
Jeej 96:8cac3f3245b5 47 #ifdef __cplusplus
Jeej 96:8cac3f3245b5 48 extern "C" {
Jeej 96:8cac3f3245b5 49 #endif
Jeej 96:8cac3f3245b5 50
Jeej 96:8cac3f3245b5 51 //these could change accordingly with the architecture
Jeej 96:8cac3f3245b5 52
Jeej 96:8cac3f3245b5 53 #ifndef __ARCHDEP__TYPES
Jeej 96:8cac3f3245b5 54 #define __ARCHDEP__TYPES
Jeej 96:8cac3f3245b5 55
Jeej 96:8cac3f3245b5 56 typedef unsigned char u8_t;
Jeej 96:8cac3f3245b5 57 typedef unsigned short int u16_t;
Jeej 96:8cac3f3245b5 58 typedef unsigned int u32_t;
Jeej 96:8cac3f3245b5 59 typedef int i32_t;
Jeej 96:8cac3f3245b5 60 typedef short int i16_t;
Jeej 96:8cac3f3245b5 61 typedef signed char i8_t;
Jeej 96:8cac3f3245b5 62
Jeej 96:8cac3f3245b5 63 #endif /*__ARCHDEP__TYPES*/
Jeej 96:8cac3f3245b5 64
Jeej 96:8cac3f3245b5 65 /* Exported common structure --------------------------------------------------------*/
Jeej 96:8cac3f3245b5 66
Jeej 96:8cac3f3245b5 67 #ifndef __SHARED__TYPES
Jeej 96:8cac3f3245b5 68 #define __SHARED__TYPES
Jeej 96:8cac3f3245b5 69
Jeej 96:8cac3f3245b5 70 typedef union{
Jeej 96:8cac3f3245b5 71 i16_t i16bit[3];
Jeej 96:8cac3f3245b5 72 u8_t u8bit[6];
Jeej 96:8cac3f3245b5 73 } Type3Axis16bit_U;
Jeej 96:8cac3f3245b5 74
Jeej 96:8cac3f3245b5 75 typedef union{
Jeej 96:8cac3f3245b5 76 i16_t i16bit;
Jeej 96:8cac3f3245b5 77 u8_t u8bit[2];
Jeej 96:8cac3f3245b5 78 } Type1Axis16bit_U;
Jeej 96:8cac3f3245b5 79
Jeej 96:8cac3f3245b5 80 typedef union{
Jeej 96:8cac3f3245b5 81 i32_t i32bit;
Jeej 96:8cac3f3245b5 82 u8_t u8bit[4];
Jeej 96:8cac3f3245b5 83 } Type1Axis32bit_U;
Jeej 96:8cac3f3245b5 84
Jeej 96:8cac3f3245b5 85 typedef enum {
Jeej 96:8cac3f3245b5 86 MEMS_SUCCESS = 0x01,
Jeej 96:8cac3f3245b5 87 MEMS_ERROR = 0x00
Jeej 96:8cac3f3245b5 88 } status_t;
Jeej 96:8cac3f3245b5 89
Jeej 96:8cac3f3245b5 90 #endif /*__SHARED__TYPES*/
Jeej 96:8cac3f3245b5 91
Jeej 96:8cac3f3245b5 92 /* Exported macro ------------------------------------------------------------*/
Jeej 96:8cac3f3245b5 93
Jeej 96:8cac3f3245b5 94 /* Exported constants --------------------------------------------------------*/
Jeej 96:8cac3f3245b5 95
Jeej 96:8cac3f3245b5 96 /************** I2C Address *****************/
Jeej 96:8cac3f3245b5 97
Jeej 97:de5a5c00299a 98 #define LSM303C_ACC_I2C_ADDRESS 0x3A
Jeej 97:de5a5c00299a 99 #define I_AM_LSM303C_ACC 0x41
Jeej 96:8cac3f3245b5 100
Jeej 96:8cac3f3245b5 101 /* Acceleration Registers */
Jeej 96:8cac3f3245b5 102 #define LSM303C_WHO_AM_I_REG_A 0x0F /* device identification register */
Jeej 96:8cac3f3245b5 103 #define LSM303C_ACT_THS_A 0x1E
Jeej 96:8cac3f3245b5 104 #define LSM303C_ACT_DUR_A 0x1F
Jeej 96:8cac3f3245b5 105 #define LSM303C_CTRL_REG1_A 0x20 /* Control register 1 acceleration */
Jeej 96:8cac3f3245b5 106 #define LSM303C_CTRL_REG2_A 0x21 /* Control register 2 acceleration */
Jeej 96:8cac3f3245b5 107 #define LSM303C_CTRL_REG3_A 0x22 /* Control register 3 acceleration */
Jeej 96:8cac3f3245b5 108 #define LSM303C_CTRL_REG4_A 0x23 /* Control register 4 acceleration */
Jeej 96:8cac3f3245b5 109 #define LSM303C_CTRL_REG5_A 0x24 /* Control register 5 acceleration */
Jeej 96:8cac3f3245b5 110 #define LSM303C_CTRL_REG6_A 0x25 /* Control register 6 acceleration */
Jeej 96:8cac3f3245b5 111 #define LSM303C_CTRL_REG7_A 0x26 /* Control register 6 acceleration */
Jeej 96:8cac3f3245b5 112 #define LSM303C_STATUS_REG_A 0x27 /* Status register acceleration */
Jeej 96:8cac3f3245b5 113 #define LSM303C_OUT_X_L_A 0x28 /* Output Register X acceleration */
Jeej 96:8cac3f3245b5 114 #define LSM303C_OUT_X_H_A 0x29 /* Output Register X acceleration */
Jeej 96:8cac3f3245b5 115 #define LSM303C_OUT_Y_L_A 0x2A /* Output Register Y acceleration */
Jeej 96:8cac3f3245b5 116 #define LSM303C_OUT_Y_H_A 0x2B /* Output Register Y acceleration */
Jeej 96:8cac3f3245b5 117 #define LSM303C_OUT_Z_L_A 0x2C /* Output Register Z acceleration */
Jeej 96:8cac3f3245b5 118 #define LSM303C_OUT_Z_H_A 0x2D /* Output Register Z acceleration */
Jeej 96:8cac3f3245b5 119 #define LSM303C_FIFO_CTRL 0x2E /* Fifo control Register acceleration */
Jeej 96:8cac3f3245b5 120 #define LSM303C_FIFO_SRC 0x2F /* Fifo src Register acceleration */
Jeej 96:8cac3f3245b5 121
Jeej 96:8cac3f3245b5 122 #define LSM303C_IG_CFG1_A 0x30 /* Interrupt 1 configuration Register acceleration */
Jeej 96:8cac3f3245b5 123 #define LSM303C_IG_SRC1_A 0x31 /* Interrupt 1 source Register acceleration */
Jeej 96:8cac3f3245b5 124 #define LSM303C_IG_THS_X1_A 0x32
Jeej 96:8cac3f3245b5 125 #define LSM303C_IG_THS_Y1_A 0x33
Jeej 96:8cac3f3245b5 126 #define LSM303C_IG_THS_Z1_A 0x34
Jeej 96:8cac3f3245b5 127
Jeej 96:8cac3f3245b5 128 #define LSM303C_IG_DUR1_A 0x32
Jeej 96:8cac3f3245b5 129 #define LSM303C_INT1_DURATION_A 0x33 /* Interrupt 1 DURATION register acceleration */
Jeej 96:8cac3f3245b5 130
Jeej 96:8cac3f3245b5 131 #define LSM303C_INT2_CFG_A 0x34 /* Interrupt 2 configuration Register acceleration */
Jeej 96:8cac3f3245b5 132 #define LSM303C_INT2_SOURCE_A 0x35 /* Interrupt 2 source Register acceleration */
Jeej 96:8cac3f3245b5 133 #define LSM303C_INT2_THS_A 0x36 /* Interrupt 2 Threshold register acceleration */
Jeej 96:8cac3f3245b5 134 #define LSM303C_INT2_DURATION_A 0x37 /* Interrupt 2 DURATION register acceleration */
Jeej 96:8cac3f3245b5 135
Jeej 96:8cac3f3245b5 136 #define LSM303C_CLICK_CFG_A 0x38 /* Click configuration Register acceleration */
Jeej 96:8cac3f3245b5 137 #define LSM303C_CLICK_SOURCE_A 0x39 /* Click 2 source Register acceleration */
Jeej 96:8cac3f3245b5 138 #define LSM303C_CLICK_THS_A 0x3A /* Click 2 Threshold register acceleration */
Jeej 96:8cac3f3245b5 139
Jeej 96:8cac3f3245b5 140 #define LSM303C_TIME_LIMIT_A 0x3B /* Time Limit Register acceleration */
Jeej 96:8cac3f3245b5 141 #define LSM303C_TIME_LATENCY_A 0x3C /* Time Latency Register acceleration */
Jeej 96:8cac3f3245b5 142 #define LSM303C_TIME_WINDOW_A 0x3D /* Time window register acceleration */
Jeej 96:8cac3f3245b5 143
Jeej 96:8cac3f3245b5 144 /* Private Function Prototype -------------------------------------------------------*/
Jeej 96:8cac3f3245b5 145
Jeej 96:8cac3f3245b5 146 void LSM303C_ACC_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension);
Jeej 96:8cac3f3245b5 147
Jeej 96:8cac3f3245b5 148 /* Public Function Prototypes ------------------------------------------------*/
Jeej 96:8cac3f3245b5 149
Jeej 96:8cac3f3245b5 150 status_t LSM303C_ACC_ReadReg( void *handle, u8_t Reg, u8_t* Data );
Jeej 96:8cac3f3245b5 151 status_t LSM303C_ACC_WriteReg( void *handle, u8_t Reg, u8_t Data );
Jeej 96:8cac3f3245b5 152
Jeej 96:8cac3f3245b5 153
Jeej 96:8cac3f3245b5 154 /*******************************************************************************
Jeej 96:8cac3f3245b5 155 * Register : WHO_AM_I
Jeej 96:8cac3f3245b5 156 * Address : 0X0F
Jeej 96:8cac3f3245b5 157 * Bit Group Name: WHO_AM_I
Jeej 96:8cac3f3245b5 158 * Permission : RO
Jeej 96:8cac3f3245b5 159 *******************************************************************************/
Jeej 96:8cac3f3245b5 160 #define LSM303C_ACC_WHO_AM_I_MASK 0xFF
Jeej 96:8cac3f3245b5 161 #define LSM303C_ACC_WHO_AM_I_POSITION 0
Jeej 96:8cac3f3245b5 162 status_t LSM303C_ACC_R_WHO_AM_I(void *handle, u8_t *value);
Jeej 96:8cac3f3245b5 163
Jeej 96:8cac3f3245b5 164 /*******************************************************************************
Jeej 96:8cac3f3245b5 165 * Register : CTRL_REG1
Jeej 96:8cac3f3245b5 166 * Address : 0X20
Jeej 96:8cac3f3245b5 167 * Bit Group Name: XEN
Jeej 96:8cac3f3245b5 168 * Permission : RW
Jeej 96:8cac3f3245b5 169 *******************************************************************************/
Jeej 96:8cac3f3245b5 170 typedef enum {
Jeej 96:8cac3f3245b5 171 LSM303C_ACC_XEN_DISABLED =0x00,
Jeej 96:8cac3f3245b5 172 LSM303C_ACC_XEN_ENABLED =0x01,
Jeej 96:8cac3f3245b5 173 } LSM303C_ACC_XEN_t;
Jeej 96:8cac3f3245b5 174
Jeej 96:8cac3f3245b5 175 #define LSM303C_ACC_XEN_MASK 0x01
Jeej 96:8cac3f3245b5 176 status_t LSM303C_ACC_W_XEN(void *handle, LSM303C_ACC_XEN_t newValue);
Jeej 96:8cac3f3245b5 177 status_t LSM303C_ACC_R_XEN(void *handle, LSM303C_ACC_XEN_t *value);
Jeej 96:8cac3f3245b5 178
Jeej 96:8cac3f3245b5 179 /*******************************************************************************
Jeej 96:8cac3f3245b5 180 * Register : CTRL_REG1
Jeej 96:8cac3f3245b5 181 * Address : 0X20
Jeej 96:8cac3f3245b5 182 * Bit Group Name: YEN
Jeej 96:8cac3f3245b5 183 * Permission : RW
Jeej 96:8cac3f3245b5 184 *******************************************************************************/
Jeej 96:8cac3f3245b5 185 typedef enum {
Jeej 96:8cac3f3245b5 186 LSM303C_ACC_YEN_DISABLED =0x00,
Jeej 96:8cac3f3245b5 187 LSM303C_ACC_YEN_ENABLED =0x02,
Jeej 96:8cac3f3245b5 188 } LSM303C_ACC_YEN_t;
Jeej 96:8cac3f3245b5 189
Jeej 96:8cac3f3245b5 190 #define LSM303C_ACC_YEN_MASK 0x02
Jeej 96:8cac3f3245b5 191 status_t LSM303C_ACC_W_YEN(void *handle, LSM303C_ACC_YEN_t newValue);
Jeej 96:8cac3f3245b5 192 status_t LSM303C_ACC_R_YEN(void *handle, LSM303C_ACC_YEN_t *value);
Jeej 96:8cac3f3245b5 193
Jeej 96:8cac3f3245b5 194 /*******************************************************************************
Jeej 96:8cac3f3245b5 195 * Register : CTRL_REG1
Jeej 96:8cac3f3245b5 196 * Address : 0X20
Jeej 96:8cac3f3245b5 197 * Bit Group Name: ZEN
Jeej 96:8cac3f3245b5 198 * Permission : RW
Jeej 96:8cac3f3245b5 199 *******************************************************************************/
Jeej 96:8cac3f3245b5 200 typedef enum {
Jeej 96:8cac3f3245b5 201 LSM303C_ACC_ZEN_DISABLED =0x00,
Jeej 96:8cac3f3245b5 202 LSM303C_ACC_ZEN_ENABLED =0x04,
Jeej 96:8cac3f3245b5 203 } LSM303C_ACC_ZEN_t;
Jeej 96:8cac3f3245b5 204
Jeej 96:8cac3f3245b5 205 #define LSM303C_ACC_ZEN_MASK 0x04
Jeej 96:8cac3f3245b5 206 status_t LSM303C_ACC_W_ZEN(void *handle, LSM303C_ACC_ZEN_t newValue);
Jeej 96:8cac3f3245b5 207 status_t LSM303C_ACC_R_ZEN(void *handle, LSM303C_ACC_ZEN_t *value);
Jeej 96:8cac3f3245b5 208
Jeej 96:8cac3f3245b5 209 /*******************************************************************************
Jeej 96:8cac3f3245b5 210 * Register : CTRL_REG1
Jeej 96:8cac3f3245b5 211 * Address : 0X20
Jeej 96:8cac3f3245b5 212 * Bit Group Name: ODR
Jeej 96:8cac3f3245b5 213 * Permission : RW
Jeej 96:8cac3f3245b5 214 *******************************************************************************/
Jeej 96:8cac3f3245b5 215 typedef enum {
Jeej 96:8cac3f3245b5 216 LSM303C_ACC_ODR_DO_PWR_DOWN =0x00,
Jeej 96:8cac3f3245b5 217 LSM303C_ACC_ODR_DO_10Hz =0x10,
Jeej 96:8cac3f3245b5 218 LSM303C_ACC_ODR_DO_50Hz =0x20,
Jeej 96:8cac3f3245b5 219 LSM303C_ACC_ODR_DO_100Hz =0x30,
Jeej 96:8cac3f3245b5 220 LSM303C_ACC_ODR_DO_200Hz =0x40,
Jeej 96:8cac3f3245b5 221 LSM303C_ACC_ODR_DO_400Hz =0x50,
Jeej 96:8cac3f3245b5 222 LSM303C_ACC_ODR_DO_800Hz =0x60,
Jeej 96:8cac3f3245b5 223 } LSM303C_ACC_ODR_t;
Jeej 96:8cac3f3245b5 224
Jeej 96:8cac3f3245b5 225 #define LSM303C_ACC_ODR_MASK 0x70
Jeej 96:8cac3f3245b5 226 status_t LSM303C_ACC_W_ODR(void *handle, LSM303C_ACC_ODR_t newValue);
Jeej 96:8cac3f3245b5 227 status_t LSM303C_ACC_R_ODR(void *handle, LSM303C_ACC_ODR_t *value);
Jeej 96:8cac3f3245b5 228
Jeej 96:8cac3f3245b5 229 /*******************************************************************************
Jeej 96:8cac3f3245b5 230 * Register : CTRL_REG2
Jeej 96:8cac3f3245b5 231 * Address : 0X21
Jeej 96:8cac3f3245b5 232 * Bit Group Name: HPIS1
Jeej 96:8cac3f3245b5 233 * Permission : RW
Jeej 96:8cac3f3245b5 234 *******************************************************************************/
Jeej 96:8cac3f3245b5 235 typedef enum {
Jeej 96:8cac3f3245b5 236 LSM303C_ACC_HPIS1_DISABLED =0x00,
Jeej 96:8cac3f3245b5 237 LSM303C_ACC_HPIS1_ENABLED =0x01,
Jeej 96:8cac3f3245b5 238 } LSM303C_ACC_HPIS1_t;
Jeej 96:8cac3f3245b5 239
Jeej 96:8cac3f3245b5 240 #define LSM303C_ACC_HPIS1_MASK 0x01
Jeej 96:8cac3f3245b5 241 status_t LSM303C_ACC_W_hpf_aoi_en_int1(void *handle, LSM303C_ACC_HPIS1_t newValue);
Jeej 96:8cac3f3245b5 242 status_t LSM303C_ACC_R_hpf_aoi_en_int1(void *handle, LSM303C_ACC_HPIS1_t *value);
Jeej 96:8cac3f3245b5 243
Jeej 96:8cac3f3245b5 244 /*******************************************************************************
Jeej 96:8cac3f3245b5 245 * Register : CTRL_REG2
Jeej 96:8cac3f3245b5 246 * Address : 0X21
Jeej 96:8cac3f3245b5 247 * Bit Group Name: HPIS2
Jeej 96:8cac3f3245b5 248 * Permission : RW
Jeej 96:8cac3f3245b5 249 *******************************************************************************/
Jeej 96:8cac3f3245b5 250 typedef enum {
Jeej 96:8cac3f3245b5 251 LSM303C_ACC_HPIS2_DISABLED =0x00,
Jeej 96:8cac3f3245b5 252 LSM303C_ACC_HPIS2_ENABLED =0x02,
Jeej 96:8cac3f3245b5 253 } LSM303C_ACC_HPIS2_t;
Jeej 96:8cac3f3245b5 254
Jeej 96:8cac3f3245b5 255 #define LSM303C_ACC_HPIS2_MASK 0x02
Jeej 96:8cac3f3245b5 256 status_t LSM303C_ACC_W_hpf_aoi_en_int2(void *handle, LSM303C_ACC_HPIS2_t newValue);
Jeej 96:8cac3f3245b5 257 status_t LSM303C_ACC_R_hpf_aoi_en_int2(void *handle, LSM303C_ACC_HPIS2_t *value);
Jeej 96:8cac3f3245b5 258
Jeej 96:8cac3f3245b5 259 /*******************************************************************************
Jeej 96:8cac3f3245b5 260 * Register : CTRL_REG2
Jeej 96:8cac3f3245b5 261 * Address : 0X21
Jeej 96:8cac3f3245b5 262 * Bit Group Name: FDS
Jeej 96:8cac3f3245b5 263 * Permission : RW
Jeej 96:8cac3f3245b5 264 *******************************************************************************/
Jeej 96:8cac3f3245b5 265 typedef enum {
Jeej 96:8cac3f3245b5 266 LSM303C_ACC_FDS_BYPASSED =0x00,
Jeej 96:8cac3f3245b5 267 LSM303C_ACC_FDS_ENABLED =0x04,
Jeej 96:8cac3f3245b5 268 } LSM303C_ACC_FDS_t;
Jeej 96:8cac3f3245b5 269
Jeej 96:8cac3f3245b5 270 #define LSM303C_ACC_FDS_MASK 0x04
Jeej 96:8cac3f3245b5 271 status_t LSM303C_ACC_W_Data_Filter(void *handle, LSM303C_ACC_FDS_t newValue);
Jeej 96:8cac3f3245b5 272 status_t LSM303C_ACC_R_Data_Filter(void *handle, LSM303C_ACC_FDS_t *value);
Jeej 96:8cac3f3245b5 273
Jeej 96:8cac3f3245b5 274 /*******************************************************************************
Jeej 96:8cac3f3245b5 275 * Register : CTRL_REG2
Jeej 96:8cac3f3245b5 276 * Address : 0X21
Jeej 96:8cac3f3245b5 277 * Bit Group Name: DFC
Jeej 96:8cac3f3245b5 278 * Permission : RW
Jeej 96:8cac3f3245b5 279 *******************************************************************************/
Jeej 96:8cac3f3245b5 280 typedef enum {
Jeej 96:8cac3f3245b5 281 LSM303C_ACC_DFC_50 =0x00,
Jeej 96:8cac3f3245b5 282 LSM303C_ACC_DFC_100 =0x20,
Jeej 96:8cac3f3245b5 283 LSM303C_ACC_DFC_9 =0x40,
Jeej 96:8cac3f3245b5 284 LSM303C_ACC_DFC_400 =0x60,
Jeej 96:8cac3f3245b5 285 } LSM303C_ACC_DFC_t;
Jeej 96:8cac3f3245b5 286
Jeej 96:8cac3f3245b5 287 #define LSM303C_ACC_DFC_MASK 0x60
Jeej 96:8cac3f3245b5 288 status_t LSM303C_ACC_W_hpf_cutoff_freq(void *handle, LSM303C_ACC_DFC_t newValue);
Jeej 96:8cac3f3245b5 289 status_t LSM303C_ACC_R_hpf_cutoff_freq(void *handle, LSM303C_ACC_DFC_t *value);
Jeej 96:8cac3f3245b5 290
Jeej 96:8cac3f3245b5 291 /*******************************************************************************
Jeej 96:8cac3f3245b5 292 * Register : CTRL_REG2
Jeej 96:8cac3f3245b5 293 * Address : 0X21
Jeej 96:8cac3f3245b5 294 * Bit Group Name: HPM
Jeej 96:8cac3f3245b5 295 * Permission : RW
Jeej 96:8cac3f3245b5 296 *******************************************************************************/
Jeej 96:8cac3f3245b5 297 typedef enum {
Jeej 96:8cac3f3245b5 298 LSM303C_ACC_HPM_NORMAL =0x00,
Jeej 96:8cac3f3245b5 299 LSM303C_ACC_HPM_REFERENCE_SIGNAL =0x08,
Jeej 96:8cac3f3245b5 300 } LSM303C_ACC_HPM_t;
Jeej 96:8cac3f3245b5 301
Jeej 96:8cac3f3245b5 302 #define LSM303C_ACC_HPM_MASK 0x18
Jeej 96:8cac3f3245b5 303 status_t LSM303C_ACC_W_hpf_mode(void *handle, LSM303C_ACC_HPM_t newValue);
Jeej 96:8cac3f3245b5 304 status_t LSM303C_ACC_R_hpf_mode(void *handle, LSM303C_ACC_HPM_t *value);
Jeej 96:8cac3f3245b5 305
Jeej 96:8cac3f3245b5 306 /*******************************************************************************
Jeej 96:8cac3f3245b5 307 * Register : CTRL_REG1
Jeej 96:8cac3f3245b5 308 * Address : 0X23
Jeej 96:8cac3f3245b5 309 * Bit Group Name: HR
Jeej 96:8cac3f3245b5 310 * Permission : RW
Jeej 96:8cac3f3245b5 311 *******************************************************************************/
Jeej 96:8cac3f3245b5 312 typedef enum {
Jeej 96:8cac3f3245b5 313 LSM303C_ACC_HR_DISABLED =0x00,
Jeej 96:8cac3f3245b5 314 LSM303C_ACC_HR_ENABLED =0x80,
Jeej 96:8cac3f3245b5 315 } LSM303C_ACC_HR_t;
Jeej 96:8cac3f3245b5 316
Jeej 96:8cac3f3245b5 317 #define LSM303C_ACC_HR_MASK 0x80
Jeej 96:8cac3f3245b5 318 status_t LSM303C_ACC_W_HiRes(void *handle, LSM303C_ACC_HR_t newValue);
Jeej 96:8cac3f3245b5 319 status_t LSM303C_ACC_R_HiRes(void *handle, LSM303C_ACC_HR_t *value);
Jeej 96:8cac3f3245b5 320
Jeej 96:8cac3f3245b5 321 /*******************************************************************************
Jeej 96:8cac3f3245b5 322 * Register : CTRL_REG4
Jeej 96:8cac3f3245b5 323 * Address : 0X23
Jeej 96:8cac3f3245b5 324 * Bit Group Name: FS
Jeej 96:8cac3f3245b5 325 * Permission : RW
Jeej 96:8cac3f3245b5 326 *******************************************************************************/
Jeej 96:8cac3f3245b5 327 typedef enum {
Jeej 96:8cac3f3245b5 328 LSM303C_ACC_FS_2G =0x00,
Jeej 96:8cac3f3245b5 329 LSM303C_ACC_FS_4G =0x20,
Jeej 96:8cac3f3245b5 330 LSM303C_ACC_FS_8G =0x30,
Jeej 96:8cac3f3245b5 331 } LSM303C_ACC_FS_t;
Jeej 96:8cac3f3245b5 332
Jeej 96:8cac3f3245b5 333 #define LSM303C_ACC_FS_MASK 0x30
Jeej 96:8cac3f3245b5 334 status_t LSM303C_ACC_W_FullScale(void *handle, LSM303C_ACC_FS_t newValue);
Jeej 96:8cac3f3245b5 335 status_t LSM303C_ACC_R_FullScale(void *handle, LSM303C_ACC_FS_t *value);
Jeej 96:8cac3f3245b5 336
Jeej 96:8cac3f3245b5 337 /*******************************************************************************
Jeej 96:8cac3f3245b5 338 * Register : CTRL_REG1
Jeej 96:8cac3f3245b5 339 * Address : 0X23
Jeej 96:8cac3f3245b5 340 * Bit Group Name: BDU
Jeej 96:8cac3f3245b5 341 * Permission : RW
Jeej 96:8cac3f3245b5 342 *******************************************************************************/
Jeej 96:8cac3f3245b5 343 typedef enum {
Jeej 96:8cac3f3245b5 344 LSM303C_ACC_BDU_DISABLED =0x00,
Jeej 96:8cac3f3245b5 345 LSM303C_ACC_BDU_ENABLED =0x08,
Jeej 96:8cac3f3245b5 346 } LSM303C_ACC_BDU_t;
Jeej 96:8cac3f3245b5 347
Jeej 96:8cac3f3245b5 348 #define LSM303C_ACC_BDU_MASK 0x08
Jeej 96:8cac3f3245b5 349 status_t LSM303C_ACC_W_BlockDataUpdate(void *handle, LSM303C_ACC_BDU_t newValue);
Jeej 96:8cac3f3245b5 350 status_t LSM303C_ACC_R_BlockDataUpdate(void *handle, LSM303C_ACC_BDU_t *value);
Jeej 96:8cac3f3245b5 351
Jeej 96:8cac3f3245b5 352 /*******************************************************************************
Jeej 96:8cac3f3245b5 353 * Register : CTRL_REG3
Jeej 96:8cac3f3245b5 354 * Address : 0X24
Jeej 96:8cac3f3245b5 355 * Bit Group Name: FIFO_EN
Jeej 96:8cac3f3245b5 356 * Permission : RW
Jeej 96:8cac3f3245b5 357 *******************************************************************************/
Jeej 96:8cac3f3245b5 358 typedef enum {
Jeej 96:8cac3f3245b5 359 LSM303C_ACC_FIFO_EN_DISABLED =0x00,
Jeej 96:8cac3f3245b5 360 LSM303C_ACC_FIFO_EN_ENABLED =0x80,
Jeej 96:8cac3f3245b5 361 } LSM303C_ACC_FIFO_EN_t;
Jeej 96:8cac3f3245b5 362
Jeej 96:8cac3f3245b5 363 #define LSM303C_ACC_FIFO_EN_MASK 0x80
Jeej 96:8cac3f3245b5 364 status_t LSM303C_ACC_W_FIFO_EN(void *handle, LSM303C_ACC_FIFO_EN_t newValue);
Jeej 96:8cac3f3245b5 365 status_t LSM303C_ACC_R_FIFO_EN(void *handle, LSM303C_ACC_FIFO_EN_t *value);
Jeej 96:8cac3f3245b5 366
Jeej 96:8cac3f3245b5 367
Jeej 96:8cac3f3245b5 368 /*******************************************************************************
Jeej 96:8cac3f3245b5 369 * Register : CTRL_REG5
Jeej 96:8cac3f3245b5 370 * Address : 0X25
Jeej 96:8cac3f3245b5 371 * Bit Group Name: H_LACTIVE
Jeej 96:8cac3f3245b5 372 * Permission : RW
Jeej 96:8cac3f3245b5 373 *******************************************************************************/
Jeej 96:8cac3f3245b5 374 typedef enum {
Jeej 96:8cac3f3245b5 375 LSM303C_ACC_H_LACTIVE_ACTIVE_HI =0x00,
Jeej 96:8cac3f3245b5 376 LSM303C_ACC_H_LACTIVE_ACTIVE_LO =0x02,
Jeej 96:8cac3f3245b5 377 } LSM303C_ACC_H_LACTIVE_t;
Jeej 96:8cac3f3245b5 378
Jeej 96:8cac3f3245b5 379 #define LSM303C_ACC_H_LACTIVE_MASK 0x02
Jeej 96:8cac3f3245b5 380 status_t LSM303C_ACC_W_IntActive(void *handle, LSM303C_ACC_H_LACTIVE_t newValue);
Jeej 96:8cac3f3245b5 381 status_t LSM303C_ACC_R_IntActive(void *handle, LSM303C_ACC_H_LACTIVE_t *value);
Jeej 96:8cac3f3245b5 382
Jeej 96:8cac3f3245b5 383 /*******************************************************************************
Jeej 96:8cac3f3245b5 384 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 385 * Address : 0X27
Jeej 96:8cac3f3245b5 386 * Bit Group Name: XDA
Jeej 96:8cac3f3245b5 387 * Permission : RO
Jeej 96:8cac3f3245b5 388 *******************************************************************************/
Jeej 96:8cac3f3245b5 389 typedef enum {
Jeej 96:8cac3f3245b5 390 LSM303C_ACC_XDA_NOT_AVAILABLE =0x00,
Jeej 96:8cac3f3245b5 391 LSM303C_ACC_XDA_AVAILABLE =0x01,
Jeej 96:8cac3f3245b5 392 } LSM303C_ACC_XDA_t;
Jeej 96:8cac3f3245b5 393
Jeej 96:8cac3f3245b5 394 #define LSM303C_ACC_XDA_MASK 0x01
Jeej 96:8cac3f3245b5 395 status_t LSM303C_ACC_R_XDataAvail(void *handle, LSM303C_ACC_XDA_t *value);
Jeej 96:8cac3f3245b5 396
Jeej 96:8cac3f3245b5 397 /*******************************************************************************
Jeej 96:8cac3f3245b5 398 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 399 * Address : 0X27
Jeej 96:8cac3f3245b5 400 * Bit Group Name: YDA
Jeej 96:8cac3f3245b5 401 * Permission : RO
Jeej 96:8cac3f3245b5 402 *******************************************************************************/
Jeej 96:8cac3f3245b5 403 typedef enum {
Jeej 96:8cac3f3245b5 404 LSM303C_ACC_YDA_NOT_AVAILABLE =0x00,
Jeej 96:8cac3f3245b5 405 LSM303C_ACC_YDA_AVAILABLE =0x02,
Jeej 96:8cac3f3245b5 406 } LSM303C_ACC_YDA_t;
Jeej 96:8cac3f3245b5 407
Jeej 96:8cac3f3245b5 408 #define LSM303C_ACC_YDA_MASK 0x02
Jeej 96:8cac3f3245b5 409 status_t LSM303C_ACC_R_YDataAvail(void *handle, LSM303C_ACC_YDA_t *value);
Jeej 96:8cac3f3245b5 410
Jeej 96:8cac3f3245b5 411 /*******************************************************************************
Jeej 96:8cac3f3245b5 412 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 413 * Address : 0X27
Jeej 96:8cac3f3245b5 414 * Bit Group Name: ZDA
Jeej 96:8cac3f3245b5 415 * Permission : RO
Jeej 96:8cac3f3245b5 416 *******************************************************************************/
Jeej 96:8cac3f3245b5 417 typedef enum {
Jeej 96:8cac3f3245b5 418 LSM303C_ACC_ZDA_NOT_AVAILABLE =0x00,
Jeej 96:8cac3f3245b5 419 LSM303C_ACC_ZDA_AVAILABLE =0x04,
Jeej 96:8cac3f3245b5 420 } LSM303C_ACC_ZDA_t;
Jeej 96:8cac3f3245b5 421
Jeej 96:8cac3f3245b5 422 #define LSM303C_ACC_ZDA_MASK 0x04
Jeej 96:8cac3f3245b5 423 status_t LSM303C_ACC_R_ZDataAvail(void *handle, LSM303C_ACC_ZDA_t *value);
Jeej 96:8cac3f3245b5 424
Jeej 96:8cac3f3245b5 425 /*******************************************************************************
Jeej 96:8cac3f3245b5 426 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 427 * Address : 0X27
Jeej 96:8cac3f3245b5 428 * Bit Group Name: ZYXDA
Jeej 96:8cac3f3245b5 429 * Permission : RO
Jeej 96:8cac3f3245b5 430 *******************************************************************************/
Jeej 96:8cac3f3245b5 431 typedef enum {
Jeej 96:8cac3f3245b5 432 LSM303C_ACC_ZYXDA_NOT_AVAILABLE =0x00,
Jeej 96:8cac3f3245b5 433 LSM303C_ACC_ZYXDA_AVAILABLE =0x08,
Jeej 96:8cac3f3245b5 434 } LSM303C_ACC_ZYXDA_t;
Jeej 96:8cac3f3245b5 435
Jeej 96:8cac3f3245b5 436 #define LSM303C_ACC_ZYXDA_MASK 0x08
Jeej 96:8cac3f3245b5 437 status_t LSM303C_ACC_R_XYZDataAvail(void *handle, LSM303C_ACC_ZYXDA_t *value);
Jeej 96:8cac3f3245b5 438
Jeej 96:8cac3f3245b5 439 /*******************************************************************************
Jeej 96:8cac3f3245b5 440 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 441 * Address : 0X27
Jeej 96:8cac3f3245b5 442 * Bit Group Name: XOR
Jeej 96:8cac3f3245b5 443 * Permission : RO
Jeej 96:8cac3f3245b5 444 *******************************************************************************/
Jeej 96:8cac3f3245b5 445 typedef enum {
Jeej 96:8cac3f3245b5 446 LSM303C_ACC_XOR_NO_OVERRUN =0x00,
Jeej 96:8cac3f3245b5 447 LSM303C_ACC_XOR_OVERRUN =0x10,
Jeej 96:8cac3f3245b5 448 } LSM303C_ACC_XOR_t;
Jeej 96:8cac3f3245b5 449
Jeej 96:8cac3f3245b5 450 #define LSM303C_ACC_XOR_MASK 0x10
Jeej 96:8cac3f3245b5 451 status_t LSM303C_ACC_R_XDataOverrun(void *handle, LSM303C_ACC_XOR_t *value);
Jeej 96:8cac3f3245b5 452
Jeej 96:8cac3f3245b5 453 /*******************************************************************************
Jeej 96:8cac3f3245b5 454 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 455 * Address : 0X27
Jeej 96:8cac3f3245b5 456 * Bit Group Name: YOR
Jeej 96:8cac3f3245b5 457 * Permission : RO
Jeej 96:8cac3f3245b5 458 *******************************************************************************/
Jeej 96:8cac3f3245b5 459 typedef enum {
Jeej 96:8cac3f3245b5 460 LSM303C_ACC_YOR_NO_OVERRUN =0x00,
Jeej 96:8cac3f3245b5 461 LSM303C_ACC_YOR_OVERRUN =0x20,
Jeej 96:8cac3f3245b5 462 } LSM303C_ACC_YOR_t;
Jeej 96:8cac3f3245b5 463
Jeej 96:8cac3f3245b5 464 #define LSM303C_ACC_YOR_MASK 0x20
Jeej 96:8cac3f3245b5 465 status_t LSM303C_ACC_R_YDataOverrun(void *handle, LSM303C_ACC_YOR_t *value);
Jeej 96:8cac3f3245b5 466
Jeej 96:8cac3f3245b5 467 /*******************************************************************************
Jeej 96:8cac3f3245b5 468 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 469 * Address : 0X27
Jeej 96:8cac3f3245b5 470 * Bit Group Name: ZOR
Jeej 96:8cac3f3245b5 471 * Permission : RO
Jeej 96:8cac3f3245b5 472 *******************************************************************************/
Jeej 96:8cac3f3245b5 473 typedef enum {
Jeej 96:8cac3f3245b5 474 LSM303C_ACC_ZOR_NO_OVERRUN =0x00,
Jeej 96:8cac3f3245b5 475 LSM303C_ACC_ZOR_OVERRUN =0x40,
Jeej 96:8cac3f3245b5 476 } LSM303C_ACC_ZOR_t;
Jeej 96:8cac3f3245b5 477
Jeej 96:8cac3f3245b5 478 #define LSM303C_ACC_ZOR_MASK 0x40
Jeej 96:8cac3f3245b5 479 status_t LSM303C_ACC_R_ZDataOverrun(void *handle, LSM303C_ACC_ZOR_t *value);
Jeej 96:8cac3f3245b5 480
Jeej 96:8cac3f3245b5 481 /*******************************************************************************
Jeej 96:8cac3f3245b5 482 * Register : STATUS_REG2
Jeej 96:8cac3f3245b5 483 * Address : 0X27
Jeej 96:8cac3f3245b5 484 * Bit Group Name: ZYXOR
Jeej 96:8cac3f3245b5 485 * Permission : RO
Jeej 96:8cac3f3245b5 486 *******************************************************************************/
Jeej 96:8cac3f3245b5 487 typedef enum {
Jeej 96:8cac3f3245b5 488 LSM303C_ACC_ZYXOR_NO_OVERRUN =0x00,
Jeej 96:8cac3f3245b5 489 LSM303C_ACC_ZYXOR_OVERRUN =0x80,
Jeej 96:8cac3f3245b5 490 } LSM303C_ACC_ZYXOR_t;
Jeej 96:8cac3f3245b5 491
Jeej 96:8cac3f3245b5 492 #define LSM303C_ACC_ZYXOR_MASK 0x80
Jeej 96:8cac3f3245b5 493 status_t LSM303C_ACC_R_XYZDataOverrun(void *handle, LSM303C_ACC_ZYXOR_t *value);
Jeej 96:8cac3f3245b5 494
Jeej 96:8cac3f3245b5 495 /*******************************************************************************
Jeej 96:8cac3f3245b5 496 * Register : <REGISTER_L> - <REGISTER_H>
Jeej 96:8cac3f3245b5 497 * Output Type : Acceleration
Jeej 96:8cac3f3245b5 498 * Permission : RO
Jeej 96:8cac3f3245b5 499 *******************************************************************************/
Jeej 96:8cac3f3245b5 500 status_t LSM303C_ACC_Get_Raw_Acceleration(void *handle, u8_t *buff);
Jeej 96:8cac3f3245b5 501 status_t LSM303C_ACC_Get_Acceleration(void *handle, int *buff);
Jeej 96:8cac3f3245b5 502
Jeej 96:8cac3f3245b5 503 #ifdef __cplusplus
Jeej 96:8cac3f3245b5 504 }
Jeej 96:8cac3f3245b5 505 #endif
Jeej 96:8cac3f3245b5 506
Jeej 96:8cac3f3245b5 507 #endif