For mbed OS-5 version for WIZnet Ethernet Interface, this is Library using Hardware TCP/IP chip, W5500 and TCP/IP Offload Engine, W7500.
Warning
- If you want to use existing codes, you need to change the class used as EthernetInterface to WIZnetInterface.
This is WIZnet Ethernet Interface using Hardware TCP/IP chip, W5500 and TCP/IP Offload Engine, W7500.
- WIZwiki_W7500 : /platforms/WIZwiki-W7500/
- WIZwiki_W7500P : /platforms/WIZwiki-W7500P/
- WIZwiki_W7500ECO : /platforms/WIZwiki-W7500ECO/
- W5500 Ethernet Shield : /components/W5500-Ethernet-Kit-for-IoT/
This library is an Ethernet Interface library port-based on [EthernetInterface](https://developer.mbed.org/users/mbed_official/code/EthernetInterface/docs/tip/).
For more detail, visit http://embeddist.blogspot.kr/2015/06/wiznetinterface-for-armmbed.html
arch/int/W7500x_toe.cpp@0:d4c8fe4d9b29, 2017-09-04 (annotated)
- Committer:
- justinkim
- Date:
- Mon Sep 04 00:23:04 2017 +0000
- Revision:
- 0:d4c8fe4d9b29
mbed OS 5 version migration...
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
justinkim | 0:d4c8fe4d9b29 | 1 | /* Copyright (C) 2012 mbed.org, MIT License |
justinkim | 0:d4c8fe4d9b29 | 2 | * |
justinkim | 0:d4c8fe4d9b29 | 3 | * and associated documentation files (the "Software"), to deal in the Software without restriction, |
justinkim | 0:d4c8fe4d9b29 | 4 | * including without limitation the rights to use, copy, modify, merge, publish, distribute, |
justinkim | 0:d4c8fe4d9b29 | 5 | * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is |
justinkim | 0:d4c8fe4d9b29 | 6 | * furnished to do so, subject to the following conditions: |
justinkim | 0:d4c8fe4d9b29 | 7 | * |
justinkim | 0:d4c8fe4d9b29 | 8 | * The above copyright notice and this permission notice shall be included in all copies or |
justinkim | 0:d4c8fe4d9b29 | 9 | * substantial portions of the Software. |
justinkim | 0:d4c8fe4d9b29 | 10 | * |
justinkim | 0:d4c8fe4d9b29 | 11 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
justinkim | 0:d4c8fe4d9b29 | 12 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
justinkim | 0:d4c8fe4d9b29 | 13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
justinkim | 0:d4c8fe4d9b29 | 14 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
justinkim | 0:d4c8fe4d9b29 | 15 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
justinkim | 0:d4c8fe4d9b29 | 16 | */ |
justinkim | 0:d4c8fe4d9b29 | 17 | #include "eth_arch.h" |
justinkim | 0:d4c8fe4d9b29 | 18 | #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500P) || defined(TARGET_WIZwiki_W7500ECO) |
justinkim | 0:d4c8fe4d9b29 | 19 | |
justinkim | 0:d4c8fe4d9b29 | 20 | |
justinkim | 0:d4c8fe4d9b29 | 21 | #include "mbed.h" |
justinkim | 0:d4c8fe4d9b29 | 22 | #include "mbed_debug.h" |
justinkim | 0:d4c8fe4d9b29 | 23 | #include "DNSClient.h" |
justinkim | 0:d4c8fe4d9b29 | 24 | |
justinkim | 0:d4c8fe4d9b29 | 25 | |
justinkim | 0:d4c8fe4d9b29 | 26 | /* |
justinkim | 0:d4c8fe4d9b29 | 27 | * MDIO via GPIO |
justinkim | 0:d4c8fe4d9b29 | 28 | * mdio via gpio is supported and related functions as follows. |
justinkim | 0:d4c8fe4d9b29 | 29 | * - mdio_init(),mdio_read(),mdio_write() |
justinkim | 0:d4c8fe4d9b29 | 30 | * - input_MDIO(),output_MDIO(),turnaroud_MDIO(),idle_MDIO() |
justinkim | 0:d4c8fe4d9b29 | 31 | * called by ethernet_link() and ethernet_set_link() |
justinkim | 0:d4c8fe4d9b29 | 32 | */ |
justinkim | 0:d4c8fe4d9b29 | 33 | |
justinkim | 0:d4c8fe4d9b29 | 34 | #if defined (TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO) |
justinkim | 0:d4c8fe4d9b29 | 35 | |
justinkim | 0:d4c8fe4d9b29 | 36 | #define MDIO GPIO_Pin_14 |
justinkim | 0:d4c8fe4d9b29 | 37 | #define MDC GPIO_Pin_15 |
justinkim | 0:d4c8fe4d9b29 | 38 | #define GPIO_MDC GPIOB |
justinkim | 0:d4c8fe4d9b29 | 39 | #define PHY_ADDR_IP101G 0x07 |
justinkim | 0:d4c8fe4d9b29 | 40 | #define PHY_ADDR PHY_ADDR_IP101G |
justinkim | 0:d4c8fe4d9b29 | 41 | #define SVAL 0x2 //right shift val = 2 |
justinkim | 0:d4c8fe4d9b29 | 42 | #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register) |
justinkim | 0:d4c8fe4d9b29 | 43 | #define PHYREG_STATUS 0x1 //Status Register address (Status basic register) |
justinkim | 0:d4c8fe4d9b29 | 44 | #define CNTL_DUPLEX (0x01ul<< 7) |
justinkim | 0:d4c8fe4d9b29 | 45 | #define CNTL_AUTONEGO (0x01ul<<11) |
justinkim | 0:d4c8fe4d9b29 | 46 | #define CNTL_SPEED (0x01ul<<12) |
justinkim | 0:d4c8fe4d9b29 | 47 | #define MDC_WAIT (1) |
justinkim | 0:d4c8fe4d9b29 | 48 | |
justinkim | 0:d4c8fe4d9b29 | 49 | #elif defined (TARGET_WIZwiki_W7500P) |
justinkim | 0:d4c8fe4d9b29 | 50 | |
justinkim | 0:d4c8fe4d9b29 | 51 | #define MDIO GPIO_Pin_15 |
justinkim | 0:d4c8fe4d9b29 | 52 | #define MDC GPIO_Pin_14 |
justinkim | 0:d4c8fe4d9b29 | 53 | #define GPIO_MDC GPIOB |
justinkim | 0:d4c8fe4d9b29 | 54 | #define PHY_ADDR_IP101G 0x01 |
justinkim | 0:d4c8fe4d9b29 | 55 | #define PHY_ADDR PHY_ADDR_IP101G |
justinkim | 0:d4c8fe4d9b29 | 56 | #define SVAL 0x2 //right shift val = 2 |
justinkim | 0:d4c8fe4d9b29 | 57 | #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register) |
justinkim | 0:d4c8fe4d9b29 | 58 | #define PHYREG_STATUS 0x1 //Status Register address (Status basic register) |
justinkim | 0:d4c8fe4d9b29 | 59 | #define CNTL_DUPLEX (0x01ul<< 8) |
justinkim | 0:d4c8fe4d9b29 | 60 | #define CNTL_AUTONEGO (0x01ul<<12) |
justinkim | 0:d4c8fe4d9b29 | 61 | #define CNTL_SPEED (0x01ul<<13) |
justinkim | 0:d4c8fe4d9b29 | 62 | #define MDC_WAIT (1) |
justinkim | 0:d4c8fe4d9b29 | 63 | |
justinkim | 0:d4c8fe4d9b29 | 64 | #endif |
justinkim | 0:d4c8fe4d9b29 | 65 | |
justinkim | 0:d4c8fe4d9b29 | 66 | void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO); |
justinkim | 0:d4c8fe4d9b29 | 67 | void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val); |
justinkim | 0:d4c8fe4d9b29 | 68 | uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr); |
justinkim | 0:d4c8fe4d9b29 | 69 | |
justinkim | 0:d4c8fe4d9b29 | 70 | WIZnet_Chip* WIZnet_Chip::inst; |
justinkim | 0:d4c8fe4d9b29 | 71 | |
justinkim | 0:d4c8fe4d9b29 | 72 | WIZnet_Chip::WIZnet_Chip() |
justinkim | 0:d4c8fe4d9b29 | 73 | { |
justinkim | 0:d4c8fe4d9b29 | 74 | inst = this; |
justinkim | 0:d4c8fe4d9b29 | 75 | } |
justinkim | 0:d4c8fe4d9b29 | 76 | |
justinkim | 0:d4c8fe4d9b29 | 77 | bool WIZnet_Chip::setmac() |
justinkim | 0:d4c8fe4d9b29 | 78 | { |
justinkim | 0:d4c8fe4d9b29 | 79 | reg_wr_mac(SHAR, mac); |
justinkim | 0:d4c8fe4d9b29 | 80 | return true; |
justinkim | 0:d4c8fe4d9b29 | 81 | } |
justinkim | 0:d4c8fe4d9b29 | 82 | |
justinkim | 0:d4c8fe4d9b29 | 83 | // Set the IP |
justinkim | 0:d4c8fe4d9b29 | 84 | bool WIZnet_Chip::setip() |
justinkim | 0:d4c8fe4d9b29 | 85 | { |
justinkim | 0:d4c8fe4d9b29 | 86 | reg_wr<uint32_t>(SIPR, ip); |
justinkim | 0:d4c8fe4d9b29 | 87 | reg_wr<uint32_t>(GAR, gateway); |
justinkim | 0:d4c8fe4d9b29 | 88 | reg_wr<uint32_t>(SUBR, netmask); |
justinkim | 0:d4c8fe4d9b29 | 89 | return true; |
justinkim | 0:d4c8fe4d9b29 | 90 | } |
justinkim | 0:d4c8fe4d9b29 | 91 | |
justinkim | 0:d4c8fe4d9b29 | 92 | bool WIZnet_Chip::setProtocol(int socket, Protocol p) |
justinkim | 0:d4c8fe4d9b29 | 93 | { |
justinkim | 0:d4c8fe4d9b29 | 94 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 95 | return false; |
justinkim | 0:d4c8fe4d9b29 | 96 | } |
justinkim | 0:d4c8fe4d9b29 | 97 | sreg<uint8_t>(socket, Sn_MR, p); |
justinkim | 0:d4c8fe4d9b29 | 98 | return true; |
justinkim | 0:d4c8fe4d9b29 | 99 | } |
justinkim | 0:d4c8fe4d9b29 | 100 | |
justinkim | 0:d4c8fe4d9b29 | 101 | bool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms) |
justinkim | 0:d4c8fe4d9b29 | 102 | { |
justinkim | 0:d4c8fe4d9b29 | 103 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 104 | return false; |
justinkim | 0:d4c8fe4d9b29 | 105 | } |
justinkim | 0:d4c8fe4d9b29 | 106 | sreg<uint8_t>(socket, Sn_MR, TCP); |
justinkim | 0:d4c8fe4d9b29 | 107 | scmd(socket, OPEN); |
justinkim | 0:d4c8fe4d9b29 | 108 | sreg_ip(socket, Sn_DIPR, host); |
justinkim | 0:d4c8fe4d9b29 | 109 | sreg<uint16_t>(socket, Sn_DPORT, port); |
justinkim | 0:d4c8fe4d9b29 | 110 | sreg<uint16_t>(socket, Sn_PORT, new_port()); |
justinkim | 0:d4c8fe4d9b29 | 111 | scmd(socket, CONNECT); |
justinkim | 0:d4c8fe4d9b29 | 112 | Timer t; |
justinkim | 0:d4c8fe4d9b29 | 113 | t.reset(); |
justinkim | 0:d4c8fe4d9b29 | 114 | t.start(); |
justinkim | 0:d4c8fe4d9b29 | 115 | while(!is_connected(socket)) { |
justinkim | 0:d4c8fe4d9b29 | 116 | if (t.read_ms() > timeout_ms) { |
justinkim | 0:d4c8fe4d9b29 | 117 | return false; |
justinkim | 0:d4c8fe4d9b29 | 118 | } |
justinkim | 0:d4c8fe4d9b29 | 119 | } |
justinkim | 0:d4c8fe4d9b29 | 120 | return true; |
justinkim | 0:d4c8fe4d9b29 | 121 | } |
justinkim | 0:d4c8fe4d9b29 | 122 | |
justinkim | 0:d4c8fe4d9b29 | 123 | bool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip) |
justinkim | 0:d4c8fe4d9b29 | 124 | { |
justinkim | 0:d4c8fe4d9b29 | 125 | uint32_t addr = str_to_ip(host); |
justinkim | 0:d4c8fe4d9b29 | 126 | char buf[17]; |
justinkim | 0:d4c8fe4d9b29 | 127 | snprintf(buf, sizeof(buf), "%d.%d.%d.%d", |
justinkim | 0:d4c8fe4d9b29 | 128 | (uint8_t)((addr>>24)&0xff), |
justinkim | 0:d4c8fe4d9b29 | 129 | (uint8_t)((addr>>16)&0xff), |
justinkim | 0:d4c8fe4d9b29 | 130 | (uint8_t)((addr>>8)&0xff), |
justinkim | 0:d4c8fe4d9b29 | 131 | (uint8_t)(addr&0xff)); |
justinkim | 0:d4c8fe4d9b29 | 132 | if (strcmp(buf, host) == 0) { |
justinkim | 0:d4c8fe4d9b29 | 133 | *ip = addr; |
justinkim | 0:d4c8fe4d9b29 | 134 | return true; |
justinkim | 0:d4c8fe4d9b29 | 135 | } |
justinkim | 0:d4c8fe4d9b29 | 136 | DNSClient client; |
justinkim | 0:d4c8fe4d9b29 | 137 | if(client.lookup(host)) { |
justinkim | 0:d4c8fe4d9b29 | 138 | *ip = client.ip; |
justinkim | 0:d4c8fe4d9b29 | 139 | return true; |
justinkim | 0:d4c8fe4d9b29 | 140 | } |
justinkim | 0:d4c8fe4d9b29 | 141 | return false; |
justinkim | 0:d4c8fe4d9b29 | 142 | } |
justinkim | 0:d4c8fe4d9b29 | 143 | |
justinkim | 0:d4c8fe4d9b29 | 144 | |
justinkim | 0:d4c8fe4d9b29 | 145 | bool WIZnet_Chip::is_connected(int socket) |
justinkim | 0:d4c8fe4d9b29 | 146 | { |
justinkim | 0:d4c8fe4d9b29 | 147 | /* |
justinkim | 0:d4c8fe4d9b29 | 148 | if (sreg<uint8_t>(socket, Sn_SR) == SOCK_ESTABLISHED) { |
justinkim | 0:d4c8fe4d9b29 | 149 | return true; |
justinkim | 0:d4c8fe4d9b29 | 150 | } |
justinkim | 0:d4c8fe4d9b29 | 151 | */ |
justinkim | 0:d4c8fe4d9b29 | 152 | uint8_t tmpSn_SR; |
justinkim | 0:d4c8fe4d9b29 | 153 | tmpSn_SR = sreg<uint8_t>(socket, Sn_SR); |
justinkim | 0:d4c8fe4d9b29 | 154 | // packet sending is possible, when state is SOCK_CLOSE_WAIT. |
justinkim | 0:d4c8fe4d9b29 | 155 | if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) { |
justinkim | 0:d4c8fe4d9b29 | 156 | return true; |
justinkim | 0:d4c8fe4d9b29 | 157 | } |
justinkim | 0:d4c8fe4d9b29 | 158 | return false; |
justinkim | 0:d4c8fe4d9b29 | 159 | } |
justinkim | 0:d4c8fe4d9b29 | 160 | // Reset the chip & set the buffer |
justinkim | 0:d4c8fe4d9b29 | 161 | void WIZnet_Chip::reset() |
justinkim | 0:d4c8fe4d9b29 | 162 | { |
justinkim | 0:d4c8fe4d9b29 | 163 | /* S/W Reset PHY */ |
justinkim | 0:d4c8fe4d9b29 | 164 | mdio_write(GPIO_MDC, PHYREG_CONTROL, 0x8000); |
justinkim | 0:d4c8fe4d9b29 | 165 | wait_ms(10);//for S/W reset |
justinkim | 0:d4c8fe4d9b29 | 166 | wait_ms(10);//for MDC I/F RDY |
justinkim | 0:d4c8fe4d9b29 | 167 | |
justinkim | 0:d4c8fe4d9b29 | 168 | mdio_init(GPIO_MDC, MDC, MDIO); |
justinkim | 0:d4c8fe4d9b29 | 169 | |
justinkim | 0:d4c8fe4d9b29 | 170 | /* S/W Reset WZTOE */ |
justinkim | 0:d4c8fe4d9b29 | 171 | reg_wr<uint8_t>(MR, MR_RST); |
justinkim | 0:d4c8fe4d9b29 | 172 | // set PAD strengh and pull-up for TXD[3:0] and TXE |
justinkim | 0:d4c8fe4d9b29 | 173 | #ifdef __DEF_USED_IC101AG__ //For using IC+101AG |
justinkim | 0:d4c8fe4d9b29 | 174 | |
justinkim | 0:d4c8fe4d9b29 | 175 | #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO) |
justinkim | 0:d4c8fe4d9b29 | 176 | |
justinkim | 0:d4c8fe4d9b29 | 177 | *(volatile uint32_t *)(0x41003068) = 0x64; //TXD0 |
justinkim | 0:d4c8fe4d9b29 | 178 | *(volatile uint32_t *)(0x4100306C) = 0x64; //TXD1 |
justinkim | 0:d4c8fe4d9b29 | 179 | *(volatile uint32_t *)(0x41003070) = 0x64; //TXD2 |
justinkim | 0:d4c8fe4d9b29 | 180 | *(volatile uint32_t *)(0x41003074) = 0x64; //TXD3 |
justinkim | 0:d4c8fe4d9b29 | 181 | *(volatile uint32_t *)(0x41003050) = 0x64; //TXE |
justinkim | 0:d4c8fe4d9b29 | 182 | #endif |
justinkim | 0:d4c8fe4d9b29 | 183 | |
justinkim | 0:d4c8fe4d9b29 | 184 | #endif |
justinkim | 0:d4c8fe4d9b29 | 185 | |
justinkim | 0:d4c8fe4d9b29 | 186 | // set ticker counter |
justinkim | 0:d4c8fe4d9b29 | 187 | reg_wr<uint32_t>(TIC100US, (SystemCoreClock/10000)); |
justinkim | 0:d4c8fe4d9b29 | 188 | // write MAC address inside the WZTOE MAC address register |
justinkim | 0:d4c8fe4d9b29 | 189 | reg_wr_mac(SHAR, mac); |
justinkim | 0:d4c8fe4d9b29 | 190 | /* |
justinkim | 0:d4c8fe4d9b29 | 191 | * set RX and TX buffer size |
justinkim | 0:d4c8fe4d9b29 | 192 | * for (int socket = 0; socket < MAX_SOCK_NUM; socket++) { |
justinkim | 0:d4c8fe4d9b29 | 193 | * sreg<uint8_t>(socket, Sn_RXBUF_SIZE, 2); |
justinkim | 0:d4c8fe4d9b29 | 194 | * sreg<uint8_t>(socket, Sn_TXBUF_SIZE, 2); |
justinkim | 0:d4c8fe4d9b29 | 195 | * } |
justinkim | 0:d4c8fe4d9b29 | 196 | */ |
justinkim | 0:d4c8fe4d9b29 | 197 | } |
justinkim | 0:d4c8fe4d9b29 | 198 | |
justinkim | 0:d4c8fe4d9b29 | 199 | |
justinkim | 0:d4c8fe4d9b29 | 200 | bool WIZnet_Chip::close(int socket) |
justinkim | 0:d4c8fe4d9b29 | 201 | { |
justinkim | 0:d4c8fe4d9b29 | 202 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 203 | return false; |
justinkim | 0:d4c8fe4d9b29 | 204 | } |
justinkim | 0:d4c8fe4d9b29 | 205 | // if SOCK_CLOSED, return |
justinkim | 0:d4c8fe4d9b29 | 206 | if (sreg<uint8_t>(socket, Sn_SR) == SOCK_CLOSED) { |
justinkim | 0:d4c8fe4d9b29 | 207 | return true; |
justinkim | 0:d4c8fe4d9b29 | 208 | } |
justinkim | 0:d4c8fe4d9b29 | 209 | // if SOCK_ESTABLISHED, send FIN-Packet to peer |
justinkim | 0:d4c8fe4d9b29 | 210 | if (sreg<uint8_t>(socket, Sn_MR) == TCP) { |
justinkim | 0:d4c8fe4d9b29 | 211 | scmd(socket, DISCON); |
justinkim | 0:d4c8fe4d9b29 | 212 | } |
justinkim | 0:d4c8fe4d9b29 | 213 | // close socket |
justinkim | 0:d4c8fe4d9b29 | 214 | scmd(socket, CLOSE); |
justinkim | 0:d4c8fe4d9b29 | 215 | // clear Socket Interrupt Register |
justinkim | 0:d4c8fe4d9b29 | 216 | sreg<uint8_t>(socket, Sn_ICR, 0xff); |
justinkim | 0:d4c8fe4d9b29 | 217 | return true; |
justinkim | 0:d4c8fe4d9b29 | 218 | } |
justinkim | 0:d4c8fe4d9b29 | 219 | |
justinkim | 0:d4c8fe4d9b29 | 220 | int WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size) |
justinkim | 0:d4c8fe4d9b29 | 221 | { |
justinkim | 0:d4c8fe4d9b29 | 222 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 223 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 224 | } |
justinkim | 0:d4c8fe4d9b29 | 225 | Timer t; |
justinkim | 0:d4c8fe4d9b29 | 226 | t.reset(); |
justinkim | 0:d4c8fe4d9b29 | 227 | t.start(); |
justinkim | 0:d4c8fe4d9b29 | 228 | while(1) { |
justinkim | 0:d4c8fe4d9b29 | 229 | int size = sreg<uint16_t>(socket, Sn_RX_RSR); |
justinkim | 0:d4c8fe4d9b29 | 230 | if (size > req_size) { |
justinkim | 0:d4c8fe4d9b29 | 231 | return size; |
justinkim | 0:d4c8fe4d9b29 | 232 | } |
justinkim | 0:d4c8fe4d9b29 | 233 | if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) { |
justinkim | 0:d4c8fe4d9b29 | 234 | break; |
justinkim | 0:d4c8fe4d9b29 | 235 | } |
justinkim | 0:d4c8fe4d9b29 | 236 | } |
justinkim | 0:d4c8fe4d9b29 | 237 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 238 | } |
justinkim | 0:d4c8fe4d9b29 | 239 | |
justinkim | 0:d4c8fe4d9b29 | 240 | int WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size) |
justinkim | 0:d4c8fe4d9b29 | 241 | { |
justinkim | 0:d4c8fe4d9b29 | 242 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 243 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 244 | } |
justinkim | 0:d4c8fe4d9b29 | 245 | Timer t; |
justinkim | 0:d4c8fe4d9b29 | 246 | t.reset(); |
justinkim | 0:d4c8fe4d9b29 | 247 | t.start(); |
justinkim | 0:d4c8fe4d9b29 | 248 | while(1) { |
justinkim | 0:d4c8fe4d9b29 | 249 | int size = sreg<uint16_t>(socket, Sn_TX_FSR); |
justinkim | 0:d4c8fe4d9b29 | 250 | if (size > req_size) { |
justinkim | 0:d4c8fe4d9b29 | 251 | return size; |
justinkim | 0:d4c8fe4d9b29 | 252 | } |
justinkim | 0:d4c8fe4d9b29 | 253 | if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) { |
justinkim | 0:d4c8fe4d9b29 | 254 | break; |
justinkim | 0:d4c8fe4d9b29 | 255 | } |
justinkim | 0:d4c8fe4d9b29 | 256 | } |
justinkim | 0:d4c8fe4d9b29 | 257 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 258 | } |
justinkim | 0:d4c8fe4d9b29 | 259 | |
justinkim | 0:d4c8fe4d9b29 | 260 | int WIZnet_Chip::send(int socket, const char * str, int len) |
justinkim | 0:d4c8fe4d9b29 | 261 | { |
justinkim | 0:d4c8fe4d9b29 | 262 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 263 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 264 | } |
justinkim | 0:d4c8fe4d9b29 | 265 | |
justinkim | 0:d4c8fe4d9b29 | 266 | uint16_t ptr = sreg<uint16_t>(socket, Sn_TX_WR); |
justinkim | 0:d4c8fe4d9b29 | 267 | uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18); |
justinkim | 0:d4c8fe4d9b29 | 268 | |
justinkim | 0:d4c8fe4d9b29 | 269 | for(int i=0; i<len; i++) |
justinkim | 0:d4c8fe4d9b29 | 270 | *(volatile uint8_t *)(sn_tx_base + ((ptr+i)&0xFFFF)) = str[i]; |
justinkim | 0:d4c8fe4d9b29 | 271 | |
justinkim | 0:d4c8fe4d9b29 | 272 | sreg<uint16_t>(socket, Sn_TX_WR, ptr + len); |
justinkim | 0:d4c8fe4d9b29 | 273 | scmd(socket, SEND); |
justinkim | 0:d4c8fe4d9b29 | 274 | |
justinkim | 0:d4c8fe4d9b29 | 275 | uint8_t tmp_Sn_IR; |
justinkim | 0:d4c8fe4d9b29 | 276 | while (( (tmp_Sn_IR = sreg<uint8_t>(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) { |
justinkim | 0:d4c8fe4d9b29 | 277 | // @Jul.10, 2014 fix contant name, and udp sendto function. |
justinkim | 0:d4c8fe4d9b29 | 278 | switch (sreg<uint8_t>(socket, Sn_SR)) { |
justinkim | 0:d4c8fe4d9b29 | 279 | case SOCK_CLOSED : |
justinkim | 0:d4c8fe4d9b29 | 280 | close(socket); |
justinkim | 0:d4c8fe4d9b29 | 281 | return 0; |
justinkim | 0:d4c8fe4d9b29 | 282 | //break; |
justinkim | 0:d4c8fe4d9b29 | 283 | case SOCK_UDP : |
justinkim | 0:d4c8fe4d9b29 | 284 | // ARP timeout is possible. |
justinkim | 0:d4c8fe4d9b29 | 285 | if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) { |
justinkim | 0:d4c8fe4d9b29 | 286 | sreg<uint8_t>(socket, Sn_ICR, INT_TIMEOUT); |
justinkim | 0:d4c8fe4d9b29 | 287 | return 0; |
justinkim | 0:d4c8fe4d9b29 | 288 | } |
justinkim | 0:d4c8fe4d9b29 | 289 | break; |
justinkim | 0:d4c8fe4d9b29 | 290 | default : |
justinkim | 0:d4c8fe4d9b29 | 291 | break; |
justinkim | 0:d4c8fe4d9b29 | 292 | } |
justinkim | 0:d4c8fe4d9b29 | 293 | } |
justinkim | 0:d4c8fe4d9b29 | 294 | |
justinkim | 0:d4c8fe4d9b29 | 295 | sreg<uint8_t>(socket, Sn_ICR, INT_SEND_OK); |
justinkim | 0:d4c8fe4d9b29 | 296 | |
justinkim | 0:d4c8fe4d9b29 | 297 | return len; |
justinkim | 0:d4c8fe4d9b29 | 298 | } |
justinkim | 0:d4c8fe4d9b29 | 299 | |
justinkim | 0:d4c8fe4d9b29 | 300 | int WIZnet_Chip::recv(int socket, char* buf, int len) |
justinkim | 0:d4c8fe4d9b29 | 301 | { |
justinkim | 0:d4c8fe4d9b29 | 302 | if (socket < 0) { |
justinkim | 0:d4c8fe4d9b29 | 303 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 304 | } |
justinkim | 0:d4c8fe4d9b29 | 305 | uint16_t ptr = sreg<uint16_t>(socket, Sn_RX_RD); |
justinkim | 0:d4c8fe4d9b29 | 306 | uint32_t sn_rx_base = W7500x_RXMEM_BASE + (uint32_t)(socket<<18); |
justinkim | 0:d4c8fe4d9b29 | 307 | |
justinkim | 0:d4c8fe4d9b29 | 308 | for(int i=0; i<len; i++) |
justinkim | 0:d4c8fe4d9b29 | 309 | buf[i] = *(volatile uint8_t *)(sn_rx_base + ((ptr+i)&0xFFFF)); |
justinkim | 0:d4c8fe4d9b29 | 310 | |
justinkim | 0:d4c8fe4d9b29 | 311 | sreg<uint16_t>(socket, Sn_RX_RD, ptr + len); |
justinkim | 0:d4c8fe4d9b29 | 312 | scmd(socket, RECV); |
justinkim | 0:d4c8fe4d9b29 | 313 | |
justinkim | 0:d4c8fe4d9b29 | 314 | return len; |
justinkim | 0:d4c8fe4d9b29 | 315 | } |
justinkim | 0:d4c8fe4d9b29 | 316 | |
justinkim | 0:d4c8fe4d9b29 | 317 | int WIZnet_Chip::new_socket() |
justinkim | 0:d4c8fe4d9b29 | 318 | { |
justinkim | 0:d4c8fe4d9b29 | 319 | for(int s = 0; s < MAX_SOCK_NUM; s++) { |
justinkim | 0:d4c8fe4d9b29 | 320 | if (sreg<uint8_t>(s, Sn_SR) == SOCK_CLOSED) { |
justinkim | 0:d4c8fe4d9b29 | 321 | return s; |
justinkim | 0:d4c8fe4d9b29 | 322 | } |
justinkim | 0:d4c8fe4d9b29 | 323 | } |
justinkim | 0:d4c8fe4d9b29 | 324 | return -1; |
justinkim | 0:d4c8fe4d9b29 | 325 | } |
justinkim | 0:d4c8fe4d9b29 | 326 | |
justinkim | 0:d4c8fe4d9b29 | 327 | uint16_t WIZnet_Chip::new_port() |
justinkim | 0:d4c8fe4d9b29 | 328 | { |
justinkim | 0:d4c8fe4d9b29 | 329 | uint16_t port = rand(); |
justinkim | 0:d4c8fe4d9b29 | 330 | port |= 49152; |
justinkim | 0:d4c8fe4d9b29 | 331 | return port; |
justinkim | 0:d4c8fe4d9b29 | 332 | } |
justinkim | 0:d4c8fe4d9b29 | 333 | |
justinkim | 0:d4c8fe4d9b29 | 334 | bool WIZnet_Chip::link(int wait_time_ms) |
justinkim | 0:d4c8fe4d9b29 | 335 | { |
justinkim | 0:d4c8fe4d9b29 | 336 | Timer t; |
justinkim | 0:d4c8fe4d9b29 | 337 | t.reset(); |
justinkim | 0:d4c8fe4d9b29 | 338 | t.start(); |
justinkim | 0:d4c8fe4d9b29 | 339 | while(1) { |
justinkim | 0:d4c8fe4d9b29 | 340 | int is_link = ethernet_link(); |
justinkim | 0:d4c8fe4d9b29 | 341 | |
justinkim | 0:d4c8fe4d9b29 | 342 | if (is_link) { |
justinkim | 0:d4c8fe4d9b29 | 343 | return true; |
justinkim | 0:d4c8fe4d9b29 | 344 | } |
justinkim | 0:d4c8fe4d9b29 | 345 | if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) { |
justinkim | 0:d4c8fe4d9b29 | 346 | break; |
justinkim | 0:d4c8fe4d9b29 | 347 | } |
justinkim | 0:d4c8fe4d9b29 | 348 | } |
justinkim | 0:d4c8fe4d9b29 | 349 | return 0; |
justinkim | 0:d4c8fe4d9b29 | 350 | } |
justinkim | 0:d4c8fe4d9b29 | 351 | |
justinkim | 0:d4c8fe4d9b29 | 352 | void WIZnet_Chip::set_link(PHYMode phymode) |
justinkim | 0:d4c8fe4d9b29 | 353 | { |
justinkim | 0:d4c8fe4d9b29 | 354 | int speed = -1; |
justinkim | 0:d4c8fe4d9b29 | 355 | int duplex = 0; |
justinkim | 0:d4c8fe4d9b29 | 356 | |
justinkim | 0:d4c8fe4d9b29 | 357 | switch(phymode) { |
justinkim | 0:d4c8fe4d9b29 | 358 | case AutoNegotiate : speed = -1; duplex = 0; break; |
justinkim | 0:d4c8fe4d9b29 | 359 | case HalfDuplex10 : speed = 0; duplex = 0; break; |
justinkim | 0:d4c8fe4d9b29 | 360 | case FullDuplex10 : speed = 0; duplex = 1; break; |
justinkim | 0:d4c8fe4d9b29 | 361 | case HalfDuplex100 : speed = 1; duplex = 0; break; |
justinkim | 0:d4c8fe4d9b29 | 362 | case FullDuplex100 : speed = 1; duplex = 1; break; |
justinkim | 0:d4c8fe4d9b29 | 363 | } |
justinkim | 0:d4c8fe4d9b29 | 364 | |
justinkim | 0:d4c8fe4d9b29 | 365 | ethernet_set_link(speed, duplex); |
justinkim | 0:d4c8fe4d9b29 | 366 | } |
justinkim | 0:d4c8fe4d9b29 | 367 | |
justinkim | 0:d4c8fe4d9b29 | 368 | uint32_t str_to_ip(const char* str) |
justinkim | 0:d4c8fe4d9b29 | 369 | { |
justinkim | 0:d4c8fe4d9b29 | 370 | uint32_t ip = 0; |
justinkim | 0:d4c8fe4d9b29 | 371 | char* p = (char*)str; |
justinkim | 0:d4c8fe4d9b29 | 372 | for(int i = 0; i < 4; i++) { |
justinkim | 0:d4c8fe4d9b29 | 373 | ip |= atoi(p); |
justinkim | 0:d4c8fe4d9b29 | 374 | p = strchr(p, '.'); |
justinkim | 0:d4c8fe4d9b29 | 375 | if (p == NULL) { |
justinkim | 0:d4c8fe4d9b29 | 376 | break; |
justinkim | 0:d4c8fe4d9b29 | 377 | } |
justinkim | 0:d4c8fe4d9b29 | 378 | ip <<= 8; |
justinkim | 0:d4c8fe4d9b29 | 379 | p++; |
justinkim | 0:d4c8fe4d9b29 | 380 | } |
justinkim | 0:d4c8fe4d9b29 | 381 | return ip; |
justinkim | 0:d4c8fe4d9b29 | 382 | } |
justinkim | 0:d4c8fe4d9b29 | 383 | |
justinkim | 0:d4c8fe4d9b29 | 384 | void printfBytes(char* str, uint8_t* buf, int len) |
justinkim | 0:d4c8fe4d9b29 | 385 | { |
justinkim | 0:d4c8fe4d9b29 | 386 | printf("%s %d:", str, len); |
justinkim | 0:d4c8fe4d9b29 | 387 | for(int i = 0; i < len; i++) { |
justinkim | 0:d4c8fe4d9b29 | 388 | printf(" %02x", buf[i]); |
justinkim | 0:d4c8fe4d9b29 | 389 | } |
justinkim | 0:d4c8fe4d9b29 | 390 | printf("\n"); |
justinkim | 0:d4c8fe4d9b29 | 391 | } |
justinkim | 0:d4c8fe4d9b29 | 392 | |
justinkim | 0:d4c8fe4d9b29 | 393 | void printHex(uint8_t* buf, int len) |
justinkim | 0:d4c8fe4d9b29 | 394 | { |
justinkim | 0:d4c8fe4d9b29 | 395 | for(int i = 0; i < len; i++) { |
justinkim | 0:d4c8fe4d9b29 | 396 | if ((i%16) == 0) { |
justinkim | 0:d4c8fe4d9b29 | 397 | printf("%p", buf+i); |
justinkim | 0:d4c8fe4d9b29 | 398 | } |
justinkim | 0:d4c8fe4d9b29 | 399 | printf(" %02x", buf[i]); |
justinkim | 0:d4c8fe4d9b29 | 400 | if ((i%16) == 15) { |
justinkim | 0:d4c8fe4d9b29 | 401 | printf("\n"); |
justinkim | 0:d4c8fe4d9b29 | 402 | } |
justinkim | 0:d4c8fe4d9b29 | 403 | } |
justinkim | 0:d4c8fe4d9b29 | 404 | printf("\n"); |
justinkim | 0:d4c8fe4d9b29 | 405 | } |
justinkim | 0:d4c8fe4d9b29 | 406 | |
justinkim | 0:d4c8fe4d9b29 | 407 | void debug_hex(uint8_t* buf, int len) |
justinkim | 0:d4c8fe4d9b29 | 408 | { |
justinkim | 0:d4c8fe4d9b29 | 409 | for(int i = 0; i < len; i++) { |
justinkim | 0:d4c8fe4d9b29 | 410 | if ((i%16) == 0) { |
justinkim | 0:d4c8fe4d9b29 | 411 | debug("%p", buf+i); |
justinkim | 0:d4c8fe4d9b29 | 412 | } |
justinkim | 0:d4c8fe4d9b29 | 413 | debug(" %02x", buf[i]); |
justinkim | 0:d4c8fe4d9b29 | 414 | if ((i%16) == 15) { |
justinkim | 0:d4c8fe4d9b29 | 415 | debug("\n"); |
justinkim | 0:d4c8fe4d9b29 | 416 | } |
justinkim | 0:d4c8fe4d9b29 | 417 | } |
justinkim | 0:d4c8fe4d9b29 | 418 | debug("\n"); |
justinkim | 0:d4c8fe4d9b29 | 419 | } |
justinkim | 0:d4c8fe4d9b29 | 420 | |
justinkim | 0:d4c8fe4d9b29 | 421 | void WIZnet_Chip::scmd(int socket, Command cmd) |
justinkim | 0:d4c8fe4d9b29 | 422 | { |
justinkim | 0:d4c8fe4d9b29 | 423 | sreg<uint8_t>(socket, Sn_CR, cmd); |
justinkim | 0:d4c8fe4d9b29 | 424 | while(sreg<uint8_t>(socket, Sn_CR)); |
justinkim | 0:d4c8fe4d9b29 | 425 | } |
justinkim | 0:d4c8fe4d9b29 | 426 | |
justinkim | 0:d4c8fe4d9b29 | 427 | |
justinkim | 0:d4c8fe4d9b29 | 428 | void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO) |
justinkim | 0:d4c8fe4d9b29 | 429 | { |
justinkim | 0:d4c8fe4d9b29 | 430 | /* Set GPIOs for MDIO and MDC */ |
justinkim | 0:d4c8fe4d9b29 | 431 | GPIO_InitTypeDef MDIO_InitDef; |
justinkim | 0:d4c8fe4d9b29 | 432 | HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1); |
justinkim | 0:d4c8fe4d9b29 | 433 | HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1); |
justinkim | 0:d4c8fe4d9b29 | 434 | MDIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO; |
justinkim | 0:d4c8fe4d9b29 | 435 | MDIO_InitDef.GPIO_Mode = GPIO_Mode_OUT; |
justinkim | 0:d4c8fe4d9b29 | 436 | HAL_GPIO_Init(GPIOx, &MDIO_InitDef); |
justinkim | 0:d4c8fe4d9b29 | 437 | } |
justinkim | 0:d4c8fe4d9b29 | 438 | |
justinkim | 0:d4c8fe4d9b29 | 439 | void output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n) |
justinkim | 0:d4c8fe4d9b29 | 440 | { |
justinkim | 0:d4c8fe4d9b29 | 441 | for(val <<= (32-n); n; val<<=1, n--) |
justinkim | 0:d4c8fe4d9b29 | 442 | { |
justinkim | 0:d4c8fe4d9b29 | 443 | if(val & 0x80000000) |
justinkim | 0:d4c8fe4d9b29 | 444 | HAL_GPIO_SetBits(GPIOx, MDIO); |
justinkim | 0:d4c8fe4d9b29 | 445 | else |
justinkim | 0:d4c8fe4d9b29 | 446 | HAL_GPIO_ResetBits(GPIOx, MDIO); |
justinkim | 0:d4c8fe4d9b29 | 447 | |
justinkim | 0:d4c8fe4d9b29 | 448 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 449 | HAL_GPIO_SetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 450 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 451 | HAL_GPIO_ResetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 452 | } |
justinkim | 0:d4c8fe4d9b29 | 453 | } |
justinkim | 0:d4c8fe4d9b29 | 454 | |
justinkim | 0:d4c8fe4d9b29 | 455 | uint32_t input_MDIO( GPIO_TypeDef* GPIOx ) |
justinkim | 0:d4c8fe4d9b29 | 456 | { |
justinkim | 0:d4c8fe4d9b29 | 457 | uint32_t i, val=0; |
justinkim | 0:d4c8fe4d9b29 | 458 | for(i=0; i<16; i++) |
justinkim | 0:d4c8fe4d9b29 | 459 | { |
justinkim | 0:d4c8fe4d9b29 | 460 | val <<=1; |
justinkim | 0:d4c8fe4d9b29 | 461 | HAL_GPIO_SetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 462 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 463 | HAL_GPIO_ResetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 464 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 465 | val |= HAL_GPIO_ReadInputDataBit(GPIOx, MDIO); |
justinkim | 0:d4c8fe4d9b29 | 466 | } |
justinkim | 0:d4c8fe4d9b29 | 467 | return (val); |
justinkim | 0:d4c8fe4d9b29 | 468 | } |
justinkim | 0:d4c8fe4d9b29 | 469 | |
justinkim | 0:d4c8fe4d9b29 | 470 | void turnaround_MDIO( GPIO_TypeDef* GPIOx) |
justinkim | 0:d4c8fe4d9b29 | 471 | { |
justinkim | 0:d4c8fe4d9b29 | 472 | GPIOx->OUTENCLR = MDIO ; |
justinkim | 0:d4c8fe4d9b29 | 473 | HAL_GPIO_SetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 474 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 475 | HAL_GPIO_ResetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 476 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 477 | } |
justinkim | 0:d4c8fe4d9b29 | 478 | |
justinkim | 0:d4c8fe4d9b29 | 479 | void idle_MDIO( GPIO_TypeDef* GPIOx ) |
justinkim | 0:d4c8fe4d9b29 | 480 | { |
justinkim | 0:d4c8fe4d9b29 | 481 | GPIOx->OUTENSET = MDIO ; |
justinkim | 0:d4c8fe4d9b29 | 482 | HAL_GPIO_SetBits(GPIOx,MDC); |
justinkim | 0:d4c8fe4d9b29 | 483 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 484 | HAL_GPIO_ResetBits(GPIOx, MDC); |
justinkim | 0:d4c8fe4d9b29 | 485 | wait_ms(MDC_WAIT); |
justinkim | 0:d4c8fe4d9b29 | 486 | } |
justinkim | 0:d4c8fe4d9b29 | 487 | |
justinkim | 0:d4c8fe4d9b29 | 488 | uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr) |
justinkim | 0:d4c8fe4d9b29 | 489 | { |
justinkim | 0:d4c8fe4d9b29 | 490 | output_MDIO(GPIOx, 0xFFFFFFFF, 32); |
justinkim | 0:d4c8fe4d9b29 | 491 | output_MDIO(GPIOx, 0x06, 4); |
justinkim | 0:d4c8fe4d9b29 | 492 | output_MDIO(GPIOx, PHY_ADDR, 5); |
justinkim | 0:d4c8fe4d9b29 | 493 | output_MDIO(GPIOx, PhyRegAddr, 5); |
justinkim | 0:d4c8fe4d9b29 | 494 | turnaround_MDIO(GPIOx); |
justinkim | 0:d4c8fe4d9b29 | 495 | uint32_t val = input_MDIO(GPIOx ); |
justinkim | 0:d4c8fe4d9b29 | 496 | idle_MDIO(GPIOx); |
justinkim | 0:d4c8fe4d9b29 | 497 | return val; |
justinkim | 0:d4c8fe4d9b29 | 498 | } |
justinkim | 0:d4c8fe4d9b29 | 499 | |
justinkim | 0:d4c8fe4d9b29 | 500 | void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val) |
justinkim | 0:d4c8fe4d9b29 | 501 | { |
justinkim | 0:d4c8fe4d9b29 | 502 | output_MDIO(GPIOx, 0xFFFFFFFF, 32); |
justinkim | 0:d4c8fe4d9b29 | 503 | output_MDIO(GPIOx, 0x05, 4); |
justinkim | 0:d4c8fe4d9b29 | 504 | output_MDIO(GPIOx, PHY_ADDR, 5); |
justinkim | 0:d4c8fe4d9b29 | 505 | output_MDIO(GPIOx, PhyRegAddr, 5); |
justinkim | 0:d4c8fe4d9b29 | 506 | output_MDIO(GPIOx, 0x02, 2); |
justinkim | 0:d4c8fe4d9b29 | 507 | output_MDIO(GPIOx, val, 16); |
justinkim | 0:d4c8fe4d9b29 | 508 | idle_MDIO(GPIOx); |
justinkim | 0:d4c8fe4d9b29 | 509 | } |
justinkim | 0:d4c8fe4d9b29 | 510 | |
justinkim | 0:d4c8fe4d9b29 | 511 | int WIZnet_Chip::ethernet_link(void) { |
justinkim | 0:d4c8fe4d9b29 | 512 | return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01); |
justinkim | 0:d4c8fe4d9b29 | 513 | } |
justinkim | 0:d4c8fe4d9b29 | 514 | |
justinkim | 0:d4c8fe4d9b29 | 515 | void WIZnet_Chip::ethernet_set_link(int speed, int duplex) { |
justinkim | 0:d4c8fe4d9b29 | 516 | uint32_t val=0; |
justinkim | 0:d4c8fe4d9b29 | 517 | if((speed < 0) || (speed > 1)) { |
justinkim | 0:d4c8fe4d9b29 | 518 | val = CNTL_AUTONEGO; |
justinkim | 0:d4c8fe4d9b29 | 519 | } else { |
justinkim | 0:d4c8fe4d9b29 | 520 | val = ((CNTL_SPEED&(speed<<11))|(CNTL_DUPLEX&(duplex<<7))); |
justinkim | 0:d4c8fe4d9b29 | 521 | } |
justinkim | 0:d4c8fe4d9b29 | 522 | mdio_write(GPIO_MDC, PHYREG_CONTROL, val); |
justinkim | 0:d4c8fe4d9b29 | 523 | } |
justinkim | 0:d4c8fe4d9b29 | 524 | |
justinkim | 0:d4c8fe4d9b29 | 525 | void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) |
justinkim | 0:d4c8fe4d9b29 | 526 | { |
justinkim | 0:d4c8fe4d9b29 | 527 | data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3)); |
justinkim | 0:d4c8fe4d9b29 | 528 | data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2)); |
justinkim | 0:d4c8fe4d9b29 | 529 | data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1)); |
justinkim | 0:d4c8fe4d9b29 | 530 | data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0)); |
justinkim | 0:d4c8fe4d9b29 | 531 | data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7)); |
justinkim | 0:d4c8fe4d9b29 | 532 | data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6)); |
justinkim | 0:d4c8fe4d9b29 | 533 | } |
justinkim | 0:d4c8fe4d9b29 | 534 | |
justinkim | 0:d4c8fe4d9b29 | 535 | void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip) |
justinkim | 0:d4c8fe4d9b29 | 536 | { |
justinkim | 0:d4c8fe4d9b29 | 537 | uint8_t buf[4]={0,}; |
justinkim | 0:d4c8fe4d9b29 | 538 | uint32_t wr_ip = 0; |
justinkim | 0:d4c8fe4d9b29 | 539 | char* p = (char*)ip; |
justinkim | 0:d4c8fe4d9b29 | 540 | |
justinkim | 0:d4c8fe4d9b29 | 541 | for(int i = 0; i < 4; i++) { |
justinkim | 0:d4c8fe4d9b29 | 542 | wr_ip = (wr_ip<<8); |
justinkim | 0:d4c8fe4d9b29 | 543 | buf[i] = atoi(p); |
justinkim | 0:d4c8fe4d9b29 | 544 | wr_ip |= buf[i]; |
justinkim | 0:d4c8fe4d9b29 | 545 | p = strchr(p, '.'); |
justinkim | 0:d4c8fe4d9b29 | 546 | if (p == NULL) break; |
justinkim | 0:d4c8fe4d9b29 | 547 | p++; |
justinkim | 0:d4c8fe4d9b29 | 548 | } |
justinkim | 0:d4c8fe4d9b29 | 549 | *(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip; |
justinkim | 0:d4c8fe4d9b29 | 550 | } |
justinkim | 0:d4c8fe4d9b29 | 551 | |
justinkim | 0:d4c8fe4d9b29 | 552 | void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) { |
justinkim | 0:d4c8fe4d9b29 | 553 | reg_wr_ip(addr, (uint8_t)(0x01+(socket<<2)), ip); |
justinkim | 0:d4c8fe4d9b29 | 554 | } |
justinkim | 0:d4c8fe4d9b29 | 555 | |
justinkim | 0:d4c8fe4d9b29 | 556 | #endif |
justinkim | 0:d4c8fe4d9b29 | 557 | |
justinkim | 0:d4c8fe4d9b29 | 558 |