Vekatech / VK_RZ_A1H_LCD_demo

Lcd companion boards support (VKLCD50RTA & VKLCD70RT)

What is this ?

This is a demo program using Renesas RGA library & USB Camera to demonstrate VK-RZ/A1H's companion boards workability.

Supported companion Boards:

VKLCD50RTA

/media/uploads/tvendov/front_view_hmi_50.png /media/uploads/tvendov/side_view_hmi_50.png

VKLCD70RT

/media/uploads/tvendov/front_view_hmi_70.png/media/uploads/tvendov/side_view_hmi_70.png /media/uploads/tvendov/front_view_lvds.png/media/uploads/tvendov/back_view_lvds.png

How to Configure ?

You can choose which display is installed by altering the lcd_panel.h file

Leave the active one & comment out the others:

#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD50RTA
//#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD70RT

You can alter the whole demo with your pictures if you like:

How to compile ?

  • The Demo can be compiled in 3 modes:
    • I. Execution from the internal 10-MB on-chip SRAM.
      • After import in the online compiler just leave only the VKRZA1H_RAM.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
      • Save the result binary in the SD Card (<SD>:\vkrza1\lcd_sample ), altering vkrza1h.ini by this way
    • II. Execution from the on-board serial FALSH in dual (32-MB) mode.
      • After import in the online compiler just leave only the VKRZA1H_DOUBLE.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
      • Drag & drop the result binary in MBED disk, (previously inited in double flash mode)
    • III. Execution from the on-board serial FALSH in single (16-MB) mode.
      • After import in the online compiler just leave only the VKRZA1H_SINGLE.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
      • Drag & drop the result binary in MBED disk, (previously inited in single flash mode )

Quick presentation:

Other demos ?

More demos you can find on our FTP

RGA/video/vdc5.h@0:6435b67ad23c, 2017-02-16 (annotated)

Committer:
tvendov
Date:
Thu Feb 16 10:23:48 2017 +0000
Revision:
0:6435b67ad23c
Initial lcd support (VKLCD50RTA & VKLCD70RT companion boards)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tvendov 0:6435b67ad23c 1 /*******************************************************************************
tvendov 0:6435b67ad23c 2 * DISCLAIMER
tvendov 0:6435b67ad23c 3 * This software is supplied by Renesas Electronics Corporation and is only
tvendov 0:6435b67ad23c 4 * intended for use with Renesas products. No other uses are authorized. This
tvendov 0:6435b67ad23c 5 * software is owned by Renesas Electronics Corporation and is protected under
tvendov 0:6435b67ad23c 6 * all applicable laws, including copyright laws.
tvendov 0:6435b67ad23c 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
tvendov 0:6435b67ad23c 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
tvendov 0:6435b67ad23c 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
tvendov 0:6435b67ad23c 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
tvendov 0:6435b67ad23c 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
tvendov 0:6435b67ad23c 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
tvendov 0:6435b67ad23c 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
tvendov 0:6435b67ad23c 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
tvendov 0:6435b67ad23c 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
tvendov 0:6435b67ad23c 16 * Renesas reserves the right, without notice, to make changes to this software
tvendov 0:6435b67ad23c 17 * and to discontinue the availability of this software. By using this software,
tvendov 0:6435b67ad23c 18 * you agree to the additional terms and conditions found by accessing the
tvendov 0:6435b67ad23c 19 * following link:
tvendov 0:6435b67ad23c 20 * http://www.renesas.com/disclaimer
tvendov 0:6435b67ad23c 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
tvendov 0:6435b67ad23c 22 *******************************************************************************/
tvendov 0:6435b67ad23c 23 /**************************************************************************//**
tvendov 0:6435b67ad23c 24 * @file vdc5.h
tvendov 0:6435b67ad23c 25 * @version 1.00
tvendov 0:6435b67ad23c 26 * $Rev: 199 $
tvendov 0:6435b67ad23c 27 * $Date:: 2014-05-23 16:33:52 +0900#$
tvendov 0:6435b67ad23c 28 * @brief Graphics driver wrapper function definitions in C
tvendov 0:6435b67ad23c 29 ******************************************************************************/
tvendov 0:6435b67ad23c 30
tvendov 0:6435b67ad23c 31 #ifndef VDC5_H
tvendov 0:6435b67ad23c 32 #define VDC5_H
tvendov 0:6435b67ad23c 33
tvendov 0:6435b67ad23c 34 /******************************************************************************
tvendov 0:6435b67ad23c 35 Includes <System Includes> , "Project Includes"
tvendov 0:6435b67ad23c 36 ******************************************************************************/
tvendov 0:6435b67ad23c 37 #include <stdlib.h>
tvendov 0:6435b67ad23c 38
tvendov 0:6435b67ad23c 39 #include "r_typedefs.h"
tvendov 0:6435b67ad23c 40 #include "r_vdc5.h"
tvendov 0:6435b67ad23c 41 #include "pinmap.h"
tvendov 0:6435b67ad23c 42
tvendov 0:6435b67ad23c 43 #ifdef __cplusplus
tvendov 0:6435b67ad23c 44 extern "C"
tvendov 0:6435b67ad23c 45 {
tvendov 0:6435b67ad23c 46 #endif /* __cplusplus */
tvendov 0:6435b67ad23c 47
tvendov 0:6435b67ad23c 48 /******************************************************************************
tvendov 0:6435b67ad23c 49 Macro definitions
tvendov 0:6435b67ad23c 50 ******************************************************************************/
tvendov 0:6435b67ad23c 51
tvendov 0:6435b67ad23c 52 #define VSYNC_1_2_FH_TIMING (858u) /* Vsync signal 1/2fH phase timing */
tvendov 0:6435b67ad23c 53 #define VSYNC_1_4_FH_TIMING (429u) /* Vsync signal 1/4fH phase timing */
tvendov 0:6435b67ad23c 54 #define DEFAULT_INPUT_CLOCK (66.67) /* P1 clock VDC5 */
tvendov 0:6435b67ad23c 55 #define DEFAULT_OUTPUT_CLOCK (66.67) /* LVDS output clock */
tvendov 0:6435b67ad23c 56
tvendov 0:6435b67ad23c 57 #define IMGCAP_SIZE_NTSC_HS (122u)
tvendov 0:6435b67ad23c 58 #define IMGCAP_SIZE_NTSC_HW (720u)
tvendov 0:6435b67ad23c 59 #define IMGCAP_SIZE_NTSC_VS (16u)
tvendov 0:6435b67ad23c 60 #define IMGCAP_SIZE_NTSC_VW (240u)
tvendov 0:6435b67ad23c 61
tvendov 0:6435b67ad23c 62 #define IMGCAP_SIZE_PAL_HS (132u)
tvendov 0:6435b67ad23c 63 #define IMGCAP_SIZE_PAL_HW (720u)
tvendov 0:6435b67ad23c 64 #define IMGCAP_SIZE_PAL_VS (19u)
tvendov 0:6435b67ad23c 65 #define IMGCAP_SIZE_PAL_VW (280u)
tvendov 0:6435b67ad23c 66
tvendov 0:6435b67ad23c 67 typedef void (*vdc5_irq_handler)(uint32_t int_sense);
tvendov 0:6435b67ad23c 68
tvendov 0:6435b67ad23c 69 /* video channel select */
tvendov 0:6435b67ad23c 70 typedef enum {
tvendov 0:6435b67ad23c 71 DRV_VIDEO_INPUT_CHANNEL_0 = 0, /* video input channel 0 */
tvendov 0:6435b67ad23c 72 DRV_VIDEO_INPUT_CHANNEL_1 /* video input channel 1 */
tvendov 0:6435b67ad23c 73 } drv_video_input_channel_t;
tvendov 0:6435b67ad23c 74
tvendov 0:6435b67ad23c 75 /* input pin control */
tvendov 0:6435b67ad23c 76 typedef enum {
tvendov 0:6435b67ad23c 77 DRV_VIDEO_ADC_VINSEL_VIN1 = 0, /* VIN1 input */
tvendov 0:6435b67ad23c 78 DRV_VIDEO_ADC_VINSEL_VIN2 /* VIN2 input */
tvendov 0:6435b67ad23c 79 } drv_video_adc_vinsel_t;
tvendov 0:6435b67ad23c 80
tvendov 0:6435b67ad23c 81 /* graphics layer select */
tvendov 0:6435b67ad23c 82 typedef enum {
tvendov 0:6435b67ad23c 83 DRV_GRAPHICS_LAYER_0 = 0, /* graphics layer 0 */
tvendov 0:6435b67ad23c 84 DRV_GRAPHICS_LAYER_1, /* graphics layer 1 */
tvendov 0:6435b67ad23c 85 DRV_GRAPHICS_LAYER_2, /* graphics layer 2 */
tvendov 0:6435b67ad23c 86 DRV_GRAPHICS_LAYER_3 /* graphics layer 3 */
tvendov 0:6435b67ad23c 87 } drv_graphics_layer_t;
tvendov 0:6435b67ad23c 88
tvendov 0:6435b67ad23c 89 /* error codes */
tvendov 0:6435b67ad23c 90 typedef enum {
tvendov 0:6435b67ad23c 91 DRV_GRAPHICS_OK = 0, /* Normal termination */
tvendov 0:6435b67ad23c 92 DRV_GRAPHICS_VDC5_ERR = -1, /* VDC5 error */
tvendov 0:6435b67ad23c 93 DRV_GRAPHICS_FORMAT_ERR = -2, /* Not support format */
tvendov 0:6435b67ad23c 94 DRV_GRAPHICS_LAYER_ERR = -3, /* Invalid layer ID error */
tvendov 0:6435b67ad23c 95 DRV_GRAPHICS_CHANNEL_ERR = -4, /* Invalid channel error */
tvendov 0:6435b67ad23c 96 DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write */
tvendov 0:6435b67ad23c 97 DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /* Video Write */
tvendov 0:6435b67ad23c 98 DRV_GRAPHICS_PARAM_RANGE_ERR = -7 /* Parameter range error */
tvendov 0:6435b67ad23c 99 } drv_graphics_error_t;
tvendov 0:6435b67ad23c 100
tvendov 0:6435b67ad23c 101 /* graphics layer format select */
tvendov 0:6435b67ad23c 102 typedef enum {
tvendov 0:6435b67ad23c 103 DRV_GRAPHICS_FORMAT_YCBCR422 = 0, /* YCbCr422 */
tvendov 0:6435b67ad23c 104 DRV_GRAPHICS_FORMAT_RGB565, /* RGB565 */
tvendov 0:6435b67ad23c 105 DRV_GRAPHICS_FORMAT_RGB888, /* RGB888 */
tvendov 0:6435b67ad23c 106 DRV_GRAPHICS_FORMAT_ARGB8888, /* ARGB8888 */
tvendov 0:6435b67ad23c 107 DRV_GRAPHICS_FORMAT_ARGB4444 /* ARGB4444 */
tvendov 0:6435b67ad23c 108 } drv_graphics_format_t;
tvendov 0:6435b67ad23c 109
tvendov 0:6435b67ad23c 110 /* video writing format select */
tvendov 0:6435b67ad23c 111 typedef enum {
tvendov 0:6435b67ad23c 112 DRV_VIDEO_FORMAT_YCBCR422 = 0, /* YCbCr422 */
tvendov 0:6435b67ad23c 113 DRV_VIDEO_FORMAT_RGB565, /* RGB565 */
tvendov 0:6435b67ad23c 114 DRV_VIDEO_FORMAT_RGB888 /* RGB888 */
tvendov 0:6435b67ad23c 115 } drv_video_format_t;
tvendov 0:6435b67ad23c 116
tvendov 0:6435b67ad23c 117
tvendov 0:6435b67ad23c 118 /* lcd tcon output pin select */
tvendov 0:6435b67ad23c 119 typedef enum {
tvendov 0:6435b67ad23c 120 DRV_LCD_TCON_PIN_NON = -1, /* Not using output */
tvendov 0:6435b67ad23c 121 DRV_LCD_TCON_PIN_0, /* LCD_TCON0 */
tvendov 0:6435b67ad23c 122 DRV_LCD_TCON_PIN_1, /* LCD_TCON1 */
tvendov 0:6435b67ad23c 123 DRV_LCD_TCON_PIN_2 /* LCD_TCON2 */
tvendov 0:6435b67ad23c 124 } drv_lcd_tcon_pin_t;
tvendov 0:6435b67ad23c 125
tvendov 0:6435b67ad23c 126 /* lcd output format select */
tvendov 0:6435b67ad23c 127 typedef enum {
tvendov 0:6435b67ad23c 128 DRV_LCD_OUTFORMAT_RGB888 = 0, /* RGB888 or LVDS */
tvendov 0:6435b67ad23c 129 DRV_LCD_OUTFORMAT_RGB666, /* RGB666 */
tvendov 0:6435b67ad23c 130 DRV_LCD_OUTFORMAT_RGB565 /* RGB565 */
tvendov 0:6435b67ad23c 131 } drv_lcd_outformat_t;
tvendov 0:6435b67ad23c 132
tvendov 0:6435b67ad23c 133 /* frame buffer swap setting */
tvendov 0:6435b67ad23c 134 typedef enum {
tvendov 0:6435b67ad23c 135 DRV_WR_RD_WRSWA_NON = 0, /* Not swapped: 1-2-3-4-5-6-7-8 */
tvendov 0:6435b67ad23c 136 DRV_WR_RD_WRSWA_8BIT, /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
tvendov 0:6435b67ad23c 137 DRV_WR_RD_WRSWA_16BIT, /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
tvendov 0:6435b67ad23c 138 DRV_WR_RD_WRSWA_16_8BIT, /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
tvendov 0:6435b67ad23c 139 DRV_WR_RD_WRSWA_32BIT, /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
tvendov 0:6435b67ad23c 140 DRV_WR_RD_WRSWA_32_8BIT, /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
tvendov 0:6435b67ad23c 141 DRV_WR_RD_WRSWA_32_16BIT, /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
tvendov 0:6435b67ad23c 142 DRV_WR_RD_WRSWA_32_16_8BIT, /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
tvendov 0:6435b67ad23c 143 } drv_wr_rd_swa_t;
tvendov 0:6435b67ad23c 144
tvendov 0:6435b67ad23c 145 /* edge of a signal */
tvendov 0:6435b67ad23c 146 typedef enum {
tvendov 0:6435b67ad23c 147 DRV_EDGE_RISING = 0, /* Rising edge */
tvendov 0:6435b67ad23c 148 DRV_EDGE_FALLING = 1 /* Falling edge */
tvendov 0:6435b67ad23c 149 } drv_edge_t;
tvendov 0:6435b67ad23c 150
tvendov 0:6435b67ad23c 151 /* lcd type */
tvendov 0:6435b67ad23c 152 typedef enum {
tvendov 0:6435b67ad23c 153 DRV_LCD_TYPE_LVDS = 0, /* LVDS signal control */
tvendov 0:6435b67ad23c 154 DRV_LCD_TYPE_PARALLEL_RGB /* RGB parallel signal control */
tvendov 0:6435b67ad23c 155 } drv_lcd_type_t;
tvendov 0:6435b67ad23c 156
tvendov 0:6435b67ad23c 157 /* Polarity of a signal */
tvendov 0:6435b67ad23c 158 typedef enum {
tvendov 0:6435b67ad23c 159 DRV_SIG_POL_NOT_INVERTED = 0, /* Not inverted */
tvendov 0:6435b67ad23c 160 DRV_SIG_POL_INVERTED /* Inverted */
tvendov 0:6435b67ad23c 161 } drv_sig_pol_t;
tvendov 0:6435b67ad23c 162
tvendov 0:6435b67ad23c 163 /* Video color system */
tvendov 0:6435b67ad23c 164 typedef enum {
tvendov 0:6435b67ad23c 165 DRV_COL_SYS_NTSC_358 = 0, /* NTSC-3.58 */
tvendov 0:6435b67ad23c 166 DVV_COL_SYS_NTSC_443 = 1, /* NTSC-4.43 */
tvendov 0:6435b67ad23c 167 DRV_COL_SYS_PAL_443 = 2, /* PAL-4.43 */
tvendov 0:6435b67ad23c 168 DRV_COL_SYS_PAL_M = 3, /* PAL-M */
tvendov 0:6435b67ad23c 169 DRV_COL_SYS_PAL_N = 4, /* PAL-N */
tvendov 0:6435b67ad23c 170 DRV_COL_SYS_SECAM = 5, /* SECAM */
tvendov 0:6435b67ad23c 171 DRV_COL_SYS_NTSC_443_60 = 6, /* NTSC-4.43 (60Hz) */
tvendov 0:6435b67ad23c 172 DRV_COL_SYS_PAL_60 = 7, /* PAL-60 */
tvendov 0:6435b67ad23c 173 } drv_graphics_video_col_sys_t;
tvendov 0:6435b67ad23c 174
tvendov 0:6435b67ad23c 175 /* External Input select */
tvendov 0:6435b67ad23c 176 typedef enum {
tvendov 0:6435b67ad23c 177 DRV_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
tvendov 0:6435b67ad23c 178 DRV_INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
tvendov 0:6435b67ad23c 179 } drv_video_input_sel_t;
tvendov 0:6435b67ad23c 180
tvendov 0:6435b67ad23c 181 /* External input format select */
tvendov 0:6435b67ad23c 182 typedef enum {
tvendov 0:6435b67ad23c 183 DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
tvendov 0:6435b67ad23c 184 DRV_VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
tvendov 0:6435b67ad23c 185 DRV_VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
tvendov 0:6435b67ad23c 186 DRV_VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
tvendov 0:6435b67ad23c 187 DRV_VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
tvendov 0:6435b67ad23c 188 DRV_VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
tvendov 0:6435b67ad23c 189 DRV_VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
tvendov 0:6435b67ad23c 190 } drv_video_extin_format_t;
tvendov 0:6435b67ad23c 191
tvendov 0:6435b67ad23c 192 /* On/off */
tvendov 0:6435b67ad23c 193 typedef enum {
tvendov 0:6435b67ad23c 194 DRV_OFF = 0, /*!< Off */
tvendov 0:6435b67ad23c 195 DRV_ON = 1 /*!< On */
tvendov 0:6435b67ad23c 196 } drv_onoff_t;
tvendov 0:6435b67ad23c 197
tvendov 0:6435b67ad23c 198 /* Number of lines for BT.656 external input */
tvendov 0:6435b67ad23c 199 typedef enum {
tvendov 0:6435b67ad23c 200 DRV_EXTIN_LINE_525 = 0, /*!< 525 lines */
tvendov 0:6435b67ad23c 201 DRV_EXTIN_LINE_625 = 1 /*!< 625 lines */
tvendov 0:6435b67ad23c 202 } drv_extin_input_line_t;
tvendov 0:6435b67ad23c 203
tvendov 0:6435b67ad23c 204 /* Y/Cb/Y/Cr data string start timing */
tvendov 0:6435b67ad23c 205 typedef enum {
tvendov 0:6435b67ad23c 206 DRV_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
tvendov 0:6435b67ad23c 207 DRV_EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
tvendov 0:6435b67ad23c 208 DRV_EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
tvendov 0:6435b67ad23c 209 DRV_EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
tvendov 0:6435b67ad23c 210 } drv_extin_h_pos_t;
tvendov 0:6435b67ad23c 211
tvendov 0:6435b67ad23c 212 /* The relative position within the graphics display area */
tvendov 0:6435b67ad23c 213 typedef struct {
tvendov 0:6435b67ad23c 214 uint16_t vs; /* Vertical start pos */
tvendov 0:6435b67ad23c 215 uint16_t vw; /* Vertical width (height) */
tvendov 0:6435b67ad23c 216 uint16_t hs; /* Horizontal start pos */
tvendov 0:6435b67ad23c 217 uint16_t hw; /* Horizontal width */
tvendov 0:6435b67ad23c 218 } drv_rect_t;
tvendov 0:6435b67ad23c 219
tvendov 0:6435b67ad23c 220 /* lcd configuration */
tvendov 0:6435b67ad23c 221 typedef struct {
tvendov 0:6435b67ad23c 222 drv_lcd_type_t lcd_type; /* LVDS or Pararel RGB */
tvendov 0:6435b67ad23c 223 double intputClock; /* P1 clk [MHz] ex. 66.67 */
tvendov 0:6435b67ad23c 224 double outputClock; /* LCD clk [MHz] ex. 33.33 */
tvendov 0:6435b67ad23c 225
tvendov 0:6435b67ad23c 226 drv_lcd_outformat_t lcd_outformat; /* Output format select */
tvendov 0:6435b67ad23c 227 drv_edge_t lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
tvendov 0:6435b67ad23c 228
tvendov 0:6435b67ad23c 229 uint16_t h_toatal_period; /* Free-running Hsync period */
tvendov 0:6435b67ad23c 230 uint16_t v_toatal_period; /* Free-running Vsync period */
tvendov 0:6435b67ad23c 231 uint16_t h_disp_widht; /* LCD display area size, horizontal width */
tvendov 0:6435b67ad23c 232 uint16_t v_disp_widht; /* LCD display area size, vertical width */
tvendov 0:6435b67ad23c 233 uint16_t h_back_porch; /* LCD display horizontal back porch period */
tvendov 0:6435b67ad23c 234 uint16_t v_back_porch; /* LCD display vertical back porch period */
tvendov 0:6435b67ad23c 235
tvendov 0:6435b67ad23c 236 drv_lcd_tcon_pin_t h_sync_port; /* TCONn or Not use(-1) */
tvendov 0:6435b67ad23c 237 drv_sig_pol_t h_sync_port_polarity; /* Polarity inversion control of signal */
tvendov 0:6435b67ad23c 238 uint16_t h_sync_width; /* Hsync width */
tvendov 0:6435b67ad23c 239
tvendov 0:6435b67ad23c 240 drv_lcd_tcon_pin_t v_sync_port; /* TCONn or Not use(-1) */
tvendov 0:6435b67ad23c 241 drv_sig_pol_t v_sync_port_polarity; /* Polarity inversion control of signal */
tvendov 0:6435b67ad23c 242 uint16_t v_sync_width; /* Vsync width */
tvendov 0:6435b67ad23c 243
tvendov 0:6435b67ad23c 244 drv_lcd_tcon_pin_t de_port; /* TCONn or Not use(-1) */
tvendov 0:6435b67ad23c 245 drv_sig_pol_t de_port_polarity; /* Polarity inversion control of signal */
tvendov 0:6435b67ad23c 246
tvendov 0:6435b67ad23c 247 } drv_lcd_config_t;
tvendov 0:6435b67ad23c 248
tvendov 0:6435b67ad23c 249 /* Digital video input configuration */
tvendov 0:6435b67ad23c 250 typedef struct {
tvendov 0:6435b67ad23c 251 drv_video_extin_format_t inp_format; /*!< External Input Format Select */
tvendov 0:6435b67ad23c 252 drv_edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
tvendov 0:6435b67ad23c 253 drv_edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
tvendov 0:6435b67ad23c 254 drv_edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
tvendov 0:6435b67ad23c 255 drv_onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
tvendov 0:6435b67ad23c 256 drv_onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
tvendov 0:6435b67ad23c 257 drv_sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
tvendov 0:6435b67ad23c 258 drv_sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
tvendov 0:6435b67ad23c 259 drv_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
tvendov 0:6435b67ad23c 260 drv_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
tvendov 0:6435b67ad23c 261 } drv_video_ext_in_config_t;
tvendov 0:6435b67ad23c 262
tvendov 0:6435b67ad23c 263 /******************************************************************************
tvendov 0:6435b67ad23c 264 Typedef definitions
tvendov 0:6435b67ad23c 265 ******************************************************************************/
tvendov 0:6435b67ad23c 266 typedef enum
tvendov 0:6435b67ad23c 267 {
tvendov 0:6435b67ad23c 268 SLIDE_OUT_RIGHT = 0,
tvendov 0:6435b67ad23c 269 SLIDE_IN_RIGHT,
tvendov 0:6435b67ad23c 270 SLIDE_OUT_BOTTOM,
tvendov 0:6435b67ad23c 271 SLIDE_IN_BOTTOM,
tvendov 0:6435b67ad23c 272 SLIDE_OUT_LEFT,
tvendov 0:6435b67ad23c 273 SLIDE_IN_LEFT,
tvendov 0:6435b67ad23c 274 SLIDE_OUT_TOP,
tvendov 0:6435b67ad23c 275 SLIDE_IN_TOP,
tvendov 0:6435b67ad23c 276 SLIDE_NONE,
tvendov 0:6435b67ad23c 277 } slide_dir_t;
tvendov 0:6435b67ad23c 278 /******************************************************************************
tvendov 0:6435b67ad23c 279 Exported global functions (to be accessed by other files)
tvendov 0:6435b67ad23c 280 ******************************************************************************/
tvendov 0:6435b67ad23c 281 drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config );
tvendov 0:6435b67ad23c 282 drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config );
tvendov 0:6435b67ad23c 283
tvendov 0:6435b67ad23c 284 drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count );
tvendov 0:6435b67ad23c 285 drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count );
tvendov 0:6435b67ad23c 286 drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count );
tvendov 0:6435b67ad23c 287
tvendov 0:6435b67ad23c 288 drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t) );
tvendov 0:6435b67ad23c 289
tvendov 0:6435b67ad23c 290 drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id );
tvendov 0:6435b67ad23c 291 drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id );
tvendov 0:6435b67ad23c 292 drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch );
tvendov 0:6435b67ad23c 293 drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch );
tvendov 0:6435b67ad23c 294
tvendov 0:6435b67ad23c 295 drv_graphics_error_t DRV_Graphics_Read_Setting (
tvendov 0:6435b67ad23c 296 drv_graphics_layer_t layer_id,
tvendov 0:6435b67ad23c 297 void * framebuff,
tvendov 0:6435b67ad23c 298 uint32_t fb_stride,
tvendov 0:6435b67ad23c 299 drv_graphics_format_t gr_format,
tvendov 0:6435b67ad23c 300 drv_wr_rd_swa_t wr_rd_swa,
tvendov 0:6435b67ad23c 301 drv_rect_t * gr_rect );
tvendov 0:6435b67ad23c 302
tvendov 0:6435b67ad23c 303 drv_graphics_error_t DRV_Graphics_Read_Change (
tvendov 0:6435b67ad23c 304 drv_graphics_layer_t layer_id,
tvendov 0:6435b67ad23c 305 void * framebuff);
tvendov 0:6435b67ad23c 306
tvendov 0:6435b67ad23c 307 drv_graphics_error_t DRV_Graphics_Read_Change_More (
tvendov 0:6435b67ad23c 308 drv_graphics_layer_t layer_id,
tvendov 0:6435b67ad23c 309 void * framebuff,
tvendov 0:6435b67ad23c 310 uint32_t fb_stride,
tvendov 0:6435b67ad23c 311 void * slide_dir);
tvendov 0:6435b67ad23c 312
tvendov 0:6435b67ad23c 313 drv_graphics_error_t DRV_Video_Write_Setting (
tvendov 0:6435b67ad23c 314 drv_video_input_channel_t video_input_ch,
tvendov 0:6435b67ad23c 315 drv_graphics_video_col_sys_t col_sys,
tvendov 0:6435b67ad23c 316 void * framebuff,
tvendov 0:6435b67ad23c 317 uint32_t fb_stride,
tvendov 0:6435b67ad23c 318 drv_video_format_t video_format,
tvendov 0:6435b67ad23c 319 drv_wr_rd_swa_t wr_rd_swa,
tvendov 0:6435b67ad23c 320 uint16_t video_write_buff_vw,
tvendov 0:6435b67ad23c 321 uint16_t video_write_buff_hw,
tvendov 0:6435b67ad23c 322 drv_video_adc_vinsel_t video_adc_vinsel );
tvendov 0:6435b67ad23c 323
tvendov 0:6435b67ad23c 324 drv_graphics_error_t DRV_Video_Write_Setting_Digital (
tvendov 0:6435b67ad23c 325 void * framebuff,
tvendov 0:6435b67ad23c 326 uint32_t fb_stride,
tvendov 0:6435b67ad23c 327 drv_video_format_t video_format,
tvendov 0:6435b67ad23c 328 drv_wr_rd_swa_t wr_rd_swa,
tvendov 0:6435b67ad23c 329 uint16_t video_write_buff_vw,
tvendov 0:6435b67ad23c 330 uint16_t video_write_buff_hw,
tvendov 0:6435b67ad23c 331 drv_rect_t * cap_area );
tvendov 0:6435b67ad23c 332
tvendov 0:6435b67ad23c 333 drv_graphics_error_t DRV_Video_Write_Change (
tvendov 0:6435b67ad23c 334 drv_video_input_channel_t video_input_ch,
tvendov 0:6435b67ad23c 335 void * framebuff,
tvendov 0:6435b67ad23c 336 uint32_t fb_stride );
tvendov 0:6435b67ad23c 337
tvendov 0:6435b67ad23c 338 #ifdef __cplusplus
tvendov 0:6435b67ad23c 339 }
tvendov 0:6435b67ad23c 340 #endif /* __cplusplus */
tvendov 0:6435b67ad23c 341
tvendov 0:6435b67ad23c 342 #endif /* VDC5_H */
tvendov 0:6435b67ad23c 343