VK_RZ_A1H_LCD_demo - Lcd companion boards support (VKLCD50RTA & VKLCD7…

Vekatech » Code » VK_RZ_A1H_LCD_demo

Lcd companion boards support (VKLCD50RTA & VKLCD70RT)

What is this ?

This is a demo program using Renesas RGA library & USB Camera to demonstrate VK-RZ/A1H's companion boards workability.

Supported companion Boards:

VKLCD50RTA

/media/uploads/tvendov/front_view_hmi_50.png /media/uploads/tvendov/side_view_hmi_50.png

VKLCD70RT

/media/uploads/tvendov/front_view_hmi_70.png /media/uploads/tvendov/side_view_hmi_70.png /media/uploads/tvendov/back_view_lvds.png

How to Configure ?

You can choose which display is installed by altering the lcd_panel.h file

Leave the active one & comment out the others:

#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD50RTA
//#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD70RT

You can alter the whole demo with your pictures if you like:

How to compile ?

The Demo can be compiled in 3 modes:
- I. Execution from the internal 10-MB on-chip SRAM.
  - After import in the online compiler just leave only the VKRZA1H_RAM.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
  - Save the result binary in the SD Card (<SD>:\vkrza1\lcd_sample ), altering vkrza1h.ini by this way
- II. Execution from the on-board serial FALSH in dual (32-MB) mode.
  - After import in the online compiler just leave only the VKRZA1H_DOUBLE.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
  - Drag & drop the result binary in MBED disk, (previously inited in double flash mode)
- III. Execution from the on-board serial FALSH in single (16-MB) mode.
  - After import in the online compiler just leave only the VKRZA1H_SINGLE.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
  - Drag & drop the result binary in MBED disk, (previously inited in single flash mode )

Quick presentation:

Other demos ?

More demos you can find on our FTP

RGA/video/vdc5.c@0:6435b67ad23c, 2017-02-16 (annotated)

Committer:: tvendov
Date:: Thu Feb 16 10:23:48 2017 +0000
Revision:: 0:6435b67ad23c

Initial lcd support (VKLCD50RTA & VKLCD70RT companion boards)

Who changed what in which revision?

User	Revision	Line number	New contents of line
tvendov	0:6435b67ad23c	1	/*******************************************************************************
tvendov	0:6435b67ad23c	2	* DISCLAIMER
tvendov	0:6435b67ad23c	3	* This software is supplied by Renesas Electronics Corporation and is only
tvendov	0:6435b67ad23c	4	* intended for use with Renesas products. No other uses are authorized. This
tvendov	0:6435b67ad23c	5	* software is owned by Renesas Electronics Corporation and is protected under
tvendov	0:6435b67ad23c	6	* all applicable laws, including copyright laws.
tvendov	0:6435b67ad23c	7	* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
tvendov	0:6435b67ad23c	8	* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
tvendov	0:6435b67ad23c	9	* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
tvendov	0:6435b67ad23c	10	* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
tvendov	0:6435b67ad23c	11	* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
tvendov	0:6435b67ad23c	12	* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
tvendov	0:6435b67ad23c	13	* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
tvendov	0:6435b67ad23c	14	* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
tvendov	0:6435b67ad23c	15	* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
tvendov	0:6435b67ad23c	16	* Renesas reserves the right, without notice, to make changes to this software
tvendov	0:6435b67ad23c	17	* and to discontinue the availability of this software. By using this software,
tvendov	0:6435b67ad23c	18	* you agree to the additional terms and conditions found by accessing the
tvendov	0:6435b67ad23c	19	* following link:
tvendov	0:6435b67ad23c	20	* http://www.renesas.com/disclaimer
tvendov	0:6435b67ad23c	21	* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
tvendov	0:6435b67ad23c	22	*******************************************************************************/
tvendov	0:6435b67ad23c	23	/************************************************************************//
tvendov	0:6435b67ad23c	24	* @file vdc5.c
tvendov	0:6435b67ad23c	25	* @version
tvendov	0:6435b67ad23c	26	* $Rev:
tvendov	0:6435b67ad23c	27	* $Date::
tvendov	0:6435b67ad23c	28	* @brief VDC5 driver API wrapper function in C interface
tvendov	0:6435b67ad23c	29	******************************************************************************/
tvendov	0:6435b67ad23c	30
tvendov	0:6435b67ad23c	31	/******************************************************************************
tvendov	0:6435b67ad23c	32	Includes <System Includes> , "Project Includes"
tvendov	0:6435b67ad23c	33	******************************************************************************/
tvendov	0:6435b67ad23c	34	#include <stdio.h>
tvendov	0:6435b67ad23c	35	#include <string.h>
tvendov	0:6435b67ad23c	36
tvendov	0:6435b67ad23c	37	#include "r_typedefs.h"
tvendov	0:6435b67ad23c	38	#include "r_vdc5.h"
tvendov	0:6435b67ad23c	39	#include "video_decoder.h"
tvendov	0:6435b67ad23c	40	#include "lvds_pll_calc.h"
tvendov	0:6435b67ad23c	41	#include "vdc5.h"
tvendov	0:6435b67ad23c	42
tvendov	0:6435b67ad23c	43	#include "mbed_assert.h"
tvendov	0:6435b67ad23c	44	#include "pinmap.h"
tvendov	0:6435b67ad23c	45
tvendov	0:6435b67ad23c	46	#include "lcd_panel.h"
tvendov	0:6435b67ad23c	47
tvendov	0:6435b67ad23c	48	/******************************************************************************
tvendov	0:6435b67ad23c	49	Macro definitions
tvendov	0:6435b67ad23c	50	******************************************************************************/
tvendov	0:6435b67ad23c	51	#define STP91_BIT (0x02u)
tvendov	0:6435b67ad23c	52	#define STP90_BIT (0x01u)
tvendov	0:6435b67ad23c	53	#define STBRQ25_BIT (0x20u)
tvendov	0:6435b67ad23c	54	#define STBAK25_BIT (0x20u)
tvendov	0:6435b67ad23c	55	#define STBRQ24_BIT (0x10u)
tvendov	0:6435b67ad23c	56	#define STBAK24_BIT (0x10u)
tvendov	0:6435b67ad23c	57
tvendov	0:6435b67ad23c	58	/******************************************************************************
tvendov	0:6435b67ad23c	59	Typedef definitions
tvendov	0:6435b67ad23c	60	******************************************************************************/
tvendov	0:6435b67ad23c	61	typedef enum {
tvendov	0:6435b67ad23c	62	VDC5_CH0, VDC5_CH1,
tvendov	0:6435b67ad23c	63	} VDC5Name;
tvendov	0:6435b67ad23c	64
tvendov	0:6435b67ad23c	65	/******************************************************************************
tvendov	0:6435b67ad23c	66	Imported global variables and functions (from other files)
tvendov	0:6435b67ad23c	67	******************************************************************************/
tvendov	0:6435b67ad23c	68
tvendov	0:6435b67ad23c	69	/******************************************************************************
tvendov	0:6435b67ad23c	70	Exported global variables (to be accessed by other files)
tvendov	0:6435b67ad23c	71	******************************************************************************/
tvendov	0:6435b67ad23c	72	static const PinMap PinMap_DV_INPUT_PIN[] = { { P8_11, VDC5_CH0, 8 }, /* DV0_CLK */
tvendov	0:6435b67ad23c	73	{ P1_12, VDC5_CH0, 2 }, /* DV0_VSYNC */
tvendov	0:6435b67ad23c	74	{ P1_13, VDC5_CH0, 2 }, /* DV0_HSYNC */
tvendov	0:6435b67ad23c	75	{ P1_1, VDC5_CH0, 6 }, /* DV0_HSYNC */
tvendov	0:6435b67ad23c	76	{ P1_0, VDC5_CH0, 6 }, /* DV0_VSYNC */
tvendov	0:6435b67ad23c	77	{ P1_9, VDC5_CH0, 6 }, /* DV0_DATA15 */
tvendov	0:6435b67ad23c	78	{ P2_15, VDC5_CH0, 3 }, /* DV0_DATA15 */
tvendov	0:6435b67ad23c	79	{ P4_7, VDC5_CH0, 7 }, /* DV0_DATA15 */
tvendov	0:6435b67ad23c	80	{ P5_7, VDC5_CH0, 4 }, /* DV0_DATA15 */
tvendov	0:6435b67ad23c	81	{ P1_8, VDC5_CH0, 6 }, /* DV0_DATA14 */
tvendov	0:6435b67ad23c	82	{ P2_14, VDC5_CH0, 3 }, /* DV0_DATA14 */
tvendov	0:6435b67ad23c	83	{ P4_6, VDC5_CH0, 7 }, /* DV0_DATA14 */
tvendov	0:6435b67ad23c	84	{ P5_6, VDC5_CH0, 4 }, /* DV0_DATA14 */
tvendov	0:6435b67ad23c	85	{ P1_7, VDC5_CH0, 6 }, /* DV0_DATA13 */
tvendov	0:6435b67ad23c	86	{ P2_13, VDC5_CH0, 3 }, /* DV0_DATA13 */
tvendov	0:6435b67ad23c	87	{ P4_5, VDC5_CH0, 7 }, /* DV0_DATA13 */
tvendov	0:6435b67ad23c	88	{ P5_5, VDC5_CH0, 4 }, /* DV0_DATA13 */
tvendov	0:6435b67ad23c	89	{ P1_6, VDC5_CH0, 6 }, /* DV0_DATA12 */
tvendov	0:6435b67ad23c	90	{ P4_4, VDC5_CH0, 7 }, /* DV0_DATA12 */
tvendov	0:6435b67ad23c	91	{ P5_4, VDC5_CH0, 4 }, /* DV0_DATA12 */
tvendov	0:6435b67ad23c	92	{ P2_10, VDC5_CH0, 3 }, /* DV0_DATA10 */
tvendov	0:6435b67ad23c	93	{ P2_9, VDC5_CH0, 3 }, /* DV0_DATA9 */
tvendov	0:6435b67ad23c	94	{ P2_7, VDC5_CH0, 3 }, /* DV0_DATA7 */
tvendov	0:6435b67ad23c	95	{ P2_6, VDC5_CH0, 3 }, /* DV0_DATA6 */
tvendov	0:6435b67ad23c	96	{ P2_5, VDC5_CH0, 3 }, /* DV0_DATA5 */
tvendov	0:6435b67ad23c	97	{ P2_4, VDC5_CH0, 3 }, /* DV0_DATA4 */
tvendov	0:6435b67ad23c	98	{ P2_3, VDC5_CH0, 3 }, /* DV0_DATA3 */
tvendov	0:6435b67ad23c	99	{ P2_2, VDC5_CH0, 3 }, /* DV0_DATA2 */
tvendov	0:6435b67ad23c	100	{ P2_1, VDC5_CH0, 3 }, /* DV0_DATA1 */
tvendov	0:6435b67ad23c	101	{ P2_0, VDC5_CH0, 3 }, /* DV0_DATA0 */
tvendov	0:6435b67ad23c	102	{ NC, NC, 0 } };
tvendov	0:6435b67ad23c	103
tvendov	0:6435b67ad23c	104	#ifdef MAX_PERI
tvendov	0:6435b67ad23c	105	static const PinMap PinMap_LCD_DISP_PIN[] = {
tvendov	0:6435b67ad23c	106	{ P2_7 , VDC5_CH0, 8}, {P4_15 , VDC5_CH0, 1}, {P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23 */
tvendov	0:6435b67ad23c	107	{ P2_6 , VDC5_CH0, 8}, {P4_14 , VDC5_CH0, 1}, {P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22 */
tvendov	0:6435b67ad23c	108	{ P2_5 , VDC5_CH0, 8}, {P4_13 , VDC5_CH0, 1}, {P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21 */
tvendov	0:6435b67ad23c	109	{ P2_4 , VDC5_CH0, 8}, {P4_12 , VDC5_CH0, 1}, {P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20 */
tvendov	0:6435b67ad23c	110	{ P2_3 , VDC5_CH0, 8}, {P4_11 , VDC5_CH0, 1}, {P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19 */
tvendov	0:6435b67ad23c	111	{ P2_2 , VDC5_CH0, 8}, {P4_10 , VDC5_CH0, 1}, {P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18 */
tvendov	0:6435b67ad23c	112	{ P2_1 , VDC5_CH0, 8}, {P4_9 , VDC5_CH0, 1}, {P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17 */
tvendov	0:6435b67ad23c	113	{ P2_0 , VDC5_CH0, 8}, {P4_8 , VDC5_CH0, 1}, {P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16 */
tvendov	0:6435b67ad23c	114	{ P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */
tvendov	0:6435b67ad23c	115	{ P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */
tvendov	0:6435b67ad23c	116	{ P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */
tvendov	0:6435b67ad23c	117	{ P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */
tvendov	0:6435b67ad23c	118	{ P4_3 , VDC5_CH0, 1}, /* LCD0_DATA11 */
tvendov	0:6435b67ad23c	119	{ P4_2 , VDC5_CH0, 1}, /* LCD0_DATA10 */
tvendov	0:6435b67ad23c	120	{ P4_1 , VDC5_CH0, 1}, /* LCD0_DATA9 */
tvendov	0:6435b67ad23c	121	{ P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8 */
tvendov	0:6435b67ad23c	122	{ P3_15 , VDC5_CH0, 1}, {P6_15 , VDC5_CH0, 6}, /* LCD0_DATA7 */
tvendov	0:6435b67ad23c	123	{ P3_14 , VDC5_CH0, 1}, {P6_14 , VDC5_CH0, 6}, /* LCD0_DATA6 */
tvendov	0:6435b67ad23c	124	{ P3_13 , VDC5_CH0, 1}, {P6_13 , VDC5_CH0, 6}, /* LCD0_DATA5 */
tvendov	0:6435b67ad23c	125	{ P3_12 , VDC5_CH0, 1}, {P6_12 , VDC5_CH0, 6}, /* LCD0_DATA4 */
tvendov	0:6435b67ad23c	126	{ P3_11 , VDC5_CH0, 1}, {P6_11 , VDC5_CH0, 6}, /* LCD0_DATA3 */
tvendov	0:6435b67ad23c	127	{ P3_10 , VDC5_CH0, 1}, {P6_10 , VDC5_CH0, 6}, /* LCD0_DATA2 */
tvendov	0:6435b67ad23c	128	{ P3_9 , VDC5_CH0, 1}, {P6_9 , VDC5_CH0, 6}, /* LCD0_DATA1 */
tvendov	0:6435b67ad23c	129	{ P3_8 , VDC5_CH0, 1}, {P6_8 , VDC5_CH0, 6}, /* LCD0_DATA0 */
tvendov	0:6435b67ad23c	130	{ P3_7 , VDC5_CH0, 1}, {P6_7 , VDC5_CH0, 4}, {P2_8 , VDC5_CH0, 5}, /* LCD0_TCON6 {P6_11 , VDC5_CH0, 4} */
tvendov	0:6435b67ad23c	131	{ P3_6 , VDC5_CH0, 1}, {P6_6 , VDC5_CH0, 4}, /* LCD0_TCON5 {P6_10 , VDC5_CH0, 4} */
tvendov	0:6435b67ad23c	132	{ P3_5 , VDC5_CH0, 1}, /* LCD0_TCON4 */
tvendov	0:6435b67ad23c	133	{ P3_4 , VDC5_CH0, 1}, /* LCD0_TCON3 */
tvendov	0:6435b67ad23c	134	{ P3_3 , VDC5_CH0, 1}, /* LCD0_TCON2 */
tvendov	0:6435b67ad23c	135	{ P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1 */
tvendov	0:6435b67ad23c	136	{ P3_1 , VDC5_CH0, 1}, /* LCD0_TCON0 */
tvendov	0:6435b67ad23c	137	{ P3_0 , VDC5_CH0, 1}, /* LCD0_CLK */
tvendov	0:6435b67ad23c	138	{ P5_8 , VDC5_CH0, 1}, /* LCD0_EXTCLK */
tvendov	0:6435b67ad23c	139	{ NC , NC , 0}
tvendov	0:6435b67ad23c	140	};
tvendov	0:6435b67ad23c	141	#else
tvendov	0:6435b67ad23c	142	static const PinMap PinMap_LCD_DISP_PIN[] = {
tvendov	0:6435b67ad23c	143	//R
tvendov	0:6435b67ad23c	144	{ P4_7, VDC5_CH0, 1 }, /* LCD0_DATA15 */
tvendov	0:6435b67ad23c	145	{ P4_6, VDC5_CH0, 1 }, /* LCD0_DATA14 */
tvendov	0:6435b67ad23c	146	{ P4_5, VDC5_CH0, 1 }, /* LCD0_DATA13 */
tvendov	0:6435b67ad23c	147	{ P4_4, VDC5_CH0, 1 }, /* LCD0_DATA12 */
tvendov	0:6435b67ad23c	148	{ P4_3, VDC5_CH0, 1 }, /* LCD0_DATA11 */
tvendov	0:6435b67ad23c	149	//G
tvendov	0:6435b67ad23c	150	{ P4_2, VDC5_CH0, 1 }, /* LCD0_DATA10 */
tvendov	0:6435b67ad23c	151	{ P4_1, VDC5_CH0, 1 }, /* LCD0_DATA9 */
tvendov	0:6435b67ad23c	152	{ P4_0, VDC5_CH0, 1 }, /* LCD0_DATA8 */
tvendov	0:6435b67ad23c	153	{ P3_15, VDC5_CH0, 1 }, /* LCD0_DATA7 */
tvendov	0:6435b67ad23c	154	{ P3_14, VDC5_CH0, 1 }, /* LCD0_DATA6 */
tvendov	0:6435b67ad23c	155	{ P3_13, VDC5_CH0, 1 }, /* LCD0_DATA5 */
tvendov	0:6435b67ad23c	156	//B
tvendov	0:6435b67ad23c	157	{ P3_12, VDC5_CH0, 1 }, /* LCD0_DATA4 */
tvendov	0:6435b67ad23c	158	{ P3_11, VDC5_CH0, 1 }, /* LCD0_DATA3 */
tvendov	0:6435b67ad23c	159	{ P3_10, VDC5_CH0, 1 }, /* LCD0_DATA2 */
tvendov	0:6435b67ad23c	160	{ P3_9, VDC5_CH0, 1 }, /* LCD0_DATA1 */
tvendov	0:6435b67ad23c	161	{ P3_8, VDC5_CH0, 1 }, /* LCD0_DATA0 */
tvendov	0:6435b67ad23c	162	//DE
tvendov	0:6435b67ad23c	163	{ P3_1, VDC5_CH0, 1 }, /* LCD0_TCON0 */
tvendov	0:6435b67ad23c	164	{ P3_0, VDC5_CH0, 1 }, /* LCD0_CLK */
tvendov	0:6435b67ad23c	165	{ NC, NC, 0 } };
tvendov	0:6435b67ad23c	166	#endif
tvendov	0:6435b67ad23c	167
tvendov	0:6435b67ad23c	168	#if 0
tvendov	0:6435b67ad23c	169	static const PinMap PinMap_LCD_DISP_PIN[] = {
tvendov	0:6435b67ad23c	170	{ P2_7 , VDC5_CH0, 8}, /* LCD0_DATA23 */
tvendov	0:6435b67ad23c	171	{ P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23 */
tvendov	0:6435b67ad23c	172	{ P2_6 , VDC5_CH0, 8}, /* LCD0_DATA22 */
tvendov	0:6435b67ad23c	173	{ P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22 */
tvendov	0:6435b67ad23c	174	{ P2_5 , VDC5_CH0, 8}, /* LCD0_DATA21 */
tvendov	0:6435b67ad23c	175	{ P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21 */
tvendov	0:6435b67ad23c	176	{ P2_4 , VDC5_CH0, 8}, /* LCD0_DATA20 */
tvendov	0:6435b67ad23c	177	{ P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20 */
tvendov	0:6435b67ad23c	178	{ P2_3 , VDC5_CH0, 8}, /* LCD0_DATA19 */
tvendov	0:6435b67ad23c	179	{ P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19 */
tvendov	0:6435b67ad23c	180	{ P2_2 , VDC5_CH0, 8}, /* LCD0_DATA18 */
tvendov	0:6435b67ad23c	181	{ P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18 */
tvendov	0:6435b67ad23c	182	{ P2_1 , VDC5_CH0, 8}, /* LCD0_DATA17 */
tvendov	0:6435b67ad23c	183	{ P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17 */
tvendov	0:6435b67ad23c	184	{ P2_0 , VDC5_CH0, 8}, /* LCD0_DATA16 */
tvendov	0:6435b67ad23c	185	{ P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16 */
tvendov	0:6435b67ad23c	186	{ P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */
tvendov	0:6435b67ad23c	187	{ P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */
tvendov	0:6435b67ad23c	188	{ P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */
tvendov	0:6435b67ad23c	189	{ P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */
tvendov	0:6435b67ad23c	190	{ P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8 */
tvendov	0:6435b67ad23c	191	{ P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7 */
tvendov	0:6435b67ad23c	192	{ P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6 */
tvendov	0:6435b67ad23c	193	{ P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5 */
tvendov	0:6435b67ad23c	194	{ P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4 */
tvendov	0:6435b67ad23c	195	{ P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3 */
tvendov	0:6435b67ad23c	196	{ P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2 */
tvendov	0:6435b67ad23c	197	{ P3_9 , VDC5_CH0, 1}, /* LCD0_DATA1 */
tvendov	0:6435b67ad23c	198	{ P3_8 , VDC5_CH0, 1}, /* LCD0_DATA0 */
tvendov	0:6435b67ad23c	199	{ P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1 */
tvendov	0:6435b67ad23c	200	{ NC , NC , 0}
tvendov	0:6435b67ad23c	201	};
tvendov	0:6435b67ad23c	202	#endif
tvendov	0:6435b67ad23c	203
tvendov	0:6435b67ad23c	204	static const PinMap PinMap_LVDS_DISP_PIN[] = { { P5_7, VDC5_CH0, 1 }, /* TXOUT0M */
tvendov	0:6435b67ad23c	205	{ P5_6, VDC5_CH0, 1 }, /* TXOUT0P */
tvendov	0:6435b67ad23c	206	{ P5_5, VDC5_CH0, 1 }, /* TXOUT1M */
tvendov	0:6435b67ad23c	207	{ P5_4, VDC5_CH0, 1 }, /* TXOUT1P */
tvendov	0:6435b67ad23c	208	{ P5_3, VDC5_CH0, 1 }, /* TXOUT2M */
tvendov	0:6435b67ad23c	209	{ P5_2, VDC5_CH0, 1 }, /* TXOUT2P */
tvendov	0:6435b67ad23c	210	{ P5_1, VDC5_CH0, 1 }, /* TXCLKOUTM */
tvendov	0:6435b67ad23c	211	{ P5_0, VDC5_CH0, 1 }, /* TXCLKOUTP */
tvendov	0:6435b67ad23c	212	{ NC, NC, 0 } };
tvendov	0:6435b67ad23c	213
tvendov	0:6435b67ad23c	214	static const IRQn_Type vdc5_irq_set_tbl[] = { S0_VI_VSYNC0_IRQn,
tvendov	0:6435b67ad23c	215	S0_LO_VSYNC0_IRQn, S0_VSYNCERR0_IRQn, GR3_VLINE0_IRQn, S0_VFIELD0_IRQn,
tvendov	0:6435b67ad23c	216	IV1_VBUFERR0_IRQn, IV3_VBUFERR0_IRQn, IV5_VBUFERR0_IRQn,
tvendov	0:6435b67ad23c	217	IV6_VBUFERR0_IRQn, S0_WLINE0_IRQn, S1_VI_VSYNC0_IRQn, S1_LO_VSYNC0_IRQn,
tvendov	0:6435b67ad23c	218	S1_VSYNCERR0_IRQn, S1_VFIELD0_IRQn, IV2_VBUFERR0_IRQn,
tvendov	0:6435b67ad23c	219	IV4_VBUFERR0_IRQn, S1_WLINE0_IRQn, OIR_VI_VSYNC0_IRQn,
tvendov	0:6435b67ad23c	220	OIR_LO_VSYNC0_IRQn, OIR_VSYNCERR0_IRQn, OIR_VFIELD0_IRQn,
tvendov	0:6435b67ad23c	221	IV7_VBUFERR0_IRQn, IV8_VBUFERR0_IRQn };
tvendov	0:6435b67ad23c	222
tvendov	0:6435b67ad23c	223	/******************************************************************************
tvendov	0:6435b67ad23c	224	Private global variables and functions
tvendov	0:6435b67ad23c	225	******************************************************************************/
tvendov	0:6435b67ad23c	226	static void init_func(const uint32_t user_num);
tvendov	0:6435b67ad23c	227	static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
tvendov	0:6435b67ad23c	228
tvendov	0:6435b67ad23c	229	/************************************************************************//
tvendov	0:6435b67ad23c	230	* @brief User-defined function within R_VDC5_Initialize
tvendov	0:6435b67ad23c	231	* @param[in] user_num : VDC5 channel
tvendov	0:6435b67ad23c	232	* @retval None
tvendov	0:6435b67ad23c	233	******************************************************************************/
tvendov	0:6435b67ad23c	234	static void init_func(const uint32_t user_num) {
tvendov	0:6435b67ad23c	235	uint32_t reg_data;
tvendov	0:6435b67ad23c	236	volatile uint8_t dummy_read;
tvendov	0:6435b67ad23c	237
tvendov	0:6435b67ad23c	238	if ((vdc5_channel_t) user_num == VDC5_CHANNEL_0) {
tvendov	0:6435b67ad23c	239
tvendov	0:6435b67ad23c	240	/* Standby control register 9 (STBCR9)
tvendov	0:6435b67ad23c	241	b1 ------0-; MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
tvendov	0:6435b67ad23c	242	reg_data = (uint32_t) CPG.STBCR9 & (uint32_t) ~STP91_BIT;
tvendov	0:6435b67ad23c	243	CPG.STBCR9 = (uint8_t) reg_data;
tvendov	0:6435b67ad23c	244	/* In order to reflect the change, a dummy read should be done. */
tvendov	0:6435b67ad23c	245	dummy_read = CPG.STBCR9;
tvendov	0:6435b67ad23c	246
tvendov	0:6435b67ad23c	247	/* Standby Request Register 2 (STBREQ2)
tvendov	0:6435b67ad23c	248	b5 --0-----; STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
tvendov	0:6435b67ad23c	249	reg_data = (uint32_t) CPG.STBREQ2 & (uint32_t) ~STBRQ25_BIT;
tvendov	0:6435b67ad23c	250	CPG.STBREQ2 = (uint8_t) reg_data;
tvendov	0:6435b67ad23c	251	/* Standby Acknowledge Register 2 (STBACK2)
tvendov	0:6435b67ad23c	252	b5 -------; STBAK25 : Standby acknowledgement from VDC5 channel 0. /
tvendov	0:6435b67ad23c	253	while (((uint32_t) CPG.STBACK2 & (uint32_t) STBAK25_BIT) != 0u) {
tvendov	0:6435b67ad23c	254	/* Wait for the STBAK25 to be cleared to 0. */
tvendov	0:6435b67ad23c	255	}
tvendov	0:6435b67ad23c	256
tvendov	0:6435b67ad23c	257	/* Standby control register 9 (STBCR9)
tvendov	0:6435b67ad23c	258	b0 -------0; MSTP90 : 0 : Video display controller channel 1 enable */
tvendov	0:6435b67ad23c	259	reg_data = (uint32_t) CPG.STBCR9 & (uint32_t) ~(STP91_BIT \| STP90_BIT);
tvendov	0:6435b67ad23c	260	CPG.STBCR9 = (uint8_t) reg_data;
tvendov	0:6435b67ad23c	261	/* In order to reflect the change, a dummy read should be done. */
tvendov	0:6435b67ad23c	262	dummy_read = CPG.STBCR9;
tvendov	0:6435b67ad23c	263
tvendov	0:6435b67ad23c	264	/* Standby Request Register 2 (STBREQ2)
tvendov	0:6435b67ad23c	265	b4 ---0----; STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
tvendov	0:6435b67ad23c	266	reg_data = (uint32_t) CPG.STBREQ2 & (uint32_t) ~STBRQ24_BIT;
tvendov	0:6435b67ad23c	267	CPG.STBREQ2 = (uint8_t) reg_data;
tvendov	0:6435b67ad23c	268	/* Standby Acknowledge Register 2 (STBACK2)
tvendov	0:6435b67ad23c	269	b4 -------; STBAK24 : Standby acknowledgement from VDC5 channel 1. /
tvendov	0:6435b67ad23c	270	while (((uint32_t) CPG.STBACK2 & (uint32_t) STBAK24_BIT) != 0u) {
tvendov	0:6435b67ad23c	271	/* Wait for the STBAK24 to be cleared to 0. */
tvendov	0:6435b67ad23c	272	}
tvendov	0:6435b67ad23c	273	}
tvendov	0:6435b67ad23c	274	} /* End of function init_func() */
tvendov	0:6435b67ad23c	275
tvendov	0:6435b67ad23c	276	/************************************************************************//
tvendov	0:6435b67ad23c	277	* @brief Interrupt service routine acquisition processing
tvendov	0:6435b67ad23c	278	*
tvendov	0:6435b67ad23c	279	* Description:<br>
tvendov	0:6435b67ad23c	280	* This function returns the function pointer to the specified interrupt service routine.
tvendov	0:6435b67ad23c	281	* @param[in] irq : VDC5 interrupt type
tvendov	0:6435b67ad23c	282	* @param[in] enable : VDC5 interrupt enable
tvendov	0:6435b67ad23c	283	* @retval None
tvendov	0:6435b67ad23c	284	******************************************************************************/
tvendov	0:6435b67ad23c	285	static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable) {
tvendov	0:6435b67ad23c	286	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	287	IRQn_Type IRQn;
tvendov	0:6435b67ad23c	288	IRQHandler handler;
tvendov	0:6435b67ad23c	289
tvendov	0:6435b67ad23c	290	IRQn = vdc5_irq_set_tbl[irq];
tvendov	0:6435b67ad23c	291	handler = R_VDC5_GetISR(ch, irq);
tvendov	0:6435b67ad23c	292
tvendov	0:6435b67ad23c	293	if (enable) {
tvendov	0:6435b67ad23c	294	InterruptHandlerRegister(IRQn, (void (*)(uint32_t)) handler);
tvendov	0:6435b67ad23c	295	GIC_SetPriority(IRQn, 5);
tvendov	0:6435b67ad23c	296	GIC_EnableIRQ(IRQn);
tvendov	0:6435b67ad23c	297	} else {
tvendov	0:6435b67ad23c	298	GIC_DisableIRQ(IRQn);
tvendov	0:6435b67ad23c	299	}
tvendov	0:6435b67ad23c	300	} /* End of function DRV_Graphics_Irq_Set() */
tvendov	0:6435b67ad23c	301
tvendov	0:6435b67ad23c	302	/************************************************************************//
tvendov	0:6435b67ad23c	303	* @brief Interrupt callback setup
tvendov	0:6435b67ad23c	304	* This function performs the following processing:
tvendov	0:6435b67ad23c	305	* - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
tvendov	0:6435b67ad23c	306	* - Registers the specified interrupt callback function.
tvendov	0:6435b67ad23c	307	* - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
tvendov	0:6435b67ad23c	308	* specified.
tvendov	0:6435b67ad23c	309	* @param[in] irq : VDC5 interrupt type
tvendov	0:6435b67ad23c	310	* @param[in] num : Interrupt line number
tvendov	0:6435b67ad23c	311	* @param[in] * callback : Interrupt callback function pointer
tvendov	0:6435b67ad23c	312	* @retval Error code
tvendov	0:6435b67ad23c	313	******************************************************************************/
tvendov	0:6435b67ad23c	314	drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(vdc5_int_type_t irq,
tvendov	0:6435b67ad23c	315	uint16_t num, void (*callback)(vdc5_int_type_t)) {
tvendov	0:6435b67ad23c	316	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	317	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	318	vdc5_error_t error;
tvendov	0:6435b67ad23c	319	vdc5_int_t interrupt;
tvendov	0:6435b67ad23c	320
tvendov	0:6435b67ad23c	321	if (callback == NULL) {
tvendov	0:6435b67ad23c	322	DRV_Graphics_Irq_Set(irq, 0);
tvendov	0:6435b67ad23c	323	} else {
tvendov	0:6435b67ad23c	324	DRV_Graphics_Irq_Set(irq, 1);
tvendov	0:6435b67ad23c	325	}
tvendov	0:6435b67ad23c	326
tvendov	0:6435b67ad23c	327	/* Interrupt parameter */
tvendov	0:6435b67ad23c	328	interrupt.type = irq; /* Interrupt type */
tvendov	0:6435b67ad23c	329	interrupt.line_num = num; /* Line number */
tvendov	0:6435b67ad23c	330
tvendov	0:6435b67ad23c	331	/* Interrupt parameter */
tvendov	0:6435b67ad23c	332	interrupt.callback = callback; /* Callback function pointer */
tvendov	0:6435b67ad23c	333	/* Set interrupt service routine */
tvendov	0:6435b67ad23c	334	error = R_VDC5_CallbackISR(ch, &interrupt);
tvendov	0:6435b67ad23c	335	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	336	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	337	}
tvendov	0:6435b67ad23c	338	return drv_error;
tvendov	0:6435b67ad23c	339	} /* End of function DRV_Graphics_Irq_Handler_Set() */
tvendov	0:6435b67ad23c	340
tvendov	0:6435b67ad23c	341	/************************************************************************//
tvendov	0:6435b67ad23c	342	* @brief LCD output port initialization processing
tvendov	0:6435b67ad23c	343	* @param[in] pin : Pin assign for LCD output
tvendov	0:6435b67ad23c	344	* @param[in] pin_count : Total number of pin assign
tvendov	0:6435b67ad23c	345	* @retval Error code
tvendov	0:6435b67ad23c	346	******************************************************************************/
tvendov	0:6435b67ad23c	347	drv_graphics_error_t DRV_Graphics_Lcd_Port_Init(PinName *pin,
tvendov	0:6435b67ad23c	348	uint32_t pin_count) {
tvendov	0:6435b67ad23c	349	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	350	uint32_t count;
tvendov	0:6435b67ad23c	351
tvendov	0:6435b67ad23c	352	for (count = 0; count < pin_count; count++) {
tvendov	0:6435b67ad23c	353	pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
tvendov	0:6435b67ad23c	354	pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
tvendov	0:6435b67ad23c	355	}
tvendov	0:6435b67ad23c	356	return drv_error;
tvendov	0:6435b67ad23c	357	} /* End of function DRV_Graphics_Lcd_Port_Init() */
tvendov	0:6435b67ad23c	358
tvendov	0:6435b67ad23c	359	/************************************************************************//
tvendov	0:6435b67ad23c	360	* @brief LVDS output port initialization processing
tvendov	0:6435b67ad23c	361	* @param[in] pin : Pin assign for LVDS output
tvendov	0:6435b67ad23c	362	* @param[in] pin_count : Total number of pin assign
tvendov	0:6435b67ad23c	363	* @retval Error code
tvendov	0:6435b67ad23c	364	******************************************************************************/
tvendov	0:6435b67ad23c	365	drv_graphics_error_t DRV_Graphics_Lvds_Port_Init(PinName *pin,
tvendov	0:6435b67ad23c	366	uint32_t pin_count) {
tvendov	0:6435b67ad23c	367	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	368	uint32_t count;
tvendov	0:6435b67ad23c	369
tvendov	0:6435b67ad23c	370	for (count = 0; count < pin_count; count++) {
tvendov	0:6435b67ad23c	371	pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
tvendov	0:6435b67ad23c	372	pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
tvendov	0:6435b67ad23c	373	}
tvendov	0:6435b67ad23c	374	return drv_error;
tvendov	0:6435b67ad23c	375	} /* End of function DRV_Graphics_Lvds_Port_Init() */
tvendov	0:6435b67ad23c	376
tvendov	0:6435b67ad23c	377	/************************************************************************//
tvendov	0:6435b67ad23c	378	* @brief Digital video inpout port initialization processing
tvendov	0:6435b67ad23c	379	* @param[in] pin : Pin assign for digital video input port
tvendov	0:6435b67ad23c	380	* @param[in] pin_count : Total number of pin assign
tvendov	0:6435b67ad23c	381	* @retval Error code
tvendov	0:6435b67ad23c	382	******************************************************************************/
tvendov	0:6435b67ad23c	383	drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init(PinName *pin,
tvendov	0:6435b67ad23c	384	uint32_t pin_count) {
tvendov	0:6435b67ad23c	385	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	386	uint32_t count;
tvendov	0:6435b67ad23c	387
tvendov	0:6435b67ad23c	388	for (count = 0; count < pin_count; count++) {
tvendov	0:6435b67ad23c	389	pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
tvendov	0:6435b67ad23c	390	pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
tvendov	0:6435b67ad23c	391	}
tvendov	0:6435b67ad23c	392	return drv_error;
tvendov	0:6435b67ad23c	393	} /* End of function DRV_Graphics_Dvinput_Port_Init() */
tvendov	0:6435b67ad23c	394
tvendov	0:6435b67ad23c	395	/************************************************************************//
tvendov	0:6435b67ad23c	396	* @brief Graphics initialization processing
tvendov	0:6435b67ad23c	397	* @param[in] drv_lcd_config : LCD configuration
tvendov	0:6435b67ad23c	398	* @retval Error code
tvendov	0:6435b67ad23c	399	******************************************************************************/
tvendov	0:6435b67ad23c	400	drv_graphics_error_t DRV_Graphics_Init(drv_lcd_config_t * drv_lcd_config) {
tvendov	0:6435b67ad23c	401	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	402	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	403	vdc5_error_t error;
tvendov	0:6435b67ad23c	404	vdc5_init_t init;
tvendov	0:6435b67ad23c	405	vdc5_lvds_t vdc5_lvds;
tvendov	0:6435b67ad23c	406	pll_parameter_t pll_parameter;
tvendov	0:6435b67ad23c	407	double InputClock = DEFAULT_INPUT_CLOCK;
tvendov	0:6435b67ad23c	408	double OutputClock = DEFAULT_OUTPUT_CLOCK;
tvendov	0:6435b67ad23c	409	uint32_t LvdsUsed = LVDS_IF_USE;
tvendov	0:6435b67ad23c	410
tvendov	0:6435b67ad23c	411	if (drv_lcd_config != NULL) {
tvendov	0:6435b67ad23c	412	InputClock = drv_lcd_config->intputClock;
tvendov	0:6435b67ad23c	413	OutputClock = drv_lcd_config->outputClock;
tvendov	0:6435b67ad23c	414	LvdsUsed =
tvendov	0:6435b67ad23c	415	(drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS) ?
tvendov	0:6435b67ad23c	416	LVDS_IF_USE : LVDS_IF_NOT_USE;
tvendov	0:6435b67ad23c	417	}
tvendov	0:6435b67ad23c	418
tvendov	0:6435b67ad23c	419	/* Initialization parameter */
tvendov	0:6435b67ad23c	420	if (LvdsUsed) {
tvendov	0:6435b67ad23c	421	/* LVDS PLL Setting Calculation */
tvendov	0:6435b67ad23c	422	init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS_DIV7; /* Panel clock select */
tvendov	0:6435b67ad23c	423	init.panel_dcdr = VDC5_PANEL_CLKDIV_1_2; /* Panel clock frequency division ratio */
tvendov	0:6435b67ad23c	424	lvds_pll_calc(InputClock, OutputClock, LvdsUsed, &pll_parameter);
tvendov	0:6435b67ad23c	425
tvendov	0:6435b67ad23c	426	vdc5_lvds.lvds_in_clk_sel = VDC5_LVDS_INCLK_SEL_PERI; /* P1 */
tvendov	0:6435b67ad23c	427	vdc5_lvds.lvds_idiv_set = (vdc5_lvds_ndiv_t) pll_parameter.nidiv;
tvendov	0:6435b67ad23c	428	vdc5_lvds.lvdspll_tst = 16u;
tvendov	0:6435b67ad23c	429	vdc5_lvds.lvds_odiv_set = (vdc5_lvds_ndiv_t) pll_parameter.nodiv;
tvendov	0:6435b67ad23c	430	vdc5_lvds.lvdspll_tst = 16u;
tvendov	0:6435b67ad23c	431	vdc5_lvds.lvds_vdc_sel = ch;
tvendov	0:6435b67ad23c	432	vdc5_lvds.lvdspll_fd = pll_parameter.nfd;
tvendov	0:6435b67ad23c	433	vdc5_lvds.lvdspll_rd = pll_parameter.nrd;
tvendov	0:6435b67ad23c	434	vdc5_lvds.lvdspll_od = (vdc5_lvds_pll_nod_t) pll_parameter.nod;
tvendov	0:6435b67ad23c	435	init.lvds = &vdc5_lvds; /* LVDS parameter */
tvendov	0:6435b67ad23c	436	} else {
tvendov	0:6435b67ad23c	437	init.panel_icksel = VDC5_PANEL_ICKSEL_PERI; /* Panel clock select */
tvendov	0:6435b67ad23c	438	init.panel_dcdr = VDC5_PANEL_CLKDIV_1_7; /* Panel clock frequency division ratio */
tvendov	0:6435b67ad23c	439	init.lvds = NULL;
tvendov	0:6435b67ad23c	440	}
tvendov	0:6435b67ad23c	441
tvendov	0:6435b67ad23c	442	/* Initialize (Set module clock to VDC5) */
tvendov	0:6435b67ad23c	443	error = R_VDC5_Initialize(ch, &init, &init_func, (uint32_t) ch);
tvendov	0:6435b67ad23c	444	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	445	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	446	}
tvendov	0:6435b67ad23c	447
tvendov	0:6435b67ad23c	448	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	449	vdc5_sync_ctrl_t sync_ctrl;
tvendov	0:6435b67ad23c	450
tvendov	0:6435b67ad23c	451	/* Sync signal control */
tvendov	0:6435b67ad23c	452	sync_ctrl.res_vs_sel = VDC5_ON; /* Vsync signal output select (free-running Vsync on/off control) */
tvendov	0:6435b67ad23c	453	/* Sync signal output and full-screen enable signal select */
tvendov	0:6435b67ad23c	454	sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
tvendov	0:6435b67ad23c	455	sync_ctrl.res_fv = drv_lcd_config->v_toatal_period - 1; /* Free-running Vsync period setting */
tvendov	0:6435b67ad23c	456	sync_ctrl.res_fh = drv_lcd_config->h_toatal_period - 1; /* Hsync period setting */
tvendov	0:6435b67ad23c	457	sync_ctrl.res_vsdly = (uint16_t) 0u; /* Vsync signal delay control */
tvendov	0:6435b67ad23c	458	/* Full-screen enable control */
tvendov	0:6435b67ad23c	459	sync_ctrl.res_f.vs = (drv_lcd_config->v_back_porch);
tvendov	0:6435b67ad23c	460	sync_ctrl.res_f.vw = (drv_lcd_config->v_disp_widht);
tvendov	0:6435b67ad23c	461	sync_ctrl.res_f.hs = (drv_lcd_config->h_back_porch);
tvendov	0:6435b67ad23c	462	sync_ctrl.res_f.hw = (drv_lcd_config->h_disp_widht);
tvendov	0:6435b67ad23c	463	sync_ctrl.vsync_cpmpe = NULL; /* Vsync signal compensation */
tvendov	0:6435b67ad23c	464	/* Sync control */
tvendov	0:6435b67ad23c	465	error = R_VDC5_SyncControl(ch, &sync_ctrl);
tvendov	0:6435b67ad23c	466	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	467	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	468	}
tvendov	0:6435b67ad23c	469	}
tvendov	0:6435b67ad23c	470
tvendov	0:6435b67ad23c	471	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	472	vdc5_output_t output;
tvendov	0:6435b67ad23c	473	vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS;
tvendov	0:6435b67ad23c	474	vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE;
tvendov	0:6435b67ad23c	475	vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS;
tvendov	0:6435b67ad23c	476	vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE;
tvendov	0:6435b67ad23c	477	vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE;
tvendov	0:6435b67ad23c	478
tvendov	0:6435b67ad23c	479	/* Output parameter */
tvendov	0:6435b67ad23c	480	output.tcon_half = (drv_lcd_config->h_toatal_period - 1) / 2; /* TCON reference timing, 1/2fH timing */
tvendov	0:6435b67ad23c	481	output.tcon_offset = 0; /* TCON reference timing, offset Hsync signal timing */
tvendov	0:6435b67ad23c	482
tvendov	0:6435b67ad23c	483	/* LCD TCON timing setting */
tvendov	0:6435b67ad23c	484	if (drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON) {
tvendov	0:6435b67ad23c	485	lcd_tcon_timing_VS.tcon_hsvs = 0u;
tvendov	0:6435b67ad23c	486	lcd_tcon_timing_VS.tcon_hwvw = (drv_lcd_config->v_sync_width * 2u);
tvendov	0:6435b67ad23c	487	lcd_tcon_timing_VS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
tvendov	0:6435b67ad23c	488	lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
tvendov	0:6435b67ad23c	489	lcd_tcon_timing_VS.tcon_inv =
tvendov	0:6435b67ad23c	490	(vdc5_sig_pol_t) drv_lcd_config->v_sync_port_polarity;
tvendov	0:6435b67ad23c	491	lcd_tcon_timing_VS.tcon_pin =
tvendov	0:6435b67ad23c	492	(vdc5_lcd_tcon_pin_t) drv_lcd_config->v_sync_port;
tvendov	0:6435b67ad23c	493	lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
tvendov	0:6435b67ad23c	494	output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
tvendov	0:6435b67ad23c	495	} else {
tvendov	0:6435b67ad23c	496	output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL; /* STVA/VS: Vsync */
tvendov	0:6435b67ad23c	497	}
tvendov	0:6435b67ad23c	498
tvendov	0:6435b67ad23c	499	if (drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON) {
tvendov	0:6435b67ad23c	500	lcd_tcon_timing_HS.tcon_hsvs = 0u;
tvendov	0:6435b67ad23c	501	lcd_tcon_timing_HS.tcon_hwvw = drv_lcd_config->h_sync_width;
tvendov	0:6435b67ad23c	502	lcd_tcon_timing_HS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
tvendov	0:6435b67ad23c	503	lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
tvendov	0:6435b67ad23c	504	lcd_tcon_timing_HS.tcon_inv =
tvendov	0:6435b67ad23c	505	(vdc5_sig_pol_t) drv_lcd_config->h_sync_port_polarity;
tvendov	0:6435b67ad23c	506	lcd_tcon_timing_HS.tcon_pin =
tvendov	0:6435b67ad23c	507	(vdc5_lcd_tcon_pin_t) drv_lcd_config->h_sync_port;
tvendov	0:6435b67ad23c	508	lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
tvendov	0:6435b67ad23c	509	output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
tvendov	0:6435b67ad23c	510	} else {
tvendov	0:6435b67ad23c	511	output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Hsync */
tvendov	0:6435b67ad23c	512	}
tvendov	0:6435b67ad23c	513
tvendov	0:6435b67ad23c	514	if (drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON) {
tvendov	0:6435b67ad23c	515	lcd_tcon_timing_VE.tcon_hsvs = (drv_lcd_config->v_back_porch * 2u);
tvendov	0:6435b67ad23c	516	lcd_tcon_timing_VE.tcon_hwvw = (drv_lcd_config->v_disp_widht * 2u);
tvendov	0:6435b67ad23c	517	lcd_tcon_timing_VE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
tvendov	0:6435b67ad23c	518	lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
tvendov	0:6435b67ad23c	519	lcd_tcon_timing_VE.tcon_inv =
tvendov	0:6435b67ad23c	520	(vdc5_sig_pol_t) drv_lcd_config->de_port_polarity;
tvendov	0:6435b67ad23c	521	lcd_tcon_timing_VE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
tvendov	0:6435b67ad23c	522	lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
tvendov	0:6435b67ad23c	523	output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = &lcd_tcon_timing_VE; /* STVB/VE: Not used */
tvendov	0:6435b67ad23c	524
tvendov	0:6435b67ad23c	525	lcd_tcon_timing_HE.tcon_hsvs = drv_lcd_config->h_back_porch;
tvendov	0:6435b67ad23c	526	lcd_tcon_timing_HE.tcon_hwvw = drv_lcd_config->h_disp_widht;
tvendov	0:6435b67ad23c	527	lcd_tcon_timing_HE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
tvendov	0:6435b67ad23c	528	lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
tvendov	0:6435b67ad23c	529	lcd_tcon_timing_HE.tcon_inv =
tvendov	0:6435b67ad23c	530	(vdc5_sig_pol_t) drv_lcd_config->de_port_polarity;
tvendov	0:6435b67ad23c	531	lcd_tcon_timing_HE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
tvendov	0:6435b67ad23c	532	lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
tvendov	0:6435b67ad23c	533	output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */
tvendov	0:6435b67ad23c	534
tvendov	0:6435b67ad23c	535	lcd_tcon_timing_DE.tcon_hsvs = 0u;
tvendov	0:6435b67ad23c	536	lcd_tcon_timing_DE.tcon_hwvw = 0u;
tvendov	0:6435b67ad23c	537	lcd_tcon_timing_DE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
tvendov	0:6435b67ad23c	538	lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
tvendov	0:6435b67ad23c	539	lcd_tcon_timing_DE.tcon_inv =
tvendov	0:6435b67ad23c	540	(vdc5_sig_pol_t) drv_lcd_config->de_port_polarity;
tvendov	0:6435b67ad23c	541	lcd_tcon_timing_DE.tcon_pin =
tvendov	0:6435b67ad23c	542	(vdc5_lcd_tcon_pin_t) drv_lcd_config->de_port;
tvendov	0:6435b67ad23c	543	lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
tvendov	0:6435b67ad23c	544	output.outctrl[VDC5_LCD_TCONSIG_DE] = &lcd_tcon_timing_DE; /* DE */
tvendov	0:6435b67ad23c	545	} else {
tvendov	0:6435b67ad23c	546	output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
tvendov	0:6435b67ad23c	547	output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
tvendov	0:6435b67ad23c	548	output.outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE */
tvendov	0:6435b67ad23c	549	}
tvendov	0:6435b67ad23c	550
tvendov	0:6435b67ad23c	551	output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL;
tvendov	0:6435b67ad23c	552	output.outctrl[VDC5_LCD_TCONSIG_POLA] = NULL;
tvendov	0:6435b67ad23c	553	output.outctrl[VDC5_LCD_TCONSIG_POLB] = NULL;
tvendov	0:6435b67ad23c	554
tvendov	0:6435b67ad23c	555	output.outcnt_lcd_edge = (vdc5_edge_t) drv_lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
tvendov	0:6435b67ad23c	556	output.out_endian_on = VDC5_OFF; /* Bit endian change on/off control */
tvendov	0:6435b67ad23c	557	output.out_swap_on = VDC5_OFF; /* B/R signal swap on/off control */
tvendov	0:6435b67ad23c	558	output.out_format =
tvendov	0:6435b67ad23c	559	(vdc5_lcd_outformat_t) drv_lcd_config->lcd_outformat; /* Output format select */
tvendov	0:6435b67ad23c	560	output.out_frq_sel = VDC5_LCD_PARALLEL_CLKFRQ_1; /* Clock frequency control */
tvendov	0:6435b67ad23c	561	output.out_dir_sel = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
tvendov	0:6435b67ad23c	562	output.out_phase = VDC5_LCD_SERIAL_CLKPHASE_0; /* Clock phase adjustment */
tvendov	0:6435b67ad23c	563	output.bg_color = (uint32_t) 0x00000000u; /* Background color in 24-bit RGB color format */
tvendov	0:6435b67ad23c	564	/* Display output */
tvendov	0:6435b67ad23c	565	error = R_VDC5_DisplayOutput(ch, &output);
tvendov	0:6435b67ad23c	566	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	567	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	568	}
tvendov	0:6435b67ad23c	569	}
tvendov	0:6435b67ad23c	570	return drv_error;
tvendov	0:6435b67ad23c	571	} /* End of function DRV_Graphics_Init() */
tvendov	0:6435b67ad23c	572
tvendov	0:6435b67ad23c	573	/************************************************************************//
tvendov	0:6435b67ad23c	574	* @brief Video initialization processing
tvendov	0:6435b67ad23c	575	* @param[in] drv_video_ext_in_config : Video configuration
tvendov	0:6435b67ad23c	576	* @retval Error code
tvendov	0:6435b67ad23c	577	******************************************************************************/
tvendov	0:6435b67ad23c	578	drv_graphics_error_t DRV_Graphics_Video_init(
tvendov	0:6435b67ad23c	579	drv_video_input_sel_t drv_video_input_sel,
tvendov	0:6435b67ad23c	580	drv_video_ext_in_config_t * drv_video_ext_in_config) {
tvendov	0:6435b67ad23c	581	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	582	vdc5_error_t error;
tvendov	0:6435b67ad23c	583	vdc5_input_t input;
tvendov	0:6435b67ad23c	584	vdc5_ext_in_sig_t ext_in_sig;
tvendov	0:6435b67ad23c	585	vdc5_sync_delay_t sync_delay;
tvendov	0:6435b67ad23c	586
tvendov	0:6435b67ad23c	587	input.inp_sel = (vdc5_input_sel_t) drv_video_input_sel; /* Input select */
tvendov	0:6435b67ad23c	588	input.inp_fh50 = (uint16_t) VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
tvendov	0:6435b67ad23c	589	input.inp_fh25 = (uint16_t) VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
tvendov	0:6435b67ad23c	590
tvendov	0:6435b67ad23c	591	if (drv_video_input_sel == DRV_INPUT_SEL_VDEC) {
tvendov	0:6435b67ad23c	592	input.dly = NULL; /* Sync signal delay adjustment */
tvendov	0:6435b67ad23c	593	input.ext_sig = NULL; /* External input signal */
tvendov	0:6435b67ad23c	594	} else {
tvendov	0:6435b67ad23c	595	ext_in_sig.inp_format =
tvendov	0:6435b67ad23c	596	(vdc5_extin_format_t) drv_video_ext_in_config->inp_format;
tvendov	0:6435b67ad23c	597	ext_in_sig.inp_pxd_edge =
tvendov	0:6435b67ad23c	598	(vdc5_edge_t) drv_video_ext_in_config->inp_pxd_edge;
tvendov	0:6435b67ad23c	599	ext_in_sig.inp_vs_edge =
tvendov	0:6435b67ad23c	600	(vdc5_edge_t) drv_video_ext_in_config->inp_vs_edge;
tvendov	0:6435b67ad23c	601	ext_in_sig.inp_hs_edge =
tvendov	0:6435b67ad23c	602	(vdc5_edge_t) drv_video_ext_in_config->inp_hs_edge;
tvendov	0:6435b67ad23c	603	ext_in_sig.inp_endian_on =
tvendov	0:6435b67ad23c	604	(vdc5_onoff_t) drv_video_ext_in_config->inp_endian_on;
tvendov	0:6435b67ad23c	605	ext_in_sig.inp_swap_on =
tvendov	0:6435b67ad23c	606	(vdc5_onoff_t) drv_video_ext_in_config->inp_swap_on;
tvendov	0:6435b67ad23c	607	ext_in_sig.inp_vs_inv =
tvendov	0:6435b67ad23c	608	(vdc5_sig_pol_t) drv_video_ext_in_config->inp_vs_inv;
tvendov	0:6435b67ad23c	609	ext_in_sig.inp_hs_inv =
tvendov	0:6435b67ad23c	610	(vdc5_sig_pol_t) drv_video_ext_in_config->inp_hs_inv;
tvendov	0:6435b67ad23c	611	ext_in_sig.inp_h_edge_sel =
tvendov	0:6435b67ad23c	612	(vdc5_extin_ref_hsync_t) drv_video_ext_in_config->inp_hs_edge;
tvendov	0:6435b67ad23c	613	ext_in_sig.inp_f525_625 =
tvendov	0:6435b67ad23c	614	(vdc5_extin_input_line_t) drv_video_ext_in_config->inp_f525_625;
tvendov	0:6435b67ad23c	615	ext_in_sig.inp_h_pos =
tvendov	0:6435b67ad23c	616	(vdc5_extin_h_pos_t) drv_video_ext_in_config->inp_h_pos;
tvendov	0:6435b67ad23c	617
tvendov	0:6435b67ad23c	618	sync_delay.inp_vs_dly_l = 0u;
tvendov	0:6435b67ad23c	619	sync_delay.inp_vs_dly = 16u;
tvendov	0:6435b67ad23c	620	sync_delay.inp_hs_dly = 16u;
tvendov	0:6435b67ad23c	621	sync_delay.inp_fld_dly = 16u;
tvendov	0:6435b67ad23c	622
tvendov	0:6435b67ad23c	623	input.dly = &sync_delay; /* Sync signal delay adjustment */
tvendov	0:6435b67ad23c	624	input.ext_sig = &ext_in_sig; /* External input signal */
tvendov	0:6435b67ad23c	625	}
tvendov	0:6435b67ad23c	626	/* Video input 0ch */
tvendov	0:6435b67ad23c	627	error = R_VDC5_VideoInput(VDC5_CHANNEL_0, &input);
tvendov	0:6435b67ad23c	628	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	629	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	630	}
tvendov	0:6435b67ad23c	631
tvendov	0:6435b67ad23c	632	if (drv_video_input_sel == DRV_INPUT_SEL_VDEC) {
tvendov	0:6435b67ad23c	633	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	634	/* Video input 1ch */
tvendov	0:6435b67ad23c	635	error = R_VDC5_VideoInput(VDC5_CHANNEL_1, &input);
tvendov	0:6435b67ad23c	636	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	637	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	638	}
tvendov	0:6435b67ad23c	639	}
tvendov	0:6435b67ad23c	640	}
tvendov	0:6435b67ad23c	641	return drv_error;
tvendov	0:6435b67ad23c	642	} /* End of function DRV_Video_Init() */
tvendov	0:6435b67ad23c	643
tvendov	0:6435b67ad23c	644	/************************************************************************//
tvendov	0:6435b67ad23c	645	* @brief Start the graphics surface read process
tvendov	0:6435b67ad23c	646	* @param[in] layer_id : Graphics layer ID
tvendov	0:6435b67ad23c	647	* @retval drv_graphics_error_t
tvendov	0:6435b67ad23c	648	******************************************************************************/
tvendov	0:6435b67ad23c	649	drv_graphics_error_t DRV_Graphics_Start(drv_graphics_layer_t layer_id) {
tvendov	0:6435b67ad23c	650	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	651	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	652	vdc5_error_t error;
tvendov	0:6435b67ad23c	653	vdc5_start_t start;
tvendov	0:6435b67ad23c	654	vdc5_gr_disp_sel_t gr_disp_sel;
tvendov	0:6435b67ad23c	655	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	656
tvendov	0:6435b67ad23c	657	switch (layer_id) {
tvendov	0:6435b67ad23c	658	case DRV_GRAPHICS_LAYER_0:
tvendov	0:6435b67ad23c	659	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
tvendov	0:6435b67ad23c	660	gr_disp_sel = VDC5_DISPSEL_CURRENT;
tvendov	0:6435b67ad23c	661	break;
tvendov	0:6435b67ad23c	662	case DRV_GRAPHICS_LAYER_1:
tvendov	0:6435b67ad23c	663	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
tvendov	0:6435b67ad23c	664	gr_disp_sel = VDC5_DISPSEL_BLEND;
tvendov	0:6435b67ad23c	665	break;
tvendov	0:6435b67ad23c	666	case DRV_GRAPHICS_LAYER_2:
tvendov	0:6435b67ad23c	667	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
tvendov	0:6435b67ad23c	668	gr_disp_sel = VDC5_DISPSEL_BLEND;
tvendov	0:6435b67ad23c	669	break;
tvendov	0:6435b67ad23c	670	case DRV_GRAPHICS_LAYER_3:
tvendov	0:6435b67ad23c	671	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
tvendov	0:6435b67ad23c	672	gr_disp_sel = VDC5_DISPSEL_BLEND;
tvendov	0:6435b67ad23c	673	break;
tvendov	0:6435b67ad23c	674	default:
tvendov	0:6435b67ad23c	675	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	676	break;
tvendov	0:6435b67ad23c	677	}
tvendov	0:6435b67ad23c	678
tvendov	0:6435b67ad23c	679	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	680	/* Start process */
tvendov	0:6435b67ad23c	681	start.gr_disp_sel = &gr_disp_sel;
tvendov	0:6435b67ad23c	682	error = R_VDC5_StartProcess(ch, vdc5_layer_id, &start);
tvendov	0:6435b67ad23c	683	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	684	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	685	}
tvendov	0:6435b67ad23c	686	}
tvendov	0:6435b67ad23c	687	return drv_error;
tvendov	0:6435b67ad23c	688	} /* End of function DRV_Graphics_Start() */
tvendov	0:6435b67ad23c	689
tvendov	0:6435b67ad23c	690	/************************************************************************//
tvendov	0:6435b67ad23c	691	* @brief Stop the graphics surface read process
tvendov	0:6435b67ad23c	692	* @param[in] layer_id : Graphics layer ID
tvendov	0:6435b67ad23c	693	* @retval Error code
tvendov	0:6435b67ad23c	694	******************************************************************************/
tvendov	0:6435b67ad23c	695	drv_graphics_error_t DRV_Graphics_Stop(drv_graphics_layer_t layer_id) {
tvendov	0:6435b67ad23c	696	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	697	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	698	vdc5_error_t error;
tvendov	0:6435b67ad23c	699	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	700
tvendov	0:6435b67ad23c	701	switch (layer_id) {
tvendov	0:6435b67ad23c	702	case DRV_GRAPHICS_LAYER_0:
tvendov	0:6435b67ad23c	703	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
tvendov	0:6435b67ad23c	704	break;
tvendov	0:6435b67ad23c	705	case DRV_GRAPHICS_LAYER_1:
tvendov	0:6435b67ad23c	706	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
tvendov	0:6435b67ad23c	707	break;
tvendov	0:6435b67ad23c	708	case DRV_GRAPHICS_LAYER_2:
tvendov	0:6435b67ad23c	709	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
tvendov	0:6435b67ad23c	710	break;
tvendov	0:6435b67ad23c	711	case DRV_GRAPHICS_LAYER_3:
tvendov	0:6435b67ad23c	712	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
tvendov	0:6435b67ad23c	713	break;
tvendov	0:6435b67ad23c	714	default:
tvendov	0:6435b67ad23c	715	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	716	break;
tvendov	0:6435b67ad23c	717	}
tvendov	0:6435b67ad23c	718
tvendov	0:6435b67ad23c	719	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	720	/* Stop process */
tvendov	0:6435b67ad23c	721	error = R_VDC5_StopProcess(ch, vdc5_layer_id);
tvendov	0:6435b67ad23c	722	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	723	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	724	}
tvendov	0:6435b67ad23c	725	}
tvendov	0:6435b67ad23c	726	return drv_error;
tvendov	0:6435b67ad23c	727	} /* End of function DRV_Graphics_Stop() */
tvendov	0:6435b67ad23c	728
tvendov	0:6435b67ad23c	729	/************************************************************************//
tvendov	0:6435b67ad23c	730	* @brief Start the video surface write process
tvendov	0:6435b67ad23c	731	* @param[in] video_input_ch : Video input channel
tvendov	0:6435b67ad23c	732	* @retval Error code
tvendov	0:6435b67ad23c	733	******************************************************************************/
tvendov	0:6435b67ad23c	734	drv_graphics_error_t DRV_Video_Start(drv_video_input_channel_t video_input_ch) {
tvendov	0:6435b67ad23c	735	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	736	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	737	vdc5_error_t error;
tvendov	0:6435b67ad23c	738	vdc5_start_t start;
tvendov	0:6435b67ad23c	739	vdc5_gr_disp_sel_t gr_disp_sel;
tvendov	0:6435b67ad23c	740	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	741
tvendov	0:6435b67ad23c	742	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
tvendov	0:6435b67ad23c	743	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
tvendov	0:6435b67ad23c	744	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
tvendov	0:6435b67ad23c	745	vdc5_layer_id = VDC5_LAYER_ID_1_WR;
tvendov	0:6435b67ad23c	746	} else {
tvendov	0:6435b67ad23c	747	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	748	}
tvendov	0:6435b67ad23c	749
tvendov	0:6435b67ad23c	750	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	751	/* Start process */
tvendov	0:6435b67ad23c	752	gr_disp_sel = VDC5_DISPSEL_CURRENT; /* CURRENT fixed for weave input mode */
tvendov	0:6435b67ad23c	753	start.gr_disp_sel = &gr_disp_sel;
tvendov	0:6435b67ad23c	754	error = R_VDC5_StartProcess(ch, vdc5_layer_id, &start);
tvendov	0:6435b67ad23c	755	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	756	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	757	}
tvendov	0:6435b67ad23c	758	}
tvendov	0:6435b67ad23c	759	return drv_error;
tvendov	0:6435b67ad23c	760	} /* End of function DRV_Video_Start() */
tvendov	0:6435b67ad23c	761
tvendov	0:6435b67ad23c	762	/************************************************************************//
tvendov	0:6435b67ad23c	763	* @brief Stop the video surface write process
tvendov	0:6435b67ad23c	764	* @param[in] video_input_ch : Video input channel
tvendov	0:6435b67ad23c	765	* @retval Error code
tvendov	0:6435b67ad23c	766	******************************************************************************/
tvendov	0:6435b67ad23c	767	drv_graphics_error_t DRV_Video_Stop(drv_video_input_channel_t video_input_ch) {
tvendov	0:6435b67ad23c	768	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	769	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	770	vdc5_error_t error;
tvendov	0:6435b67ad23c	771	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	772
tvendov	0:6435b67ad23c	773	switch (video_input_ch) {
tvendov	0:6435b67ad23c	774	case DRV_VIDEO_INPUT_CHANNEL_0:
tvendov	0:6435b67ad23c	775	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
tvendov	0:6435b67ad23c	776	break;
tvendov	0:6435b67ad23c	777	case DRV_VIDEO_INPUT_CHANNEL_1:
tvendov	0:6435b67ad23c	778	vdc5_layer_id = VDC5_LAYER_ID_1_WR;
tvendov	0:6435b67ad23c	779	break;
tvendov	0:6435b67ad23c	780	default:
tvendov	0:6435b67ad23c	781	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	782	break;
tvendov	0:6435b67ad23c	783	}
tvendov	0:6435b67ad23c	784
tvendov	0:6435b67ad23c	785	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	786	/* Stop process */
tvendov	0:6435b67ad23c	787	error = R_VDC5_StopProcess(ch, vdc5_layer_id);
tvendov	0:6435b67ad23c	788	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	789	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	790	}
tvendov	0:6435b67ad23c	791	}
tvendov	0:6435b67ad23c	792	return drv_error;
tvendov	0:6435b67ad23c	793	} /* End of function DRV_Video_Stop() */
tvendov	0:6435b67ad23c	794
tvendov	0:6435b67ad23c	795	/************************************************************************//
tvendov	0:6435b67ad23c	796	* @brief Graphics surface read process setting
tvendov	0:6435b67ad23c	797	*
tvendov	0:6435b67ad23c	798	* Description:<br>
tvendov	0:6435b67ad23c	799	* This function supports the following 4 image format.
tvendov	0:6435b67ad23c	800	* YCbCr422, RGB565, RGB888, ARGB8888
tvendov	0:6435b67ad23c	801	* @param[in] layer_id : Graphics layer ID
tvendov	0:6435b67ad23c	802	* @param[in] framebuff : Base address of the frame buffer
tvendov	0:6435b67ad23c	803	* @param[in] fb_stride : Line offset address of the frame buffer
tvendov	0:6435b67ad23c	804	* @param[in] gr_format : Format of the frame buffer read signal
tvendov	0:6435b67ad23c	805	* @param[in] gr_rect : Graphics display area
tvendov	0:6435b67ad23c	806	* @retval Error code
tvendov	0:6435b67ad23c	807	******************************************************************************/
tvendov	0:6435b67ad23c	808	drv_graphics_error_t DRV_Graphics_Read_Setting(drv_graphics_layer_t layer_id,
tvendov	0:6435b67ad23c	809	void * framebuff, uint32_t fb_stride, drv_graphics_format_t gr_format,
tvendov	0:6435b67ad23c	810	drv_wr_rd_swa_t wr_rd_swa, drv_rect_t * gr_rect) {
tvendov	0:6435b67ad23c	811	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	812	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	813	vdc5_error_t error;
tvendov	0:6435b67ad23c	814	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	815	vdc5_gr_format_t vdc5_gr_format;
tvendov	0:6435b67ad23c	816	vdc5_read_t read;
tvendov	0:6435b67ad23c	817
tvendov	0:6435b67ad23c	818	switch (layer_id) {
tvendov	0:6435b67ad23c	819	case DRV_GRAPHICS_LAYER_0:
tvendov	0:6435b67ad23c	820	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
tvendov	0:6435b67ad23c	821	break;
tvendov	0:6435b67ad23c	822	case DRV_GRAPHICS_LAYER_1:
tvendov	0:6435b67ad23c	823	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
tvendov	0:6435b67ad23c	824	break;
tvendov	0:6435b67ad23c	825	case DRV_GRAPHICS_LAYER_2:
tvendov	0:6435b67ad23c	826	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
tvendov	0:6435b67ad23c	827	break;
tvendov	0:6435b67ad23c	828	case DRV_GRAPHICS_LAYER_3:
tvendov	0:6435b67ad23c	829	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
tvendov	0:6435b67ad23c	830	break;
tvendov	0:6435b67ad23c	831	default:
tvendov	0:6435b67ad23c	832	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	833	break;
tvendov	0:6435b67ad23c	834	}
tvendov	0:6435b67ad23c	835
tvendov	0:6435b67ad23c	836	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	837	switch (gr_format) {
tvendov	0:6435b67ad23c	838	case DRV_GRAPHICS_FORMAT_YCBCR422:
tvendov	0:6435b67ad23c	839	vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
tvendov	0:6435b67ad23c	840	break;
tvendov	0:6435b67ad23c	841	case DRV_GRAPHICS_FORMAT_RGB565:
tvendov	0:6435b67ad23c	842	vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
tvendov	0:6435b67ad23c	843	break;
tvendov	0:6435b67ad23c	844	case DRV_GRAPHICS_FORMAT_RGB888:
tvendov	0:6435b67ad23c	845	vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
tvendov	0:6435b67ad23c	846	break;
tvendov	0:6435b67ad23c	847	case DRV_GRAPHICS_FORMAT_ARGB8888:
tvendov	0:6435b67ad23c	848	vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
tvendov	0:6435b67ad23c	849	break;
tvendov	0:6435b67ad23c	850	case DRV_GRAPHICS_FORMAT_ARGB4444:
tvendov	0:6435b67ad23c	851	vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444;
tvendov	0:6435b67ad23c	852	break;
tvendov	0:6435b67ad23c	853	default:
tvendov	0:6435b67ad23c	854	drv_error = DRV_GRAPHICS_FORMAT_ERR;
tvendov	0:6435b67ad23c	855	break;
tvendov	0:6435b67ad23c	856	}
tvendov	0:6435b67ad23c	857	}
tvendov	0:6435b67ad23c	858
tvendov	0:6435b67ad23c	859	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	860	/* Read data parameter */
tvendov	0:6435b67ad23c	861	read.gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC; /* Line offset address direction of the frame buffer */
tvendov	0:6435b67ad23c	862	read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM; /* Selects a frame buffer address setting signal */
tvendov	0:6435b67ad23c	863	read.gr_imr_flm_inv = VDC5_OFF; /* Frame buffer number for distortion correction */
tvendov	0:6435b67ad23c	864	read.gr_bst_md = VDC5_BST_MD_32BYTE; /* Frame buffer burst transfer mode */
tvendov	0:6435b67ad23c	865	read.gr_base = framebuff; /* Frame buffer base address */
tvendov	0:6435b67ad23c	866	read.gr_ln_off = fb_stride; /* Frame buffer line offset address */
tvendov	0:6435b67ad23c	867
tvendov	0:6435b67ad23c	868	read.width_read_fb = NULL; /* Width of the image read from frame buffer */
tvendov	0:6435b67ad23c	869
tvendov	0:6435b67ad23c	870	read.adj_sel = VDC5_OFF; /* Measures to decrease the influence
tvendov	0:6435b67ad23c	871	by folding pixels/lines (on/off) */
tvendov	0:6435b67ad23c	872	read.gr_format = vdc5_gr_format; /* Format of the frame buffer read signal */
tvendov	0:6435b67ad23c	873	read.gr_ycc_swap = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
tvendov	0:6435b67ad23c	874	in the YCbCr422 format */
tvendov	0:6435b67ad23c	875	read.gr_rdswa = (vdc5_wr_rd_swa_t) wr_rd_swa; /* Frame buffer swap setting */
tvendov	0:6435b67ad23c	876	/* Display area */
tvendov	0:6435b67ad23c	877	read.gr_grc.vs = gr_rect->vs;
tvendov	0:6435b67ad23c	878	read.gr_grc.vw = gr_rect->vw;
tvendov	0:6435b67ad23c	879	read.gr_grc.hs = gr_rect->hs;
tvendov	0:6435b67ad23c	880	read.gr_grc.hw = gr_rect->hw;
tvendov	0:6435b67ad23c	881
tvendov	0:6435b67ad23c	882	/* Read data control */
tvendov	0:6435b67ad23c	883	error = R_VDC5_ReadDataControl(ch, vdc5_layer_id, &read);
tvendov	0:6435b67ad23c	884	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	885	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	886	}
tvendov	0:6435b67ad23c	887	}
tvendov	0:6435b67ad23c	888	return drv_error;
tvendov	0:6435b67ad23c	889	} /* End of function DRV_Graphics_Read_Setting() */
tvendov	0:6435b67ad23c	890
tvendov	0:6435b67ad23c	891	/************************************************************************//
tvendov	0:6435b67ad23c	892	* @brief Graphics surface read buffer change process
tvendov	0:6435b67ad23c	893	* @param[in] layer_id : Graphics layer ID
tvendov	0:6435b67ad23c	894	* @param[in] framebuff : Base address of the frame buffer
tvendov	0:6435b67ad23c	895	* @retval Error code
tvendov	0:6435b67ad23c	896	******************************************************************************/
tvendov	0:6435b67ad23c	897	drv_graphics_error_t DRV_Graphics_Read_Change(drv_graphics_layer_t layer_id,
tvendov	0:6435b67ad23c	898	void * framebuff) {
tvendov	0:6435b67ad23c	899	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	900	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	901	vdc5_error_t error;
tvendov	0:6435b67ad23c	902	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	903	vdc5_read_chg_t read_chg;
tvendov	0:6435b67ad23c	904
tvendov	0:6435b67ad23c	905	switch (layer_id) {
tvendov	0:6435b67ad23c	906	case DRV_GRAPHICS_LAYER_0:
tvendov	0:6435b67ad23c	907	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
tvendov	0:6435b67ad23c	908	break;
tvendov	0:6435b67ad23c	909	case DRV_GRAPHICS_LAYER_1:
tvendov	0:6435b67ad23c	910	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
tvendov	0:6435b67ad23c	911	break;
tvendov	0:6435b67ad23c	912	case DRV_GRAPHICS_LAYER_2:
tvendov	0:6435b67ad23c	913	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
tvendov	0:6435b67ad23c	914	break;
tvendov	0:6435b67ad23c	915	case DRV_GRAPHICS_LAYER_3:
tvendov	0:6435b67ad23c	916	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
tvendov	0:6435b67ad23c	917	break;
tvendov	0:6435b67ad23c	918	default:
tvendov	0:6435b67ad23c	919	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	920	break;
tvendov	0:6435b67ad23c	921	}
tvendov	0:6435b67ad23c	922
tvendov	0:6435b67ad23c	923	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	924	/* Read data parameter */
tvendov	0:6435b67ad23c	925	read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
tvendov	0:6435b67ad23c	926	read_chg.gr_grc = NULL; /* Display area */
tvendov	0:6435b67ad23c	927	read_chg.gr_disp_sel = NULL; /* Graphics display mode */
tvendov	0:6435b67ad23c	928	read_chg.gr_base = framebuff; /* Frame buffer base address */
tvendov	0:6435b67ad23c	929
tvendov	0:6435b67ad23c	930	/* Change read process */
tvendov	0:6435b67ad23c	931	error = R_VDC5_ChangeReadProcess(ch, vdc5_layer_id, &read_chg);
tvendov	0:6435b67ad23c	932	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	933	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	934	}
tvendov	0:6435b67ad23c	935	}
tvendov	0:6435b67ad23c	936	return drv_error;
tvendov	0:6435b67ad23c	937	} /* End of function DRV_Graphics_Read_Change() */
tvendov	0:6435b67ad23c	938
tvendov	0:6435b67ad23c	939	//touch_pos_t dot_border
tvendov	0:6435b67ad23c	940	void Slide(uint32_t fb_stride, vdc5_chg_read_chg_t * param, slide_dir_t* slide_dir) {
tvendov	0:6435b67ad23c	941
tvendov	0:6435b67ad23c	942	#define SLIDE_STEP 12
tvendov	0:6435b67ad23c	943
tvendov	0:6435b67ad23c	944	static int32_t v_line = 0; /* Vertical direction offset variable */
tvendov	0:6435b67ad23c	945	static int32_t h_pixel = 0; /* Horizontal direction offset variable */
tvendov	0:6435b67ad23c	946	int32_t stride_pix = fb_stride / LCD_CH0_DISP_HW; /* Size(px) of image buffer stride */
tvendov	0:6435b67ad23c	947	uint16_t pos_buff = (uint16_t ) param->gr_base; /* Image buffer position */
tvendov	0:6435b67ad23c	948
tvendov	0:6435b67ad23c	949	/* Wait Vsync */
tvendov	0:6435b67ad23c	950
tvendov	0:6435b67ad23c	951	switch (*slide_dir) {
tvendov	0:6435b67ad23c	952	case SLIDE_OUT_RIGHT:
tvendov	0:6435b67ad23c	953	h_pixel += SLIDE_STEP; /* Increment offset value : 0u -> 800u by 16u step */
tvendov	0:6435b67ad23c	954	if (h_pixel >= LCD_CH0_DISP_HW) /* 800u */
tvendov	0:6435b67ad23c	955	{
tvendov	0:6435b67ad23c	956	h_pixel = LCD_CH0_DISP_HW;
tvendov	0:6435b67ad23c	957	*slide_dir = SLIDE_NONE;
tvendov	0:6435b67ad23c	958	}
tvendov	0:6435b67ad23c	959	param->gr_grc->hs = (uint16_t) ((int32_t) LCD_CH0_DISP_HS + h_pixel);
tvendov	0:6435b67ad23c	960	param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
tvendov	0:6435b67ad23c	961	break;
tvendov	0:6435b67ad23c	962	case SLIDE_IN_RIGHT:
tvendov	0:6435b67ad23c	963	h_pixel -= SLIDE_STEP; /* Decrement offset value : 800u -> 0u by 16u step */
tvendov	0:6435b67ad23c	964	if (h_pixel <= 0) /* 0u */
tvendov	0:6435b67ad23c	965	{
tvendov	0:6435b67ad23c	966	h_pixel = 0;
tvendov	0:6435b67ad23c	967	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	968	}
tvendov	0:6435b67ad23c	969	param->gr_grc->hs = (uint16_t) ((int32_t) LCD_CH0_DISP_HS + h_pixel);
tvendov	0:6435b67ad23c	970	param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
tvendov	0:6435b67ad23c	971	break;
tvendov	0:6435b67ad23c	972
tvendov	0:6435b67ad23c	973	case SLIDE_OUT_BOTTOM:
tvendov	0:6435b67ad23c	974	v_line += SLIDE_STEP; /* Increment offset value : 0u -> 600u by 16u step */
tvendov	0:6435b67ad23c	975	if (v_line >= LCD_CH0_DISP_VW) /* 600u */
tvendov	0:6435b67ad23c	976	{
tvendov	0:6435b67ad23c	977	v_line = LCD_CH0_DISP_VW;
tvendov	0:6435b67ad23c	978	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	979	}
tvendov	0:6435b67ad23c	980	param->gr_grc->vs = (uint16_t) ((int32_t) LCD_CH0_DISP_VS + v_line);
tvendov	0:6435b67ad23c	981	param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
tvendov	0:6435b67ad23c	982	break;
tvendov	0:6435b67ad23c	983	case SLIDE_IN_BOTTOM:
tvendov	0:6435b67ad23c	984	v_line -= SLIDE_STEP; /* Decrement offset value : 600u -> 0u by 16u step */
tvendov	0:6435b67ad23c	985	if (v_line <= 0) /* 0u */
tvendov	0:6435b67ad23c	986	{
tvendov	0:6435b67ad23c	987	v_line = 0;
tvendov	0:6435b67ad23c	988	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	989	}
tvendov	0:6435b67ad23c	990	param->gr_grc->vs = (uint16_t) ((int32_t) LCD_CH0_DISP_VS + v_line);
tvendov	0:6435b67ad23c	991	param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
tvendov	0:6435b67ad23c	992	break;
tvendov	0:6435b67ad23c	993
tvendov	0:6435b67ad23c	994	case SLIDE_OUT_LEFT:
tvendov	0:6435b67ad23c	995	h_pixel += SLIDE_STEP; /* Increment offset value : 0u -> 800u by 16u step */
tvendov	0:6435b67ad23c	996	if (h_pixel >= LCD_CH0_DISP_HW) /* 800u */
tvendov	0:6435b67ad23c	997	{
tvendov	0:6435b67ad23c	998	h_pixel = LCD_CH0_DISP_HW;
tvendov	0:6435b67ad23c	999	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	1000	}
tvendov	0:6435b67ad23c	1001	param->gr_base = &pos_buff[h_pixel];
tvendov	0:6435b67ad23c	1002	param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
tvendov	0:6435b67ad23c	1003	break;
tvendov	0:6435b67ad23c	1004	case SLIDE_IN_LEFT:
tvendov	0:6435b67ad23c	1005	h_pixel -= SLIDE_STEP; /* Decrement offset value : 800u -> 0u by 16u step */
tvendov	0:6435b67ad23c	1006	if (h_pixel <= 0) /* 0u */
tvendov	0:6435b67ad23c	1007	{
tvendov	0:6435b67ad23c	1008	h_pixel = 0;
tvendov	0:6435b67ad23c	1009	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	1010	}
tvendov	0:6435b67ad23c	1011	param->gr_base = &pos_buff[h_pixel];
tvendov	0:6435b67ad23c	1012	param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
tvendov	0:6435b67ad23c	1013	break;
tvendov	0:6435b67ad23c	1014
tvendov	0:6435b67ad23c	1015	case SLIDE_OUT_TOP:
tvendov	0:6435b67ad23c	1016	v_line += SLIDE_STEP; /* Increment offset value : 0u -> 800u by 16u step */
tvendov	0:6435b67ad23c	1017	if (v_line >= LCD_CH0_DISP_VW) /* 600u */
tvendov	0:6435b67ad23c	1018	{
tvendov	0:6435b67ad23c	1019	v_line = LCD_CH0_DISP_VW;
tvendov	0:6435b67ad23c	1020	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	1021	}
tvendov	0:6435b67ad23c	1022	param->gr_base = &pos_buff[v_line * stride_pix];
tvendov	0:6435b67ad23c	1023	param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
tvendov	0:6435b67ad23c	1024	break;
tvendov	0:6435b67ad23c	1025	case SLIDE_IN_TOP:
tvendov	0:6435b67ad23c	1026	v_line -= SLIDE_STEP; /* Decrement offset value : 800u -> 0u by 16u step */
tvendov	0:6435b67ad23c	1027	if (v_line <= 0) /* 0u */
tvendov	0:6435b67ad23c	1028	{
tvendov	0:6435b67ad23c	1029	v_line = 0;
tvendov	0:6435b67ad23c	1030	*slide_dir = SLIDE_NONE;;
tvendov	0:6435b67ad23c	1031	}
tvendov	0:6435b67ad23c	1032	param->gr_base = &pos_buff[v_line * stride_pix];
tvendov	0:6435b67ad23c	1033	param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
tvendov	0:6435b67ad23c	1034	break;
tvendov	0:6435b67ad23c	1035
tvendov	0:6435b67ad23c	1036	default:
tvendov	0:6435b67ad23c	1037	*slide_dir = SLIDE_NONE;
tvendov	0:6435b67ad23c	1038	h_pixel = 0;
tvendov	0:6435b67ad23c	1039	v_line = 0;
tvendov	0:6435b67ad23c	1040	break;
tvendov	0:6435b67ad23c	1041	}
tvendov	0:6435b67ad23c	1042	}
tvendov	0:6435b67ad23c	1043
tvendov	0:6435b67ad23c	1044	/************************************************************************//
tvendov	0:6435b67ad23c	1045	* @brief Graphics surface read buffer change process
tvendov	0:6435b67ad23c	1046	* @param[in] layer_id : Graphics layer ID
tvendov	0:6435b67ad23c	1047	* @param[in] framebuff : Base address of the frame buffer
tvendov	0:6435b67ad23c	1048	* @retval Error code
tvendov	0:6435b67ad23c	1049	******************************************************************************/
tvendov	0:6435b67ad23c	1050	drv_graphics_error_t DRV_Graphics_Read_Change_More(
tvendov	0:6435b67ad23c	1051	drv_graphics_layer_t layer_id, void * framebuff, uint32_t fb_stride, void * slide_dir) {
tvendov	0:6435b67ad23c	1052	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	1053	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	1054	vdc5_error_t error;
tvendov	0:6435b67ad23c	1055	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	1056	vdc5_chg_read_chg_t read_chg;
tvendov	0:6435b67ad23c	1057
tvendov	0:6435b67ad23c	1058	vdc5_period_rect_t grN_grc = { LCD_CH0_DISP_VS, LCD_CH0_DISP_VW,
tvendov	0:6435b67ad23c	1059	LCD_CH0_DISP_HS, LCD_CH0_DISP_HW };
tvendov	0:6435b67ad23c	1060
tvendov	0:6435b67ad23c	1061	switch (layer_id) {
tvendov	0:6435b67ad23c	1062	case DRV_GRAPHICS_LAYER_0:
tvendov	0:6435b67ad23c	1063	vdc5_layer_id = VDC5_LAYER_ID_0_RD;
tvendov	0:6435b67ad23c	1064	break;
tvendov	0:6435b67ad23c	1065	case DRV_GRAPHICS_LAYER_1:
tvendov	0:6435b67ad23c	1066	vdc5_layer_id = VDC5_LAYER_ID_1_RD;
tvendov	0:6435b67ad23c	1067	break;
tvendov	0:6435b67ad23c	1068	case DRV_GRAPHICS_LAYER_2:
tvendov	0:6435b67ad23c	1069	vdc5_layer_id = VDC5_LAYER_ID_2_RD;
tvendov	0:6435b67ad23c	1070	break;
tvendov	0:6435b67ad23c	1071	case DRV_GRAPHICS_LAYER_3:
tvendov	0:6435b67ad23c	1072	vdc5_layer_id = VDC5_LAYER_ID_3_RD;
tvendov	0:6435b67ad23c	1073	break;
tvendov	0:6435b67ad23c	1074	default:
tvendov	0:6435b67ad23c	1075	drv_error = DRV_GRAPHICS_LAYER_ERR;
tvendov	0:6435b67ad23c	1076	break;
tvendov	0:6435b67ad23c	1077	}
tvendov	0:6435b67ad23c	1078
tvendov	0:6435b67ad23c	1079	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	1080	/* Read data parameter */
tvendov	0:6435b67ad23c	1081
tvendov	0:6435b67ad23c	1082	read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
tvendov	0:6435b67ad23c	1083	read_chg.gr_grc = &grN_grc; /* Display area */
tvendov	0:6435b67ad23c	1084	read_chg.gr_disp_sel = NULL; /* Graphics display mode */
tvendov	0:6435b67ad23c	1085	read_chg.gr_base = framebuff;
tvendov	0:6435b67ad23c	1086
tvendov	0:6435b67ad23c	1087	Slide( fb_stride, &read_chg, (slide_dir_t*)slide_dir);
tvendov	0:6435b67ad23c	1088
tvendov	0:6435b67ad23c	1089	//read_chg.gr_base = framebuff; /* Frame buffer base address */
tvendov	0:6435b67ad23c	1090
tvendov	0:6435b67ad23c	1091	/* Change read process */
tvendov	0:6435b67ad23c	1092	error = R_VDC5_ChangeReadProcess(ch, vdc5_layer_id,
tvendov	0:6435b67ad23c	1093	(vdc5_read_chg_t*) &read_chg);
tvendov	0:6435b67ad23c	1094	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	1095	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	1096	}
tvendov	0:6435b67ad23c	1097	}
tvendov	0:6435b67ad23c	1098	return drv_error;
tvendov	0:6435b67ad23c	1099	} /* End of function DRV_Graphics_Read_Change_More() */
tvendov	0:6435b67ad23c	1100
tvendov	0:6435b67ad23c	1101	/************************************************************************//
tvendov	0:6435b67ad23c	1102	* @brief Video surface write process setting
tvendov	0:6435b67ad23c	1103	*
tvendov	0:6435b67ad23c	1104	* Description:<br>
tvendov	0:6435b67ad23c	1105	* This function set the video write process. Input form is weave
tvendov	0:6435b67ad23c	1106	* (progressive) mode fixed.
tvendov	0:6435b67ad23c	1107	* This function supports the following 3 image format.
tvendov	0:6435b67ad23c	1108	* YCbCr422, RGB565, RGB888
tvendov	0:6435b67ad23c	1109	* @param[in] video_input_ch : Video input channel
tvendov	0:6435b67ad23c	1110	* @param[in] col_sys : Analog video signal color system
tvendov	0:6435b67ad23c	1111	* @param[in] adc_vinsel : Video input pin
tvendov	0:6435b67ad23c	1112	* @param[in] framebuff : Base address of the frame buffer
tvendov	0:6435b67ad23c	1113	* @param[in] fb_stride [byte] : Line offset address of the frame buffer
tvendov	0:6435b67ad23c	1114	* @param[in] video_format : Frame buffer video-signal writing format
tvendov	0:6435b67ad23c	1115	* @param[in] wr_rd_swa : Frame buffer swap setting
tvendov	0:6435b67ad23c	1116	* @param[in] video_write_size_vw [px]: output height
tvendov	0:6435b67ad23c	1117	* @param[in] video_write_size_hw [px]: output width
tvendov	0:6435b67ad23c	1118	* @param[in] video_adc_vinsel : Input pin control
tvendov	0:6435b67ad23c	1119	* @retval Error code
tvendov	0:6435b67ad23c	1120	******************************************************************************/
tvendov	0:6435b67ad23c	1121	drv_graphics_error_t DRV_Video_Write_Setting(
tvendov	0:6435b67ad23c	1122	drv_video_input_channel_t video_input_ch,
tvendov	0:6435b67ad23c	1123	drv_graphics_video_col_sys_t col_sys, void * framebuff,
tvendov	0:6435b67ad23c	1124	uint32_t fb_stride, drv_video_format_t video_format,
tvendov	0:6435b67ad23c	1125	drv_wr_rd_swa_t wr_rd_swa, uint16_t video_write_buff_vw,
tvendov	0:6435b67ad23c	1126	uint16_t video_write_buff_hw, drv_video_adc_vinsel_t video_adc_vinsel) {
tvendov	0:6435b67ad23c	1127	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	1128	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	1129	vdc5_error_t error;
tvendov	0:6435b67ad23c	1130	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	1131	vdc5_write_t write;
tvendov	0:6435b67ad23c	1132	vdc5_scalingdown_rot_t * scldw_rot;
tvendov	0:6435b67ad23c	1133	vdc5_res_md_t res_md;
tvendov	0:6435b67ad23c	1134	drv_rect_t video_in_rect;
tvendov	0:6435b67ad23c	1135	uint8_t * framebuffer_t;
tvendov	0:6435b67ad23c	1136	uint8_t * framebuffer_b;
tvendov	0:6435b67ad23c	1137
tvendov	0:6435b67ad23c	1138	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
tvendov	0:6435b67ad23c	1139	GRAPHICS_VideoDecoderInit((vdec_adc_vinsel_t) video_adc_vinsel,
tvendov	0:6435b67ad23c	1140	VDEC_CHANNEL_0, (graphics_col_sys_t) col_sys);
tvendov	0:6435b67ad23c	1141	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
tvendov	0:6435b67ad23c	1142	GRAPHICS_VideoDecoderInit((vdec_adc_vinsel_t) video_adc_vinsel,
tvendov	0:6435b67ad23c	1143	VDEC_CHANNEL_1, (graphics_col_sys_t) col_sys);
tvendov	0:6435b67ad23c	1144	} else {
tvendov	0:6435b67ad23c	1145	drv_error = DRV_GRAPHICS_CHANNEL_ERR;
tvendov	0:6435b67ad23c	1146	}
tvendov	0:6435b67ad23c	1147
tvendov	0:6435b67ad23c	1148	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	1149	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
tvendov	0:6435b67ad23c	1150	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
tvendov	0:6435b67ad23c	1151	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
tvendov	0:6435b67ad23c	1152	vdc5_layer_id = VDC5_LAYER_ID_1_WR;
tvendov	0:6435b67ad23c	1153	} else {
tvendov	0:6435b67ad23c	1154	drv_error = DRV_GRAPHICS_CHANNEL_ERR;
tvendov	0:6435b67ad23c	1155	}
tvendov	0:6435b67ad23c	1156	}
tvendov	0:6435b67ad23c	1157
tvendov	0:6435b67ad23c	1158	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	1159	if (video_format == DRV_VIDEO_FORMAT_YCBCR422) {
tvendov	0:6435b67ad23c	1160	res_md = VDC5_RES_MD_YCBCR422;
tvendov	0:6435b67ad23c	1161	} else if (video_format == DRV_VIDEO_FORMAT_RGB888) {
tvendov	0:6435b67ad23c	1162	res_md = VDC5_RES_MD_RGB888;
tvendov	0:6435b67ad23c	1163	} else if (video_format == DRV_VIDEO_FORMAT_RGB565) {
tvendov	0:6435b67ad23c	1164	res_md = VDC5_RES_MD_RGB565;
tvendov	0:6435b67ad23c	1165	} else {
tvendov	0:6435b67ad23c	1166	drv_error = DRV_GRAPHICS_FORMAT_ERR;
tvendov	0:6435b67ad23c	1167	}
tvendov	0:6435b67ad23c	1168	}
tvendov	0:6435b67ad23c	1169
tvendov	0:6435b67ad23c	1170	if (col_sys == DRV_COL_SYS_NTSC_358 \|\| col_sys == DVV_COL_SYS_NTSC_443
tvendov	0:6435b67ad23c	1171	\|\| col_sys == DRV_COL_SYS_NTSC_443_60) {
tvendov	0:6435b67ad23c	1172	video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2;
tvendov	0:6435b67ad23c	1173	video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2;
tvendov	0:6435b67ad23c	1174	video_in_rect.vs = IMGCAP_SIZE_NTSC_VS;
tvendov	0:6435b67ad23c	1175	video_in_rect.vw = IMGCAP_SIZE_NTSC_VW;
tvendov	0:6435b67ad23c	1176	} else {
tvendov	0:6435b67ad23c	1177	video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2;
tvendov	0:6435b67ad23c	1178	video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2;
tvendov	0:6435b67ad23c	1179	video_in_rect.vs = IMGCAP_SIZE_PAL_VS;
tvendov	0:6435b67ad23c	1180	video_in_rect.vw = IMGCAP_SIZE_PAL_VW;
tvendov	0:6435b67ad23c	1181	}
tvendov	0:6435b67ad23c	1182
tvendov	0:6435b67ad23c	1183	#ifdef NO_SCALE_UP
tvendov	0:6435b67ad23c	1184	if( drv_error == DRV_GRAPHICS_OK ) {
tvendov	0:6435b67ad23c	1185	if( col_sys == DRV_COL_SYS_NTSC_358 \|\| col_sys == DVV_COL_SYS_NTSC_443 \|\| col_sys == DRV_COL_SYS_NTSC_443_60 ) {
tvendov	0:6435b67ad23c	1186	if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
tvendov	0:6435b67ad23c	1187	drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR;
tvendov	0:6435b67ad23c	1188	}
tvendov	0:6435b67ad23c	1189	} else {
tvendov	0:6435b67ad23c	1190	if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
tvendov	0:6435b67ad23c	1191	drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR;
tvendov	0:6435b67ad23c	1192	}
tvendov	0:6435b67ad23c	1193	}
tvendov	0:6435b67ad23c	1194	}
tvendov	0:6435b67ad23c	1195
tvendov	0:6435b67ad23c	1196	if( drv_error == DRV_GRAPHICS_OK ) {
tvendov	0:6435b67ad23c	1197	if( video_write_buff_hw > 800 ) {
tvendov	0:6435b67ad23c	1198	drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
tvendov	0:6435b67ad23c	1199	}
tvendov	0:6435b67ad23c	1200	}
tvendov	0:6435b67ad23c	1201	#endif
tvendov	0:6435b67ad23c	1202
tvendov	0:6435b67ad23c	1203	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	1204	/* Scaling-down and rotation parameter */
tvendov	0:6435b67ad23c	1205	scldw_rot = &write.scalingdown_rot;
tvendov	0:6435b67ad23c	1206	/* Image area to be captured */
tvendov	0:6435b67ad23c	1207	scldw_rot->res.vs = (uint16_t) ((uint32_t) video_in_rect.vs - 1u);
tvendov	0:6435b67ad23c	1208	scldw_rot->res.vw = video_in_rect.vw;
tvendov	0:6435b67ad23c	1209	scldw_rot->res.hs = video_in_rect.hs;
tvendov	0:6435b67ad23c	1210	scldw_rot->res.hw = video_in_rect.hw;
tvendov	0:6435b67ad23c	1211
tvendov	0:6435b67ad23c	1212	/* Width of the image output from scaling-down control block
tvendov	0:6435b67ad23c	1213	Width of the image read from frame buffer */
tvendov	0:6435b67ad23c	1214	if (video_write_buff_vw > LCD_CH0_DISP_VW) {
tvendov	0:6435b67ad23c	1215	video_write_buff_vw = LCD_CH0_DISP_VW;
tvendov	0:6435b67ad23c	1216	}
tvendov	0:6435b67ad23c	1217
tvendov	0:6435b67ad23c	1218	if (video_write_buff_hw > LCD_CH0_DISP_HW) {
tvendov	0:6435b67ad23c	1219	video_write_buff_hw = LCD_CH0_DISP_HW;
tvendov	0:6435b67ad23c	1220	}
tvendov	0:6435b67ad23c	1221
tvendov	0:6435b67ad23c	1222	//scldw_rot->res
tvendov	0:6435b67ad23c	1223	/* Write data parameter */
tvendov	0:6435b67ad23c	1224	framebuffer_t = framebuff;
tvendov	0:6435b67ad23c	1225	framebuffer_b = &framebuffer_t[fb_stride];
tvendov	0:6435b67ad23c	1226	scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
tvendov	0:6435b67ad23c	1227	scldw_rot->res_out_vw = video_write_buff_vw / 2u; /* Number of valid lines in vertical direction
tvendov	0:6435b67ad23c	1228	output by scaling-down control block */
tvendov	0:6435b67ad23c	1229	scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
tvendov	0:6435b67ad23c	1230	output by scaling-down control block */
tvendov	0:6435b67ad23c	1231	scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
tvendov	0:6435b67ad23c	1232	by lack of last-input line (on/off) */
tvendov	0:6435b67ad23c	1233	scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
tvendov	0:6435b67ad23c	1234	write.res_wrswa = (vdc5_wr_rd_swa_t) wr_rd_swa; /* Frame buffer swap setting */
tvendov	0:6435b67ad23c	1235	write.res_md = res_md; /* Frame buffer video-signal writing format */
tvendov	0:6435b67ad23c	1236	write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
tvendov	0:6435b67ad23c	1237	write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
tvendov	0:6435b67ad23c	1238	write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
tvendov	0:6435b67ad23c	1239	write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
tvendov	0:6435b67ad23c	1240	write.res_dth_on = VDC5_ON; /* Dither correction on/off */
tvendov	0:6435b67ad23c	1241	write.base = framebuff; /* Frame buffer base address */
tvendov	0:6435b67ad23c	1242	write.ln_off = fb_stride * 2u; /* Frame buffer line offset address [byte] */
tvendov	0:6435b67ad23c	1243	write.flm_num = (uint32_t) (1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
tvendov	0:6435b67ad23c	1244	/* Frame buffer frame offset address */
tvendov	0:6435b67ad23c	1245	write.flm_off = fb_stride * 2u * (uint32_t) scldw_rot->res_out_vw;
tvendov	0:6435b67ad23c	1246	write.btm_base = framebuffer_b; /* Frame buffer base address for bottom */
tvendov	0:6435b67ad23c	1247
tvendov	0:6435b67ad23c	1248	/* Write data control */
tvendov	0:6435b67ad23c	1249	error = R_VDC5_WriteDataControl(ch, vdc5_layer_id, &write);
tvendov	0:6435b67ad23c	1250	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	1251	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	1252	}
tvendov	0:6435b67ad23c	1253	}
tvendov	0:6435b67ad23c	1254	return drv_error;
tvendov	0:6435b67ad23c	1255	} /* End of function DRV_Video_Write_Setting() */
tvendov	0:6435b67ad23c	1256
tvendov	0:6435b67ad23c	1257	/************************************************************************//
tvendov	0:6435b67ad23c	1258	* @brief Video surface write process setting for digital input
tvendov	0:6435b67ad23c	1259	*
tvendov	0:6435b67ad23c	1260	* Description:<br>
tvendov	0:6435b67ad23c	1261	* This function set the video write process for digital input.
tvendov	0:6435b67ad23c	1262	* This function supports the following 3 image format.
tvendov	0:6435b67ad23c	1263	* YCbCr422, RGB565, RGB888
tvendov	0:6435b67ad23c	1264	* @param[in] framebuff : Base address of the frame buffer
tvendov	0:6435b67ad23c	1265	* @param[in] fb_stride [byte] : Line offset address of the frame buffer
tvendov	0:6435b67ad23c	1266	* @param[in] video_format : Frame buffer video-signal writing format
tvendov	0:6435b67ad23c	1267	* @param[in] wr_rd_swa : Frame buffer swap setting
tvendov	0:6435b67ad23c	1268	* @param[in] video_write_size_vw [px]: output height
tvendov	0:6435b67ad23c	1269	* @param[in] video_write_size_hw [px]: output width
tvendov	0:6435b67ad23c	1270	* @param[in] cap_area : Capture area
tvendov	0:6435b67ad23c	1271	* @retval Error code
tvendov	0:6435b67ad23c	1272	******************************************************************************/
tvendov	0:6435b67ad23c	1273	drv_graphics_error_t DRV_Video_Write_Setting_Digital(void * framebuff,
tvendov	0:6435b67ad23c	1274	uint32_t fb_stride, drv_video_format_t video_format,
tvendov	0:6435b67ad23c	1275	drv_wr_rd_swa_t wr_rd_swa, uint16_t video_write_buff_vw,
tvendov	0:6435b67ad23c	1276	uint16_t video_write_buff_hw, drv_rect_t * cap_area) {
tvendov	0:6435b67ad23c	1277	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	1278	vdc5_channel_t ch = VDC5_CHANNEL_0;
tvendov	0:6435b67ad23c	1279	vdc5_error_t error;
tvendov	0:6435b67ad23c	1280	vdc5_layer_id_t vdc5_layer_id;
tvendov	0:6435b67ad23c	1281	vdc5_write_t write;
tvendov	0:6435b67ad23c	1282	vdc5_scalingdown_rot_t * scldw_rot;
tvendov	0:6435b67ad23c	1283	vdc5_res_md_t res_md;
tvendov	0:6435b67ad23c	1284
tvendov	0:6435b67ad23c	1285	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
tvendov	0:6435b67ad23c	1286
tvendov	0:6435b67ad23c	1287	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	1288	if (video_format == DRV_VIDEO_FORMAT_YCBCR422) {
tvendov	0:6435b67ad23c	1289	res_md = VDC5_RES_MD_YCBCR422;
tvendov	0:6435b67ad23c	1290	} else if (video_format == DRV_VIDEO_FORMAT_RGB888) {
tvendov	0:6435b67ad23c	1291	res_md = VDC5_RES_MD_RGB888;
tvendov	0:6435b67ad23c	1292	} else if (video_format == DRV_VIDEO_FORMAT_RGB565) {
tvendov	0:6435b67ad23c	1293	res_md = VDC5_RES_MD_RGB565;
tvendov	0:6435b67ad23c	1294	} else {
tvendov	0:6435b67ad23c	1295	drv_error = DRV_GRAPHICS_FORMAT_ERR;
tvendov	0:6435b67ad23c	1296	}
tvendov	0:6435b67ad23c	1297	}
tvendov	0:6435b67ad23c	1298
tvendov	0:6435b67ad23c	1299	if (drv_error == DRV_GRAPHICS_OK) {
tvendov	0:6435b67ad23c	1300	/* Scaling-down and rotation parameter */
tvendov	0:6435b67ad23c	1301	scldw_rot = &write.scalingdown_rot;
tvendov	0:6435b67ad23c	1302	/* Image area to be captured */
tvendov	0:6435b67ad23c	1303	scldw_rot->res.vs = (uint16_t) ((uint32_t) cap_area->vs - 1u);
tvendov	0:6435b67ad23c	1304	scldw_rot->res.vw = cap_area->vw;
tvendov	0:6435b67ad23c	1305	scldw_rot->res.hs = cap_area->hs;
tvendov	0:6435b67ad23c	1306	scldw_rot->res.hw = cap_area->hw;
tvendov	0:6435b67ad23c	1307
tvendov	0:6435b67ad23c	1308	/* Write data parameter */
tvendov	0:6435b67ad23c	1309	scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
tvendov	0:6435b67ad23c	1310	scldw_rot->res_out_vw = video_write_buff_vw; /* Number of valid lines in vertical direction
tvendov	0:6435b67ad23c	1311	output by scaling-down control block */
tvendov	0:6435b67ad23c	1312	scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
tvendov	0:6435b67ad23c	1313	output by scaling-down control block */
tvendov	0:6435b67ad23c	1314	scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
tvendov	0:6435b67ad23c	1315	by lack of last-input line (on/off) */
tvendov	0:6435b67ad23c	1316	scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
tvendov	0:6435b67ad23c	1317	write.res_wrswa = (vdc5_wr_rd_swa_t) wr_rd_swa; /* Frame buffer swap setting */
tvendov	0:6435b67ad23c	1318	write.res_md = res_md; /* Frame buffer video-signal writing format */
tvendov	0:6435b67ad23c	1319	write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
tvendov	0:6435b67ad23c	1320	write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
tvendov	0:6435b67ad23c	1321	write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
tvendov	0:6435b67ad23c	1322	write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
tvendov	0:6435b67ad23c	1323	write.res_dth_on = VDC5_ON; /* Dither correction on/off */
tvendov	0:6435b67ad23c	1324	write.base = framebuff; /* Frame buffer base address */
tvendov	0:6435b67ad23c	1325	write.ln_off = fb_stride;
tvendov	0:6435b67ad23c	1326	/* Frame buffer line offset address [byte] */
tvendov	0:6435b67ad23c	1327	write.flm_num = (uint32_t) (1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
tvendov	0:6435b67ad23c	1328	/* Frame buffer frame offset address */
tvendov	0:6435b67ad23c	1329	write.flm_off = fb_stride * (uint32_t) scldw_rot->res_out_vw;
tvendov	0:6435b67ad23c	1330	write.btm_base = NULL; /* Frame buffer base address for bottom */
tvendov	0:6435b67ad23c	1331
tvendov	0:6435b67ad23c	1332	/* Write data control */
tvendov	0:6435b67ad23c	1333	error = R_VDC5_WriteDataControl(ch, vdc5_layer_id, &write);
tvendov	0:6435b67ad23c	1334	if (error != VDC5_OK) {
tvendov	0:6435b67ad23c	1335	drv_error = DRV_GRAPHICS_VDC5_ERR;
tvendov	0:6435b67ad23c	1336	}
tvendov	0:6435b67ad23c	1337	}
tvendov	0:6435b67ad23c	1338	return drv_error;
tvendov	0:6435b67ad23c	1339	} /* End of function DRV_Video_Write_Setting_Digital() */
tvendov	0:6435b67ad23c	1340
tvendov	0:6435b67ad23c	1341	/************************************************************************//
tvendov	0:6435b67ad23c	1342	* @brief Video surface write buffer change process
tvendov	0:6435b67ad23c	1343	* @param[in] video_input_ch : Video input channle
tvendov	0:6435b67ad23c	1344	* @param[in] framebuff : Base address of the frame buffer
tvendov	0:6435b67ad23c	1345	* @param[in] fb_stride : Line offset address of the frame buffer
tvendov	0:6435b67ad23c	1346	* @retval Error code
tvendov	0:6435b67ad23c	1347	******************************************************************************/
tvendov	0:6435b67ad23c	1348	drv_graphics_error_t DRV_Video_Write_Change(
tvendov	0:6435b67ad23c	1349	drv_video_input_channel_t video_input_ch, void * framebuff,
tvendov	0:6435b67ad23c	1350	uint32_t fb_stride) {
tvendov	0:6435b67ad23c	1351	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
tvendov	0:6435b67ad23c	1352	uint8_t * framebuffer_t;
tvendov	0:6435b67ad23c	1353	uint8_t * framebuffer_b;
tvendov	0:6435b67ad23c	1354
tvendov	0:6435b67ad23c	1355	framebuffer_t = (uint8_t *) ((uint32_t) framebuff & ~0x1F);
tvendov	0:6435b67ad23c	1356	framebuffer_b = &framebuffer_t[fb_stride];
tvendov	0:6435b67ad23c	1357
tvendov	0:6435b67ad23c	1358	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
tvendov	0:6435b67ad23c	1359	VDC50.SC0_SCL1_WR2 = (uint32_t) framebuffer_t;
tvendov	0:6435b67ad23c	1360	VDC50.SC0_SCL1_WR8 = (uint32_t) framebuffer_b;
tvendov	0:6435b67ad23c	1361	VDC50.SC0_SCL1_UPDATE = 0x10;
tvendov	0:6435b67ad23c	1362	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
tvendov	0:6435b67ad23c	1363	VDC50.SC1_SCL1_WR2 = (uint32_t) framebuffer_t;
tvendov	0:6435b67ad23c	1364	VDC50.SC1_SCL1_WR8 = (uint32_t) framebuffer_b;
tvendov	0:6435b67ad23c	1365	VDC50.SC1_SCL1_UPDATE = 0x10;
tvendov	0:6435b67ad23c	1366	} else {
tvendov	0:6435b67ad23c	1367	drv_error = DRV_GRAPHICS_CHANNEL_ERR;
tvendov	0:6435b67ad23c	1368	}
tvendov	0:6435b67ad23c	1369	return drv_error;
tvendov	0:6435b67ad23c	1370	} /* End of function DRV_Video_Write_Change() */
tvendov	0:6435b67ad23c	1371
tvendov	0:6435b67ad23c	1372	/* End of file */
tvendov	0:6435b67ad23c	1373

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Type:	Program
Created:	14 Mar 2019
Imports:	1
Forks:	0
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