stm32l4xx_hal_tim.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of TIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_TIM_H
00040 #define __STM32L4xx_HAL_TIM_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048 
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup TIM
00054   * @{
00055   */
00056 
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIM_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061 
00062 /**
00063   * @brief  TIM Time base Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00068                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00069 
00070   uint32_t CounterMode;       /*!< Specifies the counter mode.
00071                                    This parameter can be a value of @ref TIM_Counter_Mode */
00072 
00073   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00074                                    Auto-Reload Register at the next update event.
00075                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00076 
00077   uint32_t ClockDivision;     /*!< Specifies the clock division.
00078                                    This parameter can be a value of @ref TIM_ClockDivision */
00079 
00080   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00081                                     reaches zero, an update event is generated and counting restarts
00082                                     from the RCR value (N).
00083                                     This means in PWM mode that (N+1) corresponds to:
00084                                         - the number of PWM periods in edge-aligned mode
00085                                         - the number of half PWM period in center-aligned mode
00086                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00087                                      @note This parameter is valid only for TIM1 and TIM8. */
00088 } TIM_Base_InitTypeDef;
00089 
00090 /**
00091   * @brief  TIM Output Compare Configuration Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t OCMode;        /*!< Specifies the TIM mode.
00096                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00097 
00098   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00099                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00100 
00101   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00102                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00103 
00104   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00105                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00106                                @note This parameter is valid only for TIM1 and TIM8. */
00107 
00108   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00109                                This parameter can be a value of @ref TIM_Output_Fast_State
00110                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00111 
00112 
00113   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00114                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00115                                @note This parameter is valid only for TIM1 and TIM8. */
00116 
00117   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00118                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00119                                @note This parameter is valid only for TIM1 and TIM8. */
00120 } TIM_OC_InitTypeDef;
00121 
00122 /**
00123   * @brief  TIM One Pulse Mode Configuration Structure definition
00124   */
00125 typedef struct
00126 {
00127   uint32_t OCMode;        /*!< Specifies the TIM mode.
00128                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00129 
00130   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00131                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00132 
00133   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00134                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00135 
00136   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00137                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00138                                @note This parameter is valid only for TIM1 and TIM8. */
00139 
00140   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00141                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00142                                @note This parameter is valid only for TIM1 and TIM8. */
00143 
00144   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00145                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00146                                @note This parameter is valid only for TIM1 and TIM8. */
00147 
00148   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00149                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00150 
00151   uint32_t ICSelection;   /*!< Specifies the input.
00152                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00153 
00154   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00155                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00156 } TIM_OnePulse_InitTypeDef;
00157 
00158 
00159 /**
00160   * @brief  TIM Input Capture Configuration Structure definition
00161   */
00162 typedef struct
00163 {
00164   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00165                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00166 
00167   uint32_t ICSelection;  /*!< Specifies the input.
00168                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00169 
00170   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00171                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00172 
00173   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00174                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00175 } TIM_IC_InitTypeDef;
00176 
00177 /**
00178   * @brief  TIM Encoder Configuration Structure definition
00179   */
00180 typedef struct
00181 {
00182   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00183                                This parameter can be a value of @ref TIM_Encoder_Mode */
00184 
00185   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00186                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00187 
00188   uint32_t IC1Selection;  /*!< Specifies the input.
00189                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00190 
00191   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00192                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00193 
00194   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00195                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00196 
00197   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00198                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00199 
00200   uint32_t IC2Selection;  /*!< Specifies the input.
00201                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00202 
00203   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00204                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00205 
00206   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00207                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00208 } TIM_Encoder_InitTypeDef;
00209 
00210 
00211 /**
00212   * @brief  Clock Configuration Handle Structure definition
00213   */
00214 typedef struct
00215 {
00216   uint32_t ClockSource;     /*!< TIM clock sources
00217                                  This parameter can be a value of @ref TIM_Clock_Source */
00218   uint32_t ClockPolarity;   /*!< TIM clock polarity
00219                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00220   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00221                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00222   uint32_t ClockFilter;    /*!< TIM clock filter
00223                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00224 }TIM_ClockConfigTypeDef;
00225 
00226 /**
00227   * @brief  Clear Input Configuration Handle Structure definition
00228   */
00229 typedef struct
00230 {
00231   uint32_t ClearInputState;      /*!< TIM clear Input state
00232                                       This parameter can be ENABLE or DISABLE */
00233   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00234                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00235   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00236                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00237   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00238                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00239   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
00240                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00241 }TIM_ClearInputConfigTypeDef;
00242 
00243 /**
00244   * @brief  TIM Master configuration Structure definition
00245   * @note   Advanced timers provide TRGO2 internal line which is redirected
00246   *         to the ADC
00247   */
00248 typedef struct {
00249   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00250                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00251   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00252                                       This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00253   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00254                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00255 }TIM_MasterConfigTypeDef;
00256 
00257 /**
00258   * @brief  TIM Slave configuration Structure definition
00259   */
00260 typedef struct {
00261   uint32_t  SlaveMode;      /*!< Slave mode selection
00262                                This parameter can be a value of @ref TIM_Slave_Mode */
00263   uint32_t  InputTrigger;      /*!< Input Trigger source
00264                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00265   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00266                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00267   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00268                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00269   uint32_t  TriggerFilter;     /*!< Input trigger filter
00270                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00271 
00272 }TIM_SlaveConfigTypeDef;
00273 
00274 /**
00275   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00276   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00277   *        filter and polarity.
00278   */
00279 typedef struct
00280 {
00281   uint32_t OffStateRunMode;       /*!< TIM off state in run mode
00282                                          This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00283   uint32_t OffStateIDLEMode;          /*!< TIM off state in IDLE mode
00284                                          This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00285   uint32_t LockLevel;             /*!< TIM Lock level
00286                                          This parameter can be a value of @ref TIM_Lock_level */
00287   uint32_t DeadTime;              /*!< TIM dead Time
00288                                          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00289   uint32_t BreakState;            /*!< TIM Break State
00290                                          This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00291   uint32_t BreakPolarity;             /*!< TIM Break input polarity
00292                                          This parameter can be a value of @ref TIM_Break_Polarity */
00293   uint32_t BreakFilter;               /*!< Specifies the break input filter.
00294                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00295   uint32_t Break2State;           /*!< TIM Break2 State
00296                                          This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
00297   uint32_t Break2Polarity;            /*!< TIM Break2 input polarity
00298                                          This parameter can be a value of @ref TIM_Break2_Polarity */
00299   uint32_t Break2Filter;              /*!< TIM break2 input filter.
00300                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00301   uint32_t AutomaticOutput;           /*!< TIM Automatic Output Enable state
00302                                          This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00303 } TIM_BreakDeadTimeConfigTypeDef;
00304 
00305 /**
00306   * @brief  HAL State structures definition
00307   */
00308 typedef enum
00309 {
00310   HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
00311   HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
00312   HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
00313   HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
00314   HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
00315 }HAL_TIM_StateTypeDef;
00316 
00317 /**
00318   * @brief  HAL Active channel structures definition
00319   */
00320 typedef enum
00321 {
00322   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
00323   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
00324   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
00325   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
00326   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10,    /*!< The active channel is 5     */
00327   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20,    /*!< The active channel is 6     */
00328   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
00329 }HAL_TIM_ActiveChannel;
00330 
00331 /**
00332   * @brief  TIM Time Base Handle Structure definition
00333   */
00334 typedef struct
00335 {
00336   TIM_TypeDef              *Instance;     /*!< Register base address             */
00337   TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
00338   HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
00339   DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
00340                                              This array is accessed by a @ref DMA_Handle_index */
00341   HAL_LockTypeDef          Lock;          /*!< Locking object                    */
00342   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00343 }TIM_HandleTypeDef;
00344 
00345 /**
00346   * @}
00347   */
00348 /* End of exported types -----------------------------------------------------*/
00349 
00350 /* Exported constants --------------------------------------------------------*/
00351 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00352   * @{
00353   */
00354 
00355 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00356   * @{
00357   */
00358 #define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001)
00359 #define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002)
00360 #define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
00361 /**
00362   * @}
00363   */
00364 
00365 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00366   * @{
00367   */
00368 #define TIM_DMABASE_CR1                    (0x00000000)
00369 #define TIM_DMABASE_CR2                    (0x00000001)
00370 #define TIM_DMABASE_SMCR                   (0x00000002)
00371 #define TIM_DMABASE_DIER                   (0x00000003)
00372 #define TIM_DMABASE_SR                     (0x00000004)
00373 #define TIM_DMABASE_EGR                    (0x00000005)
00374 #define TIM_DMABASE_CCMR1                  (0x00000006)
00375 #define TIM_DMABASE_CCMR2                  (0x00000007)
00376 #define TIM_DMABASE_CCER                   (0x00000008)
00377 #define TIM_DMABASE_CNT                    (0x00000009)
00378 #define TIM_DMABASE_PSC                    (0x0000000A)
00379 #define TIM_DMABASE_ARR                    (0x0000000B)
00380 #define TIM_DMABASE_RCR                    (0x0000000C)
00381 #define TIM_DMABASE_CCR1                   (0x0000000D)
00382 #define TIM_DMABASE_CCR2                   (0x0000000E)
00383 #define TIM_DMABASE_CCR3                   (0x0000000F)
00384 #define TIM_DMABASE_CCR4                   (0x00000010)
00385 #define TIM_DMABASE_BDTR                   (0x00000011)
00386 #define TIM_DMABASE_DCR                    (0x00000012)
00387 #define TIM_DMABASE_DMAR                   (0x00000013)
00388 #define TIM_DMABASE_OR1                    (0x00000014)
00389 #define TIM_DMABASE_CCMR3                  (0x00000015)
00390 #define TIM_DMABASE_CCR5                   (0x00000016)
00391 #define TIM_DMABASE_CCR6                   (0x00000017)
00392 #define TIM_DMABASE_OR2                    (0x00000018)
00393 #define TIM_DMABASE_OR3                    (0x00000019)
00394 /**
00395   * @}
00396   */
00397 
00398 /** @defgroup TIM_Event_Source TIM  Extended Event Source
00399   * @{
00400   */
00401 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00402 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00403 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00404 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00405 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00406 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00407 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00408 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00409 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00410 /**
00411   * @}
00412   */
00413 
00414 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00415   * @{
00416   */
00417 #define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
00418 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00419 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00420 /**
00421   * @}
00422   */
00423 
00424 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00425   * @{
00426   */
00427 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00428 #define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
00429 /**
00430   * @}
00431   */
00432 
00433 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00434   * @{
00435   */
00436 #define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
00437 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
00438 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
00439 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
00440 /**
00441   * @}
00442   */
00443 
00444 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00445   * @{
00446   */
00447 #define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
00448 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
00449 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
00450 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
00451 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
00452 /**
00453   * @}
00454   */
00455 
00456 /** @defgroup TIM_ClockDivision TIM Clock Division
00457   * @{
00458   */
00459 #define TIM_CLOCKDIVISION_DIV1             ((uint32_t)0x0000)
00460 #define TIM_CLOCKDIVISION_DIV2             (TIM_CR1_CKD_0)
00461 #define TIM_CLOCKDIVISION_DIV4             (TIM_CR1_CKD_1)
00462 /**
00463   * @}
00464   */
00465 
00466 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00467   * @{
00468   */
00469 #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
00470 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
00471 /**
00472   * @}
00473   */
00474 
00475 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00476   * @{
00477   */
00478 #define TIM_OCFAST_DISABLE                 ((uint32_t)0x0000)
00479 #define TIM_OCFAST_ENABLE                  (TIM_CCMR1_OC1FE)
00480 /**
00481   * @}
00482   */
00483 
00484 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00485   * @{
00486   */
00487 #define TIM_OUTPUTNSTATE_DISABLE           ((uint32_t)0x0000)
00488 #define TIM_OUTPUTNSTATE_ENABLE            (TIM_CCER_CC1NE)
00489 /**
00490   * @}
00491   */
00492 
00493 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00494   * @{
00495   */
00496 #define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
00497 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00498 /**
00499   * @}
00500   */
00501 
00502 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00503   * @{
00504   */
00505 #define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
00506 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00507 /**
00508   * @}
00509   */
00510 
00511 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00512   * @{
00513   */
00514 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00515 #define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
00516 /**
00517   * @}
00518   */
00519 
00520 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00521   * @{
00522   */
00523 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00524 #define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
00525 /**
00526   * @}
00527   */
00528 
00529 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00530   * @{
00531   */
00532 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00533 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00534 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
00535 /**
00536   * @}
00537   */
00538 
00539 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00540   * @{
00541   */
00542 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00543                                                                                connected to IC1, IC2, IC3 or IC4, respectively */
00544 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00545                                                                                connected to IC2, IC1, IC4 or IC3, respectively */
00546 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00547 /**
00548   * @}
00549   */
00550 
00551 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00552   * @{
00553   */
00554 #define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)                 /*!< Capture performed each time an edge is detected on the capture input */
00555 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00556 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00557 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00558 /**
00559   * @}
00560   */
00561 
00562 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00563   * @{
00564   */
00565 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00566 #define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
00567 /**
00568   * @}
00569   */
00570 
00571 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00572   * @{
00573   */
00574 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00575 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00576 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00577 /**
00578   * @}
00579   */
00580 
00581 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00582   * @{
00583   */
00584 #define TIM_IT_UPDATE                      (TIM_DIER_UIE)
00585 #define TIM_IT_CC1                         (TIM_DIER_CC1IE)
00586 #define TIM_IT_CC2                         (TIM_DIER_CC2IE)
00587 #define TIM_IT_CC3                         (TIM_DIER_CC3IE)
00588 #define TIM_IT_CC4                         (TIM_DIER_CC4IE)
00589 #define TIM_IT_COM                         (TIM_DIER_COMIE)
00590 #define TIM_IT_TRIGGER                     (TIM_DIER_TIE)
00591 #define TIM_IT_BREAK                       (TIM_DIER_BIE)
00592 /**
00593   * @}
00594   */
00595 
00596 /** @defgroup TIM_Commutation_Source  TIM Commutation Source 
00597   * @{
00598   */  
00599 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00600 #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
00601 /**
00602   * @}
00603   */
00604 
00605 /** @defgroup TIM_DMA_sources TIM DMA Sources
00606   * @{
00607   */
00608 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00609 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00610 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00611 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00612 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00613 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00614 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00615 /**
00616   * @}
00617   */
00618 
00619 /** @defgroup TIM_Flag_definition TIM Flag Definition
00620   * @{
00621   */
00622 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00623 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00624 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00625 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00626 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00627 #define TIM_FLAG_CC5                       (TIM_SR_CC5IF)
00628 #define TIM_FLAG_CC6                       (TIM_SR_CC6IF)
00629 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00630 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00631 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00632 #define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
00633 #define TIM_FLAG_SYSTEM_BREAK              (TIM_SR_SBIF)
00634 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00635 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00636 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00637 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00638 /**
00639   * @}
00640   */
00641 
00642 /** @defgroup TIM_Channel TIM Channel
00643   * @{
00644   */
00645 #define TIM_CHANNEL_1                      ((uint32_t)0x0000)
00646 #define TIM_CHANNEL_2                      ((uint32_t)0x0004)
00647 #define TIM_CHANNEL_3                      ((uint32_t)0x0008)
00648 #define TIM_CHANNEL_4                      ((uint32_t)0x000C)
00649 #define TIM_CHANNEL_5                      ((uint32_t)0x0010)
00650 #define TIM_CHANNEL_6                      ((uint32_t)0x0014)
00651 #define TIM_CHANNEL_ALL                    ((uint32_t)0x003C)
00652 /**
00653   * @}
00654   */
00655 
00656 /** @defgroup TIM_Clock_Source TIM Clock Source
00657   * @{
00658   */
00659 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00660 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00661 #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
00662 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00663 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00664 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00665 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00666 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00667 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00668 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
00669 /**
00670   * @}
00671   */
00672 
00673 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00674   * @{
00675   */
00676 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
00677 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
00678 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
00679 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00680 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00681 /**
00682   * @}
00683   */
00684 
00685 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00686   * @{
00687   */
00688 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00689 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00690 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00691 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00692 /**
00693   * @}
00694   */
00695 
00696 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00697   * @{
00698   */
00699 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00700 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
00701 /**
00702   * @}
00703   */
00704 
00705 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00706   * @{
00707   */
00708 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00709 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00710 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00711 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00712 /**
00713   * @}
00714   */
00715 
00716 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00717   * @{
00718   */
00719 #define TIM_OSSR_ENABLE                      (TIM_BDTR_OSSR)
00720 #define TIM_OSSR_DISABLE                   ((uint32_t)0x0000)
00721 /**
00722   * @}
00723   */
00724 
00725 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00726   * @{
00727   */
00728 #define TIM_OSSI_ENABLE                      (TIM_BDTR_OSSI)
00729 #define TIM_OSSI_DISABLE                   ((uint32_t)0x0000)
00730 /**
00731   * @}
00732   */
00733 /** @defgroup TIM_Lock_level  TIM Lock level
00734   * @{
00735   */
00736 #define TIM_LOCKLEVEL_OFF                    ((uint32_t)0x0000)
00737 #define TIM_LOCKLEVEL_1                    (TIM_BDTR_LOCK_0)
00738 #define TIM_LOCKLEVEL_2                    (TIM_BDTR_LOCK_1)
00739 #define TIM_LOCKLEVEL_3                    (TIM_BDTR_LOCK)
00740 /**
00741   * @}
00742   */
00743 
00744 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00745   * @{
00746   */
00747 #define TIM_BREAK_ENABLE                   (TIM_BDTR_BKE)
00748 #define TIM_BREAK_DISABLE                  ((uint32_t)0x0000)
00749 /**
00750   * @}
00751   */
00752 
00753 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00754   * @{
00755   */
00756 #define TIM_BREAKPOLARITY_LOW              ((uint32_t)0x0000)
00757 #define TIM_BREAKPOLARITY_HIGH             (TIM_BDTR_BKP)
00758 /**
00759   * @}
00760   */
00761 
00762 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
00763   * @{
00764   */
00765 #define TIM_BREAK2_DISABLE                 ((uint32_t)0x00000000)
00766 #define TIM_BREAK2_ENABLE                  ((uint32_t)TIM_BDTR_BK2E)
00767 /**
00768   * @}
00769   */
00770 
00771 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
00772   * @{
00773   */
00774 #define TIM_BREAK2POLARITY_LOW             ((uint32_t)0x00000000)
00775 #define TIM_BREAK2POLARITY_HIGH            ((uint32_t)TIM_BDTR_BK2P)
00776 /**
00777   * @}
00778   */
00779 
00780 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00781   * @{
00782   */
00783 #define TIM_AUTOMATICOUTPUT_ENABLE         (TIM_BDTR_AOE)
00784 #define TIM_AUTOMATICOUTPUT_DISABLE        ((uint32_t)0x0000)
00785 /**
00786   * @}
00787   */
00788 
00789 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
00790   * @{
00791   */
00792 #define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00793 #define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
00794 #define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
00795 #define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)      /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
00796 /**
00797   * @}
00798   */
00799 
00800 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00801   * @{
00802   */
00803 #define TIM_TRGO_RESET            ((uint32_t)0x0000)
00804 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00805 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00806 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00807 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00808 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00809 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00810 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00811 /**
00812   * @}
00813   */
00814 
00815 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
00816   * @{
00817   */
00818 #define TIM_TRGO2_RESET                          ((uint32_t)0x00000000)
00819 #define TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
00820 #define TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
00821 #define TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00822 #define TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
00823 #define TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00824 #define TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
00825 #define TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00826 #define TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
00827 #define TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
00828 #define TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
00829 #define TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00830 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
00831 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00832 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
00833 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00834 /**
00835   * @}
00836   */
00837 
00838 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
00839   * @{
00840   */
00841 #define TIM_MASTERSLAVEMODE_ENABLE         ((uint32_t)0x0080)
00842 #define TIM_MASTERSLAVEMODE_DISABLE        ((uint32_t)0x0000)
00843 /**
00844   * @}
00845   */
00846 
00847 /** @defgroup TIM_Slave_Mode TIM Slave mode
00848   * @{
00849   */
00850 #define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000)
00851 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
00852 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
00853 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
00854 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
00855 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
00856 /**
00857   * @}
00858   */
00859 
00860 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
00861   * @{
00862   */
00863 #define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
00864 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
00865 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
00866 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00867 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
00868 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00869 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
00870 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
00871 
00872 #define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
00873 #define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
00874 #define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
00875 #define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00876 #define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00877 #define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
00878 /**
00879   * @}
00880   */
00881 
00882 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00883   * @{
00884   */
00885 #define TIM_TS_ITR0                        ((uint32_t)0x0000)
00886 #define TIM_TS_ITR1                        ((uint32_t)0x0010)
00887 #define TIM_TS_ITR2                        ((uint32_t)0x0020)
00888 #define TIM_TS_ITR3                        ((uint32_t)0x0030)
00889 #define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
00890 #define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
00891 #define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
00892 #define TIM_TS_ETRF                        ((uint32_t)0x0070)
00893 #define TIM_TS_NONE                        ((uint32_t)0xFFFF)
00894 /**
00895   * @}
00896   */
00897 
00898 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00899   * @{
00900   */
00901 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
00902 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
00903 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00904 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00905 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00906 /**
00907   * @}
00908   */
00909 
00910 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00911   * @{
00912   */
00913 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00914 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00915 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00916 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00917 /**
00918   * @}
00919   */
00920 
00921 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
00922   * @{
00923   */
00924 #define TIM_TI1SELECTION_CH1               ((uint32_t)0x0000)
00925 #define TIM_TI1SELECTION_XORCOMBINATION    (TIM_CR2_TI1S)
00926 /**
00927   * @}
00928   */
00929 
00930 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
00931   * @{
00932   */
00933 #define TIM_DMABURSTLENGTH_1TRANSFER       (0x00000000)
00934 #define TIM_DMABURSTLENGTH_2TRANSFERS      (0x00000100)
00935 #define TIM_DMABURSTLENGTH_3TRANSFERS      (0x00000200)
00936 #define TIM_DMABURSTLENGTH_4TRANSFERS      (0x00000300)
00937 #define TIM_DMABURSTLENGTH_5TRANSFERS      (0x00000400)
00938 #define TIM_DMABURSTLENGTH_6TRANSFERS      (0x00000500)
00939 #define TIM_DMABURSTLENGTH_7TRANSFERS      (0x00000600)
00940 #define TIM_DMABURSTLENGTH_8TRANSFERS      (0x00000700)
00941 #define TIM_DMABURSTLENGTH_9TRANSFERS      (0x00000800)
00942 #define TIM_DMABURSTLENGTH_10TRANSFERS     (0x00000900)
00943 #define TIM_DMABURSTLENGTH_11TRANSFERS     (0x00000A00)
00944 #define TIM_DMABURSTLENGTH_12TRANSFERS     (0x00000B00)
00945 #define TIM_DMABURSTLENGTH_13TRANSFERS     (0x00000C00)
00946 #define TIM_DMABURSTLENGTH_14TRANSFERS     (0x00000D00)
00947 #define TIM_DMABURSTLENGTH_15TRANSFERS     (0x00000E00)
00948 #define TIM_DMABURSTLENGTH_16TRANSFERS     (0x00000F00)
00949 #define TIM_DMABURSTLENGTH_17TRANSFERS     (0x00001000)
00950 #define TIM_DMABURSTLENGTH_18TRANSFERS     (0x00001100)
00951 /**
00952   * @}
00953   */
00954 
00955 /** @defgroup DMA_Handle_index TIM DMA Handle Index
00956   * @{
00957   */
00958 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
00959 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00960 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00961 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00962 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00963 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
00964 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
00965 /**
00966   * @}
00967   */
00968 
00969 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
00970   * @{
00971   */
00972 #define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
00973 #define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
00974 #define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
00975 #define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
00976 /**
00977   * @}
00978   */
00979 
00980 /** @defgroup TIM_Break_System TIM Break System
00981   * @{
00982   */
00983 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
00984 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
00985 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
00986 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
00987 /**
00988   * @}
00989   */
00990 
00991 /**
00992   * @}
00993   */
00994 /* End of exported constants -------------------------------------------------*/
00995 
00996 /* Exported macros -----------------------------------------------------------*/
00997 /** @defgroup TIM_Exported_Macros TIM Exported Macros
00998   * @{
00999   */
01000 
01001 /** @brief  Reset TIM handle state.
01002   * @param  __HANDLE__: TIM handle.
01003   * @retval None
01004   */
01005 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
01006 
01007 /**
01008   * @brief  Enable the TIM peripheral.
01009   * @param  __HANDLE__: TIM handle
01010   * @retval None
01011  */
01012 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01013 
01014 /**
01015   * @brief  Enable the TIM main Output.
01016   * @param  __HANDLE__: TIM handle
01017   * @retval None
01018   */
01019 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01020 
01021 /**
01022   * @brief  Disable the TIM peripheral.
01023   * @param  __HANDLE__: TIM handle
01024   * @retval None
01025   */
01026 #define __HAL_TIM_DISABLE(__HANDLE__) \
01027                         do { \
01028                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
01029                             { \
01030                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
01031                             { \
01032                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01033                             } \
01034                           } \
01035                         } while(0)
01036 
01037 /**
01038   * @brief  Disable the TIM main Output.
01039   * @param  __HANDLE__: TIM handle
01040   * @retval None
01041   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
01042   */
01043 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01044                         do { \
01045                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
01046                           { \
01047                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
01048                             { \
01049                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01050                             } \
01051                             } \
01052                         } while(0)
01053 
01054 /** @brief  Enable the specified TIM interrupt.
01055   * @param  __HANDLE__: specifies the TIM Handle.
01056   * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
01057   *          This parameter can be one of the following values:
01058   *            @arg TIM_IT_UPDATE: Update interrupt
01059   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01060   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01061   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01062   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01063   *            @arg TIM_IT_COM:   Commutation interrupt
01064   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01065   *            @arg TIM_IT_BREAK: Break interrupt
01066   * @retval None
01067   */
01068 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01069 
01070 
01071 /** @brief  Disable the specified TIM interrupt.
01072   * @param  __HANDLE__: specifies the TIM Handle.
01073   * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
01074   *          This parameter can be one of the following values:
01075   *            @arg TIM_IT_UPDATE: Update interrupt
01076   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01077   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01078   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01079   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01080   *            @arg TIM_IT_COM:   Commutation interrupt
01081   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01082   *            @arg TIM_IT_BREAK: Break interrupt
01083   * @retval None
01084   */
01085 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01086 
01087 /** @brief  Enable the specified DMA request.
01088   * @param  __HANDLE__: specifies the TIM Handle.
01089   * @param  __DMA__: specifies the TIM DMA request to enable.
01090   *          This parameter can be one of the following values:
01091   *            @arg TIM_DMA_UPDATE: Update DMA request
01092   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01093   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01094   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01095   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01096   *            @arg TIM_DMA_COM:   Commutation DMA request
01097   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01098   *            @arg TIM_DMA_BREAK: Break DMA request
01099   * @retval None
01100   */
01101 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01102 
01103 /** @brief  Disable the specified DMA request.
01104   * @param  __HANDLE__: specifies the TIM Handle.
01105   * @param  __DMA__: specifies the TIM DMA request to disable.
01106   *          This parameter can be one of the following values:
01107   *            @arg TIM_DMA_UPDATE: Update DMA request
01108   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01109   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01110   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01111   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01112   *            @arg TIM_DMA_COM:   Commutation DMA request
01113   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01114   *            @arg TIM_DMA_BREAK: Break DMA request
01115   * @retval None
01116   */
01117 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01118 
01119 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01120   * @param  __HANDLE__: specifies the TIM Handle.
01121   * @param  __FLAG__: specifies the TIM interrupt flag to check.
01122   *        This parameter can be one of the following values:
01123   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01124   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01125   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01126   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01127   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01128   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01129   *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
01130   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01131   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01132   *            @arg TIM_FLAG_BREAK: Break interrupt flag   
01133   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
01134   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01135   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01136   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01137   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01138   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01139   * @retval The new state of __FLAG__ (TRUE or FALSE).
01140   */
01141 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01142 
01143 /** @brief  Clear the specified TIM interrupt flag.
01144   * @param  __HANDLE__: specifies the TIM Handle.
01145   * @param  __FLAG__: specifies the TIM interrupt flag to clear.
01146   *        This parameter can be one of the following values:
01147   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01148   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01149   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01150   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01151   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01152   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01153   *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
01154   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01155   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01156   *            @arg TIM_FLAG_BREAK: Break interrupt flag   
01157   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag                     
01158   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01159   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01160   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01161   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01162   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01163   * @retval The new state of __FLAG__ (TRUE or FALSE).
01164   */
01165 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01166 
01167 /**
01168   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01169   * @param  __HANDLE__: TIM handle
01170   * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
01171   *          This parameter can be one of the following values:
01172   *            @arg TIM_IT_UPDATE: Update interrupt
01173   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01174   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01175   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01176   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01177   *            @arg TIM_IT_COM:   Commutation interrupt
01178   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01179   *            @arg TIM_IT_BREAK: Break interrupt
01180   * @retval The state of TIM_IT (SET or RESET).
01181   */
01182 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
01183 
01184 /** @brief Clear the TIM interrupt pending bits.
01185   * @param  __HANDLE__: TIM handle
01186   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
01187   *          This parameter can be one of the following values:
01188   *            @arg TIM_IT_UPDATE: Update interrupt
01189   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01190   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01191   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01192   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01193   *            @arg TIM_IT_COM:   Commutation interrupt
01194   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01195   *            @arg TIM_IT_BREAK: Break interrupt
01196   * @retval None
01197   */
01198 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01199 
01200 /**
01201   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01202   * @param  __HANDLE__: TIM handle.
01203   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01204   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
01205 mode.
01206   */
01207 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01208 
01209 
01210 /**
01211   * @brief  Set the TIM Prescaler on runtime.
01212   * @param  __HANDLE__: TIM handle.
01213   * @param  __PRESC__: specifies the Prescaler new value.
01214   * @retval None
01215   */
01216 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01217 
01218 /**
01219   * @brief  Set the TIM Counter Register value on runtime.
01220   * @param  __HANDLE__: TIM handle.
01221   * @param  __COUNTER__: specifies the Counter register new value.
01222   * @retval None
01223   */
01224 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01225 
01226 /**
01227   * @brief  Get the TIM Counter Register value on runtime.
01228   * @param  __HANDLE__: TIM handle.
01229   * @retval None
01230   */
01231 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
01232    ((__HANDLE__)->Instance->CNT)
01233 
01234 /**
01235   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01236   * @param  __HANDLE__: TIM handle.
01237   * @param  __AUTORELOAD__: specifies the Counter register new value.
01238   * @retval None
01239   */
01240 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01241                         do{                                                    \
01242                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01243                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01244                           } while(0)
01245 
01246 /**
01247   * @brief  Get the TIM Autoreload Register value on runtime.
01248   * @param  __HANDLE__: TIM handle.
01249   * @retval None
01250   */
01251 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
01252    ((__HANDLE__)->Instance->ARR)
01253 
01254 /**
01255   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01256   * @param  __HANDLE__: TIM handle.
01257   * @param  __CKD__: specifies the clock division value.
01258   *          This parameter can be one of the following value:
01259   *            @arg TIM_CLOCKDIVISION_DIV1
01260   *            @arg TIM_CLOCKDIVISION_DIV2
01261   *            @arg TIM_CLOCKDIVISION_DIV4
01262   * @retval None
01263   */
01264 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01265                         do{                                                    \
01266                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
01267                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
01268                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
01269                           } while(0)
01270 
01271 /**
01272   * @brief  Get the TIM Clock Division value on runtime.
01273   * @param  __HANDLE__: TIM handle.
01274   * @retval None
01275   */
01276 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
01277    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01278 
01279 /**
01280   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
01281   * @param  __HANDLE__: TIM handle.
01282   * @param  __CHANNEL__: TIM Channels to be configured.
01283   *          This parameter can be one of the following values:
01284   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01285   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01286   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01287   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01288   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
01289   *          This parameter can be one of the following values:
01290   *            @arg TIM_ICPSC_DIV1: no prescaler
01291   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01292   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01293   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01294   * @retval None
01295   */
01296 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01297                         do{                                                    \
01298                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01299                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01300                           } while(0)
01301 
01302 /**
01303   * @brief  Get the TIM Input Capture prescaler on runtime.
01304   * @param  __HANDLE__: TIM handle.
01305   * @param  __CHANNEL__: TIM Channels to be configured.
01306   *          This parameter can be one of the following values:
01307   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01308   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01309   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01310   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01311   * @retval None
01312   */
01313 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01314   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01315    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
01316    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01317    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
01318 
01319 /**
01320   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01321   * @param  __HANDLE__: TIM handle.
01322   * @param  __CHANNEL__: TIM Channels to be configured.
01323   *          This parameter can be one of the following values:
01324   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01325   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01326   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01327   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01328   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01329   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01330   * @param  __COMPARE__: specifies the Capture Compare register new value.
01331   * @retval None
01332   */
01333 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01334 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01335  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01336  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01337  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01338  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01339  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01340 
01341 /**
01342   * @brief  Get the TIM Capture Compare Register value on runtime.
01343   * @param  __HANDLE__: TIM handle.
01344   * @param  __CHANNEL__: TIM Channel associated with the capture compare register
01345   *          This parameter can be one of the following values:
01346   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01347   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01348   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01349   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01350   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01351   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01352   * @retval None
01353   */
01354 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01355 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01356  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01357  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01358  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01359  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01360  ((__HANDLE__)->Instance->CCR6))
01361 
01362 /**
01363   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
01364   * @param  __HANDLE__: TIM handle.
01365   * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
01366   *        overflow/underflow generates an update interrupt or DMA request (if
01367   *        enabled)
01368   * @retval None
01369   */
01370 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
01371     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
01372 
01373 /**
01374   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
01375   * @param  __HANDLE__: TIM handle.
01376   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
01377   *        following events generate an update interrupt or DMA request (if 
01378   *        enabled):
01379   *           _ Counter overflow underflow
01380   *           _ Setting the UG bit
01381   *           _ Update generation through the slave mode controller
01382   * @retval None
01383   */
01384 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
01385       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
01386         
01387 /**
01388   * @brief  Set the TIM Capture x input polarity on runtime.
01389   * @param  __HANDLE__: TIM handle.
01390   * @param  __CHANNEL__: TIM Channels to be configured.
01391   *          This parameter can be one of the following values:
01392   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01393   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01394   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01395   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01396   * @param  __POLARITY__: Polarity for TIx source   
01397   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01398   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01399   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01400   * @retval None
01401   */
01402 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01403         do{                                                                     \
01404           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01405           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01406         }while(0)
01407           
01408 /**
01409   * @}
01410   */
01411 /* End of exported macros ----------------------------------------------------*/
01412 
01413 /* Private constants ---------------------------------------------------------*/
01414 /** @defgroup TIM_Private_Constants TIM Private Constants
01415   * @{
01416   */
01417 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01418    channels have been disabled */
01419 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01420 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01421 /**
01422   * @}
01423   */
01424 /* End of private constants --------------------------------------------------*/
01425   
01426 /* Private macros ------------------------------------------------------------*/
01427 /** @defgroup TIM_Private_Macros TIM Private Macros
01428   * @{
01429   */
01430 
01431 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01432                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
01433                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01434 
01435 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01436                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01437                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01438                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01439                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01440                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01441                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01442                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01443                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01444                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01445                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01446                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01447                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01448                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01449                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01450                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01451                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01452                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01453                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01454                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01455                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01456                                    ((__BASE__) == TIM_DMABASE_OR1)   || \
01457                                    ((__BASE__) == TIM_DMABASE_OR2)   || \
01458                                    ((__BASE__) == TIM_DMABASE_OR3))
01459 
01460 
01461 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
01462 
01463 
01464 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01465                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01466                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01467                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01468                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01469 
01470 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01471                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01472                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01473 
01474 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01475                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01476 
01477 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01478                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01479 
01480 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01481                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01482 
01483 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01484                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01485 
01486 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01487                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01488 
01489 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01490                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01491                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01492 
01493 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01494                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01495                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01496 
01497 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01498                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01499                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01500                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01501 
01502 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01503                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01504 
01505 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01506                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01507                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
01508 
01509 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
01510 
01511 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01512                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01513                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01514                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01515                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01516                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01517                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01518 
01519 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01520                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01521 
01522 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
01523                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
01524                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
01525 
01526 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01527                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01528                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01529                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01530                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01531                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
01532                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01533                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01534                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01535                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
01536 
01537 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01538                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01539                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01540                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01541                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01542 
01543 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01544                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01545                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01546                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01547 
01548 #define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF)
01549 
01550 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01551                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01552 
01553 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01554                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01555                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01556                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01557 
01558 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
01559 
01560 
01561 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
01562                                             ((__STATE__) == TIM_OSSR_DISABLE))
01563 
01564 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
01565                                             ((__STATE__) == TIM_OSSI_DISABLE))
01566 
01567 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01568                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
01569                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
01570                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
01571 
01572 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
01573 
01574 
01575 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
01576                                             ((__STATE__) == TIM_BREAK_DISABLE))
01577 
01578 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01579                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01580 
01581 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
01582                                             ((__STATE__) == TIM_BREAK2_DISABLE))
01583 
01584 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
01585                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
01586 
01587 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01588                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01589 
01590 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
01591 
01592 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
01593                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01594                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01595                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
01596                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01597                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01598                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01599                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01600 
01601 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
01602                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
01603                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
01604                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
01605                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
01606                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
01607                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01608                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01609                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
01610                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
01611                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
01612                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
01613                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
01614                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
01615                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
01616                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
01617                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
01618 
01619 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01620                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01621 
01622 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
01623                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
01624                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
01625                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
01626                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
01627                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01628 
01629 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
01630                                      ((__MODE__) == TIM_OCMODE_PWM2)               || \
01631                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
01632                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
01633                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
01634                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
01635 
01636 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
01637                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
01638                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
01639                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
01640                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
01641                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
01642                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
01643                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
01644 
01645 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01646                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
01647                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
01648                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
01649                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
01650                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
01651                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
01652                                                  ((__SELECTION__) == TIM_TS_ETRF))
01653 
01654 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01655                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
01656                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
01657                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
01658                                                                ((__SELECTION__) == TIM_TS_NONE))
01659 
01660 
01661 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01662                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01663                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
01664                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01665                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01666 
01667 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
01668                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
01669                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
01670                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
01671 
01672 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
01673 
01674 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
01675                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
01676 
01677 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01678                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01679                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01680                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01681                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01682                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01683                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01684                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01685                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01686                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01687                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01688                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01689                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01690                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01691                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01692                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01693                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01694                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
01695 
01696 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xF)
01697 
01698 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFF)
01699 
01700 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
01701                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
01702                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
01703                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
01704 
01705 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01706 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01707  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
01708  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01709  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
01710 
01711 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01712 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
01713  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
01714  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
01715  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
01716 
01717 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01718 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01719  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
01720  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
01721  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
01722 
01723 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01724 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01725  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01726  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01727  ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
01728 
01729 /**
01730   * @}
01731   */
01732 /* End of private macros -----------------------------------------------------*/
01733 
01734 /* Include TIM HAL Extended module */
01735 #include "stm32l4xx_hal_tim_ex.h"
01736 
01737 /* Exported functions --------------------------------------------------------*/
01738 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
01739   * @{
01740   */
01741 
01742 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
01743  *  @brief    Time Base functions
01744  * @{
01745  */
01746 /* Time Base functions ********************************************************/
01747 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01748 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01749 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01750 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01751 /* Blocking mode: Polling */
01752 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01753 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01754 /* Non-Blocking mode: Interrupt */
01755 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01756 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01757 /* Non-Blocking mode: DMA */
01758 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01759 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01760 /**
01761   * @}
01762   */
01763 
01764 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
01765  *  @brief    Time Output Compare functions
01766  * @{
01767  */
01768 /* Timer Output Compare functions *********************************************/
01769 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01770 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01771 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01772 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01773 /* Blocking mode: Polling */
01774 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01775 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01776 /* Non-Blocking mode: Interrupt */
01777 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01778 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01779 /* Non-Blocking mode: DMA */
01780 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01781 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01782 /**
01783   * @}
01784   */
01785 
01786 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
01787  *  @brief    Time PWM functions
01788  * @{
01789  */
01790 /* Timer PWM functions ********************************************************/
01791 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01792 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01793 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01794 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01795 /* Blocking mode: Polling */
01796 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01797 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01798 /* Non-Blocking mode: Interrupt */
01799 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01800 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01801 /* Non-Blocking mode: DMA */
01802 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01803 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01804 /**
01805   * @}
01806   */
01807 
01808 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
01809  *  @brief    Time Input Capture functions
01810  * @{
01811  */
01812 /* Timer Input Capture functions **********************************************/
01813 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01814 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01815 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01816 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01817 /* Blocking mode: Polling */
01818 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01819 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01820 /* Non-Blocking mode: Interrupt */
01821 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01822 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01823 /* Non-Blocking mode: DMA */
01824 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01825 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01826 /**
01827   * @}
01828   */
01829 
01830 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
01831  *  @brief    Time One Pulse functions
01832  * @{
01833  */
01834 /* Timer One Pulse functions **************************************************/
01835 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01836 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01837 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01838 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01839 /* Blocking mode: Polling */
01840 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01841 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01842 /* Non-Blocking mode: Interrupt */
01843 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01844 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01845 /**
01846   * @}
01847   */
01848 
01849 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
01850  *  @brief    Time Encoder functions
01851  * @{
01852  */
01853 /* Timer Encoder functions ****************************************************/
01854 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01855 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01856 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01857 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01858  /* Blocking mode: Polling */
01859 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01860 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01861 /* Non-Blocking mode: Interrupt */
01862 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01863 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01864 /* Non-Blocking mode: DMA */
01865 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01866 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01867 /**
01868   * @}
01869   */
01870 
01871 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
01872  *  @brief    IRQ handler management
01873   * @{
01874   */
01875 /* Interrupt Handler functions  ***********************************************/
01876 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01877 /**
01878   * @}
01879   */
01880 
01881 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
01882  *  @brief      Peripheral Control functions
01883   * @{
01884   */
01885 /* Control functions  *********************************************************/
01886 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01887 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01888 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01889 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01890 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01891 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01892 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01893 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01895 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01896                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01897 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01898 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01899                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01900 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01901 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01902 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01903 /**
01904   * @}
01905   */
01906 
01907 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
01908  *  @brief    TIM Callbacks functions
01909   * @{
01910   */
01911 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01912 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01913 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01914 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01915 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01916 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01917 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01918 /**
01919   * @}
01920   */
01921 
01922 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
01923  *  @brief   Peripheral State functions
01924  * @{
01925  */
01926 /* Peripheral State functions  ************************************************/
01927 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01928 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01929 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01930 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01931 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01932 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01933 /**
01934   * @}
01935   */
01936 
01937 /**
01938   * @}
01939   */
01940 /* End of exported functions -------------------------------------------------*/
01941 
01942 /* Private functions----------------------------------------------------------*/
01943 /** @defgroup TIM_Private_Functions TIM Private Functions
01944 * @{
01945 */
01946 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01947 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01948 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01949 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
01950                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
01951 
01952 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01953 void TIM_DMAError(DMA_HandleTypeDef *hdma);
01954 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01955 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01956 /**
01957 * @}
01958 */ 
01959 /* End of private functions --------------------------------------------------*/
01960 
01961 /**
01962   * @}
01963   */
01964 
01965 /**
01966   * @}
01967   */
01968 
01969 #ifdef __cplusplus
01970 }
01971 #endif
01972 
01973 #endif /* __STM32L4xx_HAL_TIM_H */
01974 
01975 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/