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HAL_L476/stm32l4xx_hal_adc.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:: elmot
Date:: Fri Feb 24 21:13:56 2017 +0000
Revision:: 1:d0dfbce63a89

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elmot	1:d0dfbce63a89	1	/**
elmot	1:d0dfbce63a89	2	******************************************************************************
elmot	1:d0dfbce63a89	3	* @file stm32l4xx_hal_adc.c
elmot	1:d0dfbce63a89	4	* @author MCD Application conversion
elmot	1:d0dfbce63a89	5	* @version V1.5.1
elmot	1:d0dfbce63a89	6	* @date 31-May-2016
elmot	1:d0dfbce63a89	7	* @brief This file provides firmware functions to manage the following
elmot	1:d0dfbce63a89	8	* functionalities of the Analog to Digital Convertor (ADC)
elmot	1:d0dfbce63a89	9	* peripheral:
elmot	1:d0dfbce63a89	10	* + Initialization and de-initialization functions
elmot	1:d0dfbce63a89	11	* ++ Configuration of ADC
elmot	1:d0dfbce63a89	12	* + Operation functions
elmot	1:d0dfbce63a89	13	* ++ Start, stop, get result of regular conversions of regular
elmot	1:d0dfbce63a89	14	* using 3 possible modes: polling, interruption or DMA.
elmot	1:d0dfbce63a89	15	* + Control functions
elmot	1:d0dfbce63a89	16	* ++ Analog Watchdog configuration
elmot	1:d0dfbce63a89	17	* ++ Channels configuration on regular group
elmot	1:d0dfbce63a89	18	* + State functions
elmot	1:d0dfbce63a89	19	* ++ ADC state machine management
elmot	1:d0dfbce63a89	20	* ++ Interrupts and flags management
elmot	1:d0dfbce63a89	21	*
elmot	1:d0dfbce63a89	22	@verbatim
elmot	1:d0dfbce63a89	23	==============================================================================
elmot	1:d0dfbce63a89	24	##### ADC specific features #####
elmot	1:d0dfbce63a89	25	==============================================================================
elmot	1:d0dfbce63a89	26	[..]
elmot	1:d0dfbce63a89	27	(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
elmot	1:d0dfbce63a89	28
elmot	1:d0dfbce63a89	29	(#) Interrupt generation at the end of regular conversion and in case of
elmot	1:d0dfbce63a89	30	analog watchdog and overrun events.
elmot	1:d0dfbce63a89	31
elmot	1:d0dfbce63a89	32	(#) Single and continuous conversion modes.
elmot	1:d0dfbce63a89	33
elmot	1:d0dfbce63a89	34	(#) Scan mode for automatic conversion of channel 0 to channel 'n'.
elmot	1:d0dfbce63a89	35
elmot	1:d0dfbce63a89	36	(#) Data alignment with in-built data coherency.
elmot	1:d0dfbce63a89	37
elmot	1:d0dfbce63a89	38	(#) Channel-wise programmable sampling time.
elmot	1:d0dfbce63a89	39
elmot	1:d0dfbce63a89	40	(#) External trigger (timer or EXTI) with configurable polarity for
elmot	1:d0dfbce63a89	41	regular groups.
elmot	1:d0dfbce63a89	42
elmot	1:d0dfbce63a89	43	(#) DMA request generation for transfer of regular group converted data.
elmot	1:d0dfbce63a89	44
elmot	1:d0dfbce63a89	45	(#) Configurable delay between conversions in Dual interleaved mode.
elmot	1:d0dfbce63a89	46
elmot	1:d0dfbce63a89	47	(#) ADC channels selectable single/differential input.
elmot	1:d0dfbce63a89	48
elmot	1:d0dfbce63a89	49	(#) ADC offset on regular groups.
elmot	1:d0dfbce63a89	50
elmot	1:d0dfbce63a89	51	(#) ADC supply requirements: 1.62 V to 3.6 V.
elmot	1:d0dfbce63a89	52
elmot	1:d0dfbce63a89	53	(#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to
elmot	1:d0dfbce63a89	54	Vdda or to an external voltage reference).
elmot	1:d0dfbce63a89	55
elmot	1:d0dfbce63a89	56
elmot	1:d0dfbce63a89	57
elmot	1:d0dfbce63a89	58	##### How to use this driver #####
elmot	1:d0dfbce63a89	59	==============================================================================
elmot	1:d0dfbce63a89	60	[..]
elmot	1:d0dfbce63a89	61
elmot	1:d0dfbce63a89	62	(#) Enable the ADC interface
elmot	1:d0dfbce63a89	63	As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be
elmot	1:d0dfbce63a89	64	configured at RCC top level.
elmot	1:d0dfbce63a89	65
elmot	1:d0dfbce63a89	66	Two different clock sources are available:
elmot	1:d0dfbce63a89	67	(++) - the ADC clock can be a specific clock source, coming from the system
elmot	1:d0dfbce63a89	68	clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
elmot	1:d0dfbce63a89	69	(++) - or the ADC clock can be derived from the AHB clock of the ADC bus
elmot	1:d0dfbce63a89	70	interface, divided by a programmable factor
elmot	1:d0dfbce63a89	71
elmot	1:d0dfbce63a89	72
elmot	1:d0dfbce63a89	73	(++) For example, in case of PLLSAI2:
elmot	1:d0dfbce63a89	74	(+++) __HAL_RCC_ADC_CLK_ENABLE();
elmot	1:d0dfbce63a89	75	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
elmot	1:d0dfbce63a89	76	(+++) where
elmot	1:d0dfbce63a89	77	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
elmot	1:d0dfbce63a89	78	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI2
elmot	1:d0dfbce63a89	79
elmot	1:d0dfbce63a89	80
elmot	1:d0dfbce63a89	81	(#) ADC pins configuration
elmot	1:d0dfbce63a89	82	(++) Enable the clock for the ADC GPIOs using the following function:
elmot	1:d0dfbce63a89	83	__HAL_RCC_GPIOx_CLK_ENABLE();
elmot	1:d0dfbce63a89	84	(++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
elmot	1:d0dfbce63a89	85
elmot	1:d0dfbce63a89	86	(#) Configure the ADC parameters (conversion resolution, data alignment,
elmot	1:d0dfbce63a89	87	continuous mode, ...) using the HAL_ADC_Init() function.
elmot	1:d0dfbce63a89	88
elmot	1:d0dfbce63a89	89	(#) Optionally, perform an automatic ADC calibration to improve the
elmot	1:d0dfbce63a89	90	conversion accuracy using function HAL_ADCEx_Calibration_Start().
elmot	1:d0dfbce63a89	91
elmot	1:d0dfbce63a89	92	(#) Activate the ADC peripheral using one of the start functions:
elmot	1:d0dfbce63a89	93	HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
elmot	1:d0dfbce63a89	94	HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
elmot	1:d0dfbce63a89	95	HAL_ADCEx_MultiModeStart_DMA() when multimode feature is available.
elmot	1:d0dfbce63a89	96
elmot	1:d0dfbce63a89	97	* Channels to regular group configuration *
elmot	1:d0dfbce63a89	98	============================================
elmot	1:d0dfbce63a89	99	[..]
elmot	1:d0dfbce63a89	100	(+) To configure the ADC regular group features, use
elmot	1:d0dfbce63a89	101	HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
elmot	1:d0dfbce63a89	102	(+) To activate the continuous mode, use the HAL_ADC_Init() function.
elmot	1:d0dfbce63a89	103	(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
elmot	1:d0dfbce63a89	104
elmot	1:d0dfbce63a89	105	* DMA for regular configuration *
elmot	1:d0dfbce63a89	106	=============================================================
elmot	1:d0dfbce63a89	107	[..]
elmot	1:d0dfbce63a89	108	(+) To enable the DMA mode for regular group, use the
elmot	1:d0dfbce63a89	109	HAL_ADC_Start_DMA() function.
elmot	1:d0dfbce63a89	110	(+) To enable the generation of DMA requests continuously at the end of
elmot	1:d0dfbce63a89	111	the last DMA transfer, resort to DMAContinuousRequests parameter of
elmot	1:d0dfbce63a89	112	ADC handle initialization structure.
elmot	1:d0dfbce63a89	113
elmot	1:d0dfbce63a89	114
elmot	1:d0dfbce63a89	115
elmot	1:d0dfbce63a89	116	@endverbatim
elmot	1:d0dfbce63a89	117	******************************************************************************
elmot	1:d0dfbce63a89	118	* @attention
elmot	1:d0dfbce63a89	119	*
elmot	1:d0dfbce63a89	120	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot	1:d0dfbce63a89	121	*
elmot	1:d0dfbce63a89	122	* Redistribution and use in source and binary forms, with or without modification,
elmot	1:d0dfbce63a89	123	* are permitted provided that the following conditions are met:
elmot	1:d0dfbce63a89	124	* 1. Redistributions of source code must retain the above copyright notice,
elmot	1:d0dfbce63a89	125	* this list of conditions and the following disclaimer.
elmot	1:d0dfbce63a89	126	* 2. Redistributions in binary form must reproduce the above copyright notice,
elmot	1:d0dfbce63a89	127	* this list of conditions and the following disclaimer in the documentation
elmot	1:d0dfbce63a89	128	* and/or other materials provided with the distribution.
elmot	1:d0dfbce63a89	129	* 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot	1:d0dfbce63a89	130	* may be used to endorse or promote products derived from this software
elmot	1:d0dfbce63a89	131	* without specific prior written permission.
elmot	1:d0dfbce63a89	132	*
elmot	1:d0dfbce63a89	133	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot	1:d0dfbce63a89	134	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot	1:d0dfbce63a89	135	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot	1:d0dfbce63a89	136	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot	1:d0dfbce63a89	137	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot	1:d0dfbce63a89	138	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot	1:d0dfbce63a89	139	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot	1:d0dfbce63a89	140	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot	1:d0dfbce63a89	141	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot	1:d0dfbce63a89	142	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot	1:d0dfbce63a89	143	*
elmot	1:d0dfbce63a89	144	******************************************************************************
elmot	1:d0dfbce63a89	145	*/
elmot	1:d0dfbce63a89	146
elmot	1:d0dfbce63a89	147	/* Includes ------------------------------------------------------------------*/
elmot	1:d0dfbce63a89	148	#include "stm32l4xx_hal.h"
elmot	1:d0dfbce63a89	149
elmot	1:d0dfbce63a89	150	/** @addtogroup STM32L4xx_HAL_Driver
elmot	1:d0dfbce63a89	151	* @{
elmot	1:d0dfbce63a89	152	*/
elmot	1:d0dfbce63a89	153
elmot	1:d0dfbce63a89	154	/** @defgroup ADC ADC
elmot	1:d0dfbce63a89	155	* @brief ADC HAL module driver
elmot	1:d0dfbce63a89	156	* @{
elmot	1:d0dfbce63a89	157	*/
elmot	1:d0dfbce63a89	158
elmot	1:d0dfbce63a89	159	#ifdef HAL_ADC_MODULE_ENABLED
elmot	1:d0dfbce63a89	160
elmot	1:d0dfbce63a89	161	/* Private typedef -----------------------------------------------------------*/
elmot	1:d0dfbce63a89	162	/* Private define ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	163
elmot	1:d0dfbce63a89	164	/** @defgroup ADC_Private_Constants ADC Private Constants
elmot	1:d0dfbce63a89	165	* @{
elmot	1:d0dfbce63a89	166	*/
elmot	1:d0dfbce63a89	167
elmot	1:d0dfbce63a89	168	#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES \| ADC_CFGR_ALIGN \|\
elmot	1:d0dfbce63a89	169	ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
elmot	1:d0dfbce63a89	170	ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM \|\
elmot	1:d0dfbce63a89	171	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
elmot	1:d0dfbce63a89	172	when no regular conversion is on-going */
elmot	1:d0dfbce63a89	173
elmot	1:d0dfbce63a89	174	#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE \| ADC_CFGR2_OVSR \|\
elmot	1:d0dfbce63a89	175	ADC_CFGR2_OVSS \| ADC_CFGR2_TROVS \|\
elmot	1:d0dfbce63a89	176	ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
elmot	1:d0dfbce63a89	177	(neither regular nor injected) is on-going */
elmot	1:d0dfbce63a89	178
elmot	1:d0dfbce63a89	179	#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN \| \
elmot	1:d0dfbce63a89	180	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
elmot	1:d0dfbce63a89	181	conversion (neither regular nor injected) is on-going */
elmot	1:d0dfbce63a89	182
elmot	1:d0dfbce63a89	183	#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
elmot	1:d0dfbce63a89	184	(neither regular nor injected) is on-going */
elmot	1:d0dfbce63a89	185
elmot	1:d0dfbce63a89	186
elmot	1:d0dfbce63a89	187
elmot	1:d0dfbce63a89	188	/* Delay to wait before setting ADEN once ADCAL has been reset
elmot	1:d0dfbce63a89	189	must be at least 4 ADC clock cycles.
elmot	1:d0dfbce63a89	190	Assuming lowest ADC clock (140 KHz according to DS), this
elmot	1:d0dfbce63a89	191	4 ADC clock cycles duration is equal to
elmot	1:d0dfbce63a89	192	4 / 140,000 = 0.028 ms.
elmot	1:d0dfbce63a89	193	ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
elmot	1:d0dfbce63a89	194	the 4 ADC clock cycles have elapsed while waiting for ADRDY
elmot	1:d0dfbce63a89	195	to become 1 */
elmot	1:d0dfbce63a89	196	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /!< ADC enable time-out value /
elmot	1:d0dfbce63a89	197	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /!< ADC disable time-out value /
elmot	1:d0dfbce63a89	198
elmot	1:d0dfbce63a89	199
elmot	1:d0dfbce63a89	200
elmot	1:d0dfbce63a89	201	/* Delay for ADC voltage regulator startup time */
elmot	1:d0dfbce63a89	202	/* Maximum delay is 10 microseconds */
elmot	1:d0dfbce63a89	203	/* (refer device RM, parameter Tadcvreg_stup). */
elmot	1:d0dfbce63a89	204	#define ADC_STAB_DELAY_US ((uint32_t) 10) /!< ADC voltage regulator startup time /
elmot	1:d0dfbce63a89	205
elmot	1:d0dfbce63a89	206
elmot	1:d0dfbce63a89	207	/* Timeout to wait for current conversion on going to be completed. */
elmot	1:d0dfbce63a89	208	/* Timeout fixed to worst case, for 1 channel. */
elmot	1:d0dfbce63a89	209	/* - maximum sampling time (640.5 adc_clk) */
elmot	1:d0dfbce63a89	210	/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
elmot	1:d0dfbce63a89	211	/* - ADC clock with prescaler 256 */
elmot	1:d0dfbce63a89	212	/* 653 * 256 = 167168 clock cycles max */
elmot	1:d0dfbce63a89	213	/* Unit: cycles of CPU clock. */
elmot	1:d0dfbce63a89	214	#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168) /!< ADC conversion completion time-out value /
elmot	1:d0dfbce63a89	215
elmot	1:d0dfbce63a89	216
elmot	1:d0dfbce63a89	217
elmot	1:d0dfbce63a89	218
elmot	1:d0dfbce63a89	219	/**
elmot	1:d0dfbce63a89	220	* @}
elmot	1:d0dfbce63a89	221	*/
elmot	1:d0dfbce63a89	222
elmot	1:d0dfbce63a89	223	/* Private macro -------------------------------------------------------------*/
elmot	1:d0dfbce63a89	224	/* Private variables ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	225	/* Private function prototypes -----------------------------------------------*/
elmot	1:d0dfbce63a89	226	/* Exported functions --------------------------------------------------------*/
elmot	1:d0dfbce63a89	227
elmot	1:d0dfbce63a89	228	/** @defgroup ADC_Exported_Functions ADC Exported Functions
elmot	1:d0dfbce63a89	229	* @{
elmot	1:d0dfbce63a89	230	*/
elmot	1:d0dfbce63a89	231
elmot	1:d0dfbce63a89	232	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
elmot	1:d0dfbce63a89	233	* @brief Initialization and Configuration functions
elmot	1:d0dfbce63a89	234	*
elmot	1:d0dfbce63a89	235	@verbatim
elmot	1:d0dfbce63a89	236	===============================================================================
elmot	1:d0dfbce63a89	237	##### Initialization and de-initialization functions #####
elmot	1:d0dfbce63a89	238	===============================================================================
elmot	1:d0dfbce63a89	239	[..] This section provides functions allowing to:
elmot	1:d0dfbce63a89	240	(+) Initialize and configure the ADC.
elmot	1:d0dfbce63a89	241	(+) De-initialize the ADC.
elmot	1:d0dfbce63a89	242
elmot	1:d0dfbce63a89	243	@endverbatim
elmot	1:d0dfbce63a89	244	* @{
elmot	1:d0dfbce63a89	245	*/
elmot	1:d0dfbce63a89	246
elmot	1:d0dfbce63a89	247	/**
elmot	1:d0dfbce63a89	248	* @brief Initialize the ADC peripheral and regular group according to
elmot	1:d0dfbce63a89	249	* parameters specified in structure "ADC_InitTypeDef".
elmot	1:d0dfbce63a89	250	* @note As prerequisite, ADC clock must be configured at RCC top level
elmot	1:d0dfbce63a89	251	* depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks
elmot	1:d0dfbce63a89	252	* or AHB clock.
elmot	1:d0dfbce63a89	253	* @note Possibility to update parameters on the fly:
elmot	1:d0dfbce63a89	254	* this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
elmot	1:d0dfbce63a89	255	* coming from ADC state reset. Following calls to this function can
elmot	1:d0dfbce63a89	256	* be used to reconfigure some parameters of ADC_InitTypeDef
elmot	1:d0dfbce63a89	257	* structure on the fly, without modifying MSP configuration. If ADC
elmot	1:d0dfbce63a89	258	* MSP has to be modified again, HAL_ADC_DeInit() must be called
elmot	1:d0dfbce63a89	259	* before HAL_ADC_Init().
elmot	1:d0dfbce63a89	260	* The setting of these parameters is conditioned by ADC state.
elmot	1:d0dfbce63a89	261	* For parameters constraints, see comments of structure
elmot	1:d0dfbce63a89	262	* "ADC_InitTypeDef".
elmot	1:d0dfbce63a89	263	* @note This function configures the ADC within 2 scopes: scope of entire
elmot	1:d0dfbce63a89	264	* ADC and scope of regular group. For parameters details, see comments
elmot	1:d0dfbce63a89	265	* of structure "ADC_InitTypeDef".
elmot	1:d0dfbce63a89	266	* @note Parameters related to common ADC registers (ADC clock mode) are set
elmot	1:d0dfbce63a89	267	* only if all ADCs are disabled.
elmot	1:d0dfbce63a89	268	* If this is not the case, these common parameters setting are
elmot	1:d0dfbce63a89	269	* bypassed without error reporting: it can be the intended behaviour in
elmot	1:d0dfbce63a89	270	* case of update of a parameter of ADC_InitTypeDef on the fly,
elmot	1:d0dfbce63a89	271	* without disabling the other ADCs.
elmot	1:d0dfbce63a89	272	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	273	* @retval HAL status
elmot	1:d0dfbce63a89	274	*/
elmot	1:d0dfbce63a89	275	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	276	{
elmot	1:d0dfbce63a89	277	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	278
elmot	1:d0dfbce63a89	279	ADC_Common_TypeDef *tmpADC_Common;
elmot	1:d0dfbce63a89	280	uint32_t tmpCFGR = 0;
elmot	1:d0dfbce63a89	281	__IO uint32_t wait_loop_index = 0;
elmot	1:d0dfbce63a89	282
elmot	1:d0dfbce63a89	283	/* Check ADC handle */
elmot	1:d0dfbce63a89	284	if(hadc == NULL)
elmot	1:d0dfbce63a89	285	{
elmot	1:d0dfbce63a89	286	return HAL_ERROR;
elmot	1:d0dfbce63a89	287	}
elmot	1:d0dfbce63a89	288
elmot	1:d0dfbce63a89	289	/* Check the parameters */
elmot	1:d0dfbce63a89	290	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	291	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
elmot	1:d0dfbce63a89	292	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
elmot	1:d0dfbce63a89	293	assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
elmot	1:d0dfbce63a89	294	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
elmot	1:d0dfbce63a89	295	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
elmot	1:d0dfbce63a89	296	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
elmot	1:d0dfbce63a89	297	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
elmot	1:d0dfbce63a89	298	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
elmot	1:d0dfbce63a89	299	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
elmot	1:d0dfbce63a89	300	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
elmot	1:d0dfbce63a89	301	assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
elmot	1:d0dfbce63a89	302	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
elmot	1:d0dfbce63a89	303	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
elmot	1:d0dfbce63a89	304
elmot	1:d0dfbce63a89	305	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
elmot	1:d0dfbce63a89	306	{
elmot	1:d0dfbce63a89	307	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
elmot	1:d0dfbce63a89	308	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
elmot	1:d0dfbce63a89	309
elmot	1:d0dfbce63a89	310	if (hadc->Init.DiscontinuousConvMode == ENABLE)
elmot	1:d0dfbce63a89	311	{
elmot	1:d0dfbce63a89	312	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
elmot	1:d0dfbce63a89	313	}
elmot	1:d0dfbce63a89	314	}
elmot	1:d0dfbce63a89	315
elmot	1:d0dfbce63a89	316
elmot	1:d0dfbce63a89	317	/* DISCEN and CONT bits can't be set at the same time */
elmot	1:d0dfbce63a89	318	assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
elmot	1:d0dfbce63a89	319
elmot	1:d0dfbce63a89	320
elmot	1:d0dfbce63a89	321	/* Actions performed only if ADC is coming from state reset: */
elmot	1:d0dfbce63a89	322	/* - Initialization of ADC MSP */
elmot	1:d0dfbce63a89	323	if (hadc->State == HAL_ADC_STATE_RESET)
elmot	1:d0dfbce63a89	324	{
elmot	1:d0dfbce63a89	325	/* Init the low level hardware */
elmot	1:d0dfbce63a89	326	HAL_ADC_MspInit(hadc);
elmot	1:d0dfbce63a89	327
elmot	1:d0dfbce63a89	328	/* Set ADC error code to none */
elmot	1:d0dfbce63a89	329	ADC_CLEAR_ERRORCODE(hadc);
elmot	1:d0dfbce63a89	330
elmot	1:d0dfbce63a89	331	/* Initialize Lock */
elmot	1:d0dfbce63a89	332	hadc->Lock = HAL_UNLOCKED;
elmot	1:d0dfbce63a89	333	}
elmot	1:d0dfbce63a89	334
elmot	1:d0dfbce63a89	335
elmot	1:d0dfbce63a89	336	/* - Exit from deep-power-down mode and ADC voltage regulator enable */
elmot	1:d0dfbce63a89	337	/* Exit deep power down mode if still in that state */
elmot	1:d0dfbce63a89	338	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
elmot	1:d0dfbce63a89	339	{
elmot	1:d0dfbce63a89	340	/* Exit deep power down mode */
elmot	1:d0dfbce63a89	341	CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
elmot	1:d0dfbce63a89	342
elmot	1:d0dfbce63a89	343	/* System was in deep power down mode, calibration must
elmot	1:d0dfbce63a89	344	be relaunched or a previously saved calibration factor
elmot	1:d0dfbce63a89	345	re-applied once the ADC voltage regulator is enabled */
elmot	1:d0dfbce63a89	346	}
elmot	1:d0dfbce63a89	347
elmot	1:d0dfbce63a89	348
elmot	1:d0dfbce63a89	349	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
elmot	1:d0dfbce63a89	350	{
elmot	1:d0dfbce63a89	351	/* Enable ADC internal voltage regulator */
elmot	1:d0dfbce63a89	352	SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
elmot	1:d0dfbce63a89	353
elmot	1:d0dfbce63a89	354	/* Delay for ADC stabilization time */
elmot	1:d0dfbce63a89	355	/* Wait loop initialization and execution */
elmot	1:d0dfbce63a89	356	/* Note: Variable divided by 2 to compensate partially */
elmot	1:d0dfbce63a89	357	/* CPU processing cycles. */
elmot	1:d0dfbce63a89	358	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
elmot	1:d0dfbce63a89	359	while(wait_loop_index != 0)
elmot	1:d0dfbce63a89	360	{
elmot	1:d0dfbce63a89	361	wait_loop_index--;
elmot	1:d0dfbce63a89	362	}
elmot	1:d0dfbce63a89	363	}
elmot	1:d0dfbce63a89	364
elmot	1:d0dfbce63a89	365
elmot	1:d0dfbce63a89	366
elmot	1:d0dfbce63a89	367
elmot	1:d0dfbce63a89	368	/* Verification that ADC voltage regulator is correctly enabled, whether */
elmot	1:d0dfbce63a89	369	/* or not ADC is coming from state reset (if any potential problem of */
elmot	1:d0dfbce63a89	370	/* clocking, voltage regulator would not be enabled). */
elmot	1:d0dfbce63a89	371	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
elmot	1:d0dfbce63a89	372	{
elmot	1:d0dfbce63a89	373	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	374	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	375
elmot	1:d0dfbce63a89	376	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	377	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	378
elmot	1:d0dfbce63a89	379	tmp_status = HAL_ERROR;
elmot	1:d0dfbce63a89	380	}
elmot	1:d0dfbce63a89	381
elmot	1:d0dfbce63a89	382
elmot	1:d0dfbce63a89	383	/* Configuration of ADC parameters if previous preliminary actions are */
elmot	1:d0dfbce63a89	384	/* correctly completed and if there is no conversion on going on regular */
elmot	1:d0dfbce63a89	385	/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
elmot	1:d0dfbce63a89	386	/* called to update a parameter on the fly). */
elmot	1:d0dfbce63a89	387	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
elmot	1:d0dfbce63a89	388	(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
elmot	1:d0dfbce63a89	389	{
elmot	1:d0dfbce63a89	390
elmot	1:d0dfbce63a89	391	/* Initialize the ADC state */
elmot	1:d0dfbce63a89	392	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
elmot	1:d0dfbce63a89	393
elmot	1:d0dfbce63a89	394	/* Configuration of common ADC parameters */
elmot	1:d0dfbce63a89	395
elmot	1:d0dfbce63a89	396	/* Pointer to the common control register */
elmot	1:d0dfbce63a89	397	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
elmot	1:d0dfbce63a89	398
elmot	1:d0dfbce63a89	399
elmot	1:d0dfbce63a89	400	/* Parameters update conditioned to ADC state: */
elmot	1:d0dfbce63a89	401	/* Parameters that can be updated only when ADC is disabled: */
elmot	1:d0dfbce63a89	402	/* - clock configuration */
elmot	1:d0dfbce63a89	403	if ((ADC_IS_ENABLE(hadc) == RESET) &&
elmot	1:d0dfbce63a89	404	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
elmot	1:d0dfbce63a89	405	{
elmot	1:d0dfbce63a89	406	/* Reset configuration of ADC common register CCR: */
elmot	1:d0dfbce63a89	407	/* */
elmot	1:d0dfbce63a89	408	/* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
elmot	1:d0dfbce63a89	409	/* according to adc->Init.ClockPrescaler. It selects the clock */
elmot	1:d0dfbce63a89	410	/* source and sets the clock division factor. */
elmot	1:d0dfbce63a89	411	/* */
elmot	1:d0dfbce63a89	412	/* Some parameters of this register are not reset, since they are set */
elmot	1:d0dfbce63a89	413	/* by other functions and must be kept in case of usage of this */
elmot	1:d0dfbce63a89	414	/* function on the fly (update of a parameter of ADC_InitTypeDef */
elmot	1:d0dfbce63a89	415	/* without needing to reconfigure all other ADC groups/channels */
elmot	1:d0dfbce63a89	416	/* parameters): */
elmot	1:d0dfbce63a89	417	/* - when multimode feature is available, multimode-related */
elmot	1:d0dfbce63a89	418	/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
elmot	1:d0dfbce63a89	419	/* HAL_ADCEx_MultiModeConfigChannel() ) */
elmot	1:d0dfbce63a89	420	/* - internal measurement paths: Vbat, temperature sensor, Vref */
elmot	1:d0dfbce63a89	421	/* (set into HAL_ADC_ConfigChannel() or */
elmot	1:d0dfbce63a89	422	/* HAL_ADCEx_InjectedConfigChannel() ) */
elmot	1:d0dfbce63a89	423
elmot	1:d0dfbce63a89	424	MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC\|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
elmot	1:d0dfbce63a89	425	}
elmot	1:d0dfbce63a89	426
elmot	1:d0dfbce63a89	427
elmot	1:d0dfbce63a89	428	/* Configuration of ADC: */
elmot	1:d0dfbce63a89	429	/* - resolution Init.Resolution */
elmot	1:d0dfbce63a89	430	/* - data alignment Init.DataAlign */
elmot	1:d0dfbce63a89	431	/* - external trigger to start conversion Init.ExternalTrigConv */
elmot	1:d0dfbce63a89	432	/* - external trigger polarity Init.ExternalTrigConvEdge */
elmot	1:d0dfbce63a89	433	/* - continuous conversion mode Init.ContinuousConvMode */
elmot	1:d0dfbce63a89	434	/* - overrun Init.Overrun */
elmot	1:d0dfbce63a89	435	/* - discontinuous mode Init.DiscontinuousConvMode */
elmot	1:d0dfbce63a89	436	/* - discontinuous mode channel count Init.NbrOfDiscConversion */
elmot	1:d0dfbce63a89	437	tmpCFGR = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) \|
elmot	1:d0dfbce63a89	438	hadc->Init.Overrun \|
elmot	1:d0dfbce63a89	439	hadc->Init.DataAlign \|
elmot	1:d0dfbce63a89	440	hadc->Init.Resolution \|
elmot	1:d0dfbce63a89	441	ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) \|
elmot	1:d0dfbce63a89	442	ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
elmot	1:d0dfbce63a89	443
elmot	1:d0dfbce63a89	444	/* Enable external trigger if trigger selection is different of software */
elmot	1:d0dfbce63a89	445	/* start. */
elmot	1:d0dfbce63a89	446	/* - external trigger to start conversion Init.ExternalTrigConv */
elmot	1:d0dfbce63a89	447	/* - external trigger polarity Init.ExternalTrigConvEdge */
elmot	1:d0dfbce63a89	448	/* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */
elmot	1:d0dfbce63a89	449	/* equivalent to software start. */
elmot	1:d0dfbce63a89	450	if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
elmot	1:d0dfbce63a89	451	&& (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
elmot	1:d0dfbce63a89	452	{
elmot	1:d0dfbce63a89	453	tmpCFGR \|= ( hadc->Init.ExternalTrigConv \| hadc->Init.ExternalTrigConvEdge);
elmot	1:d0dfbce63a89	454	}
elmot	1:d0dfbce63a89	455
elmot	1:d0dfbce63a89	456	/* Update Configuration Register CFGR */
elmot	1:d0dfbce63a89	457	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
elmot	1:d0dfbce63a89	458
elmot	1:d0dfbce63a89	459
elmot	1:d0dfbce63a89	460	/* Parameters update conditioned to ADC state: */
elmot	1:d0dfbce63a89	461	/* Parameters that can be updated when ADC is disabled or enabled without */
elmot	1:d0dfbce63a89	462	/* conversion on going on regular and injected groups: */
elmot	1:d0dfbce63a89	463	/* - DMA continuous request Init.DMAContinuousRequests */
elmot	1:d0dfbce63a89	464	/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
elmot	1:d0dfbce63a89	465	/* - Oversampling parameters Init.Oversampling */
elmot	1:d0dfbce63a89	466	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
elmot	1:d0dfbce63a89	467	{
elmot	1:d0dfbce63a89	468	tmpCFGR = ( ADC_CFGR_DFSDM(hadc) \|
elmot	1:d0dfbce63a89	469	ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) \|
elmot	1:d0dfbce63a89	470	ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
elmot	1:d0dfbce63a89	471
elmot	1:d0dfbce63a89	472	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
elmot	1:d0dfbce63a89	473
elmot	1:d0dfbce63a89	474
elmot	1:d0dfbce63a89	475	if (hadc->Init.OversamplingMode == ENABLE)
elmot	1:d0dfbce63a89	476	{
elmot	1:d0dfbce63a89	477	assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
elmot	1:d0dfbce63a89	478	assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
elmot	1:d0dfbce63a89	479	assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
elmot	1:d0dfbce63a89	480	assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
elmot	1:d0dfbce63a89	481
elmot	1:d0dfbce63a89	482	if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
elmot	1:d0dfbce63a89	483	\|\| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
elmot	1:d0dfbce63a89	484	{
elmot	1:d0dfbce63a89	485	/* Multi trigger is not applicable to software-triggered conversions */
elmot	1:d0dfbce63a89	486	assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
elmot	1:d0dfbce63a89	487	}
elmot	1:d0dfbce63a89	488
elmot	1:d0dfbce63a89	489
elmot	1:d0dfbce63a89	490	/* Configuration of Oversampler: */
elmot	1:d0dfbce63a89	491	/* - Oversampling Ratio */
elmot	1:d0dfbce63a89	492	/* - Right bit shift */
elmot	1:d0dfbce63a89	493	/* - Triggered mode */
elmot	1:d0dfbce63a89	494	/* - Oversampling mode (continued/resumed) */
elmot	1:d0dfbce63a89	495	MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
elmot	1:d0dfbce63a89	496	ADC_CFGR2_ROVSE \|
elmot	1:d0dfbce63a89	497	hadc->Init.Oversampling.Ratio \|
elmot	1:d0dfbce63a89	498	hadc->Init.Oversampling.RightBitShift \|
elmot	1:d0dfbce63a89	499	hadc->Init.Oversampling.TriggeredMode \|
elmot	1:d0dfbce63a89	500	hadc->Init.Oversampling.OversamplingStopReset);
elmot	1:d0dfbce63a89	501	}
elmot	1:d0dfbce63a89	502	else
elmot	1:d0dfbce63a89	503	{
elmot	1:d0dfbce63a89	504	/* Disable Regular OverSampling */
elmot	1:d0dfbce63a89	505	CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
elmot	1:d0dfbce63a89	506	}
elmot	1:d0dfbce63a89	507
elmot	1:d0dfbce63a89	508
elmot	1:d0dfbce63a89	509	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
elmot	1:d0dfbce63a89	510
elmot	1:d0dfbce63a89	511
elmot	1:d0dfbce63a89	512
elmot	1:d0dfbce63a89	513
elmot	1:d0dfbce63a89	514	/* Configuration of regular group sequencer: */
elmot	1:d0dfbce63a89	515	/* - if scan mode is disabled, regular channels sequence length is set to */
elmot	1:d0dfbce63a89	516	/* 0x00: 1 channel converted (channel on regular rank 1) */
elmot	1:d0dfbce63a89	517	/* Parameter "NbrOfConversion" is discarded. */
elmot	1:d0dfbce63a89	518	/* Note: Scan mode is not present by hardware on this device, but */
elmot	1:d0dfbce63a89	519	/* emulated by software for alignment over all STM32 devices. */
elmot	1:d0dfbce63a89	520	/* - if scan mode is enabled, regular channels sequence length is set to */
elmot	1:d0dfbce63a89	521	/* parameter "NbrOfConversion" */
elmot	1:d0dfbce63a89	522
elmot	1:d0dfbce63a89	523	if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
elmot	1:d0dfbce63a89	524	{
elmot	1:d0dfbce63a89	525	/* Set number of ranks in regular group sequencer */
elmot	1:d0dfbce63a89	526	MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
elmot	1:d0dfbce63a89	527	}
elmot	1:d0dfbce63a89	528	else
elmot	1:d0dfbce63a89	529	{
elmot	1:d0dfbce63a89	530	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
elmot	1:d0dfbce63a89	531	}
elmot	1:d0dfbce63a89	532
elmot	1:d0dfbce63a89	533
elmot	1:d0dfbce63a89	534	/* Initialize the ADC state */
elmot	1:d0dfbce63a89	535	/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	536	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	537	}
elmot	1:d0dfbce63a89	538	else
elmot	1:d0dfbce63a89	539	{
elmot	1:d0dfbce63a89	540	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	541	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	542
elmot	1:d0dfbce63a89	543	tmp_status = HAL_ERROR;
elmot	1:d0dfbce63a89	544	} /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */
elmot	1:d0dfbce63a89	545
elmot	1:d0dfbce63a89	546
elmot	1:d0dfbce63a89	547	/* Return function status */
elmot	1:d0dfbce63a89	548	return tmp_status;
elmot	1:d0dfbce63a89	549
elmot	1:d0dfbce63a89	550	}
elmot	1:d0dfbce63a89	551
elmot	1:d0dfbce63a89	552	/**
elmot	1:d0dfbce63a89	553	* @brief Deinitialize the ADC peripheral registers to their default reset
elmot	1:d0dfbce63a89	554	* values, with deinitialization of the ADC MSP.
elmot	1:d0dfbce63a89	555	* @note Keep in mind that all ADCs use the same clock: disabling
elmot	1:d0dfbce63a89	556	* the clock will reset all ADCs.
elmot	1:d0dfbce63a89	557	* @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
elmot	1:d0dfbce63a89	558	* reducing the leakage currents and is particularly interesting before
elmot	1:d0dfbce63a89	559	* entering STOP 1 or STOP 2 modes.
elmot	1:d0dfbce63a89	560	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	561	* @retval HAL status
elmot	1:d0dfbce63a89	562	*/
elmot	1:d0dfbce63a89	563	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	564	{
elmot	1:d0dfbce63a89	565	/* Check ADC handle */
elmot	1:d0dfbce63a89	566	if(hadc == NULL)
elmot	1:d0dfbce63a89	567	{
elmot	1:d0dfbce63a89	568	return HAL_ERROR;
elmot	1:d0dfbce63a89	569	}
elmot	1:d0dfbce63a89	570
elmot	1:d0dfbce63a89	571	/* Check the parameters */
elmot	1:d0dfbce63a89	572	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	573
elmot	1:d0dfbce63a89	574	/* Change ADC state */
elmot	1:d0dfbce63a89	575	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
elmot	1:d0dfbce63a89	576
elmot	1:d0dfbce63a89	577	/* Stop potential conversion on going, on regular and injected groups */
elmot	1:d0dfbce63a89	578	/* No check on ADC_ConversionStop() return status, if the conversion
elmot	1:d0dfbce63a89	579	stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
elmot	1:d0dfbce63a89	580	ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
elmot	1:d0dfbce63a89	581
elmot	1:d0dfbce63a89	582
elmot	1:d0dfbce63a89	583	/* Disable ADC peripheral if conversions are effectively stopped */
elmot	1:d0dfbce63a89	584	/* Flush register JSQR: reset the queue sequencer when injected */
elmot	1:d0dfbce63a89	585	/* queue sequencer is enabled and ADC disabled. */
elmot	1:d0dfbce63a89	586	/* The software and hardware triggers of the injected sequence are both */
elmot	1:d0dfbce63a89	587	/* internally disabled just after the completion of the last valid */
elmot	1:d0dfbce63a89	588	/* injected sequence. */
elmot	1:d0dfbce63a89	589	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
elmot	1:d0dfbce63a89	590
elmot	1:d0dfbce63a89	591	/* Disable the ADC peripheral */
elmot	1:d0dfbce63a89	592	/* No check on ADC_Disable() return status, if the ADC disabling process
elmot	1:d0dfbce63a89	593	failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
elmot	1:d0dfbce63a89	594	ADC_Disable(hadc);
elmot	1:d0dfbce63a89	595
elmot	1:d0dfbce63a89	596
elmot	1:d0dfbce63a89	597	/* ========== Reset ADC registers ========== */
elmot	1:d0dfbce63a89	598	/* Reset register IER */
elmot	1:d0dfbce63a89	599	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 \| ADC_IT_AWD2 \| ADC_IT_AWD1 \|
elmot	1:d0dfbce63a89	600	ADC_IT_JQOVF \| ADC_IT_OVR \|
elmot	1:d0dfbce63a89	601	ADC_IT_JEOS \| ADC_IT_JEOC \|
elmot	1:d0dfbce63a89	602	ADC_IT_EOS \| ADC_IT_EOC \|
elmot	1:d0dfbce63a89	603	ADC_IT_EOSMP \| ADC_IT_RDY ) );
elmot	1:d0dfbce63a89	604
elmot	1:d0dfbce63a89	605	/* Reset register ISR */
elmot	1:d0dfbce63a89	606	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD1 \|
elmot	1:d0dfbce63a89	607	ADC_FLAG_JQOVF \| ADC_FLAG_OVR \|
elmot	1:d0dfbce63a89	608	ADC_FLAG_JEOS \| ADC_FLAG_JEOC \|
elmot	1:d0dfbce63a89	609	ADC_FLAG_EOS \| ADC_FLAG_EOC \|
elmot	1:d0dfbce63a89	610	ADC_FLAG_EOSMP \| ADC_FLAG_RDY ) );
elmot	1:d0dfbce63a89	611
elmot	1:d0dfbce63a89	612	/* Reset register CR */
elmot	1:d0dfbce63a89	613	/* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
elmot	1:d0dfbce63a89	614	ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
elmot	1:d0dfbce63a89	615	no direct reset applicable.
elmot	1:d0dfbce63a89	616	Update CR register to reset value where doable by software */
elmot	1:d0dfbce63a89	617	CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN \| ADC_CR_ADCALDIF);
elmot	1:d0dfbce63a89	618	SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
elmot	1:d0dfbce63a89	619
elmot	1:d0dfbce63a89	620	/* Reset register CFGR */
elmot	1:d0dfbce63a89	621	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
elmot	1:d0dfbce63a89	622	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
elmot	1:d0dfbce63a89	623
elmot	1:d0dfbce63a89	624	/* Reset register CFGR2 */
elmot	1:d0dfbce63a89	625	CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM \| ADC_CFGR2_TROVS \| ADC_CFGR2_OVSS \|
elmot	1:d0dfbce63a89	626	ADC_CFGR2_OVSR \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE );
elmot	1:d0dfbce63a89	627
elmot	1:d0dfbce63a89	628	/* Reset register SMPR1 */
elmot	1:d0dfbce63a89	629	CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
elmot	1:d0dfbce63a89	630
elmot	1:d0dfbce63a89	631	/* Reset register SMPR2 */
elmot	1:d0dfbce63a89	632	CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 \| ADC_SMPR2_SMP17 \| ADC_SMPR2_SMP16 \|
elmot	1:d0dfbce63a89	633	ADC_SMPR2_SMP15 \| ADC_SMPR2_SMP14 \| ADC_SMPR2_SMP13 \|
elmot	1:d0dfbce63a89	634	ADC_SMPR2_SMP12 \| ADC_SMPR2_SMP11 \| ADC_SMPR2_SMP10 );
elmot	1:d0dfbce63a89	635
elmot	1:d0dfbce63a89	636	/* Reset register TR1 */
elmot	1:d0dfbce63a89	637	CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1);
elmot	1:d0dfbce63a89	638
elmot	1:d0dfbce63a89	639	/* Reset register TR2 */
elmot	1:d0dfbce63a89	640	CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2);
elmot	1:d0dfbce63a89	641
elmot	1:d0dfbce63a89	642	/* Reset register TR3 */
elmot	1:d0dfbce63a89	643	CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3);
elmot	1:d0dfbce63a89	644
elmot	1:d0dfbce63a89	645	/* Reset register SQR1 */
elmot	1:d0dfbce63a89	646	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 \| ADC_SQR1_SQ3 \| ADC_SQR1_SQ2 \|
elmot	1:d0dfbce63a89	647	ADC_SQR1_SQ1 \| ADC_SQR1_L);
elmot	1:d0dfbce63a89	648
elmot	1:d0dfbce63a89	649	/* Reset register SQR2 */
elmot	1:d0dfbce63a89	650	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 \|
elmot	1:d0dfbce63a89	651	ADC_SQR2_SQ6 \| ADC_SQR2_SQ5);
elmot	1:d0dfbce63a89	652
elmot	1:d0dfbce63a89	653	/* Reset register SQR3 */
elmot	1:d0dfbce63a89	654	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 \| ADC_SQR3_SQ13 \| ADC_SQR3_SQ12 \|
elmot	1:d0dfbce63a89	655	ADC_SQR3_SQ11 \| ADC_SQR3_SQ10);
elmot	1:d0dfbce63a89	656
elmot	1:d0dfbce63a89	657	/* Reset register SQR4 */
elmot	1:d0dfbce63a89	658	CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 \| ADC_SQR4_SQ15);
elmot	1:d0dfbce63a89	659
elmot	1:d0dfbce63a89	660	/* Register JSQR was reset when the ADC was disabled */
elmot	1:d0dfbce63a89	661
elmot	1:d0dfbce63a89	662	/* Reset register DR */
elmot	1:d0dfbce63a89	663	/* bits in access mode read only, no direct reset applicable*/
elmot	1:d0dfbce63a89	664
elmot	1:d0dfbce63a89	665	/* Reset register OFR1 */
elmot	1:d0dfbce63a89	666	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1);
elmot	1:d0dfbce63a89	667	/* Reset register OFR2 */
elmot	1:d0dfbce63a89	668	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN \| ADC_OFR2_OFFSET2_CH \| ADC_OFR2_OFFSET2);
elmot	1:d0dfbce63a89	669	/* Reset register OFR3 */
elmot	1:d0dfbce63a89	670	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN \| ADC_OFR3_OFFSET3_CH \| ADC_OFR3_OFFSET3);
elmot	1:d0dfbce63a89	671	/* Reset register OFR4 */
elmot	1:d0dfbce63a89	672	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN \| ADC_OFR4_OFFSET4_CH \| ADC_OFR4_OFFSET4);
elmot	1:d0dfbce63a89	673
elmot	1:d0dfbce63a89	674	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
elmot	1:d0dfbce63a89	675	/* bits in access mode read only, no direct reset applicable*/
elmot	1:d0dfbce63a89	676
elmot	1:d0dfbce63a89	677	/* Reset register AWD2CR */
elmot	1:d0dfbce63a89	678	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
elmot	1:d0dfbce63a89	679
elmot	1:d0dfbce63a89	680	/* Reset register AWD3CR */
elmot	1:d0dfbce63a89	681	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
elmot	1:d0dfbce63a89	682
elmot	1:d0dfbce63a89	683	/* Reset register DIFSEL */
elmot	1:d0dfbce63a89	684	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
elmot	1:d0dfbce63a89	685
elmot	1:d0dfbce63a89	686	/* Reset register CALFACT */
elmot	1:d0dfbce63a89	687	CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S);
elmot	1:d0dfbce63a89	688
elmot	1:d0dfbce63a89	689
elmot	1:d0dfbce63a89	690
elmot	1:d0dfbce63a89	691
elmot	1:d0dfbce63a89	692
elmot	1:d0dfbce63a89	693
elmot	1:d0dfbce63a89	694	/* ========== Reset common ADC registers ========== */
elmot	1:d0dfbce63a89	695
elmot	1:d0dfbce63a89	696	/* Software is allowed to change common parameters only when all the other
elmot	1:d0dfbce63a89	697	ADCs are disabled. */
elmot	1:d0dfbce63a89	698	if ((ADC_IS_ENABLE(hadc) == RESET) &&
elmot	1:d0dfbce63a89	699	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
elmot	1:d0dfbce63a89	700	{
elmot	1:d0dfbce63a89	701	/* Reset configuration of ADC common register CCR:
elmot	1:d0dfbce63a89	702	- clock mode: CKMODE, PRESCEN
elmot	1:d0dfbce63a89	703	- multimode related parameters (when this feature is available): MDMA,
elmot	1:d0dfbce63a89	704	DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
elmot	1:d0dfbce63a89	705	- internal measurement paths: Vbat, temperature sensor, Vref (set into
elmot	1:d0dfbce63a89	706	HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
elmot	1:d0dfbce63a89	707	*/
elmot	1:d0dfbce63a89	708	ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
elmot	1:d0dfbce63a89	709	}
elmot	1:d0dfbce63a89	710
elmot	1:d0dfbce63a89	711	/* DeInit the low level hardware.
elmot	1:d0dfbce63a89	712
elmot	1:d0dfbce63a89	713	For example:
elmot	1:d0dfbce63a89	714	__HAL_RCC_ADC_FORCE_RESET();
elmot	1:d0dfbce63a89	715	__HAL_RCC_ADC_RELEASE_RESET();
elmot	1:d0dfbce63a89	716	__HAL_RCC_ADC_CLK_DISABLE();
elmot	1:d0dfbce63a89	717
elmot	1:d0dfbce63a89	718	Keep in mind that all ADCs use the same clock: disabling
elmot	1:d0dfbce63a89	719	the clock will reset all ADCs.
elmot	1:d0dfbce63a89	720
elmot	1:d0dfbce63a89	721	*/
elmot	1:d0dfbce63a89	722	HAL_ADC_MspDeInit(hadc);
elmot	1:d0dfbce63a89	723
elmot	1:d0dfbce63a89	724	/* Set ADC error code to none */
elmot	1:d0dfbce63a89	725	ADC_CLEAR_ERRORCODE(hadc);
elmot	1:d0dfbce63a89	726
elmot	1:d0dfbce63a89	727	/* Reset injected channel configuration parameters */
elmot	1:d0dfbce63a89	728	hadc->InjectionConfig.ContextQueue = 0;
elmot	1:d0dfbce63a89	729	hadc->InjectionConfig.ChannelCount = 0;
elmot	1:d0dfbce63a89	730
elmot	1:d0dfbce63a89	731	/* Change ADC state */
elmot	1:d0dfbce63a89	732	hadc->State = HAL_ADC_STATE_RESET;
elmot	1:d0dfbce63a89	733
elmot	1:d0dfbce63a89	734	/* Process unlocked */
elmot	1:d0dfbce63a89	735	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	736
elmot	1:d0dfbce63a89	737
elmot	1:d0dfbce63a89	738	/* Return function status */
elmot	1:d0dfbce63a89	739	return HAL_OK;
elmot	1:d0dfbce63a89	740
elmot	1:d0dfbce63a89	741	}
elmot	1:d0dfbce63a89	742
elmot	1:d0dfbce63a89	743	/**
elmot	1:d0dfbce63a89	744	* @brief Initialize the ADC MSP.
elmot	1:d0dfbce63a89	745	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	746	* @retval None
elmot	1:d0dfbce63a89	747	*/
elmot	1:d0dfbce63a89	748	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	749	{
elmot	1:d0dfbce63a89	750	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	751	UNUSED(hadc);
elmot	1:d0dfbce63a89	752
elmot	1:d0dfbce63a89	753	/* NOTE : This function should not be modified. When the callback is needed,
elmot	1:d0dfbce63a89	754	function HAL_ADC_MspInit must be implemented in the user file.
elmot	1:d0dfbce63a89	755	*/
elmot	1:d0dfbce63a89	756	}
elmot	1:d0dfbce63a89	757
elmot	1:d0dfbce63a89	758	/**
elmot	1:d0dfbce63a89	759	* @brief DeInitialize the ADC MSP.
elmot	1:d0dfbce63a89	760	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	761	* @note All ADCs use the same clock: disabling the clock will reset all ADCs.
elmot	1:d0dfbce63a89	762	* @retval None
elmot	1:d0dfbce63a89	763	*/
elmot	1:d0dfbce63a89	764	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	765	{
elmot	1:d0dfbce63a89	766	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	767	UNUSED(hadc);
elmot	1:d0dfbce63a89	768
elmot	1:d0dfbce63a89	769	/* NOTE : This function should not be modified. When the callback is needed,
elmot	1:d0dfbce63a89	770	function HAL_ADC_MspDeInit must be implemented in the user file.
elmot	1:d0dfbce63a89	771	*/
elmot	1:d0dfbce63a89	772	}
elmot	1:d0dfbce63a89	773
elmot	1:d0dfbce63a89	774	/**
elmot	1:d0dfbce63a89	775	* @}
elmot	1:d0dfbce63a89	776	*/
elmot	1:d0dfbce63a89	777
elmot	1:d0dfbce63a89	778	/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
elmot	1:d0dfbce63a89	779	* @brief IO operation functions
elmot	1:d0dfbce63a89	780	*
elmot	1:d0dfbce63a89	781	@verbatim
elmot	1:d0dfbce63a89	782	===============================================================================
elmot	1:d0dfbce63a89	783	##### IO operation functions #####
elmot	1:d0dfbce63a89	784	===============================================================================
elmot	1:d0dfbce63a89	785	[..] This section provides functions allowing to:
elmot	1:d0dfbce63a89	786	(+) Start conversion of regular group.
elmot	1:d0dfbce63a89	787	(+) Stop conversion of regular group.
elmot	1:d0dfbce63a89	788	(+) Poll for conversion complete on regular group.
elmot	1:d0dfbce63a89	789	(+) Poll for conversion event.
elmot	1:d0dfbce63a89	790	(+) Get result of regular channel conversion.
elmot	1:d0dfbce63a89	791	(+) Start conversion of regular group and enable interruptions.
elmot	1:d0dfbce63a89	792	(+) Stop conversion of regular group and disable interruptions.
elmot	1:d0dfbce63a89	793	(+) Handle ADC interrupt request
elmot	1:d0dfbce63a89	794	(+) Start conversion of regular group and enable DMA transfer.
elmot	1:d0dfbce63a89	795	(+) Stop conversion of regular group and disable ADC DMA transfer.
elmot	1:d0dfbce63a89	796
elmot	1:d0dfbce63a89	797	@endverbatim
elmot	1:d0dfbce63a89	798	* @{
elmot	1:d0dfbce63a89	799	*/
elmot	1:d0dfbce63a89	800
elmot	1:d0dfbce63a89	801	/**
elmot	1:d0dfbce63a89	802	* @brief Enable ADC, start conversion of regular group.
elmot	1:d0dfbce63a89	803	* @note Interruptions enabled in this function: None.
elmot	1:d0dfbce63a89	804	* @note Case of multimode enabled (when multimode feature is available):
elmot	1:d0dfbce63a89	805	* if ADC is Slave, ADC is enabled but conversion is not started,
elmot	1:d0dfbce63a89	806	* if ADC is master, ADC is enabled and multimode conversion is started.
elmot	1:d0dfbce63a89	807	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	808	* @retval HAL status
elmot	1:d0dfbce63a89	809	*/
elmot	1:d0dfbce63a89	810	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	811	{
elmot	1:d0dfbce63a89	812	ADC_TypeDef *tmpADC_Master;
elmot	1:d0dfbce63a89	813	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	814
elmot	1:d0dfbce63a89	815	/* Check the parameters */
elmot	1:d0dfbce63a89	816	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	817
elmot	1:d0dfbce63a89	818
elmot	1:d0dfbce63a89	819	/* if a regular conversion is already on-going (i.e. ADSTART is set),
elmot	1:d0dfbce63a89	820	don't restart the conversion. */
elmot	1:d0dfbce63a89	821	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
elmot	1:d0dfbce63a89	822	{
elmot	1:d0dfbce63a89	823	return HAL_BUSY;
elmot	1:d0dfbce63a89	824	}
elmot	1:d0dfbce63a89	825	else
elmot	1:d0dfbce63a89	826	{
elmot	1:d0dfbce63a89	827	/* Process locked */
elmot	1:d0dfbce63a89	828	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	829
elmot	1:d0dfbce63a89	830	/* Enable the ADC peripheral */
elmot	1:d0dfbce63a89	831	tmp_status = ADC_Enable(hadc);
elmot	1:d0dfbce63a89	832
elmot	1:d0dfbce63a89	833	/* Start conversion if ADC is effectively enabled */
elmot	1:d0dfbce63a89	834	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	835	{
elmot	1:d0dfbce63a89	836	/* State machine update: Check if an injected conversion is ongoing */
elmot	1:d0dfbce63a89	837	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	838	{
elmot	1:d0dfbce63a89	839	/* Reset ADC error code fields related to regular conversions only */
elmot	1:d0dfbce63a89	840	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
elmot	1:d0dfbce63a89	841	}
elmot	1:d0dfbce63a89	842	else
elmot	1:d0dfbce63a89	843	{
elmot	1:d0dfbce63a89	844	/* Set ADC error code to none */
elmot	1:d0dfbce63a89	845	ADC_CLEAR_ERRORCODE(hadc);
elmot	1:d0dfbce63a89	846	}
elmot	1:d0dfbce63a89	847	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
elmot	1:d0dfbce63a89	848	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	849
elmot	1:d0dfbce63a89	850	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
elmot	1:d0dfbce63a89	851	- by default if ADC is Master or Independent or if multimode feature is not available
elmot	1:d0dfbce63a89	852	- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
elmot	1:d0dfbce63a89	853	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
elmot	1:d0dfbce63a89	854	{
elmot	1:d0dfbce63a89	855	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
elmot	1:d0dfbce63a89	856	}
elmot	1:d0dfbce63a89	857
elmot	1:d0dfbce63a89	858	/* Clear regular group conversion flag and overrun flag */
elmot	1:d0dfbce63a89	859	/* (To ensure of no unknown state from potential previous ADC operations) */
elmot	1:d0dfbce63a89	860	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
elmot	1:d0dfbce63a89	861
elmot	1:d0dfbce63a89	862	/* Enable conversion of regular group. */
elmot	1:d0dfbce63a89	863	/* If software start has been selected, conversion starts immediately. */
elmot	1:d0dfbce63a89	864	/* If external trigger has been selected, conversion starts at next */
elmot	1:d0dfbce63a89	865	/* trigger event. */
elmot	1:d0dfbce63a89	866	/* Case of multimode enabled (when multimode feature is available): */
elmot	1:d0dfbce63a89	867	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
elmot	1:d0dfbce63a89	868	/* enabled only (conversion is not started), */
elmot	1:d0dfbce63a89	869	/* - if ADC is master, ADC is enabled and conversion is started. */
elmot	1:d0dfbce63a89	870	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
elmot	1:d0dfbce63a89	871	{
elmot	1:d0dfbce63a89	872	/* Multimode feature is not available or ADC Instance is Independent or Master,
elmot	1:d0dfbce63a89	873	or is not Slave ADC with dual regular conversions enabled.
elmot	1:d0dfbce63a89	874	Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
elmot	1:d0dfbce63a89	875	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
elmot	1:d0dfbce63a89	876	{
elmot	1:d0dfbce63a89	877	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
elmot	1:d0dfbce63a89	878	}
elmot	1:d0dfbce63a89	879	/* Process unlocked */
elmot	1:d0dfbce63a89	880	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	881	/* Start ADC */
elmot	1:d0dfbce63a89	882	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
elmot	1:d0dfbce63a89	883	}
elmot	1:d0dfbce63a89	884	else
elmot	1:d0dfbce63a89	885	{
elmot	1:d0dfbce63a89	886	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
elmot	1:d0dfbce63a89	887	/* if Master ADC JAUTO bit is set, update Slave State in setting
elmot	1:d0dfbce63a89	888	HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
elmot	1:d0dfbce63a89	889	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
elmot	1:d0dfbce63a89	890	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
elmot	1:d0dfbce63a89	891	{
elmot	1:d0dfbce63a89	892	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
elmot	1:d0dfbce63a89	893
elmot	1:d0dfbce63a89	894	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
elmot	1:d0dfbce63a89	895	/* Process unlocked */
elmot	1:d0dfbce63a89	896	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	897	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
elmot	1:d0dfbce63a89	898	}
elmot	1:d0dfbce63a89	899	else
elmot	1:d0dfbce63a89	900	{
elmot	1:d0dfbce63a89	901	/* Process unlocked */
elmot	1:d0dfbce63a89	902	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	903	}
elmot	1:d0dfbce63a89	904
elmot	1:d0dfbce63a89	905	/* Return function status */
elmot	1:d0dfbce63a89	906	return tmp_status;
elmot	1:d0dfbce63a89	907	}
elmot	1:d0dfbce63a89	908	}
elmot	1:d0dfbce63a89	909
elmot	1:d0dfbce63a89	910	/**
elmot	1:d0dfbce63a89	911	* @brief Stop ADC conversion of regular and injected groups, disable ADC peripheral.
elmot	1:d0dfbce63a89	912	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	913	* @retval HAL status.
elmot	1:d0dfbce63a89	914	*/
elmot	1:d0dfbce63a89	915	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	916	{
elmot	1:d0dfbce63a89	917	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	918
elmot	1:d0dfbce63a89	919	/* Check the parameters */
elmot	1:d0dfbce63a89	920	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	921
elmot	1:d0dfbce63a89	922	/* Process locked */
elmot	1:d0dfbce63a89	923	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	924
elmot	1:d0dfbce63a89	925	/* 1. Stop potential regular and injected on-going conversions */
elmot	1:d0dfbce63a89	926	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
elmot	1:d0dfbce63a89	927
elmot	1:d0dfbce63a89	928	/* Disable ADC peripheral if conversions are effectively stopped */
elmot	1:d0dfbce63a89	929	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	930	{
elmot	1:d0dfbce63a89	931	/* 2. Disable the ADC peripheral */
elmot	1:d0dfbce63a89	932	tmp_status = ADC_Disable(hadc);
elmot	1:d0dfbce63a89	933
elmot	1:d0dfbce63a89	934	/* Check if ADC is effectively disabled */
elmot	1:d0dfbce63a89	935	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	936	{
elmot	1:d0dfbce63a89	937	/* Change ADC state */
elmot	1:d0dfbce63a89	938	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	939	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	940	}
elmot	1:d0dfbce63a89	941	}
elmot	1:d0dfbce63a89	942
elmot	1:d0dfbce63a89	943	/* Process unlocked */
elmot	1:d0dfbce63a89	944	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	945
elmot	1:d0dfbce63a89	946	/* Return function status */
elmot	1:d0dfbce63a89	947	return tmp_status;
elmot	1:d0dfbce63a89	948	}
elmot	1:d0dfbce63a89	949
elmot	1:d0dfbce63a89	950
elmot	1:d0dfbce63a89	951
elmot	1:d0dfbce63a89	952	/**
elmot	1:d0dfbce63a89	953	* @brief Wait for regular group conversion to be completed.
elmot	1:d0dfbce63a89	954	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	955	* @param Timeout: Timeout value in millisecond.
elmot	1:d0dfbce63a89	956	* @note Depending on hadc->Init.EOCSelection, EOS or EOC is
elmot	1:d0dfbce63a89	957	* checked and cleared depending on AUTDLY bit status.
elmot	1:d0dfbce63a89	958	* @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
elmot	1:d0dfbce63a89	959	* DMA-managed conversions configuration: indeed, EOC is immediately
elmot	1:d0dfbce63a89	960	* reset by the DMA reading the DR register when the converted data is
elmot	1:d0dfbce63a89	961	* available. Therefore, EOC is set for a too short period to be
elmot	1:d0dfbce63a89	962	* reliably polled.
elmot	1:d0dfbce63a89	963	* @retval HAL status
elmot	1:d0dfbce63a89	964	*/
elmot	1:d0dfbce63a89	965	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
elmot	1:d0dfbce63a89	966	{
elmot	1:d0dfbce63a89	967	uint32_t tickstart;
elmot	1:d0dfbce63a89	968	uint32_t tmp_Flag_End = 0x00;
elmot	1:d0dfbce63a89	969	ADC_TypeDef *tmpADC_Master;
elmot	1:d0dfbce63a89	970	uint32_t tmp_cfgr = 0x00;
elmot	1:d0dfbce63a89	971	uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
elmot	1:d0dfbce63a89	972	tmp_eos_raised will be corrected
elmot	1:d0dfbce63a89	973	accordingly during API execution */
elmot	1:d0dfbce63a89	974
elmot	1:d0dfbce63a89	975	/* Check the parameters */
elmot	1:d0dfbce63a89	976	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	977
elmot	1:d0dfbce63a89	978	/* If end of sequence selected */
elmot	1:d0dfbce63a89	979	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
elmot	1:d0dfbce63a89	980	{
elmot	1:d0dfbce63a89	981	tmp_Flag_End = ADC_FLAG_EOS;
elmot	1:d0dfbce63a89	982	}
elmot	1:d0dfbce63a89	983	else /* end of conversion selected */
elmot	1:d0dfbce63a89	984	{
elmot	1:d0dfbce63a89	985	/* Check that the ADC is not in a DMA-based configuration. Otherwise,
elmot	1:d0dfbce63a89	986	returns an error. */
elmot	1:d0dfbce63a89	987
elmot	1:d0dfbce63a89	988	/* Check whether dual regular conversions are disabled or unavailable. */
elmot	1:d0dfbce63a89	989	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
elmot	1:d0dfbce63a89	990	{
elmot	1:d0dfbce63a89	991	/* Check DMAEN bit in handle ADC CFGR register */
elmot	1:d0dfbce63a89	992	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
elmot	1:d0dfbce63a89	993	{
elmot	1:d0dfbce63a89	994	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
elmot	1:d0dfbce63a89	995	return HAL_ERROR;
elmot	1:d0dfbce63a89	996	}
elmot	1:d0dfbce63a89	997	}
elmot	1:d0dfbce63a89	998	else
elmot	1:d0dfbce63a89	999	{
elmot	1:d0dfbce63a89	1000	/* Else need to check Common register CCR MDMA bit field. */
elmot	1:d0dfbce63a89	1001	if (ADC_MULTIMODE_DMA_ENABLED())
elmot	1:d0dfbce63a89	1002	{
elmot	1:d0dfbce63a89	1003	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
elmot	1:d0dfbce63a89	1004	return HAL_ERROR;
elmot	1:d0dfbce63a89	1005	}
elmot	1:d0dfbce63a89	1006	}
elmot	1:d0dfbce63a89	1007
elmot	1:d0dfbce63a89	1008	/* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
elmot	1:d0dfbce63a89	1009	tmp_Flag_End = ADC_FLAG_EOC;
elmot	1:d0dfbce63a89	1010	}
elmot	1:d0dfbce63a89	1011
elmot	1:d0dfbce63a89	1012	/* Get timeout */
elmot	1:d0dfbce63a89	1013	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	1014
elmot	1:d0dfbce63a89	1015	/* Wait until End of Conversion or Sequence flag is raised */
elmot	1:d0dfbce63a89	1016	while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
elmot	1:d0dfbce63a89	1017	{
elmot	1:d0dfbce63a89	1018	/* Check if timeout is disabled (set to infinite wait) */
elmot	1:d0dfbce63a89	1019	if(Timeout != HAL_MAX_DELAY)
elmot	1:d0dfbce63a89	1020	{
elmot	1:d0dfbce63a89	1021	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
elmot	1:d0dfbce63a89	1022	{
elmot	1:d0dfbce63a89	1023	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
elmot	1:d0dfbce63a89	1024	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	1025	}
elmot	1:d0dfbce63a89	1026	}
elmot	1:d0dfbce63a89	1027	}
elmot	1:d0dfbce63a89	1028
elmot	1:d0dfbce63a89	1029	/* Next, to clear the polled flag as well as to update the handle State,
elmot	1:d0dfbce63a89	1030	EOS is checked and the relevant configuration register is retrieved. */
elmot	1:d0dfbce63a89	1031	/* 1. Check whether or not EOS is set */
elmot	1:d0dfbce63a89	1032	if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
elmot	1:d0dfbce63a89	1033	{
elmot	1:d0dfbce63a89	1034	tmp_eos_raised = 0;
elmot	1:d0dfbce63a89	1035	}
elmot	1:d0dfbce63a89	1036	/* 2. Check whether or not hadc is the handle of a Slave ADC with dual
elmot	1:d0dfbce63a89	1037	regular conversions enabled. */
elmot	1:d0dfbce63a89	1038	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
elmot	1:d0dfbce63a89	1039	{
elmot	1:d0dfbce63a89	1040	/* Retrieve handle ADC CFGR register */
elmot	1:d0dfbce63a89	1041	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
elmot	1:d0dfbce63a89	1042	}
elmot	1:d0dfbce63a89	1043	else
elmot	1:d0dfbce63a89	1044	{
elmot	1:d0dfbce63a89	1045	/* Retrieve Master ADC CFGR register */
elmot	1:d0dfbce63a89	1046	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
elmot	1:d0dfbce63a89	1047	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
elmot	1:d0dfbce63a89	1048	}
elmot	1:d0dfbce63a89	1049
elmot	1:d0dfbce63a89	1050	/* Clear polled flag */
elmot	1:d0dfbce63a89	1051	if (tmp_Flag_End == ADC_FLAG_EOS)
elmot	1:d0dfbce63a89	1052	{
elmot	1:d0dfbce63a89	1053	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
elmot	1:d0dfbce63a89	1054	}
elmot	1:d0dfbce63a89	1055	else
elmot	1:d0dfbce63a89	1056	{
elmot	1:d0dfbce63a89	1057
elmot	1:d0dfbce63a89	1058	/* Clear end of conversion EOC flag of regular group if low power feature */
elmot	1:d0dfbce63a89	1059	/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
elmot	1:d0dfbce63a89	1060	/* until data register is read using function HAL_ADC_GetValue(). */
elmot	1:d0dfbce63a89	1061	/* For regular groups, no new conversion will start before EOC is cleared.*/
elmot	1:d0dfbce63a89	1062	/* Note that 1. reading DR clears EOC. */
elmot	1:d0dfbce63a89	1063	/* 2. in multimode with dual regular conversions enabled (when */
elmot	1:d0dfbce63a89	1064	/* multimode feature is available), Master AUTDLY bit is */
elmot	1:d0dfbce63a89	1065	/* checked. */
elmot	1:d0dfbce63a89	1066	if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
elmot	1:d0dfbce63a89	1067	{
elmot	1:d0dfbce63a89	1068	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
elmot	1:d0dfbce63a89	1069	}
elmot	1:d0dfbce63a89	1070	}
elmot	1:d0dfbce63a89	1071
elmot	1:d0dfbce63a89	1072
elmot	1:d0dfbce63a89	1073	/* Update ADC state machine */
elmot	1:d0dfbce63a89	1074	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
elmot	1:d0dfbce63a89	1075	/* If 1. EOS is set
elmot	1:d0dfbce63a89	1076	2. conversions are software-triggered
elmot	1:d0dfbce63a89	1077	3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
elmot	1:d0dfbce63a89	1078	Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
elmot	1:d0dfbce63a89	1079	4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
elmot	1:d0dfbce63a89	1080	can be set */
elmot	1:d0dfbce63a89	1081	if ((tmp_eos_raised)
elmot	1:d0dfbce63a89	1082	&& (ADC_IS_SOFTWARE_START_REGULAR(hadc))
elmot	1:d0dfbce63a89	1083	&& (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
elmot	1:d0dfbce63a89	1084	{
elmot	1:d0dfbce63a89	1085	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	1086	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	1087	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	1088	{
elmot	1:d0dfbce63a89	1089	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	1090	}
elmot	1:d0dfbce63a89	1091	}
elmot	1:d0dfbce63a89	1092
elmot	1:d0dfbce63a89	1093
elmot	1:d0dfbce63a89	1094	/* Return API HAL status */
elmot	1:d0dfbce63a89	1095	return HAL_OK;
elmot	1:d0dfbce63a89	1096	}
elmot	1:d0dfbce63a89	1097
elmot	1:d0dfbce63a89	1098	/**
elmot	1:d0dfbce63a89	1099	* @brief Poll for ADC event.
elmot	1:d0dfbce63a89	1100	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1101	* @param EventType: the ADC event type.
elmot	1:d0dfbce63a89	1102	* This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1103	* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
elmot	1:d0dfbce63a89	1104	* @arg @ref ADC_AWD_EVENT ADC Analog watchdog 1 event
elmot	1:d0dfbce63a89	1105	* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event
elmot	1:d0dfbce63a89	1106	* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event
elmot	1:d0dfbce63a89	1107	* @arg @ref ADC_OVR_EVENT ADC Overrun event
elmot	1:d0dfbce63a89	1108	* @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
elmot	1:d0dfbce63a89	1109	* @param Timeout: Timeout value in millisecond.
elmot	1:d0dfbce63a89	1110	* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
elmot	1:d0dfbce63a89	1111	* Indeed, the latter is reset only if hadc->Init.Overrun field is set
elmot	1:d0dfbce63a89	1112	* to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten
elmot	1:d0dfbce63a89	1113	* by a new converted data as soon as OVR is cleared.
elmot	1:d0dfbce63a89	1114	* To reset OVR flag once the preserved data is retrieved, the user can resort
elmot	1:d0dfbce63a89	1115	* to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
elmot	1:d0dfbce63a89	1116	* @retval HAL status
elmot	1:d0dfbce63a89	1117	*/
elmot	1:d0dfbce63a89	1118	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
elmot	1:d0dfbce63a89	1119	{
elmot	1:d0dfbce63a89	1120	uint32_t tickstart;
elmot	1:d0dfbce63a89	1121
elmot	1:d0dfbce63a89	1122	/* Check the parameters */
elmot	1:d0dfbce63a89	1123	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1124	assert_param(IS_ADC_EVENT_TYPE(EventType));
elmot	1:d0dfbce63a89	1125
elmot	1:d0dfbce63a89	1126	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	1127
elmot	1:d0dfbce63a89	1128	/* Check selected event flag */
elmot	1:d0dfbce63a89	1129	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
elmot	1:d0dfbce63a89	1130	{
elmot	1:d0dfbce63a89	1131	/* Check if timeout is disabled (set to infinite wait) */
elmot	1:d0dfbce63a89	1132	if(Timeout != HAL_MAX_DELAY)
elmot	1:d0dfbce63a89	1133	{
elmot	1:d0dfbce63a89	1134	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
elmot	1:d0dfbce63a89	1135	{
elmot	1:d0dfbce63a89	1136	/* Update ADC state machine to timeout */
elmot	1:d0dfbce63a89	1137	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
elmot	1:d0dfbce63a89	1138
elmot	1:d0dfbce63a89	1139	/* Process unlocked */
elmot	1:d0dfbce63a89	1140	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1141
elmot	1:d0dfbce63a89	1142	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	1143	}
elmot	1:d0dfbce63a89	1144	}
elmot	1:d0dfbce63a89	1145	}
elmot	1:d0dfbce63a89	1146
elmot	1:d0dfbce63a89	1147
elmot	1:d0dfbce63a89	1148	switch(EventType)
elmot	1:d0dfbce63a89	1149	{
elmot	1:d0dfbce63a89	1150	/* End Of Sampling event */
elmot	1:d0dfbce63a89	1151	case ADC_EOSMP_EVENT:
elmot	1:d0dfbce63a89	1152	/* Change ADC state */
elmot	1:d0dfbce63a89	1153	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
elmot	1:d0dfbce63a89	1154
elmot	1:d0dfbce63a89	1155	/* Clear the End Of Sampling flag */
elmot	1:d0dfbce63a89	1156	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
elmot	1:d0dfbce63a89	1157
elmot	1:d0dfbce63a89	1158	break;
elmot	1:d0dfbce63a89	1159
elmot	1:d0dfbce63a89	1160	/* Analog watchdog (level out of window) event */
elmot	1:d0dfbce63a89	1161	/* Note: In case of several analog watchdog enabled, if needed to know */
elmot	1:d0dfbce63a89	1162	/* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
elmot	1:d0dfbce63a89	1163	/* flags HAL_ADC_STATE_AWD/2/3 function. */
elmot	1:d0dfbce63a89	1164	/* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */
elmot	1:d0dfbce63a89	1165	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */
elmot	1:d0dfbce63a89	1166	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */
elmot	1:d0dfbce63a89	1167	case ADC_AWD_EVENT:
elmot	1:d0dfbce63a89	1168	/* Change ADC state */
elmot	1:d0dfbce63a89	1169	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
elmot	1:d0dfbce63a89	1170
elmot	1:d0dfbce63a89	1171	/* Clear ADC analog watchdog flag */
elmot	1:d0dfbce63a89	1172	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
elmot	1:d0dfbce63a89	1173
elmot	1:d0dfbce63a89	1174	break;
elmot	1:d0dfbce63a89	1175
elmot	1:d0dfbce63a89	1176	/* Check analog watchdog 2 flag */
elmot	1:d0dfbce63a89	1177	case ADC_AWD2_EVENT:
elmot	1:d0dfbce63a89	1178	/* Change ADC state */
elmot	1:d0dfbce63a89	1179	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
elmot	1:d0dfbce63a89	1180
elmot	1:d0dfbce63a89	1181	/* Clear ADC analog watchdog flag */
elmot	1:d0dfbce63a89	1182	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
elmot	1:d0dfbce63a89	1183
elmot	1:d0dfbce63a89	1184	break;
elmot	1:d0dfbce63a89	1185
elmot	1:d0dfbce63a89	1186	/* Check analog watchdog 3 flag */
elmot	1:d0dfbce63a89	1187	case ADC_AWD3_EVENT:
elmot	1:d0dfbce63a89	1188	/* Change ADC state */
elmot	1:d0dfbce63a89	1189	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
elmot	1:d0dfbce63a89	1190
elmot	1:d0dfbce63a89	1191	/* Clear ADC analog watchdog flag */
elmot	1:d0dfbce63a89	1192	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
elmot	1:d0dfbce63a89	1193
elmot	1:d0dfbce63a89	1194	break;
elmot	1:d0dfbce63a89	1195
elmot	1:d0dfbce63a89	1196	/* Injected context queue overflow event */
elmot	1:d0dfbce63a89	1197	case ADC_JQOVF_EVENT:
elmot	1:d0dfbce63a89	1198	/* Change ADC state */
elmot	1:d0dfbce63a89	1199	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
elmot	1:d0dfbce63a89	1200
elmot	1:d0dfbce63a89	1201	/* Set ADC error code to Injected context queue overflow */
elmot	1:d0dfbce63a89	1202	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
elmot	1:d0dfbce63a89	1203
elmot	1:d0dfbce63a89	1204	/* Clear ADC Injected context queue overflow flag */
elmot	1:d0dfbce63a89	1205	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
elmot	1:d0dfbce63a89	1206
elmot	1:d0dfbce63a89	1207	break;
elmot	1:d0dfbce63a89	1208
elmot	1:d0dfbce63a89	1209	/* Overrun event */
elmot	1:d0dfbce63a89	1210	default: /* Case ADC_OVR_EVENT */
elmot	1:d0dfbce63a89	1211	/* If overrun is set to overwrite previous data, overrun event is not */
elmot	1:d0dfbce63a89	1212	/* considered as an error. */
elmot	1:d0dfbce63a89	1213	/* (cf ref manual "Managing conversions without using the DMA and without */
elmot	1:d0dfbce63a89	1214	/* overrun ") */
elmot	1:d0dfbce63a89	1215	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
elmot	1:d0dfbce63a89	1216	{
elmot	1:d0dfbce63a89	1217	/* Change ADC state */
elmot	1:d0dfbce63a89	1218	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
elmot	1:d0dfbce63a89	1219
elmot	1:d0dfbce63a89	1220	/* Set ADC error code to overrun */
elmot	1:d0dfbce63a89	1221	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
elmot	1:d0dfbce63a89	1222	}
elmot	1:d0dfbce63a89	1223	else
elmot	1:d0dfbce63a89	1224	{
elmot	1:d0dfbce63a89	1225	/* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
elmot	1:d0dfbce63a89	1226	otherwise, DR is potentially overwritten by new converted data as soon
elmot	1:d0dfbce63a89	1227	as OVR is cleared. */
elmot	1:d0dfbce63a89	1228	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
elmot	1:d0dfbce63a89	1229	}
elmot	1:d0dfbce63a89	1230	break;
elmot	1:d0dfbce63a89	1231	}
elmot	1:d0dfbce63a89	1232
elmot	1:d0dfbce63a89	1233	/* Return API HAL status */
elmot	1:d0dfbce63a89	1234	return HAL_OK;
elmot	1:d0dfbce63a89	1235	}
elmot	1:d0dfbce63a89	1236
elmot	1:d0dfbce63a89	1237
elmot	1:d0dfbce63a89	1238	/**
elmot	1:d0dfbce63a89	1239	* @brief Enable ADC, start conversion of regular group with interruption.
elmot	1:d0dfbce63a89	1240	* @note Interruptions enabled in this function according to initialization
elmot	1:d0dfbce63a89	1241	* setting : EOC (end of conversion), EOS (end of sequence),
elmot	1:d0dfbce63a89	1242	* OVR overrun.
elmot	1:d0dfbce63a89	1243	* Each of these interruptions has its dedicated callback function.
elmot	1:d0dfbce63a89	1244	* @note Case of multimode enabled (when multimode feature is available):
elmot	1:d0dfbce63a89	1245	* HAL_ADC_Start_IT() must be called for ADC Slave first, then for
elmot	1:d0dfbce63a89	1246	* ADC Master.
elmot	1:d0dfbce63a89	1247	* For ADC Slave, ADC is enabled only (conversion is not started).
elmot	1:d0dfbce63a89	1248	* For ADC Master, ADC is enabled and multimode conversion is started.
elmot	1:d0dfbce63a89	1249	* @note To guarantee a proper reset of all interruptions once all the needed
elmot	1:d0dfbce63a89	1250	* conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
elmot	1:d0dfbce63a89	1251	* a correct stop of the IT-based conversions.
elmot	1:d0dfbce63a89	1252	* @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
elmot	1:d0dfbce63a89	1253	* interruption. If required (e.g. in case of oversampling with trigger
elmot	1:d0dfbce63a89	1254	* mode), the user must
elmot	1:d0dfbce63a89	1255	* 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
elmot	1:d0dfbce63a89	1256	* 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
elmot	1:d0dfbce63a89	1257	* before calling HAL_ADC_Start_IT().
elmot	1:d0dfbce63a89	1258	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1259	* @retval HAL status
elmot	1:d0dfbce63a89	1260	*/
elmot	1:d0dfbce63a89	1261	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	1262	{
elmot	1:d0dfbce63a89	1263	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	1264	ADC_TypeDef *tmpADC_Master;
elmot	1:d0dfbce63a89	1265
elmot	1:d0dfbce63a89	1266	/* Check the parameters */
elmot	1:d0dfbce63a89	1267	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1268
elmot	1:d0dfbce63a89	1269	/* if a regular conversion is already on-going (i.e. ADSTART is set),
elmot	1:d0dfbce63a89	1270	don't restart the conversion. */
elmot	1:d0dfbce63a89	1271	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
elmot	1:d0dfbce63a89	1272	{
elmot	1:d0dfbce63a89	1273	return HAL_BUSY;
elmot	1:d0dfbce63a89	1274	}
elmot	1:d0dfbce63a89	1275	else
elmot	1:d0dfbce63a89	1276	{
elmot	1:d0dfbce63a89	1277	/* Process locked */
elmot	1:d0dfbce63a89	1278	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	1279
elmot	1:d0dfbce63a89	1280	/* Enable the ADC peripheral */
elmot	1:d0dfbce63a89	1281	tmp_status = ADC_Enable(hadc);
elmot	1:d0dfbce63a89	1282
elmot	1:d0dfbce63a89	1283	/* Start conversion if ADC is effectively enabled */
elmot	1:d0dfbce63a89	1284	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1285	{
elmot	1:d0dfbce63a89	1286	/* State machine update: Check if an injected conversion is ongoing */
elmot	1:d0dfbce63a89	1287	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	1288	{
elmot	1:d0dfbce63a89	1289	/* Reset ADC error code fields related to regular conversions only */
elmot	1:d0dfbce63a89	1290	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
elmot	1:d0dfbce63a89	1291	}
elmot	1:d0dfbce63a89	1292	else
elmot	1:d0dfbce63a89	1293	{
elmot	1:d0dfbce63a89	1294	/* Set ADC error code to none */
elmot	1:d0dfbce63a89	1295	ADC_CLEAR_ERRORCODE(hadc);
elmot	1:d0dfbce63a89	1296	}
elmot	1:d0dfbce63a89	1297	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
elmot	1:d0dfbce63a89	1298	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	1299
elmot	1:d0dfbce63a89	1300	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
elmot	1:d0dfbce63a89	1301	- by default if ADC is Master or Independent or if multimode feature is not available
elmot	1:d0dfbce63a89	1302	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
elmot	1:d0dfbce63a89	1303	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
elmot	1:d0dfbce63a89	1304	{
elmot	1:d0dfbce63a89	1305	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
elmot	1:d0dfbce63a89	1306	}
elmot	1:d0dfbce63a89	1307
elmot	1:d0dfbce63a89	1308	/* Clear regular group conversion flag and overrun flag */
elmot	1:d0dfbce63a89	1309	/* (To ensure of no unknown state from potential previous ADC operations) */
elmot	1:d0dfbce63a89	1310	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
elmot	1:d0dfbce63a89	1311
elmot	1:d0dfbce63a89	1312	/* By default, disable all interruptions before enabling the desired ones */
elmot	1:d0dfbce63a89	1313	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
elmot	1:d0dfbce63a89	1314
elmot	1:d0dfbce63a89	1315	/* Enable required interruptions */
elmot	1:d0dfbce63a89	1316	switch(hadc->Init.EOCSelection)
elmot	1:d0dfbce63a89	1317	{
elmot	1:d0dfbce63a89	1318	case ADC_EOC_SEQ_CONV:
elmot	1:d0dfbce63a89	1319	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
elmot	1:d0dfbce63a89	1320	break;
elmot	1:d0dfbce63a89	1321	/* case ADC_EOC_SINGLE_CONV */
elmot	1:d0dfbce63a89	1322	default:
elmot	1:d0dfbce63a89	1323	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
elmot	1:d0dfbce63a89	1324	break;
elmot	1:d0dfbce63a89	1325	}
elmot	1:d0dfbce63a89	1326
elmot	1:d0dfbce63a89	1327	/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
elmot	1:d0dfbce63a89	1328	ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
elmot	1:d0dfbce63a89	1329	behavior and no CPU time is lost for a non-processed interruption */
elmot	1:d0dfbce63a89	1330	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
elmot	1:d0dfbce63a89	1331	{
elmot	1:d0dfbce63a89	1332	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
elmot	1:d0dfbce63a89	1333	}
elmot	1:d0dfbce63a89	1334
elmot	1:d0dfbce63a89	1335	/* Enable conversion of regular group. */
elmot	1:d0dfbce63a89	1336	/* If software start has been selected, conversion starts immediately. */
elmot	1:d0dfbce63a89	1337	/* If external trigger has been selected, conversion starts at next */
elmot	1:d0dfbce63a89	1338	/* trigger event. */
elmot	1:d0dfbce63a89	1339	/* Case of multimode enabled (when multimode feature is available): */
elmot	1:d0dfbce63a89	1340	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
elmot	1:d0dfbce63a89	1341	/* enabled only (conversion is not started), */
elmot	1:d0dfbce63a89	1342	/* - if ADC is master, ADC is enabled and conversion is started. */
elmot	1:d0dfbce63a89	1343	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) )
elmot	1:d0dfbce63a89	1344	{
elmot	1:d0dfbce63a89	1345	/* Multimode feature is not available or ADC Instance is Independent or Master,
elmot	1:d0dfbce63a89	1346	or is not Slave ADC with dual regular conversions enabled.
elmot	1:d0dfbce63a89	1347	Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
elmot	1:d0dfbce63a89	1348	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
elmot	1:d0dfbce63a89	1349	{
elmot	1:d0dfbce63a89	1350	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
elmot	1:d0dfbce63a89	1351
elmot	1:d0dfbce63a89	1352	/* Enable as well injected interruptions in case
elmot	1:d0dfbce63a89	1353	HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
elmot	1:d0dfbce63a89	1354	allows to start regular and injected conversions when JAUTO is
elmot	1:d0dfbce63a89	1355	set with a single call to HAL_ADC_Start_IT() */
elmot	1:d0dfbce63a89	1356	switch(hadc->Init.EOCSelection)
elmot	1:d0dfbce63a89	1357	{
elmot	1:d0dfbce63a89	1358	case ADC_EOC_SEQ_CONV:
elmot	1:d0dfbce63a89	1359	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
elmot	1:d0dfbce63a89	1360	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
elmot	1:d0dfbce63a89	1361	break;
elmot	1:d0dfbce63a89	1362	/* case ADC_EOC_SINGLE_CONV */
elmot	1:d0dfbce63a89	1363	default:
elmot	1:d0dfbce63a89	1364	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
elmot	1:d0dfbce63a89	1365	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
elmot	1:d0dfbce63a89	1366	break;
elmot	1:d0dfbce63a89	1367	}
elmot	1:d0dfbce63a89	1368	} /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
elmot	1:d0dfbce63a89	1369	/* Process unlocked */
elmot	1:d0dfbce63a89	1370	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1371	/* Start ADC */
elmot	1:d0dfbce63a89	1372	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
elmot	1:d0dfbce63a89	1373	}
elmot	1:d0dfbce63a89	1374	else
elmot	1:d0dfbce63a89	1375	{
elmot	1:d0dfbce63a89	1376	/* hadc is the handle of a Slave ADC with dual regular conversions
elmot	1:d0dfbce63a89	1377	enabled. Therefore, ADC_CR_ADSTART is NOT set */
elmot	1:d0dfbce63a89	1378	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
elmot	1:d0dfbce63a89	1379	/* if Master ADC JAUTO bit is set, Slave injected interruptions
elmot	1:d0dfbce63a89	1380	are enabled nevertheless (for same reason as above) */
elmot	1:d0dfbce63a89	1381	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
elmot	1:d0dfbce63a89	1382	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
elmot	1:d0dfbce63a89	1383	{
elmot	1:d0dfbce63a89	1384	/* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
elmot	1:d0dfbce63a89	1385	and in resetting HAL_ADC_STATE_INJ_EOC bit */
elmot	1:d0dfbce63a89	1386	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
elmot	1:d0dfbce63a89	1387	/* Next, set Slave injected interruptions */
elmot	1:d0dfbce63a89	1388	switch(hadc->Init.EOCSelection)
elmot	1:d0dfbce63a89	1389	{
elmot	1:d0dfbce63a89	1390	case ADC_EOC_SEQ_CONV:
elmot	1:d0dfbce63a89	1391	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
elmot	1:d0dfbce63a89	1392	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
elmot	1:d0dfbce63a89	1393	break;
elmot	1:d0dfbce63a89	1394	/* case ADC_EOC_SINGLE_CONV */
elmot	1:d0dfbce63a89	1395	default:
elmot	1:d0dfbce63a89	1396	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
elmot	1:d0dfbce63a89	1397	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
elmot	1:d0dfbce63a89	1398	break;
elmot	1:d0dfbce63a89	1399	}
elmot	1:d0dfbce63a89	1400	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
elmot	1:d0dfbce63a89	1401	/* Process unlocked */
elmot	1:d0dfbce63a89	1402	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1403	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */
elmot	1:d0dfbce63a89	1404	} /* if (tmp_status == HAL_OK) */
elmot	1:d0dfbce63a89	1405	else
elmot	1:d0dfbce63a89	1406	{
elmot	1:d0dfbce63a89	1407	/* Process unlocked */
elmot	1:d0dfbce63a89	1408	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1409	}
elmot	1:d0dfbce63a89	1410
elmot	1:d0dfbce63a89	1411	/* Return function status */
elmot	1:d0dfbce63a89	1412	return tmp_status;
elmot	1:d0dfbce63a89	1413
elmot	1:d0dfbce63a89	1414	}
elmot	1:d0dfbce63a89	1415	}
elmot	1:d0dfbce63a89	1416
elmot	1:d0dfbce63a89	1417
elmot	1:d0dfbce63a89	1418
elmot	1:d0dfbce63a89	1419	/**
elmot	1:d0dfbce63a89	1420	* @brief Stop ADC conversion of regular groups when interruptions are enabled.
elmot	1:d0dfbce63a89	1421	* @note Stop as well injected conversions and disable ADC peripheral.
elmot	1:d0dfbce63a89	1422	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1423	* @retval HAL status.
elmot	1:d0dfbce63a89	1424	*/
elmot	1:d0dfbce63a89	1425	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	1426	{
elmot	1:d0dfbce63a89	1427	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	1428
elmot	1:d0dfbce63a89	1429	/* Check the parameters */
elmot	1:d0dfbce63a89	1430	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1431
elmot	1:d0dfbce63a89	1432	/* Process locked */
elmot	1:d0dfbce63a89	1433	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	1434
elmot	1:d0dfbce63a89	1435	/* 1. Stop potential regular and injected on-going conversions */
elmot	1:d0dfbce63a89	1436	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
elmot	1:d0dfbce63a89	1437
elmot	1:d0dfbce63a89	1438	/* Disable ADC peripheral if conversions are effectively stopped */
elmot	1:d0dfbce63a89	1439	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1440	{
elmot	1:d0dfbce63a89	1441	/* Disable all interrupts */
elmot	1:d0dfbce63a89	1442	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
elmot	1:d0dfbce63a89	1443
elmot	1:d0dfbce63a89	1444	/* 2. Disable the ADC peripheral */
elmot	1:d0dfbce63a89	1445	tmp_status = ADC_Disable(hadc);
elmot	1:d0dfbce63a89	1446
elmot	1:d0dfbce63a89	1447	/* Check if ADC is effectively disabled */
elmot	1:d0dfbce63a89	1448	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1449	{
elmot	1:d0dfbce63a89	1450	/* Change ADC state */
elmot	1:d0dfbce63a89	1451	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	1452	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	1453	}
elmot	1:d0dfbce63a89	1454	}
elmot	1:d0dfbce63a89	1455
elmot	1:d0dfbce63a89	1456	/* Process unlocked */
elmot	1:d0dfbce63a89	1457	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1458
elmot	1:d0dfbce63a89	1459	/* Return function status */
elmot	1:d0dfbce63a89	1460	return tmp_status;
elmot	1:d0dfbce63a89	1461	}
elmot	1:d0dfbce63a89	1462
elmot	1:d0dfbce63a89	1463
elmot	1:d0dfbce63a89	1464	/**
elmot	1:d0dfbce63a89	1465	* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
elmot	1:d0dfbce63a89	1466	* @note Interruptions enabled in this function:
elmot	1:d0dfbce63a89	1467	* overrun (if applicable), DMA half transfer, DMA transfer complete.
elmot	1:d0dfbce63a89	1468	* Each of these interruptions has its dedicated callback function.
elmot	1:d0dfbce63a89	1469	* @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
elmot	1:d0dfbce63a89	1470	* is designed for single-ADC mode only. For multimode, the dedicated
elmot	1:d0dfbce63a89	1471	* HAL_ADCEx_MultiModeStart_DMA() function must be used.
elmot	1:d0dfbce63a89	1472	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1473	* @param pData: Destination Buffer address.
elmot	1:d0dfbce63a89	1474	* @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
elmot	1:d0dfbce63a89	1475	* @retval None
elmot	1:d0dfbce63a89	1476	*/
elmot	1:d0dfbce63a89	1477	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
elmot	1:d0dfbce63a89	1478	{
elmot	1:d0dfbce63a89	1479	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	1480
elmot	1:d0dfbce63a89	1481	/* Check the parameters */
elmot	1:d0dfbce63a89	1482	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1483
elmot	1:d0dfbce63a89	1484	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
elmot	1:d0dfbce63a89	1485	{
elmot	1:d0dfbce63a89	1486	return HAL_BUSY;
elmot	1:d0dfbce63a89	1487	}
elmot	1:d0dfbce63a89	1488	else
elmot	1:d0dfbce63a89	1489	{
elmot	1:d0dfbce63a89	1490
elmot	1:d0dfbce63a89	1491	/* Process locked */
elmot	1:d0dfbce63a89	1492	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	1493
elmot	1:d0dfbce63a89	1494	/* Ensure that dual regular conversions are not enabled or unavailable. */
elmot	1:d0dfbce63a89	1495	/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
elmot	1:d0dfbce63a89	1496	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
elmot	1:d0dfbce63a89	1497	{
elmot	1:d0dfbce63a89	1498	/* Enable the ADC peripheral */
elmot	1:d0dfbce63a89	1499	tmp_status = ADC_Enable(hadc);
elmot	1:d0dfbce63a89	1500
elmot	1:d0dfbce63a89	1501	/* Start conversion if ADC is effectively enabled */
elmot	1:d0dfbce63a89	1502	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1503	{
elmot	1:d0dfbce63a89	1504	/* State machine update: Check if an injected conversion is ongoing */
elmot	1:d0dfbce63a89	1505	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	1506	{
elmot	1:d0dfbce63a89	1507	/* Reset ADC error code fields related to regular conversions only */
elmot	1:d0dfbce63a89	1508	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
elmot	1:d0dfbce63a89	1509	}
elmot	1:d0dfbce63a89	1510	else
elmot	1:d0dfbce63a89	1511	{
elmot	1:d0dfbce63a89	1512	/* Set ADC error code to none */
elmot	1:d0dfbce63a89	1513	ADC_CLEAR_ERRORCODE(hadc);
elmot	1:d0dfbce63a89	1514	}
elmot	1:d0dfbce63a89	1515	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
elmot	1:d0dfbce63a89	1516	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	1517
elmot	1:d0dfbce63a89	1518	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
elmot	1:d0dfbce63a89	1519	- by default if ADC is Master or Independent or if multimode feature is not available
elmot	1:d0dfbce63a89	1520	- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
elmot	1:d0dfbce63a89	1521	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
elmot	1:d0dfbce63a89	1522	{
elmot	1:d0dfbce63a89	1523	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
elmot	1:d0dfbce63a89	1524	}
elmot	1:d0dfbce63a89	1525
elmot	1:d0dfbce63a89	1526	/* Set the DMA transfer complete callback */
elmot	1:d0dfbce63a89	1527	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
elmot	1:d0dfbce63a89	1528
elmot	1:d0dfbce63a89	1529	/* Set the DMA half transfer complete callback */
elmot	1:d0dfbce63a89	1530	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
elmot	1:d0dfbce63a89	1531
elmot	1:d0dfbce63a89	1532	/* Set the DMA error callback */
elmot	1:d0dfbce63a89	1533	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
elmot	1:d0dfbce63a89	1534
elmot	1:d0dfbce63a89	1535
elmot	1:d0dfbce63a89	1536	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
elmot	1:d0dfbce63a89	1537	/* ADC start (in case of SW start): */
elmot	1:d0dfbce63a89	1538
elmot	1:d0dfbce63a89	1539	/* Clear regular group conversion flag and overrun flag */
elmot	1:d0dfbce63a89	1540	/* (To ensure of no unknown state from potential previous ADC */
elmot	1:d0dfbce63a89	1541	/* operations) */
elmot	1:d0dfbce63a89	1542	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
elmot	1:d0dfbce63a89	1543
elmot	1:d0dfbce63a89	1544	/* With DMA, overrun event is always considered as an error even if
elmot	1:d0dfbce63a89	1545	hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
elmot	1:d0dfbce63a89	1546	ADC_IT_OVR is enabled. */
elmot	1:d0dfbce63a89	1547	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
elmot	1:d0dfbce63a89	1548
elmot	1:d0dfbce63a89	1549
elmot	1:d0dfbce63a89	1550	/* Enable ADC DMA mode */
elmot	1:d0dfbce63a89	1551	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
elmot	1:d0dfbce63a89	1552
elmot	1:d0dfbce63a89	1553	/* Start the DMA channel */
elmot	1:d0dfbce63a89	1554	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
elmot	1:d0dfbce63a89	1555
elmot	1:d0dfbce63a89	1556	/* Enable conversion of regular group. */
elmot	1:d0dfbce63a89	1557	/* Process unlocked */
elmot	1:d0dfbce63a89	1558	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1559	/* If software start has been selected, conversion starts immediately. */
elmot	1:d0dfbce63a89	1560	/* If external trigger has been selected, conversion will start at next */
elmot	1:d0dfbce63a89	1561	/* trigger event. */
elmot	1:d0dfbce63a89	1562	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
elmot	1:d0dfbce63a89	1563
elmot	1:d0dfbce63a89	1564	}
elmot	1:d0dfbce63a89	1565	else
elmot	1:d0dfbce63a89	1566	{
elmot	1:d0dfbce63a89	1567	/* Process unlocked */
elmot	1:d0dfbce63a89	1568	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1569	} /* if (tmp_status == HAL_OK) */
elmot	1:d0dfbce63a89	1570	}
elmot	1:d0dfbce63a89	1571	else
elmot	1:d0dfbce63a89	1572	{
elmot	1:d0dfbce63a89	1573	tmp_status = HAL_ERROR;
elmot	1:d0dfbce63a89	1574	/* Process unlocked */
elmot	1:d0dfbce63a89	1575	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1576	} /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
elmot	1:d0dfbce63a89	1577
elmot	1:d0dfbce63a89	1578
elmot	1:d0dfbce63a89	1579
elmot	1:d0dfbce63a89	1580	/* Return function status */
elmot	1:d0dfbce63a89	1581	return tmp_status;
elmot	1:d0dfbce63a89	1582	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) */
elmot	1:d0dfbce63a89	1583	}
elmot	1:d0dfbce63a89	1584
elmot	1:d0dfbce63a89	1585
elmot	1:d0dfbce63a89	1586	/**
elmot	1:d0dfbce63a89	1587	* @brief Stop ADC conversion of regular groups and disable ADC DMA transfer.
elmot	1:d0dfbce63a89	1588	* @note Stop as well injected conversions and disable ADC peripheral.
elmot	1:d0dfbce63a89	1589	* @note Case of multimode enabled (when multimode feature is available):
elmot	1:d0dfbce63a89	1590	* HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
elmot	1:d0dfbce63a89	1591	* For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
elmot	1:d0dfbce63a89	1592	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1593	* @retval HAL status.
elmot	1:d0dfbce63a89	1594	*/
elmot	1:d0dfbce63a89	1595	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	1596	{
elmot	1:d0dfbce63a89	1597	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	1598
elmot	1:d0dfbce63a89	1599	/* Check the parameters */
elmot	1:d0dfbce63a89	1600	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1601
elmot	1:d0dfbce63a89	1602	/* Process locked */
elmot	1:d0dfbce63a89	1603	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	1604
elmot	1:d0dfbce63a89	1605	/* 1. Stop potential regular conversion on going */
elmot	1:d0dfbce63a89	1606	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
elmot	1:d0dfbce63a89	1607
elmot	1:d0dfbce63a89	1608	/* Disable ADC peripheral if conversions are effectively stopped */
elmot	1:d0dfbce63a89	1609	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1610	{
elmot	1:d0dfbce63a89	1611	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
elmot	1:d0dfbce63a89	1612	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
elmot	1:d0dfbce63a89	1613
elmot	1:d0dfbce63a89	1614	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
elmot	1:d0dfbce63a89	1615	/* while DMA transfer is on going) */
elmot	1:d0dfbce63a89	1616	tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
elmot	1:d0dfbce63a89	1617
elmot	1:d0dfbce63a89	1618	/* Check if DMA channel effectively disabled */
elmot	1:d0dfbce63a89	1619	if (tmp_status != HAL_OK)
elmot	1:d0dfbce63a89	1620	{
elmot	1:d0dfbce63a89	1621	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	1622	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	1623	}
elmot	1:d0dfbce63a89	1624
elmot	1:d0dfbce63a89	1625	/* Disable ADC overrun interrupt */
elmot	1:d0dfbce63a89	1626	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
elmot	1:d0dfbce63a89	1627
elmot	1:d0dfbce63a89	1628	/* 2. Disable the ADC peripheral */
elmot	1:d0dfbce63a89	1629	/* Update "tmp_status" only if DMA channel disabling passed, to keep in */
elmot	1:d0dfbce63a89	1630	/* memory a potential failing status. */
elmot	1:d0dfbce63a89	1631	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1632	{
elmot	1:d0dfbce63a89	1633	tmp_status = ADC_Disable(hadc);
elmot	1:d0dfbce63a89	1634	}
elmot	1:d0dfbce63a89	1635	else
elmot	1:d0dfbce63a89	1636	{
elmot	1:d0dfbce63a89	1637	ADC_Disable(hadc);
elmot	1:d0dfbce63a89	1638	}
elmot	1:d0dfbce63a89	1639
elmot	1:d0dfbce63a89	1640	/* Check if ADC is effectively disabled */
elmot	1:d0dfbce63a89	1641	if (tmp_status == HAL_OK)
elmot	1:d0dfbce63a89	1642	{
elmot	1:d0dfbce63a89	1643	/* Change ADC state */
elmot	1:d0dfbce63a89	1644	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	1645	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	1646	}
elmot	1:d0dfbce63a89	1647
elmot	1:d0dfbce63a89	1648	}
elmot	1:d0dfbce63a89	1649
elmot	1:d0dfbce63a89	1650	/* Process unlocked */
elmot	1:d0dfbce63a89	1651	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	1652
elmot	1:d0dfbce63a89	1653	/* Return function status */
elmot	1:d0dfbce63a89	1654	return tmp_status;
elmot	1:d0dfbce63a89	1655	}
elmot	1:d0dfbce63a89	1656
elmot	1:d0dfbce63a89	1657
elmot	1:d0dfbce63a89	1658	/**
elmot	1:d0dfbce63a89	1659	* @brief Get ADC regular group conversion result.
elmot	1:d0dfbce63a89	1660	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1661	* @note Reading DR register automatically clears EOC flag. To reset EOS flag,
elmot	1:d0dfbce63a89	1662	* the user must resort to the macro
elmot	1:d0dfbce63a89	1663	* __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)
elmot	1:d0dfbce63a89	1664	* @retval Converted value
elmot	1:d0dfbce63a89	1665	*/
elmot	1:d0dfbce63a89	1666	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	1667	{
elmot	1:d0dfbce63a89	1668	/* Check the parameters */
elmot	1:d0dfbce63a89	1669	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1670
elmot	1:d0dfbce63a89	1671	/* Return ADC converted value */
elmot	1:d0dfbce63a89	1672	return hadc->Instance->DR;
elmot	1:d0dfbce63a89	1673	}
elmot	1:d0dfbce63a89	1674
elmot	1:d0dfbce63a89	1675
elmot	1:d0dfbce63a89	1676	/**
elmot	1:d0dfbce63a89	1677	* @brief Handle ADC interrupt request.
elmot	1:d0dfbce63a89	1678	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	1679	* @retval None
elmot	1:d0dfbce63a89	1680	*/
elmot	1:d0dfbce63a89	1681	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	1682	{
elmot	1:d0dfbce63a89	1683	uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
elmot	1:d0dfbce63a89	1684	ADC_TypeDef *tmpADC_Master;
elmot	1:d0dfbce63a89	1685	uint32_t tmp_isr = hadc->Instance->ISR;
elmot	1:d0dfbce63a89	1686	uint32_t tmp_ier = hadc->Instance->IER;
elmot	1:d0dfbce63a89	1687	uint32_t tmp_cfgr = 0x0;
elmot	1:d0dfbce63a89	1688	uint32_t tmp_cfgr_jqm = 0x0;
elmot	1:d0dfbce63a89	1689
elmot	1:d0dfbce63a89	1690
elmot	1:d0dfbce63a89	1691	/* Check the parameters */
elmot	1:d0dfbce63a89	1692	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	1693	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
elmot	1:d0dfbce63a89	1694
elmot	1:d0dfbce63a89	1695
elmot	1:d0dfbce63a89	1696	/* ====== Check End of Sampling flag for regular group ===== */
elmot	1:d0dfbce63a89	1697	if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
elmot	1:d0dfbce63a89	1698	{
elmot	1:d0dfbce63a89	1699	/* Update state machine on end of sampling status if not in error state */
elmot	1:d0dfbce63a89	1700	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
elmot	1:d0dfbce63a89	1701	{
elmot	1:d0dfbce63a89	1702	/* Change ADC state */
elmot	1:d0dfbce63a89	1703	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
elmot	1:d0dfbce63a89	1704	}
elmot	1:d0dfbce63a89	1705
elmot	1:d0dfbce63a89	1706	/* End Of Sampling callback */
elmot	1:d0dfbce63a89	1707	HAL_ADCEx_EndOfSamplingCallback(hadc);
elmot	1:d0dfbce63a89	1708
elmot	1:d0dfbce63a89	1709	/* Clear regular group conversion flag */
elmot	1:d0dfbce63a89	1710	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
elmot	1:d0dfbce63a89	1711	}
elmot	1:d0dfbce63a89	1712
elmot	1:d0dfbce63a89	1713	/* ====== Check End of Conversion or Sequence flags for regular group ===== */
elmot	1:d0dfbce63a89	1714	if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) \|\|
elmot	1:d0dfbce63a89	1715	(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
elmot	1:d0dfbce63a89	1716	{
elmot	1:d0dfbce63a89	1717	/* Update state machine on conversion status if not in error state */
elmot	1:d0dfbce63a89	1718	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
elmot	1:d0dfbce63a89	1719	{
elmot	1:d0dfbce63a89	1720	/* Change ADC state */
elmot	1:d0dfbce63a89	1721	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
elmot	1:d0dfbce63a89	1722	}
elmot	1:d0dfbce63a89	1723
elmot	1:d0dfbce63a89	1724	/* Disable interruption if no further conversion upcoming by regular */
elmot	1:d0dfbce63a89	1725	/* external trigger or by continuous mode, */
elmot	1:d0dfbce63a89	1726	/* and if scan sequence if completed. */
elmot	1:d0dfbce63a89	1727	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
elmot	1:d0dfbce63a89	1728	{
elmot	1:d0dfbce63a89	1729	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
elmot	1:d0dfbce63a89	1730	{
elmot	1:d0dfbce63a89	1731	/* check CONT bit directly in handle ADC CFGR register */
elmot	1:d0dfbce63a89	1732	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
elmot	1:d0dfbce63a89	1733	}
elmot	1:d0dfbce63a89	1734	else
elmot	1:d0dfbce63a89	1735	{
elmot	1:d0dfbce63a89	1736	/* else need to check Master ADC CONT bit */
elmot	1:d0dfbce63a89	1737	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
elmot	1:d0dfbce63a89	1738	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
elmot	1:d0dfbce63a89	1739	}
elmot	1:d0dfbce63a89	1740
elmot	1:d0dfbce63a89	1741	/* Carry on if continuous mode is disabled */
elmot	1:d0dfbce63a89	1742	if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
elmot	1:d0dfbce63a89	1743	{
elmot	1:d0dfbce63a89	1744	/* If End of Sequence is reached, disable interrupts */
elmot	1:d0dfbce63a89	1745	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
elmot	1:d0dfbce63a89	1746	{
elmot	1:d0dfbce63a89	1747	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
elmot	1:d0dfbce63a89	1748	/* ADSTART==0 (no conversion on going) */
elmot	1:d0dfbce63a89	1749	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
elmot	1:d0dfbce63a89	1750	{
elmot	1:d0dfbce63a89	1751	/* Disable ADC end of sequence conversion interrupt */
elmot	1:d0dfbce63a89	1752	/* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
elmot	1:d0dfbce63a89	1753	/* in HAL_Start_IT(), it isn't disabled here because it can be used */
elmot	1:d0dfbce63a89	1754	/* by overrun IRQ process below. */
elmot	1:d0dfbce63a89	1755	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
elmot	1:d0dfbce63a89	1756	/* Clear HAL_ADC_STATE_REG_BUSY bit */
elmot	1:d0dfbce63a89	1757	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	1758	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	1759	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	1760	{
elmot	1:d0dfbce63a89	1761	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	1762	}
elmot	1:d0dfbce63a89	1763	}
elmot	1:d0dfbce63a89	1764	else
elmot	1:d0dfbce63a89	1765	{
elmot	1:d0dfbce63a89	1766	/* Change ADC state to error state */
elmot	1:d0dfbce63a89	1767	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	1768
elmot	1:d0dfbce63a89	1769	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	1770	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	1771	}
elmot	1:d0dfbce63a89	1772	}
elmot	1:d0dfbce63a89	1773	} /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
elmot	1:d0dfbce63a89	1774	} /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */
elmot	1:d0dfbce63a89	1775
elmot	1:d0dfbce63a89	1776	/* Conversion complete callback */
elmot	1:d0dfbce63a89	1777	/* Note: HAL_ADC_ConvCpltCallback can resort to
elmot	1:d0dfbce63a89	1778	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
elmot	1:d0dfbce63a89	1779	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
elmot	1:d0dfbce63a89	1780	interruption has been triggered by end of conversion or end of
elmot	1:d0dfbce63a89	1781	sequence. */
elmot	1:d0dfbce63a89	1782	HAL_ADC_ConvCpltCallback(hadc);
elmot	1:d0dfbce63a89	1783
elmot	1:d0dfbce63a89	1784
elmot	1:d0dfbce63a89	1785	/* Clear regular group conversion flag */
elmot	1:d0dfbce63a89	1786	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS) );
elmot	1:d0dfbce63a89	1787	}
elmot	1:d0dfbce63a89	1788
elmot	1:d0dfbce63a89	1789
elmot	1:d0dfbce63a89	1790	/* ========== Check End of Conversion flag for injected group ========== */
elmot	1:d0dfbce63a89	1791	if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) \|\|
elmot	1:d0dfbce63a89	1792	(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
elmot	1:d0dfbce63a89	1793	{
elmot	1:d0dfbce63a89	1794	/* Update state machine on conversion status if not in error state */
elmot	1:d0dfbce63a89	1795	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
elmot	1:d0dfbce63a89	1796	{
elmot	1:d0dfbce63a89	1797	/* Change ADC state */
elmot	1:d0dfbce63a89	1798	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
elmot	1:d0dfbce63a89	1799	}
elmot	1:d0dfbce63a89	1800
elmot	1:d0dfbce63a89	1801
elmot	1:d0dfbce63a89	1802	/* Check whether interruptions can be disabled only if
elmot	1:d0dfbce63a89	1803	- injected conversions are software-triggered when injected queue management is disabled
elmot	1:d0dfbce63a89	1804	OR
elmot	1:d0dfbce63a89	1805	- auto-injection is enabled, continuous mode is disabled (CONT = 0)
elmot	1:d0dfbce63a89	1806	and regular conversions are software-triggered */
elmot	1:d0dfbce63a89	1807	/* If End of Sequence is reached, disable interrupts */
elmot	1:d0dfbce63a89	1808	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
elmot	1:d0dfbce63a89	1809	{
elmot	1:d0dfbce63a89	1810
elmot	1:d0dfbce63a89	1811	/* First, retrieve proper registers to check */
elmot	1:d0dfbce63a89	1812	/* 1a. Are injected conversions that of a dual Slave ? */
elmot	1:d0dfbce63a89	1813	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
elmot	1:d0dfbce63a89	1814	{
elmot	1:d0dfbce63a89	1815	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
elmot	1:d0dfbce63a89	1816	check JQM bit directly in ADC CFGR register */
elmot	1:d0dfbce63a89	1817	tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
elmot	1:d0dfbce63a89	1818	}
elmot	1:d0dfbce63a89	1819	else
elmot	1:d0dfbce63a89	1820	{
elmot	1:d0dfbce63a89	1821	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
elmot	1:d0dfbce63a89	1822	need to check JQM bit of Master ADC CFGR register */
elmot	1:d0dfbce63a89	1823	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
elmot	1:d0dfbce63a89	1824	tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
elmot	1:d0dfbce63a89	1825	}
elmot	1:d0dfbce63a89	1826	/* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
elmot	1:d0dfbce63a89	1827	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
elmot	1:d0dfbce63a89	1828	{
elmot	1:d0dfbce63a89	1829	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
elmot	1:d0dfbce63a89	1830	check JAUTO and CONT bits directly in ADC CFGR register */
elmot	1:d0dfbce63a89	1831	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
elmot	1:d0dfbce63a89	1832	}
elmot	1:d0dfbce63a89	1833	else
elmot	1:d0dfbce63a89	1834	{
elmot	1:d0dfbce63a89	1835	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
elmot	1:d0dfbce63a89	1836	check JAUTO and CONT bits of Master ADC CFGR register */
elmot	1:d0dfbce63a89	1837	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
elmot	1:d0dfbce63a89	1838	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
elmot	1:d0dfbce63a89	1839	}
elmot	1:d0dfbce63a89	1840
elmot	1:d0dfbce63a89	1841	/* Secondly, check whether JEOC and JEOS interruptions can be disabled */
elmot	1:d0dfbce63a89	1842	if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
elmot	1:d0dfbce63a89	1843	&& (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) &&
elmot	1:d0dfbce63a89	1844	(ADC_IS_SOFTWARE_START_REGULAR(hadc)))) )
elmot	1:d0dfbce63a89	1845	{
elmot	1:d0dfbce63a89	1846	/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
elmot	1:d0dfbce63a89	1847	/* JADSTART==0 (no conversion on going) */
elmot	1:d0dfbce63a89	1848	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
elmot	1:d0dfbce63a89	1849	{
elmot	1:d0dfbce63a89	1850	/* Disable ADC end of sequence conversion interrupt */
elmot	1:d0dfbce63a89	1851	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC \| ADC_IT_JEOS);
elmot	1:d0dfbce63a89	1852	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
elmot	1:d0dfbce63a89	1853	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
elmot	1:d0dfbce63a89	1854	/* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
elmot	1:d0dfbce63a89	1855	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
elmot	1:d0dfbce63a89	1856	{
elmot	1:d0dfbce63a89	1857	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	1858	}
elmot	1:d0dfbce63a89	1859	}
elmot	1:d0dfbce63a89	1860	else
elmot	1:d0dfbce63a89	1861	{
elmot	1:d0dfbce63a89	1862	/* Change ADC state to error state */
elmot	1:d0dfbce63a89	1863	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	1864
elmot	1:d0dfbce63a89	1865	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	1866	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	1867	}
elmot	1:d0dfbce63a89	1868	}
elmot	1:d0dfbce63a89	1869	} /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
elmot	1:d0dfbce63a89	1870
elmot	1:d0dfbce63a89	1871	/* Injected Conversion complete callback */
elmot	1:d0dfbce63a89	1872	/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
elmot	1:d0dfbce63a89	1873	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
elmot	1:d0dfbce63a89	1874	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
elmot	1:d0dfbce63a89	1875	interruption has been triggered by end of conversion or end of
elmot	1:d0dfbce63a89	1876	sequence. */
elmot	1:d0dfbce63a89	1877	HAL_ADCEx_InjectedConvCpltCallback(hadc);
elmot	1:d0dfbce63a89	1878
elmot	1:d0dfbce63a89	1879	/* Clear injected group conversion flag */
elmot	1:d0dfbce63a89	1880	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC \| ADC_FLAG_JEOS);
elmot	1:d0dfbce63a89	1881	}
elmot	1:d0dfbce63a89	1882
elmot	1:d0dfbce63a89	1883
elmot	1:d0dfbce63a89	1884	/* ========== Check Analog watchdog flags =================================================== */
elmot	1:d0dfbce63a89	1885
elmot	1:d0dfbce63a89	1886	/* ========== Check Analog watchdog 1 flags ========== */
elmot	1:d0dfbce63a89	1887	if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
elmot	1:d0dfbce63a89	1888	{
elmot	1:d0dfbce63a89	1889	/* Change ADC state */
elmot	1:d0dfbce63a89	1890	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
elmot	1:d0dfbce63a89	1891
elmot	1:d0dfbce63a89	1892	/* Level out of window 1 callback */
elmot	1:d0dfbce63a89	1893	HAL_ADC_LevelOutOfWindowCallback(hadc);
elmot	1:d0dfbce63a89	1894	/* Clear ADC Analog watchdog flag */
elmot	1:d0dfbce63a89	1895	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
elmot	1:d0dfbce63a89	1896	}
elmot	1:d0dfbce63a89	1897
elmot	1:d0dfbce63a89	1898	/* ========== Check Analog watchdog 2 flags ========== */
elmot	1:d0dfbce63a89	1899	if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
elmot	1:d0dfbce63a89	1900	{
elmot	1:d0dfbce63a89	1901	/* Change ADC state */
elmot	1:d0dfbce63a89	1902	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
elmot	1:d0dfbce63a89	1903
elmot	1:d0dfbce63a89	1904	/* Level out of window 2 callback */
elmot	1:d0dfbce63a89	1905	HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
elmot	1:d0dfbce63a89	1906	/* Clear ADC Analog watchdog flag */
elmot	1:d0dfbce63a89	1907	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
elmot	1:d0dfbce63a89	1908	}
elmot	1:d0dfbce63a89	1909
elmot	1:d0dfbce63a89	1910	/* ========== Check Analog watchdog 3 flags ========== */
elmot	1:d0dfbce63a89	1911	if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
elmot	1:d0dfbce63a89	1912	{
elmot	1:d0dfbce63a89	1913	/* Change ADC state */
elmot	1:d0dfbce63a89	1914	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
elmot	1:d0dfbce63a89	1915
elmot	1:d0dfbce63a89	1916	/* Level out of window 3 callback */
elmot	1:d0dfbce63a89	1917	HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
elmot	1:d0dfbce63a89	1918	/* Clear ADC Analog watchdog flag */
elmot	1:d0dfbce63a89	1919	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
elmot	1:d0dfbce63a89	1920	}
elmot	1:d0dfbce63a89	1921
elmot	1:d0dfbce63a89	1922
elmot	1:d0dfbce63a89	1923	/* ========== Check Overrun flag ========== */
elmot	1:d0dfbce63a89	1924	if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
elmot	1:d0dfbce63a89	1925	{
elmot	1:d0dfbce63a89	1926	/* If overrun is set to overwrite previous data (default setting), */
elmot	1:d0dfbce63a89	1927	/* overrun event is not considered as an error. */
elmot	1:d0dfbce63a89	1928	/* (cf ref manual "Managing conversions without using the DMA and without */
elmot	1:d0dfbce63a89	1929	/* overrun ") */
elmot	1:d0dfbce63a89	1930	/* Exception for usage with DMA overrun event always considered as an */
elmot	1:d0dfbce63a89	1931	/* error. */
elmot	1:d0dfbce63a89	1932
elmot	1:d0dfbce63a89	1933	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
elmot	1:d0dfbce63a89	1934	{
elmot	1:d0dfbce63a89	1935	overrun_error = 1;
elmot	1:d0dfbce63a89	1936	}
elmot	1:d0dfbce63a89	1937	else
elmot	1:d0dfbce63a89	1938	{
elmot	1:d0dfbce63a89	1939	/* check DMA configuration, depending on multimode set or not,
elmot	1:d0dfbce63a89	1940	or whether or not multimode feature is available */
elmot	1:d0dfbce63a89	1941	if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
elmot	1:d0dfbce63a89	1942	{
elmot	1:d0dfbce63a89	1943	/* Multimode not set or feature not available or ADC independent */
elmot	1:d0dfbce63a89	1944	if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
elmot	1:d0dfbce63a89	1945	{
elmot	1:d0dfbce63a89	1946	overrun_error = 1;
elmot	1:d0dfbce63a89	1947	}
elmot	1:d0dfbce63a89	1948	}
elmot	1:d0dfbce63a89	1949	else
elmot	1:d0dfbce63a89	1950	{
elmot	1:d0dfbce63a89	1951	/* Multimode (when feature is available) is enabled,
elmot	1:d0dfbce63a89	1952	Common Control Register MDMA bits must be checked. */
elmot	1:d0dfbce63a89	1953	if (ADC_MULTIMODE_DMA_ENABLED())
elmot	1:d0dfbce63a89	1954	{
elmot	1:d0dfbce63a89	1955	overrun_error = 1;
elmot	1:d0dfbce63a89	1956	}
elmot	1:d0dfbce63a89	1957	}
elmot	1:d0dfbce63a89	1958	}
elmot	1:d0dfbce63a89	1959
elmot	1:d0dfbce63a89	1960	if (overrun_error == 1)
elmot	1:d0dfbce63a89	1961	{
elmot	1:d0dfbce63a89	1962	/* Change ADC state to error state */
elmot	1:d0dfbce63a89	1963	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
elmot	1:d0dfbce63a89	1964
elmot	1:d0dfbce63a89	1965	/* Set ADC error code to overrun */
elmot	1:d0dfbce63a89	1966	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
elmot	1:d0dfbce63a89	1967
elmot	1:d0dfbce63a89	1968	/* Error callback */
elmot	1:d0dfbce63a89	1969	HAL_ADC_ErrorCallback(hadc);
elmot	1:d0dfbce63a89	1970	}
elmot	1:d0dfbce63a89	1971
elmot	1:d0dfbce63a89	1972	/* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
elmot	1:d0dfbce63a89	1973	old data is preserved until OVR is reset */
elmot	1:d0dfbce63a89	1974	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
elmot	1:d0dfbce63a89	1975
elmot	1:d0dfbce63a89	1976	}
elmot	1:d0dfbce63a89	1977
elmot	1:d0dfbce63a89	1978
elmot	1:d0dfbce63a89	1979	/* ========== Check Injected context queue overflow flag ========== */
elmot	1:d0dfbce63a89	1980	if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
elmot	1:d0dfbce63a89	1981	{
elmot	1:d0dfbce63a89	1982	/* Change ADC state to overrun state */
elmot	1:d0dfbce63a89	1983	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
elmot	1:d0dfbce63a89	1984
elmot	1:d0dfbce63a89	1985	/* Set ADC error code to Injected context queue overflow */
elmot	1:d0dfbce63a89	1986	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
elmot	1:d0dfbce63a89	1987
elmot	1:d0dfbce63a89	1988	/* Clear the Injected context queue overflow flag */
elmot	1:d0dfbce63a89	1989	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
elmot	1:d0dfbce63a89	1990
elmot	1:d0dfbce63a89	1991	/* Error callback */
elmot	1:d0dfbce63a89	1992	HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
elmot	1:d0dfbce63a89	1993	}
elmot	1:d0dfbce63a89	1994
elmot	1:d0dfbce63a89	1995	}
elmot	1:d0dfbce63a89	1996
elmot	1:d0dfbce63a89	1997	/**
elmot	1:d0dfbce63a89	1998	* @brief Conversion complete callback in non-blocking mode.
elmot	1:d0dfbce63a89	1999	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2000	* @retval None
elmot	1:d0dfbce63a89	2001	*/
elmot	1:d0dfbce63a89	2002	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	2003	{
elmot	1:d0dfbce63a89	2004	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	2005	UNUSED(hadc);
elmot	1:d0dfbce63a89	2006
elmot	1:d0dfbce63a89	2007	/* NOTE : This function should not be modified. When the callback is needed,
elmot	1:d0dfbce63a89	2008	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
elmot	1:d0dfbce63a89	2009	*/
elmot	1:d0dfbce63a89	2010	}
elmot	1:d0dfbce63a89	2011
elmot	1:d0dfbce63a89	2012	/**
elmot	1:d0dfbce63a89	2013	* @brief Conversion DMA half-transfer callback in non-blocking mode.
elmot	1:d0dfbce63a89	2014	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2015	* @retval None
elmot	1:d0dfbce63a89	2016	*/
elmot	1:d0dfbce63a89	2017	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	2018	{
elmot	1:d0dfbce63a89	2019	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	2020	UNUSED(hadc);
elmot	1:d0dfbce63a89	2021
elmot	1:d0dfbce63a89	2022	/* NOTE : This function should not be modified. When the callback is needed,
elmot	1:d0dfbce63a89	2023	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
elmot	1:d0dfbce63a89	2024	*/
elmot	1:d0dfbce63a89	2025	}
elmot	1:d0dfbce63a89	2026
elmot	1:d0dfbce63a89	2027	/**
elmot	1:d0dfbce63a89	2028	* @brief Analog watchdog 1 callback in non-blocking mode.
elmot	1:d0dfbce63a89	2029	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2030	* @retval None
elmot	1:d0dfbce63a89	2031	*/
elmot	1:d0dfbce63a89	2032	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	2033	{
elmot	1:d0dfbce63a89	2034	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	2035	UNUSED(hadc);
elmot	1:d0dfbce63a89	2036
elmot	1:d0dfbce63a89	2037	/* NOTE : This function should not be modified. When the callback is needed,
elmot	1:d0dfbce63a89	2038	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
elmot	1:d0dfbce63a89	2039	*/
elmot	1:d0dfbce63a89	2040	}
elmot	1:d0dfbce63a89	2041
elmot	1:d0dfbce63a89	2042	/**
elmot	1:d0dfbce63a89	2043	* @brief ADC error callback in non-blocking mode
elmot	1:d0dfbce63a89	2044	* (ADC conversion with interruption or transfer by DMA).
elmot	1:d0dfbce63a89	2045	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2046	* @retval None
elmot	1:d0dfbce63a89	2047	*/
elmot	1:d0dfbce63a89	2048	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
elmot	1:d0dfbce63a89	2049	{
elmot	1:d0dfbce63a89	2050	/* Prevent unused argument(s) compilation warning */
elmot	1:d0dfbce63a89	2051	UNUSED(hadc);
elmot	1:d0dfbce63a89	2052
elmot	1:d0dfbce63a89	2053	/* NOTE : This function should not be modified. When the callback is needed,
elmot	1:d0dfbce63a89	2054	function HAL_ADC_ErrorCallback must be implemented in the user file.
elmot	1:d0dfbce63a89	2055	*/
elmot	1:d0dfbce63a89	2056	}
elmot	1:d0dfbce63a89	2057
elmot	1:d0dfbce63a89	2058	/**
elmot	1:d0dfbce63a89	2059	* @}
elmot	1:d0dfbce63a89	2060	*/
elmot	1:d0dfbce63a89	2061
elmot	1:d0dfbce63a89	2062	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
elmot	1:d0dfbce63a89	2063	* @brief Peripheral Control functions
elmot	1:d0dfbce63a89	2064	*
elmot	1:d0dfbce63a89	2065	@verbatim
elmot	1:d0dfbce63a89	2066	===============================================================================
elmot	1:d0dfbce63a89	2067	##### Peripheral Control functions #####
elmot	1:d0dfbce63a89	2068	===============================================================================
elmot	1:d0dfbce63a89	2069	[..] This section provides functions allowing to:
elmot	1:d0dfbce63a89	2070	(+) Configure channels on regular group
elmot	1:d0dfbce63a89	2071	(+) Configure the analog watchdog
elmot	1:d0dfbce63a89	2072
elmot	1:d0dfbce63a89	2073	@endverbatim
elmot	1:d0dfbce63a89	2074	* @{
elmot	1:d0dfbce63a89	2075	*/
elmot	1:d0dfbce63a89	2076
elmot	1:d0dfbce63a89	2077
elmot	1:d0dfbce63a89	2078	/**
elmot	1:d0dfbce63a89	2079	* @brief Configure the selected channel to be linked to the regular group.
elmot	1:d0dfbce63a89	2080	* @note In case of usage of internal measurement channels (Vbat / VrefInt /
elmot	1:d0dfbce63a89	2081	* TempSensor), the recommended sampling time is provided by the
elmot	1:d0dfbce63a89	2082	* datasheet.
elmot	1:d0dfbce63a89	2083	* These internal paths can be disabled using function
elmot	1:d0dfbce63a89	2084	* HAL_ADC_DeInit().
elmot	1:d0dfbce63a89	2085	* @note Possibility to update parameters on the fly:
elmot	1:d0dfbce63a89	2086	* HAL_ADC_ConfigChannel() initializes channel into regular group,
elmot	1:d0dfbce63a89	2087	* consecutive calls to this function can be used to reconfigure some
elmot	1:d0dfbce63a89	2088	* parameters of structure "ADC_ChannelConfTypeDef" on the fly, without
elmot	1:d0dfbce63a89	2089	* resetting the ADC.
elmot	1:d0dfbce63a89	2090	* The setting of these parameters is conditioned to ADC state.
elmot	1:d0dfbce63a89	2091	* For parameters constraints, see comments of structure
elmot	1:d0dfbce63a89	2092	* "ADC_ChannelConfTypeDef".
elmot	1:d0dfbce63a89	2093	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2094	* @param sConfig: Structure ADC channel for regular group.
elmot	1:d0dfbce63a89	2095	* @retval HAL status
elmot	1:d0dfbce63a89	2096	*/
elmot	1:d0dfbce63a89	2097	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
elmot	1:d0dfbce63a89	2098	{
elmot	1:d0dfbce63a89	2099	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	2100
elmot	1:d0dfbce63a89	2101	ADC_Common_TypeDef *tmpADC_Common;
elmot	1:d0dfbce63a89	2102	uint32_t tmpOffsetShifted;
elmot	1:d0dfbce63a89	2103	__IO uint32_t wait_loop_index = 0;
elmot	1:d0dfbce63a89	2104
elmot	1:d0dfbce63a89	2105	/* Check the parameters */
elmot	1:d0dfbce63a89	2106	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	2107	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
elmot	1:d0dfbce63a89	2108	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
elmot	1:d0dfbce63a89	2109	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
elmot	1:d0dfbce63a89	2110	assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
elmot	1:d0dfbce63a89	2111	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
elmot	1:d0dfbce63a89	2112
elmot	1:d0dfbce63a89	2113	/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
elmot	1:d0dfbce63a89	2114	ignored (considered as reset) */
elmot	1:d0dfbce63a89	2115	assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
elmot	1:d0dfbce63a89	2116
elmot	1:d0dfbce63a89	2117	/* Verification of channel number */
elmot	1:d0dfbce63a89	2118	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
elmot	1:d0dfbce63a89	2119	{
elmot	1:d0dfbce63a89	2120	assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
elmot	1:d0dfbce63a89	2121	}
elmot	1:d0dfbce63a89	2122	else
elmot	1:d0dfbce63a89	2123	{
elmot	1:d0dfbce63a89	2124	assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
elmot	1:d0dfbce63a89	2125	}
elmot	1:d0dfbce63a89	2126
elmot	1:d0dfbce63a89	2127	/* Process locked */
elmot	1:d0dfbce63a89	2128	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	2129
elmot	1:d0dfbce63a89	2130
elmot	1:d0dfbce63a89	2131	/* Parameters update conditioned to ADC state: */
elmot	1:d0dfbce63a89	2132	/* Parameters that can be updated when ADC is disabled or enabled without */
elmot	1:d0dfbce63a89	2133	/* conversion on going on regular group: */
elmot	1:d0dfbce63a89	2134	/* - Channel number */
elmot	1:d0dfbce63a89	2135	/* - Channel rank */
elmot	1:d0dfbce63a89	2136	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
elmot	1:d0dfbce63a89	2137	{
elmot	1:d0dfbce63a89	2138
elmot	1:d0dfbce63a89	2139	/* Regular sequence configuration */
elmot	1:d0dfbce63a89	2140	/* Clear the old SQx bits then set the new ones for the selected rank */
elmot	1:d0dfbce63a89	2141	/* For Rank 1 to 4 */
elmot	1:d0dfbce63a89	2142	if (sConfig->Rank < 5)
elmot	1:d0dfbce63a89	2143	{
elmot	1:d0dfbce63a89	2144	MODIFY_REG(hadc->Instance->SQR1,
elmot	1:d0dfbce63a89	2145	ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
elmot	1:d0dfbce63a89	2146	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
elmot	1:d0dfbce63a89	2147	}
elmot	1:d0dfbce63a89	2148	/* For Rank 5 to 9 */
elmot	1:d0dfbce63a89	2149	else if (sConfig->Rank < 10)
elmot	1:d0dfbce63a89	2150	{
elmot	1:d0dfbce63a89	2151	MODIFY_REG(hadc->Instance->SQR2,
elmot	1:d0dfbce63a89	2152	ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
elmot	1:d0dfbce63a89	2153	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
elmot	1:d0dfbce63a89	2154	}
elmot	1:d0dfbce63a89	2155	/* For Rank 10 to 14 */
elmot	1:d0dfbce63a89	2156	else if (sConfig->Rank < 15)
elmot	1:d0dfbce63a89	2157	{
elmot	1:d0dfbce63a89	2158	MODIFY_REG(hadc->Instance->SQR3,
elmot	1:d0dfbce63a89	2159	ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
elmot	1:d0dfbce63a89	2160	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
elmot	1:d0dfbce63a89	2161	}
elmot	1:d0dfbce63a89	2162	/* For Rank 15 to 16 */
elmot	1:d0dfbce63a89	2163	else
elmot	1:d0dfbce63a89	2164	{
elmot	1:d0dfbce63a89	2165	MODIFY_REG(hadc->Instance->SQR4,
elmot	1:d0dfbce63a89	2166	ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
elmot	1:d0dfbce63a89	2167	ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
elmot	1:d0dfbce63a89	2168	}
elmot	1:d0dfbce63a89	2169
elmot	1:d0dfbce63a89	2170
elmot	1:d0dfbce63a89	2171	/* Parameters update conditioned to ADC state: */
elmot	1:d0dfbce63a89	2172	/* Parameters that can be updated when ADC is disabled or enabled without */
elmot	1:d0dfbce63a89	2173	/* conversion on going on regular group: */
elmot	1:d0dfbce63a89	2174	/* - Channel sampling time */
elmot	1:d0dfbce63a89	2175	/* - Channel offset */
elmot	1:d0dfbce63a89	2176	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
elmot	1:d0dfbce63a89	2177	{
elmot	1:d0dfbce63a89	2178
elmot	1:d0dfbce63a89	2179	/* Channel sampling time configuration */
elmot	1:d0dfbce63a89	2180	/* Clear the old sample time then set the new one for the selected channel */
elmot	1:d0dfbce63a89	2181	/* For channels 10 to 18 */
elmot	1:d0dfbce63a89	2182	if (sConfig->Channel >= ADC_CHANNEL_10)
elmot	1:d0dfbce63a89	2183	{
elmot	1:d0dfbce63a89	2184	ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
elmot	1:d0dfbce63a89	2185	}
elmot	1:d0dfbce63a89	2186	else /* For channels 0 to 9 */
elmot	1:d0dfbce63a89	2187	{
elmot	1:d0dfbce63a89	2188	ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
elmot	1:d0dfbce63a89	2189	}
elmot	1:d0dfbce63a89	2190
elmot	1:d0dfbce63a89	2191
elmot	1:d0dfbce63a89	2192	/* Configure the offset: offset enable/disable, channel, offset value */
elmot	1:d0dfbce63a89	2193
elmot	1:d0dfbce63a89	2194	/* Shift the offset with respect to the selected ADC resolution. */
elmot	1:d0dfbce63a89	2195	/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
elmot	1:d0dfbce63a89	2196	tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
elmot	1:d0dfbce63a89	2197
elmot	1:d0dfbce63a89	2198	switch (sConfig->OffsetNumber)
elmot	1:d0dfbce63a89	2199	{
elmot	1:d0dfbce63a89	2200	/* Configure offset register i when applicable: */
elmot	1:d0dfbce63a89	2201	/* - Enable offset */
elmot	1:d0dfbce63a89	2202	/* - Set channel number */
elmot	1:d0dfbce63a89	2203	/* - Set offset value */
elmot	1:d0dfbce63a89	2204	case ADC_OFFSET_1:
elmot	1:d0dfbce63a89	2205	MODIFY_REG(hadc->Instance->OFR1,
elmot	1:d0dfbce63a89	2206	ADC_OFR_FIELDS,
elmot	1:d0dfbce63a89	2207	ADC_OFR1_OFFSET1_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
elmot	1:d0dfbce63a89	2208	break;
elmot	1:d0dfbce63a89	2209
elmot	1:d0dfbce63a89	2210	case ADC_OFFSET_2:
elmot	1:d0dfbce63a89	2211	MODIFY_REG(hadc->Instance->OFR2,
elmot	1:d0dfbce63a89	2212	ADC_OFR_FIELDS,
elmot	1:d0dfbce63a89	2213	ADC_OFR2_OFFSET2_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
elmot	1:d0dfbce63a89	2214	break;
elmot	1:d0dfbce63a89	2215
elmot	1:d0dfbce63a89	2216	case ADC_OFFSET_3:
elmot	1:d0dfbce63a89	2217	MODIFY_REG(hadc->Instance->OFR3,
elmot	1:d0dfbce63a89	2218	ADC_OFR_FIELDS,
elmot	1:d0dfbce63a89	2219	ADC_OFR3_OFFSET3_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
elmot	1:d0dfbce63a89	2220	break;
elmot	1:d0dfbce63a89	2221
elmot	1:d0dfbce63a89	2222	case ADC_OFFSET_4:
elmot	1:d0dfbce63a89	2223	MODIFY_REG(hadc->Instance->OFR4,
elmot	1:d0dfbce63a89	2224	ADC_OFR_FIELDS,
elmot	1:d0dfbce63a89	2225	ADC_OFR4_OFFSET4_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
elmot	1:d0dfbce63a89	2226	break;
elmot	1:d0dfbce63a89	2227
elmot	1:d0dfbce63a89	2228	/* Case ADC_OFFSET_NONE */
elmot	1:d0dfbce63a89	2229	default :
elmot	1:d0dfbce63a89	2230	/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
elmot	1:d0dfbce63a89	2231	If this is the case, offset OFRx is disabled since
elmot	1:d0dfbce63a89	2232	sConfig->OffsetNumber = ADC_OFFSET_NONE. */
elmot	1:d0dfbce63a89	2233	if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
elmot	1:d0dfbce63a89	2234	{
elmot	1:d0dfbce63a89	2235	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
elmot	1:d0dfbce63a89	2236	}
elmot	1:d0dfbce63a89	2237	if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
elmot	1:d0dfbce63a89	2238	{
elmot	1:d0dfbce63a89	2239	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
elmot	1:d0dfbce63a89	2240	}
elmot	1:d0dfbce63a89	2241	if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
elmot	1:d0dfbce63a89	2242	{
elmot	1:d0dfbce63a89	2243	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
elmot	1:d0dfbce63a89	2244	}
elmot	1:d0dfbce63a89	2245	if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
elmot	1:d0dfbce63a89	2246	{
elmot	1:d0dfbce63a89	2247	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
elmot	1:d0dfbce63a89	2248	}
elmot	1:d0dfbce63a89	2249	break;
elmot	1:d0dfbce63a89	2250	} /* switch (sConfig->OffsetNumber) */
elmot	1:d0dfbce63a89	2251
elmot	1:d0dfbce63a89	2252	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
elmot	1:d0dfbce63a89	2253
elmot	1:d0dfbce63a89	2254
elmot	1:d0dfbce63a89	2255
elmot	1:d0dfbce63a89	2256	/* Parameters update conditioned to ADC state: */
elmot	1:d0dfbce63a89	2257	/* Parameters that can be updated only when ADC is disabled: */
elmot	1:d0dfbce63a89	2258	/* - Single or differential mode */
elmot	1:d0dfbce63a89	2259	/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
elmot	1:d0dfbce63a89	2260	if (ADC_IS_ENABLE(hadc) == RESET)
elmot	1:d0dfbce63a89	2261	{
elmot	1:d0dfbce63a89	2262	/* Configuration of differential mode */
elmot	1:d0dfbce63a89	2263	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
elmot	1:d0dfbce63a89	2264	{
elmot	1:d0dfbce63a89	2265	/* Disable differential mode (default mode: single-ended) */
elmot	1:d0dfbce63a89	2266	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
elmot	1:d0dfbce63a89	2267	}
elmot	1:d0dfbce63a89	2268	else
elmot	1:d0dfbce63a89	2269	{
elmot	1:d0dfbce63a89	2270	/* Enable differential mode */
elmot	1:d0dfbce63a89	2271	SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
elmot	1:d0dfbce63a89	2272
elmot	1:d0dfbce63a89	2273	/* Sampling time configuration of channel ADC_IN+1 (negative input) */
elmot	1:d0dfbce63a89	2274	/* Clear the old sample time then set the new one for the selected */
elmot	1:d0dfbce63a89	2275	/* channel. */
elmot	1:d0dfbce63a89	2276	/* Starting from channel 9, SMPR2 register must be configured */
elmot	1:d0dfbce63a89	2277	if (sConfig->Channel >= ADC_CHANNEL_9)
elmot	1:d0dfbce63a89	2278	{
elmot	1:d0dfbce63a89	2279	ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
elmot	1:d0dfbce63a89	2280	}
elmot	1:d0dfbce63a89	2281	else /* For channels 0 to 8, SMPR1 must be configured */
elmot	1:d0dfbce63a89	2282	{
elmot	1:d0dfbce63a89	2283	ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
elmot	1:d0dfbce63a89	2284	}
elmot	1:d0dfbce63a89	2285	}
elmot	1:d0dfbce63a89	2286
elmot	1:d0dfbce63a89	2287
elmot	1:d0dfbce63a89	2288
elmot	1:d0dfbce63a89	2289	/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
elmot	1:d0dfbce63a89	2290	/* If internal channel selected, enable dedicated internal buffers and */
elmot	1:d0dfbce63a89	2291	/* paths. */
elmot	1:d0dfbce63a89	2292	/* Note: these internal measurement paths can be disabled using */
elmot	1:d0dfbce63a89	2293	/* HAL_ADC_DeInit(). */
elmot	1:d0dfbce63a89	2294
elmot	1:d0dfbce63a89	2295	/* Configuration of common ADC parameters */
elmot	1:d0dfbce63a89	2296	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
elmot	1:d0dfbce63a89	2297
elmot	1:d0dfbce63a89	2298
elmot	1:d0dfbce63a89	2299	/* If the requested internal measurement path has already been enabled, */
elmot	1:d0dfbce63a89	2300	/* bypass the configuration processing. */
elmot	1:d0dfbce63a89	2301	if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
elmot	1:d0dfbce63a89	2302	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) \|\|
elmot	1:d0dfbce63a89	2303	( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
elmot	1:d0dfbce63a89	2304	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) \|\|
elmot	1:d0dfbce63a89	2305	( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
elmot	1:d0dfbce63a89	2306	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
elmot	1:d0dfbce63a89	2307	)
elmot	1:d0dfbce63a89	2308	{
elmot	1:d0dfbce63a89	2309	/* Configuration of common ADC parameters (continuation) */
elmot	1:d0dfbce63a89	2310
elmot	1:d0dfbce63a89	2311	/* Software is allowed to change common parameters only when all ADCs */
elmot	1:d0dfbce63a89	2312	/* of the common group are disabled. */
elmot	1:d0dfbce63a89	2313	if ((ADC_IS_ENABLE(hadc) == RESET) &&
elmot	1:d0dfbce63a89	2314	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
elmot	1:d0dfbce63a89	2315	{
elmot	1:d0dfbce63a89	2316	if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
elmot	1:d0dfbce63a89	2317	{
elmot	1:d0dfbce63a89	2318	if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
elmot	1:d0dfbce63a89	2319	{
elmot	1:d0dfbce63a89	2320	SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
elmot	1:d0dfbce63a89	2321
elmot	1:d0dfbce63a89	2322	/* Delay for temperature sensor stabilization time */
elmot	1:d0dfbce63a89	2323	/* Wait loop initialization and execution */
elmot	1:d0dfbce63a89	2324	/* Note: Variable divided by 2 to compensate partially */
elmot	1:d0dfbce63a89	2325	/* CPU processing cycles. */
elmot	1:d0dfbce63a89	2326	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
elmot	1:d0dfbce63a89	2327	while(wait_loop_index != 0)
elmot	1:d0dfbce63a89	2328	{
elmot	1:d0dfbce63a89	2329	wait_loop_index--;
elmot	1:d0dfbce63a89	2330	}
elmot	1:d0dfbce63a89	2331	}
elmot	1:d0dfbce63a89	2332	}
elmot	1:d0dfbce63a89	2333	else if (sConfig->Channel == ADC_CHANNEL_VBAT)
elmot	1:d0dfbce63a89	2334	{
elmot	1:d0dfbce63a89	2335	if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
elmot	1:d0dfbce63a89	2336	{
elmot	1:d0dfbce63a89	2337	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
elmot	1:d0dfbce63a89	2338	}
elmot	1:d0dfbce63a89	2339	}
elmot	1:d0dfbce63a89	2340	else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
elmot	1:d0dfbce63a89	2341	{
elmot	1:d0dfbce63a89	2342	if (ADC_VREFINT_INSTANCE(hadc))
elmot	1:d0dfbce63a89	2343	{
elmot	1:d0dfbce63a89	2344	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
elmot	1:d0dfbce63a89	2345	}
elmot	1:d0dfbce63a89	2346	}
elmot	1:d0dfbce63a89	2347	}
elmot	1:d0dfbce63a89	2348	/* If the requested internal measurement path has already been */
elmot	1:d0dfbce63a89	2349	/* enabled and other ADC of the common group are enabled, internal */
elmot	1:d0dfbce63a89	2350	/* measurement paths cannot be enabled. */
elmot	1:d0dfbce63a89	2351	else
elmot	1:d0dfbce63a89	2352	{
elmot	1:d0dfbce63a89	2353	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2354	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
elmot	1:d0dfbce63a89	2355
elmot	1:d0dfbce63a89	2356	tmp_status = HAL_ERROR;
elmot	1:d0dfbce63a89	2357	}
elmot	1:d0dfbce63a89	2358	}
elmot	1:d0dfbce63a89	2359
elmot	1:d0dfbce63a89	2360	} /* if (ADC_IS_ENABLE(hadc) == RESET) */
elmot	1:d0dfbce63a89	2361
elmot	1:d0dfbce63a89	2362	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
elmot	1:d0dfbce63a89	2363
elmot	1:d0dfbce63a89	2364	/* If a conversion is on going on regular group, no update on regular */
elmot	1:d0dfbce63a89	2365	/* channel could be done on neither of the channel configuration structure */
elmot	1:d0dfbce63a89	2366	/* parameters. */
elmot	1:d0dfbce63a89	2367	else
elmot	1:d0dfbce63a89	2368	{
elmot	1:d0dfbce63a89	2369	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2370	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
elmot	1:d0dfbce63a89	2371
elmot	1:d0dfbce63a89	2372	tmp_status = HAL_ERROR;
elmot	1:d0dfbce63a89	2373	}
elmot	1:d0dfbce63a89	2374
elmot	1:d0dfbce63a89	2375	/* Process unlocked */
elmot	1:d0dfbce63a89	2376	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	2377
elmot	1:d0dfbce63a89	2378	/* Return function status */
elmot	1:d0dfbce63a89	2379	return tmp_status;
elmot	1:d0dfbce63a89	2380	}
elmot	1:d0dfbce63a89	2381
elmot	1:d0dfbce63a89	2382
elmot	1:d0dfbce63a89	2383
elmot	1:d0dfbce63a89	2384	/**
elmot	1:d0dfbce63a89	2385	* @brief Configure the analog watchdog.
elmot	1:d0dfbce63a89	2386	* @note Possibility to update parameters on the fly:
elmot	1:d0dfbce63a89	2387	* This function initializes the selected analog watchdog, successive
elmot	1:d0dfbce63a89	2388	* calls to this function can be used to reconfigure some parameters
elmot	1:d0dfbce63a89	2389	* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
elmot	1:d0dfbce63a89	2390	* the ADC, e.g. to set several channels to monitor simultaneously.
elmot	1:d0dfbce63a89	2391	* The setting of these parameters is conditioned to ADC state.
elmot	1:d0dfbce63a89	2392	* For parameters constraints, see comments of structure
elmot	1:d0dfbce63a89	2393	* "ADC_AnalogWDGConfTypeDef".
elmot	1:d0dfbce63a89	2394	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2395	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
elmot	1:d0dfbce63a89	2396	* @retval HAL status
elmot	1:d0dfbce63a89	2397	*/
elmot	1:d0dfbce63a89	2398	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
elmot	1:d0dfbce63a89	2399	{
elmot	1:d0dfbce63a89	2400	HAL_StatusTypeDef tmp_status = HAL_OK;
elmot	1:d0dfbce63a89	2401
elmot	1:d0dfbce63a89	2402
elmot	1:d0dfbce63a89	2403	uint32_t tmpAWDHighThresholdShifted;
elmot	1:d0dfbce63a89	2404	uint32_t tmpAWDLowThresholdShifted;
elmot	1:d0dfbce63a89	2405
elmot	1:d0dfbce63a89	2406	uint32_t tmpADCFlagAWD2orAWD3;
elmot	1:d0dfbce63a89	2407	uint32_t tmpADCITAWD2orAWD3;
elmot	1:d0dfbce63a89	2408
elmot	1:d0dfbce63a89	2409	/* Check the parameters */
elmot	1:d0dfbce63a89	2410	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	2411	assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
elmot	1:d0dfbce63a89	2412	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
elmot	1:d0dfbce63a89	2413	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
elmot	1:d0dfbce63a89	2414
elmot	1:d0dfbce63a89	2415	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
elmot	1:d0dfbce63a89	2416	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
elmot	1:d0dfbce63a89	2417	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
elmot	1:d0dfbce63a89	2418	{
elmot	1:d0dfbce63a89	2419	assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
elmot	1:d0dfbce63a89	2420	}
elmot	1:d0dfbce63a89	2421
elmot	1:d0dfbce63a89	2422
elmot	1:d0dfbce63a89	2423	/* Verify if threshold is within the selected ADC resolution */
elmot	1:d0dfbce63a89	2424	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
elmot	1:d0dfbce63a89	2425	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
elmot	1:d0dfbce63a89	2426
elmot	1:d0dfbce63a89	2427	/* Process locked */
elmot	1:d0dfbce63a89	2428	__HAL_LOCK(hadc);
elmot	1:d0dfbce63a89	2429
elmot	1:d0dfbce63a89	2430	/* Parameters update conditioned to ADC state: */
elmot	1:d0dfbce63a89	2431	/* Parameters that can be updated when ADC is disabled or enabled without */
elmot	1:d0dfbce63a89	2432	/* conversion on going on regular and injected groups: */
elmot	1:d0dfbce63a89	2433	/* - Analog watchdog channels */
elmot	1:d0dfbce63a89	2434	/* - Analog watchdog thresholds */
elmot	1:d0dfbce63a89	2435	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
elmot	1:d0dfbce63a89	2436	{
elmot	1:d0dfbce63a89	2437
elmot	1:d0dfbce63a89	2438	/* Analog watchdogs configuration */
elmot	1:d0dfbce63a89	2439	if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
elmot	1:d0dfbce63a89	2440	{
elmot	1:d0dfbce63a89	2441	/* Configuration of analog watchdog: */
elmot	1:d0dfbce63a89	2442	/* - Set the analog watchdog enable mode: regular and/or injected */
elmot	1:d0dfbce63a89	2443	/* groups, one or overall group of channels. */
elmot	1:d0dfbce63a89	2444	/* - Set the Analog watchdog channel (is not used if watchdog */
elmot	1:d0dfbce63a89	2445	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
elmot	1:d0dfbce63a89	2446
elmot	1:d0dfbce63a89	2447	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS,
elmot	1:d0dfbce63a89	2448	AnalogWDGConfig->WatchdogMode \| ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
elmot	1:d0dfbce63a89	2449
elmot	1:d0dfbce63a89	2450	/* Shift the offset with respect to the selected ADC resolution: */
elmot	1:d0dfbce63a89	2451	/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
elmot	1:d0dfbce63a89	2452	/* are set to 0 */
elmot	1:d0dfbce63a89	2453	tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
elmot	1:d0dfbce63a89	2454	tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
elmot	1:d0dfbce63a89	2455
elmot	1:d0dfbce63a89	2456	/* Set the high and low thresholds */
elmot	1:d0dfbce63a89	2457	MODIFY_REG(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1,
elmot	1:d0dfbce63a89	2458	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
elmot	1:d0dfbce63a89	2459
elmot	1:d0dfbce63a89	2460	/* Clear the ADC Analog watchdog flag (in case left enabled by */
elmot	1:d0dfbce63a89	2461	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
elmot	1:d0dfbce63a89	2462	/* or HAL_ADC_PollForEvent(). */
elmot	1:d0dfbce63a89	2463	__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
elmot	1:d0dfbce63a89	2464
elmot	1:d0dfbce63a89	2465	/* Configure ADC Analog watchdog interrupt */
elmot	1:d0dfbce63a89	2466	if(AnalogWDGConfig->ITMode == ENABLE)
elmot	1:d0dfbce63a89	2467	{
elmot	1:d0dfbce63a89	2468	/* Enable the ADC Analog watchdog interrupt */
elmot	1:d0dfbce63a89	2469	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
elmot	1:d0dfbce63a89	2470	}
elmot	1:d0dfbce63a89	2471	else
elmot	1:d0dfbce63a89	2472	{
elmot	1:d0dfbce63a89	2473	/* Disable the ADC Analog watchdog interrupt */
elmot	1:d0dfbce63a89	2474	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
elmot	1:d0dfbce63a89	2475	}
elmot	1:d0dfbce63a89	2476
elmot	1:d0dfbce63a89	2477	/* Update state, clear previous result related to AWD1 */
elmot	1:d0dfbce63a89	2478	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
elmot	1:d0dfbce63a89	2479	}
elmot	1:d0dfbce63a89	2480	/* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
elmot	1:d0dfbce63a89	2481	else
elmot	1:d0dfbce63a89	2482	{
elmot	1:d0dfbce63a89	2483	/* Shift the threshold with respect to the selected ADC resolution */
elmot	1:d0dfbce63a89	2484	/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
elmot	1:d0dfbce63a89	2485	tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
elmot	1:d0dfbce63a89	2486	tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
elmot	1:d0dfbce63a89	2487
elmot	1:d0dfbce63a89	2488	if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
elmot	1:d0dfbce63a89	2489	{
elmot	1:d0dfbce63a89	2490	/* Set the Analog watchdog channel or group of channels. This also */
elmot	1:d0dfbce63a89	2491	/* enables the watchdog. */
elmot	1:d0dfbce63a89	2492	/* Note: Conditional register reset, because several channels can be */
elmot	1:d0dfbce63a89	2493	/* set by successive calls of this function. */
elmot	1:d0dfbce63a89	2494	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
elmot	1:d0dfbce63a89	2495	{
elmot	1:d0dfbce63a89	2496	SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
elmot	1:d0dfbce63a89	2497	}
elmot	1:d0dfbce63a89	2498	else
elmot	1:d0dfbce63a89	2499	{
elmot	1:d0dfbce63a89	2500	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
elmot	1:d0dfbce63a89	2501	}
elmot	1:d0dfbce63a89	2502
elmot	1:d0dfbce63a89	2503	/* Set the high and low thresholds */
elmot	1:d0dfbce63a89	2504	MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2,
elmot	1:d0dfbce63a89	2505	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
elmot	1:d0dfbce63a89	2506
elmot	1:d0dfbce63a89	2507	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
elmot	1:d0dfbce63a89	2508	/* settings. */
elmot	1:d0dfbce63a89	2509	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
elmot	1:d0dfbce63a89	2510	tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
elmot	1:d0dfbce63a89	2511
elmot	1:d0dfbce63a89	2512	/* Update state, clear previous result related to AWD2 */
elmot	1:d0dfbce63a89	2513	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
elmot	1:d0dfbce63a89	2514	}
elmot	1:d0dfbce63a89	2515	/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
elmot	1:d0dfbce63a89	2516	else
elmot	1:d0dfbce63a89	2517	{
elmot	1:d0dfbce63a89	2518	/* Set the Analog watchdog channel or group of channels. This also */
elmot	1:d0dfbce63a89	2519	/* enables the watchdog. */
elmot	1:d0dfbce63a89	2520	/* Note: Conditional register reset, because several channels can be */
elmot	1:d0dfbce63a89	2521	/* set by successive calls of this function. */
elmot	1:d0dfbce63a89	2522	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
elmot	1:d0dfbce63a89	2523	{
elmot	1:d0dfbce63a89	2524	SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
elmot	1:d0dfbce63a89	2525	}
elmot	1:d0dfbce63a89	2526	else
elmot	1:d0dfbce63a89	2527	{
elmot	1:d0dfbce63a89	2528	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
elmot	1:d0dfbce63a89	2529	}
elmot	1:d0dfbce63a89	2530
elmot	1:d0dfbce63a89	2531	/* Set the high and low thresholds */
elmot	1:d0dfbce63a89	2532	MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3,
elmot	1:d0dfbce63a89	2533	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
elmot	1:d0dfbce63a89	2534
elmot	1:d0dfbce63a89	2535	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
elmot	1:d0dfbce63a89	2536	/* settings. */
elmot	1:d0dfbce63a89	2537	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
elmot	1:d0dfbce63a89	2538	tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
elmot	1:d0dfbce63a89	2539
elmot	1:d0dfbce63a89	2540	/* Update state, clear previous result related to AWD3 */
elmot	1:d0dfbce63a89	2541	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
elmot	1:d0dfbce63a89	2542	}
elmot	1:d0dfbce63a89	2543
elmot	1:d0dfbce63a89	2544	/* Clear the ADC Analog watchdog flag (in case left enabled by */
elmot	1:d0dfbce63a89	2545	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
elmot	1:d0dfbce63a89	2546	/* or HAL_ADC_PollForEvent(). */
elmot	1:d0dfbce63a89	2547	__HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
elmot	1:d0dfbce63a89	2548
elmot	1:d0dfbce63a89	2549	/* Configure ADC Analog watchdog interrupt */
elmot	1:d0dfbce63a89	2550	if(AnalogWDGConfig->ITMode == ENABLE)
elmot	1:d0dfbce63a89	2551	{
elmot	1:d0dfbce63a89	2552	__HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
elmot	1:d0dfbce63a89	2553	}
elmot	1:d0dfbce63a89	2554	else
elmot	1:d0dfbce63a89	2555	{
elmot	1:d0dfbce63a89	2556	__HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
elmot	1:d0dfbce63a89	2557	}
elmot	1:d0dfbce63a89	2558	}
elmot	1:d0dfbce63a89	2559
elmot	1:d0dfbce63a89	2560	}
elmot	1:d0dfbce63a89	2561	/* If a conversion is on going on regular or injected groups, no update */
elmot	1:d0dfbce63a89	2562	/* could be done on neither of the AWD configuration structure parameters. */
elmot	1:d0dfbce63a89	2563	else
elmot	1:d0dfbce63a89	2564	{
elmot	1:d0dfbce63a89	2565	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2566	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
elmot	1:d0dfbce63a89	2567
elmot	1:d0dfbce63a89	2568	tmp_status = HAL_ERROR;
elmot	1:d0dfbce63a89	2569	}
elmot	1:d0dfbce63a89	2570
elmot	1:d0dfbce63a89	2571
elmot	1:d0dfbce63a89	2572	/* Process unlocked */
elmot	1:d0dfbce63a89	2573	__HAL_UNLOCK(hadc);
elmot	1:d0dfbce63a89	2574
elmot	1:d0dfbce63a89	2575
elmot	1:d0dfbce63a89	2576	/* Return function status */
elmot	1:d0dfbce63a89	2577	return tmp_status;
elmot	1:d0dfbce63a89	2578	}
elmot	1:d0dfbce63a89	2579
elmot	1:d0dfbce63a89	2580
elmot	1:d0dfbce63a89	2581	/**
elmot	1:d0dfbce63a89	2582	* @}
elmot	1:d0dfbce63a89	2583	*/
elmot	1:d0dfbce63a89	2584
elmot	1:d0dfbce63a89	2585	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
elmot	1:d0dfbce63a89	2586	* @brief ADC Peripheral State functions
elmot	1:d0dfbce63a89	2587	*
elmot	1:d0dfbce63a89	2588	@verbatim
elmot	1:d0dfbce63a89	2589	===============================================================================
elmot	1:d0dfbce63a89	2590	##### Peripheral state and errors functions #####
elmot	1:d0dfbce63a89	2591	===============================================================================
elmot	1:d0dfbce63a89	2592	[..]
elmot	1:d0dfbce63a89	2593	This subsection provides functions to get in run-time the status of the
elmot	1:d0dfbce63a89	2594	peripheral.
elmot	1:d0dfbce63a89	2595	(+) Check the ADC state
elmot	1:d0dfbce63a89	2596	(+) Check the ADC error code
elmot	1:d0dfbce63a89	2597
elmot	1:d0dfbce63a89	2598	@endverbatim
elmot	1:d0dfbce63a89	2599	* @{
elmot	1:d0dfbce63a89	2600	*/
elmot	1:d0dfbce63a89	2601
elmot	1:d0dfbce63a89	2602	/**
elmot	1:d0dfbce63a89	2603	* @brief Return the ADC handle state.
elmot	1:d0dfbce63a89	2604	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2605	* @retval HAL state (uint32_t bit-map)
elmot	1:d0dfbce63a89	2606	*/
elmot	1:d0dfbce63a89	2607	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	2608	{
elmot	1:d0dfbce63a89	2609	/* Check the parameters */
elmot	1:d0dfbce63a89	2610	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	2611
elmot	1:d0dfbce63a89	2612	/* Return ADC handle state */
elmot	1:d0dfbce63a89	2613	return hadc->State;
elmot	1:d0dfbce63a89	2614	}
elmot	1:d0dfbce63a89	2615
elmot	1:d0dfbce63a89	2616
elmot	1:d0dfbce63a89	2617	/**
elmot	1:d0dfbce63a89	2618	* @brief Return the ADC error code.
elmot	1:d0dfbce63a89	2619	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2620	* @retval ADC Error Code (uint32_t bit-map)
elmot	1:d0dfbce63a89	2621	*/
elmot	1:d0dfbce63a89	2622	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
elmot	1:d0dfbce63a89	2623	{
elmot	1:d0dfbce63a89	2624	/* Check the parameters */
elmot	1:d0dfbce63a89	2625	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	2626
elmot	1:d0dfbce63a89	2627	return hadc->ErrorCode;
elmot	1:d0dfbce63a89	2628	}
elmot	1:d0dfbce63a89	2629
elmot	1:d0dfbce63a89	2630	/**
elmot	1:d0dfbce63a89	2631	* @}
elmot	1:d0dfbce63a89	2632	*/
elmot	1:d0dfbce63a89	2633
elmot	1:d0dfbce63a89	2634	/**
elmot	1:d0dfbce63a89	2635	* @}
elmot	1:d0dfbce63a89	2636	*/
elmot	1:d0dfbce63a89	2637
elmot	1:d0dfbce63a89	2638
elmot	1:d0dfbce63a89	2639
elmot	1:d0dfbce63a89	2640	/** @defgroup ADC_Private_Functions ADC Private Functions
elmot	1:d0dfbce63a89	2641	* @{
elmot	1:d0dfbce63a89	2642	*/
elmot	1:d0dfbce63a89	2643
elmot	1:d0dfbce63a89	2644	/**
elmot	1:d0dfbce63a89	2645	* @brief Stop ADC conversion.
elmot	1:d0dfbce63a89	2646	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2647	* @param ConversionGroup: ADC group regular and/or injected.
elmot	1:d0dfbce63a89	2648	* This parameter can be one of the following values:
elmot	1:d0dfbce63a89	2649	* @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
elmot	1:d0dfbce63a89	2650	* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
elmot	1:d0dfbce63a89	2651	* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
elmot	1:d0dfbce63a89	2652	* @retval HAL status.
elmot	1:d0dfbce63a89	2653	*/
elmot	1:d0dfbce63a89	2654	HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
elmot	1:d0dfbce63a89	2655	{
elmot	1:d0dfbce63a89	2656	uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
elmot	1:d0dfbce63a89	2657	uint32_t tickstart = 0;
elmot	1:d0dfbce63a89	2658	uint32_t Conversion_Timeout_CPU_cycles = 0;
elmot	1:d0dfbce63a89	2659
elmot	1:d0dfbce63a89	2660	/* Check the parameters */
elmot	1:d0dfbce63a89	2661	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
elmot	1:d0dfbce63a89	2662	assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
elmot	1:d0dfbce63a89	2663
elmot	1:d0dfbce63a89	2664	/* Verification if ADC is not already stopped (on regular and injected */
elmot	1:d0dfbce63a89	2665	/* groups) to bypass this function if not needed. */
elmot	1:d0dfbce63a89	2666	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
elmot	1:d0dfbce63a89	2667	{
elmot	1:d0dfbce63a89	2668	/* Particular case of continuous auto-injection mode combined with */
elmot	1:d0dfbce63a89	2669	/* auto-delay mode. */
elmot	1:d0dfbce63a89	2670	/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
elmot	1:d0dfbce63a89	2671	/* injected group stop ADC_CR_JADSTP). */
elmot	1:d0dfbce63a89	2672	/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
elmot	1:d0dfbce63a89	2673	/* (see reference manual). */
elmot	1:d0dfbce63a89	2674	if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
elmot	1:d0dfbce63a89	2675	&& (hadc->Init.ContinuousConvMode==ENABLE)
elmot	1:d0dfbce63a89	2676	&& (hadc->Init.LowPowerAutoWait==ENABLE))
elmot	1:d0dfbce63a89	2677	{
elmot	1:d0dfbce63a89	2678	/* Use stop of regular group */
elmot	1:d0dfbce63a89	2679	ConversionGroup = ADC_REGULAR_GROUP;
elmot	1:d0dfbce63a89	2680
elmot	1:d0dfbce63a89	2681	/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
elmot	1:d0dfbce63a89	2682	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
elmot	1:d0dfbce63a89	2683	{
elmot	1:d0dfbce63a89	2684	if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
elmot	1:d0dfbce63a89	2685	{
elmot	1:d0dfbce63a89	2686	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2687	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2688
elmot	1:d0dfbce63a89	2689	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	2690	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2691
elmot	1:d0dfbce63a89	2692	return HAL_ERROR;
elmot	1:d0dfbce63a89	2693	}
elmot	1:d0dfbce63a89	2694	Conversion_Timeout_CPU_cycles ++;
elmot	1:d0dfbce63a89	2695	}
elmot	1:d0dfbce63a89	2696
elmot	1:d0dfbce63a89	2697	/* Clear JEOS */
elmot	1:d0dfbce63a89	2698	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
elmot	1:d0dfbce63a89	2699	}
elmot	1:d0dfbce63a89	2700
elmot	1:d0dfbce63a89	2701	/* Stop potential conversion on going on regular group */
elmot	1:d0dfbce63a89	2702	if (ConversionGroup != ADC_INJECTED_GROUP)
elmot	1:d0dfbce63a89	2703	{
elmot	1:d0dfbce63a89	2704	/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
elmot	1:d0dfbce63a89	2705	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
elmot	1:d0dfbce63a89	2706	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
elmot	1:d0dfbce63a89	2707	{
elmot	1:d0dfbce63a89	2708	/* Stop conversions on regular group */
elmot	1:d0dfbce63a89	2709	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
elmot	1:d0dfbce63a89	2710	}
elmot	1:d0dfbce63a89	2711	}
elmot	1:d0dfbce63a89	2712
elmot	1:d0dfbce63a89	2713	/* Stop potential conversion on going on injected group */
elmot	1:d0dfbce63a89	2714	if (ConversionGroup != ADC_REGULAR_GROUP)
elmot	1:d0dfbce63a89	2715	{
elmot	1:d0dfbce63a89	2716	/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
elmot	1:d0dfbce63a89	2717	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
elmot	1:d0dfbce63a89	2718	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
elmot	1:d0dfbce63a89	2719	{
elmot	1:d0dfbce63a89	2720	/* Stop conversions on injected group */
elmot	1:d0dfbce63a89	2721	SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
elmot	1:d0dfbce63a89	2722	}
elmot	1:d0dfbce63a89	2723	}
elmot	1:d0dfbce63a89	2724
elmot	1:d0dfbce63a89	2725	/* Selection of start and stop bits with respect to the regular or injected group */
elmot	1:d0dfbce63a89	2726	switch(ConversionGroup)
elmot	1:d0dfbce63a89	2727	{
elmot	1:d0dfbce63a89	2728	case ADC_REGULAR_INJECTED_GROUP:
elmot	1:d0dfbce63a89	2729	tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART \| ADC_CR_JADSTART);
elmot	1:d0dfbce63a89	2730	break;
elmot	1:d0dfbce63a89	2731	case ADC_INJECTED_GROUP:
elmot	1:d0dfbce63a89	2732	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
elmot	1:d0dfbce63a89	2733	break;
elmot	1:d0dfbce63a89	2734	/* Case ADC_REGULAR_GROUP only*/
elmot	1:d0dfbce63a89	2735	default:
elmot	1:d0dfbce63a89	2736	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
elmot	1:d0dfbce63a89	2737	break;
elmot	1:d0dfbce63a89	2738	}
elmot	1:d0dfbce63a89	2739
elmot	1:d0dfbce63a89	2740	/* Wait for conversion effectively stopped */
elmot	1:d0dfbce63a89	2741
elmot	1:d0dfbce63a89	2742
elmot	1:d0dfbce63a89	2743	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	2744
elmot	1:d0dfbce63a89	2745	while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
elmot	1:d0dfbce63a89	2746	{
elmot	1:d0dfbce63a89	2747	if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
elmot	1:d0dfbce63a89	2748	{
elmot	1:d0dfbce63a89	2749	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2750	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2751
elmot	1:d0dfbce63a89	2752	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	2753	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2754
elmot	1:d0dfbce63a89	2755	return HAL_ERROR;
elmot	1:d0dfbce63a89	2756	}
elmot	1:d0dfbce63a89	2757	}
elmot	1:d0dfbce63a89	2758
elmot	1:d0dfbce63a89	2759	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
elmot	1:d0dfbce63a89	2760
elmot	1:d0dfbce63a89	2761	/* Return HAL status */
elmot	1:d0dfbce63a89	2762	return HAL_OK;
elmot	1:d0dfbce63a89	2763	}
elmot	1:d0dfbce63a89	2764
elmot	1:d0dfbce63a89	2765
elmot	1:d0dfbce63a89	2766
elmot	1:d0dfbce63a89	2767	/**
elmot	1:d0dfbce63a89	2768	* @brief Enable the selected ADC.
elmot	1:d0dfbce63a89	2769	* @note Prerequisite condition to use this function: ADC must be disabled
elmot	1:d0dfbce63a89	2770	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
elmot	1:d0dfbce63a89	2771	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2772	* @retval HAL status.
elmot	1:d0dfbce63a89	2773	*/
elmot	1:d0dfbce63a89	2774	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	2775	{
elmot	1:d0dfbce63a89	2776	uint32_t tickstart = 0;
elmot	1:d0dfbce63a89	2777
elmot	1:d0dfbce63a89	2778	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
elmot	1:d0dfbce63a89	2779	/* enabling phase not yet completed: flag ADC ready not set yet). */
elmot	1:d0dfbce63a89	2780	/* Timeout implemented not to be stuck if ADC cannot be enabled (possible */
elmot	1:d0dfbce63a89	2781	/* causes: ADC clock not running, ...). */
elmot	1:d0dfbce63a89	2782	if (ADC_IS_ENABLE(hadc) == RESET)
elmot	1:d0dfbce63a89	2783	{
elmot	1:d0dfbce63a89	2784	/* Check if conditions to enable the ADC are fulfilled */
elmot	1:d0dfbce63a89	2785	if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
elmot	1:d0dfbce63a89	2786	{
elmot	1:d0dfbce63a89	2787	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2788	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2789
elmot	1:d0dfbce63a89	2790	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	2791	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2792
elmot	1:d0dfbce63a89	2793	return HAL_ERROR;
elmot	1:d0dfbce63a89	2794	}
elmot	1:d0dfbce63a89	2795
elmot	1:d0dfbce63a89	2796	/* Enable the ADC peripheral */
elmot	1:d0dfbce63a89	2797	ADC_ENABLE(hadc);
elmot	1:d0dfbce63a89	2798
elmot	1:d0dfbce63a89	2799
elmot	1:d0dfbce63a89	2800	/* Wait for ADC effectively enabled */
elmot	1:d0dfbce63a89	2801	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	2802
elmot	1:d0dfbce63a89	2803	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
elmot	1:d0dfbce63a89	2804	{
elmot	1:d0dfbce63a89	2805	/* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
elmot	1:d0dfbce63a89	2806	has been cleared (after a calibration), ADEN bit is reset by the
elmot	1:d0dfbce63a89	2807	calibration logic.
elmot	1:d0dfbce63a89	2808	The workaround is to continue setting ADEN until ADRDY is becomes 1.
elmot	1:d0dfbce63a89	2809	Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
elmot	1:d0dfbce63a89	2810	4 ADC clock cycle duration */
elmot	1:d0dfbce63a89	2811	ADC_ENABLE(hadc);
elmot	1:d0dfbce63a89	2812
elmot	1:d0dfbce63a89	2813	if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
elmot	1:d0dfbce63a89	2814	{
elmot	1:d0dfbce63a89	2815	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2816	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2817
elmot	1:d0dfbce63a89	2818	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	2819	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2820
elmot	1:d0dfbce63a89	2821	return HAL_ERROR;
elmot	1:d0dfbce63a89	2822	}
elmot	1:d0dfbce63a89	2823	}
elmot	1:d0dfbce63a89	2824	}
elmot	1:d0dfbce63a89	2825
elmot	1:d0dfbce63a89	2826	/* Return HAL status */
elmot	1:d0dfbce63a89	2827	return HAL_OK;
elmot	1:d0dfbce63a89	2828	}
elmot	1:d0dfbce63a89	2829
elmot	1:d0dfbce63a89	2830	/**
elmot	1:d0dfbce63a89	2831	* @brief Disable the selected ADC.
elmot	1:d0dfbce63a89	2832	* @note Prerequisite condition to use this function: ADC conversions must be
elmot	1:d0dfbce63a89	2833	* stopped.
elmot	1:d0dfbce63a89	2834	* @param hadc: ADC handle
elmot	1:d0dfbce63a89	2835	* @retval HAL status.
elmot	1:d0dfbce63a89	2836	*/
elmot	1:d0dfbce63a89	2837	HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
elmot	1:d0dfbce63a89	2838	{
elmot	1:d0dfbce63a89	2839	uint32_t tickstart = 0;
elmot	1:d0dfbce63a89	2840
elmot	1:d0dfbce63a89	2841	/* Verification if ADC is not already disabled: */
elmot	1:d0dfbce63a89	2842	/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
elmot	1:d0dfbce63a89	2843	/* disabled. */
elmot	1:d0dfbce63a89	2844	if (ADC_IS_ENABLE(hadc) != RESET )
elmot	1:d0dfbce63a89	2845	{
elmot	1:d0dfbce63a89	2846	/* Check if conditions to disable the ADC are fulfilled */
elmot	1:d0dfbce63a89	2847	if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
elmot	1:d0dfbce63a89	2848	{
elmot	1:d0dfbce63a89	2849	/* Disable the ADC peripheral */
elmot	1:d0dfbce63a89	2850	ADC_DISABLE(hadc);
elmot	1:d0dfbce63a89	2851	}
elmot	1:d0dfbce63a89	2852	else
elmot	1:d0dfbce63a89	2853	{
elmot	1:d0dfbce63a89	2854	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2855	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2856
elmot	1:d0dfbce63a89	2857	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	2858	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2859
elmot	1:d0dfbce63a89	2860	return HAL_ERROR;
elmot	1:d0dfbce63a89	2861	}
elmot	1:d0dfbce63a89	2862
elmot	1:d0dfbce63a89	2863	/* Wait for ADC effectively disabled */
elmot	1:d0dfbce63a89	2864	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	2865
elmot	1:d0dfbce63a89	2866	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
elmot	1:d0dfbce63a89	2867	{
elmot	1:d0dfbce63a89	2868	if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
elmot	1:d0dfbce63a89	2869	{
elmot	1:d0dfbce63a89	2870	/* Update ADC state machine to error */
elmot	1:d0dfbce63a89	2871	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2872
elmot	1:d0dfbce63a89	2873	/* Set ADC error code to ADC IP internal error */
elmot	1:d0dfbce63a89	2874	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
elmot	1:d0dfbce63a89	2875
elmot	1:d0dfbce63a89	2876	return HAL_ERROR;
elmot	1:d0dfbce63a89	2877	}
elmot	1:d0dfbce63a89	2878	}
elmot	1:d0dfbce63a89	2879	}
elmot	1:d0dfbce63a89	2880
elmot	1:d0dfbce63a89	2881	/* Return HAL status */
elmot	1:d0dfbce63a89	2882	return HAL_OK;
elmot	1:d0dfbce63a89	2883	}
elmot	1:d0dfbce63a89	2884
elmot	1:d0dfbce63a89	2885
elmot	1:d0dfbce63a89	2886	/**
elmot	1:d0dfbce63a89	2887	* @brief DMA transfer complete callback.
elmot	1:d0dfbce63a89	2888	* @param hdma: pointer to DMA handle.
elmot	1:d0dfbce63a89	2889	* @retval None
elmot	1:d0dfbce63a89	2890	*/
elmot	1:d0dfbce63a89	2891	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2892	{
elmot	1:d0dfbce63a89	2893	/* Retrieve ADC handle corresponding to current DMA handle */
elmot	1:d0dfbce63a89	2894	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2895
elmot	1:d0dfbce63a89	2896	/* Update state machine on conversion status if not in error state */
elmot	1:d0dfbce63a89	2897	if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL\|HAL_ADC_STATE_ERROR_DMA)))
elmot	1:d0dfbce63a89	2898	{
elmot	1:d0dfbce63a89	2899	/* Update ADC state machine */
elmot	1:d0dfbce63a89	2900	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
elmot	1:d0dfbce63a89	2901	/* Is it the end of the regular sequence ? */
elmot	1:d0dfbce63a89	2902	if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
elmot	1:d0dfbce63a89	2903	{
elmot	1:d0dfbce63a89	2904	/* Are conversions software-triggered ? */
elmot	1:d0dfbce63a89	2905	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
elmot	1:d0dfbce63a89	2906	{
elmot	1:d0dfbce63a89	2907	/* Is CONT bit set ? */
elmot	1:d0dfbce63a89	2908	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
elmot	1:d0dfbce63a89	2909	{
elmot	1:d0dfbce63a89	2910	/* CONT bit is not set, no more conversions expected */
elmot	1:d0dfbce63a89	2911	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	2912	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	2913	{
elmot	1:d0dfbce63a89	2914	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	2915	}
elmot	1:d0dfbce63a89	2916	}
elmot	1:d0dfbce63a89	2917	}
elmot	1:d0dfbce63a89	2918	}
elmot	1:d0dfbce63a89	2919	else
elmot	1:d0dfbce63a89	2920	{
elmot	1:d0dfbce63a89	2921	/* DMA End of Transfer interrupt was triggered but conversions sequence
elmot	1:d0dfbce63a89	2922	is not over. If DMACFG is set to 0, conversions are stopped. */
elmot	1:d0dfbce63a89	2923	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
elmot	1:d0dfbce63a89	2924	{
elmot	1:d0dfbce63a89	2925	/* DMACFG bit is not set, conversions are stopped. */
elmot	1:d0dfbce63a89	2926	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
elmot	1:d0dfbce63a89	2927	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
elmot	1:d0dfbce63a89	2928	{
elmot	1:d0dfbce63a89	2929	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
elmot	1:d0dfbce63a89	2930	}
elmot	1:d0dfbce63a89	2931	}
elmot	1:d0dfbce63a89	2932	}
elmot	1:d0dfbce63a89	2933
elmot	1:d0dfbce63a89	2934	/* Conversion complete callback */
elmot	1:d0dfbce63a89	2935	HAL_ADC_ConvCpltCallback(hadc);
elmot	1:d0dfbce63a89	2936	}
elmot	1:d0dfbce63a89	2937	else /* DMA or internal error occurred (or both) */
elmot	1:d0dfbce63a89	2938	{
elmot	1:d0dfbce63a89	2939	/* In case of internal error, */
elmot	1:d0dfbce63a89	2940	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
elmot	1:d0dfbce63a89	2941	{
elmot	1:d0dfbce63a89	2942	/* call Error Callback function */
elmot	1:d0dfbce63a89	2943	HAL_ADC_ErrorCallback(hadc);
elmot	1:d0dfbce63a89	2944	}
elmot	1:d0dfbce63a89	2945
elmot	1:d0dfbce63a89	2946	}
elmot	1:d0dfbce63a89	2947
elmot	1:d0dfbce63a89	2948
elmot	1:d0dfbce63a89	2949	}
elmot	1:d0dfbce63a89	2950
elmot	1:d0dfbce63a89	2951	/**
elmot	1:d0dfbce63a89	2952	* @brief DMA half transfer complete callback.
elmot	1:d0dfbce63a89	2953	* @param hdma: pointer to DMA handle.
elmot	1:d0dfbce63a89	2954	* @retval None
elmot	1:d0dfbce63a89	2955	*/
elmot	1:d0dfbce63a89	2956	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2957	{
elmot	1:d0dfbce63a89	2958	/* Retrieve ADC handle corresponding to current DMA handle */
elmot	1:d0dfbce63a89	2959	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2960
elmot	1:d0dfbce63a89	2961	/* Half conversion callback */
elmot	1:d0dfbce63a89	2962	HAL_ADC_ConvHalfCpltCallback(hadc);
elmot	1:d0dfbce63a89	2963	}
elmot	1:d0dfbce63a89	2964
elmot	1:d0dfbce63a89	2965	/**
elmot	1:d0dfbce63a89	2966	* @brief DMA error callback.
elmot	1:d0dfbce63a89	2967	* @param hdma: pointer to DMA handle.
elmot	1:d0dfbce63a89	2968	* @retval None
elmot	1:d0dfbce63a89	2969	*/
elmot	1:d0dfbce63a89	2970	void ADC_DMAError(DMA_HandleTypeDef *hdma)
elmot	1:d0dfbce63a89	2971	{
elmot	1:d0dfbce63a89	2972	/* Retrieve ADC handle corresponding to current DMA handle */
elmot	1:d0dfbce63a89	2973	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elmot	1:d0dfbce63a89	2974
elmot	1:d0dfbce63a89	2975	/* Change ADC state */
elmot	1:d0dfbce63a89	2976	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
elmot	1:d0dfbce63a89	2977
elmot	1:d0dfbce63a89	2978	/* Set ADC error code to DMA error */
elmot	1:d0dfbce63a89	2979	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
elmot	1:d0dfbce63a89	2980
elmot	1:d0dfbce63a89	2981	/* Error callback */
elmot	1:d0dfbce63a89	2982	HAL_ADC_ErrorCallback(hadc);
elmot	1:d0dfbce63a89	2983	}
elmot	1:d0dfbce63a89	2984
elmot	1:d0dfbce63a89	2985
elmot	1:d0dfbce63a89	2986	/**
elmot	1:d0dfbce63a89	2987	* @}
elmot	1:d0dfbce63a89	2988	*/
elmot	1:d0dfbce63a89	2989
elmot	1:d0dfbce63a89	2990
elmot	1:d0dfbce63a89	2991	#endif /* HAL_ADC_MODULE_ENABLED */
elmot	1:d0dfbce63a89	2992	/**
elmot	1:d0dfbce63a89	2993	* @}
elmot	1:d0dfbce63a89	2994	*/
elmot	1:d0dfbce63a89	2995
elmot	1:d0dfbce63a89	2996	/**
elmot	1:d0dfbce63a89	2997	* @}
elmot	1:d0dfbce63a89	2998	*/
elmot	1:d0dfbce63a89	2999
elmot	1:d0dfbce63a89	3000	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	24 Feb 2017
Imports:	19
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