Semtech / SX126xLib

SX1261 and sx1262 common library

Dependents:   SX126xDevKit SX1262PingPong SX126X_TXonly SX126X_PingPong_Demo ... more

Fork of SX126xLib by Gregory Cristian

sx126x.cpp@3:7e3595a9ebe0, 2016-10-12 (annotated)

Committer:
GregCr
Date:
Wed Oct 12 08:49:58 2016 +0000
Revision:
3:7e3595a9ebe0
Parent:
2:4ff11ea92fbe
Child:
4:c6ef863d0b07
updated version with patch RAM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:deaafdfde3bb 1 /*
GregCr 0:deaafdfde3bb 2 / _____) _ | |
GregCr 0:deaafdfde3bb 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:deaafdfde3bb 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:deaafdfde3bb 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:deaafdfde3bb 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 0:deaafdfde3bb 7 (C)2016 Semtech
GregCr 0:deaafdfde3bb 8
GregCr 0:deaafdfde3bb 9 Description: Handling of the node configuration protocol
GregCr 0:deaafdfde3bb 10
GregCr 0:deaafdfde3bb 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:deaafdfde3bb 12
GregCr 0:deaafdfde3bb 13 Maintainer: Miguel Luis, Gregory Cristian and Matthieu Verdy
GregCr 0:deaafdfde3bb 14 */
GregCr 0:deaafdfde3bb 15 #include "mbed.h"
GregCr 1:35d34672a089 16 #include "sx126x.h"
GregCr 1:35d34672a089 17 #include "sx126x-hal.h"
GregCr 0:deaafdfde3bb 18
GregCr 3:7e3595a9ebe0 19 #include "pram_c005.h"
GregCr 3:7e3595a9ebe0 20
GregCr 0:deaafdfde3bb 21 /*!
GregCr 0:deaafdfde3bb 22 * Radio registers definition
GregCr 0:deaafdfde3bb 23 *
GregCr 0:deaafdfde3bb 24 */
GregCr 0:deaafdfde3bb 25 typedef struct
GregCr 0:deaafdfde3bb 26 {
GregCr 0:deaafdfde3bb 27 uint16_t Addr; //!< The address of the register
GregCr 0:deaafdfde3bb 28 uint8_t Value; //!< The value of the register
GregCr 0:deaafdfde3bb 29 }RadioRegisters_t;
GregCr 0:deaafdfde3bb 30
GregCr 0:deaafdfde3bb 31 // [TODO] Is this also applicable for the V2 version of the chip
GregCr 0:deaafdfde3bb 32 /*!
GregCr 0:deaafdfde3bb 33 * \brief Radio hardware registers initialization definition
GregCr 0:deaafdfde3bb 34 */
GregCr 0:deaafdfde3bb 35 // { Address, RegValue }
GregCr 3:7e3595a9ebe0 36
GregCr 0:deaafdfde3bb 37 #define RADIO_INIT_REGISTERS_VALUE \
GregCr 0:deaafdfde3bb 38 { \
GregCr 0:deaafdfde3bb 39 { 0x0722, 0x53 }, \
GregCr 3:7e3595a9ebe0 40 { 0x0889, 0x01 }, \
GregCr 0:deaafdfde3bb 41 }
GregCr 0:deaafdfde3bb 42
GregCr 0:deaafdfde3bb 43 /*!
GregCr 0:deaafdfde3bb 44 * \brief Radio hardware registers initialization
GregCr 0:deaafdfde3bb 45 */
GregCr 0:deaafdfde3bb 46 const RadioRegisters_t RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:deaafdfde3bb 47
GregCr 2:4ff11ea92fbe 48 void SX126x::Init( void )
GregCr 0:deaafdfde3bb 49 {
GregCr 0:deaafdfde3bb 50 Reset( );
GregCr 0:deaafdfde3bb 51 IoIrqInit( dioIrq );
GregCr 0:deaafdfde3bb 52 Wakeup( );
GregCr 3:7e3595a9ebe0 53 /****************************************************/
GregCr 3:7e3595a9ebe0 54 SetStandby( STDBY_RC );
GregCr 3:7e3595a9ebe0 55 WriteRegister( 0x610, 0x10 );
GregCr 3:7e3595a9ebe0 56 for( uint16_t i = 0; i < PRAM_COUNT; i++ )
GregCr 3:7e3595a9ebe0 57 {
GregCr 3:7e3595a9ebe0 58 uint32_t val = pram[i];
GregCr 3:7e3595a9ebe0 59 WriteRegister( 0x8000 + 4 * i, 0 );
GregCr 3:7e3595a9ebe0 60 WriteRegister( 0x8001 + 4 * i, ( val >> 16 ) & 0xff );
GregCr 3:7e3595a9ebe0 61 WriteRegister( 0x8002 + 4 * i, ( val >> 8 ) & 0xff );
GregCr 3:7e3595a9ebe0 62 WriteRegister( 0x8003 + 4 * i, val & 0xff );
GregCr 3:7e3595a9ebe0 63 }
GregCr 3:7e3595a9ebe0 64 WriteRegister( 0x610, 0x00 );
GregCr 3:7e3595a9ebe0 65 WriteCommand( RADIO_SET_PRAMSWAPCMD, ( uint8_t[] ) { 2 } , 1 ); // RADIO_SET_PRAMSWAPCMD = 0x8D,
GregCr 3:7e3595a9ebe0 66 /****************************************************/
GregCr 0:deaafdfde3bb 67 SetRegistersDefault( );
GregCr 0:deaafdfde3bb 68 }
GregCr 0:deaafdfde3bb 69
GregCr 2:4ff11ea92fbe 70 void SX126x::SetRegistersDefault( void )
GregCr 0:deaafdfde3bb 71 {
GregCr 0:deaafdfde3bb 72 for( uint8_t i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:deaafdfde3bb 73 {
GregCr 0:deaafdfde3bb 74 WriteRegister( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:deaafdfde3bb 75 }
GregCr 0:deaafdfde3bb 76 }
GregCr 0:deaafdfde3bb 77
GregCr 2:4ff11ea92fbe 78 uint16_t SX126x::GetFirmwareVersion( void )
GregCr 0:deaafdfde3bb 79 {
GregCr 0:deaafdfde3bb 80 return( ( ( ReadRegister( 0xA8 ) ) << 8 ) | ( ReadRegister( 0xA9 ) ) );
GregCr 0:deaafdfde3bb 81 }
GregCr 0:deaafdfde3bb 82
GregCr 2:4ff11ea92fbe 83 RadioStatus_t SX126x::GetStatus( void )
GregCr 0:deaafdfde3bb 84 {
GregCr 0:deaafdfde3bb 85 uint8_t stat = 0;
GregCr 0:deaafdfde3bb 86 RadioStatus_t status;
GregCr 0:deaafdfde3bb 87
GregCr 0:deaafdfde3bb 88 ReadCommand( RADIO_GET_STATUS, ( uint8_t * )&stat, 1 );
GregCr 0:deaafdfde3bb 89 status.Value = stat;
GregCr 0:deaafdfde3bb 90
GregCr 0:deaafdfde3bb 91
GregCr 0:deaafdfde3bb 92 return( status );
GregCr 0:deaafdfde3bb 93 }
GregCr 0:deaafdfde3bb 94
GregCr 2:4ff11ea92fbe 95 void SX126x::SetSleep( SleepParams_t sleepConfig )
GregCr 0:deaafdfde3bb 96 {
GregCr 0:deaafdfde3bb 97
GregCr 0:deaafdfde3bb 98 WriteCommand( RADIO_SET_SLEEP, &sleepConfig.Value, 1 );
GregCr 0:deaafdfde3bb 99 OperatingMode = MODE_SLEEP;
GregCr 0:deaafdfde3bb 100 }
GregCr 0:deaafdfde3bb 101
GregCr 2:4ff11ea92fbe 102 void SX126x::SetStandby( RadioStandbyModes_t standbyConfig )
GregCr 0:deaafdfde3bb 103 {
GregCr 0:deaafdfde3bb 104 WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 );
GregCr 0:deaafdfde3bb 105 if( standbyConfig == STDBY_RC )
GregCr 0:deaafdfde3bb 106 {
GregCr 0:deaafdfde3bb 107 OperatingMode = MODE_STDBY_RC;
GregCr 0:deaafdfde3bb 108 }
GregCr 0:deaafdfde3bb 109 else
GregCr 0:deaafdfde3bb 110 {
GregCr 0:deaafdfde3bb 111 OperatingMode = MODE_STDBY_XOSC;
GregCr 0:deaafdfde3bb 112 }
GregCr 0:deaafdfde3bb 113 }
GregCr 0:deaafdfde3bb 114
GregCr 2:4ff11ea92fbe 115 void SX126x::SetFs( void )
GregCr 0:deaafdfde3bb 116 {
GregCr 0:deaafdfde3bb 117 WriteCommand( RADIO_SET_FS, 0, 0 );
GregCr 0:deaafdfde3bb 118 OperatingMode = MODE_FS;
GregCr 0:deaafdfde3bb 119 }
GregCr 0:deaafdfde3bb 120
GregCr 2:4ff11ea92fbe 121 void SX126x::SetTx( uint32_t timeout )
GregCr 0:deaafdfde3bb 122 {
GregCr 0:deaafdfde3bb 123 uint8_t buf[3];
GregCr 0:deaafdfde3bb 124 buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 125 buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 126 buf[2] = ( uint8_t )( timeout & 0xFF );
GregCr 0:deaafdfde3bb 127 WriteCommand( RADIO_SET_TX, buf, 3 );
GregCr 0:deaafdfde3bb 128 OperatingMode = MODE_TX;
GregCr 0:deaafdfde3bb 129 }
GregCr 0:deaafdfde3bb 130
GregCr 2:4ff11ea92fbe 131 void SX126x::SetRx( uint32_t timeout )
GregCr 0:deaafdfde3bb 132 {
GregCr 0:deaafdfde3bb 133 uint8_t buf[3];
GregCr 0:deaafdfde3bb 134 buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 135 buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 136 buf[2] = ( uint8_t )( timeout & 0xFF );
GregCr 0:deaafdfde3bb 137 WriteCommand( RADIO_SET_RX, buf, 3 );
GregCr 0:deaafdfde3bb 138 OperatingMode = MODE_RX;
GregCr 0:deaafdfde3bb 139 }
GregCr 0:deaafdfde3bb 140
GregCr 2:4ff11ea92fbe 141 void SX126x::SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime )
GregCr 0:deaafdfde3bb 142 {
GregCr 0:deaafdfde3bb 143 uint8_t buf[6];
GregCr 0:deaafdfde3bb 144
GregCr 0:deaafdfde3bb 145 buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 146 buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 147 buf[2] = ( uint8_t )( rxTime & 0xFF );
GregCr 0:deaafdfde3bb 148 buf[0] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 149 buf[1] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 150 buf[2] = ( uint8_t )( sleepTime & 0xFF );
GregCr 0:deaafdfde3bb 151 WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 );
GregCr 0:deaafdfde3bb 152 OperatingMode = MODE_RX;
GregCr 0:deaafdfde3bb 153 }
GregCr 0:deaafdfde3bb 154
GregCr 2:4ff11ea92fbe 155 void SX126x::SetCad( void )
GregCr 0:deaafdfde3bb 156 {
GregCr 0:deaafdfde3bb 157 WriteCommand( RADIO_SET_CAD, 0, 0 );
GregCr 0:deaafdfde3bb 158 OperatingMode = MODE_CAD;
GregCr 0:deaafdfde3bb 159 }
GregCr 0:deaafdfde3bb 160
GregCr 2:4ff11ea92fbe 161 void SX126x::SetAutoTxRx( uint32_t time, uint8_t intMode, uint32_t timeout )
GregCr 0:deaafdfde3bb 162 {
GregCr 0:deaafdfde3bb 163 uint32_t compensatedTime = time - ( uint16_t )AUTO_RX_TX_OFFSET;
GregCr 0:deaafdfde3bb 164 uint8_t buf[7];
GregCr 0:deaafdfde3bb 165
GregCr 0:deaafdfde3bb 166 buf[0] = ( uint8_t )( ( compensatedTime >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 167 buf[1] = ( uint8_t )( ( compensatedTime >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 168 buf[2] = ( uint8_t )( compensatedTime & 0xFF );
GregCr 0:deaafdfde3bb 169 buf[3] = intMode;
GregCr 0:deaafdfde3bb 170 buf[4] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 171 buf[5] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 172 buf[6] = ( uint8_t )( timeout & 0xFF );
GregCr 0:deaafdfde3bb 173 WriteCommand( RADIO_SET_AUTOTXRX, buf, 7 );
GregCr 0:deaafdfde3bb 174 }
GregCr 0:deaafdfde3bb 175
GregCr 0:deaafdfde3bb 176
GregCr 2:4ff11ea92fbe 177 void SX126x::SetTxContinuousWave( void )
GregCr 0:deaafdfde3bb 178 {
GregCr 0:deaafdfde3bb 179 WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 );
GregCr 0:deaafdfde3bb 180 }
GregCr 0:deaafdfde3bb 181
GregCr 2:4ff11ea92fbe 182 void SX126x::SetTxContinuousPreamble( void )
GregCr 0:deaafdfde3bb 183 {
GregCr 0:deaafdfde3bb 184 WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 );
GregCr 0:deaafdfde3bb 185 }
GregCr 0:deaafdfde3bb 186
GregCr 2:4ff11ea92fbe 187 void SX126x::SetPacketType( RadioPacketType_t packetType )
GregCr 0:deaafdfde3bb 188 {
GregCr 0:deaafdfde3bb 189 // Save packet type internally to avoid questioning the radio
GregCr 0:deaafdfde3bb 190 this->PacketType = packetType;
GregCr 0:deaafdfde3bb 191
GregCr 0:deaafdfde3bb 192 WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 );
GregCr 0:deaafdfde3bb 193 }
GregCr 0:deaafdfde3bb 194
GregCr 2:4ff11ea92fbe 195 RadioPacketType_t SX126x::GetPacketType( void )
GregCr 0:deaafdfde3bb 196 {
GregCr 0:deaafdfde3bb 197 return this->PacketType;
GregCr 0:deaafdfde3bb 198 }
GregCr 0:deaafdfde3bb 199
GregCr 2:4ff11ea92fbe 200 void SX126x::SetRfFrequency( uint32_t frequency )
GregCr 0:deaafdfde3bb 201 {
GregCr 0:deaafdfde3bb 202 uint8_t buf[4];
GregCr 0:deaafdfde3bb 203 uint32_t freq = 0;
GregCr 0:deaafdfde3bb 204
GregCr 0:deaafdfde3bb 205 freq = ( uint32_t )( ( double )frequency / ( double )FREQ_STEP );
GregCr 0:deaafdfde3bb 206 buf[0] = ( uint8_t )( ( freq >> 24 ) & 0xFF );
GregCr 0:deaafdfde3bb 207 buf[1] = ( uint8_t )( ( freq >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 208 buf[2] = ( uint8_t )( ( freq >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 209 buf[3] = ( uint8_t )( freq & 0xFF );
GregCr 0:deaafdfde3bb 210 WriteCommand( RADIO_SET_RFFREQUENCY, buf, 3 );
GregCr 0:deaafdfde3bb 211 }
GregCr 0:deaafdfde3bb 212
GregCr 2:4ff11ea92fbe 213 void SX126x::SetTxParams( int8_t power, RadioRampTimes_t rampTime )
GregCr 0:deaafdfde3bb 214 {
GregCr 0:deaafdfde3bb 215 uint8_t buf[2];
GregCr 0:deaafdfde3bb 216
GregCr 0:deaafdfde3bb 217 buf[0] = power ;
GregCr 0:deaafdfde3bb 218 buf[1] = ( uint8_t )rampTime;
GregCr 0:deaafdfde3bb 219 WriteCommand( RADIO_SET_TXPARAMS, buf, 2 );
GregCr 0:deaafdfde3bb 220 }
GregCr 0:deaafdfde3bb 221
GregCr 2:4ff11ea92fbe 222 void SX126x::SetCadConfig( RadioLoRaCadSymbols_t cadSymbolNum , uint8_t cadExitMode, uint32_t cadRxTxTimeout)
GregCr 0:deaafdfde3bb 223 {
GregCr 0:deaafdfde3bb 224 uint8_t buf[5];
GregCr 0:deaafdfde3bb 225 buf[0] = ( uint8_t )cadSymbolNum;
GregCr 0:deaafdfde3bb 226 buf[1] = cadExitMode;
GregCr 0:deaafdfde3bb 227 buf[2] = ( uint8_t )( ( cadRxTxTimeout >> 16 ) & 0xFF );
GregCr 0:deaafdfde3bb 228 buf[3] = ( uint8_t )( ( cadRxTxTimeout >> 8 ) & 0xFF );
GregCr 0:deaafdfde3bb 229 buf[4] = ( uint8_t )( cadRxTxTimeout & 0xFF );
GregCr 0:deaafdfde3bb 230 WriteCommand( RADIO_SET_CADPARAMS, buf, 5 );
GregCr 0:deaafdfde3bb 231 OperatingMode = MODE_CAD;
GregCr 0:deaafdfde3bb 232 }
GregCr 0:deaafdfde3bb 233
GregCr 2:4ff11ea92fbe 234 void SX126x::SetBufferBaseAddresses( uint8_t txBaseAddress, uint8_t rxBaseAddress )
GregCr 0:deaafdfde3bb 235 {
GregCr 0:deaafdfde3bb 236 uint8_t buf[2];
GregCr 0:deaafdfde3bb 237
GregCr 0:deaafdfde3bb 238 buf[0] = txBaseAddress;
GregCr 0:deaafdfde3bb 239 buf[1] = rxBaseAddress;
GregCr 0:deaafdfde3bb 240 WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 );
GregCr 0:deaafdfde3bb 241 }
GregCr 0:deaafdfde3bb 242
GregCr 2:4ff11ea92fbe 243 void SX126x::SetModulationParams( ModulationParams_t *modulationParams )
GregCr 0:deaafdfde3bb 244 {
GregCr 0:deaafdfde3bb 245 uint8_t n;
GregCr 3:7e3595a9ebe0 246 uint32_t tempVal = 0;
GregCr 3:7e3595a9ebe0 247 uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
GregCr 3:7e3595a9ebe0 248
GregCr 0:deaafdfde3bb 249 // Check if required configuration corresponds to the stored packet type
GregCr 0:deaafdfde3bb 250 // If not, silently update radio packet type
GregCr 0:deaafdfde3bb 251 if( this->PacketType != modulationParams->PacketType )
GregCr 0:deaafdfde3bb 252 {
GregCr 0:deaafdfde3bb 253 this->SetPacketType( modulationParams->PacketType );
GregCr 0:deaafdfde3bb 254 }
GregCr 0:deaafdfde3bb 255
GregCr 0:deaafdfde3bb 256 switch( modulationParams->PacketType )
GregCr 0:deaafdfde3bb 257 {
GregCr 0:deaafdfde3bb 258 case PACKET_TYPE_GFSK:
GregCr 3:7e3595a9ebe0 259 tempVal = ( uint32_t )( ( double )XTAL_FREQ / ( double )modulationParams->Params.Gfsk.BitRate );
GregCr 3:7e3595a9ebe0 260 tempVal = tempVal * 32;
GregCr 3:7e3595a9ebe0 261 buf[0] = ( tempVal >> 16 ) & 0xFF;
GregCr 3:7e3595a9ebe0 262 buf[1] = ( tempVal >> 8 ) & 0xFF;
GregCr 3:7e3595a9ebe0 263 buf[2] = tempVal & 0xFF;
GregCr 3:7e3595a9ebe0 264
GregCr 3:7e3595a9ebe0 265 buf[3] = modulationParams->Params.Gfsk.PulseShape;
GregCr 3:7e3595a9ebe0 266 buf[4] = modulationParams->Params.Gfsk.BW;
GregCr 3:7e3595a9ebe0 267
GregCr 3:7e3595a9ebe0 268 tempVal = ( uint32_t )( ( double )FREQ_STEP * ( double )modulationParams->Params.Gfsk.Fdev );
GregCr 3:7e3595a9ebe0 269 buf[5] = ( tempVal >> 16 ) & 0xFF;
GregCr 3:7e3595a9ebe0 270 buf[6] = ( tempVal >> 8 ) & 0xFF;
GregCr 3:7e3595a9ebe0 271 buf[7] = ( tempVal& 0xFF );
GregCr 0:deaafdfde3bb 272 n = 8;
GregCr 0:deaafdfde3bb 273 break;
GregCr 3:7e3595a9ebe0 274
GregCr 0:deaafdfde3bb 275 case PACKET_TYPE_LORA:
GregCr 0:deaafdfde3bb 276 n = 3;
GregCr 3:7e3595a9ebe0 277 buf[0] = modulationParams->Params.LoRa.SpreadingFactor;
GregCr 3:7e3595a9ebe0 278 buf[1] = modulationParams->Params.LoRa.Bandwidth;
GregCr 3:7e3595a9ebe0 279 buf[2] = modulationParams->Params.LoRa.CodingRate;
GregCr 0:deaafdfde3bb 280 break;
GregCr 3:7e3595a9ebe0 281
GregCr 3:7e3595a9ebe0 282 case PACKET_TYPE_RESERVED:
GregCr 0:deaafdfde3bb 283 return;
GregCr 0:deaafdfde3bb 284 }
GregCr 3:7e3595a9ebe0 285 WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
GregCr 0:deaafdfde3bb 286 }
GregCr 0:deaafdfde3bb 287
GregCr 2:4ff11ea92fbe 288 void SX126x::SetPacketParams( PacketParams_t *packetParams )
GregCr 0:deaafdfde3bb 289 {
GregCr 0:deaafdfde3bb 290 uint8_t n;
GregCr 0:deaafdfde3bb 291
GregCr 0:deaafdfde3bb 292 // Check if required configuration corresponds to the stored packet type
GregCr 0:deaafdfde3bb 293 // If not, silently update radio packet type
GregCr 0:deaafdfde3bb 294 if( this->PacketType != packetParams->PacketType )
GregCr 0:deaafdfde3bb 295 {
GregCr 0:deaafdfde3bb 296 this->SetPacketType( packetParams->PacketType );
GregCr 0:deaafdfde3bb 297 }
GregCr 0:deaafdfde3bb 298
GregCr 0:deaafdfde3bb 299 switch( packetParams->PacketType )
GregCr 0:deaafdfde3bb 300 {
GregCr 0:deaafdfde3bb 301 case PACKET_TYPE_GFSK:
GregCr 0:deaafdfde3bb 302 n = 8;
GregCr 3:7e3595a9ebe0 303 break;
GregCr 0:deaafdfde3bb 304 case PACKET_TYPE_LORA:
GregCr 0:deaafdfde3bb 305 n = 5;
GregCr 0:deaafdfde3bb 306 break;
GregCr 3:7e3595a9ebe0 307 case PACKET_TYPE_RESERVED:
GregCr 0:deaafdfde3bb 308 return;
GregCr 0:deaafdfde3bb 309 }
GregCr 0:deaafdfde3bb 310 WriteCommand( RADIO_SET_PACKETPARAMS, packetParams->Params.Buffer, n );
GregCr 0:deaafdfde3bb 311 }
GregCr 0:deaafdfde3bb 312
GregCr 2:4ff11ea92fbe 313 void SX126x::GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer )
GregCr 0:deaafdfde3bb 314 {
GregCr 0:deaafdfde3bb 315 uint8_t status[2];
GregCr 0:deaafdfde3bb 316
GregCr 0:deaafdfde3bb 317 ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 );
GregCr 0:deaafdfde3bb 318
GregCr 0:deaafdfde3bb 319 *payloadLength = status[0];
GregCr 0:deaafdfde3bb 320 *rxStartBufferPointer = status[1];
GregCr 0:deaafdfde3bb 321 }
GregCr 0:deaafdfde3bb 322
GregCr 2:4ff11ea92fbe 323 void SX126x::GetPacketStatus( PacketStatus_t *pktStatus )
GregCr 0:deaafdfde3bb 324 {
GregCr 0:deaafdfde3bb 325 uint8_t status[3];
GregCr 0:deaafdfde3bb 326
GregCr 0:deaafdfde3bb 327
GregCr 0:deaafdfde3bb 328 ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 );
GregCr 0:deaafdfde3bb 329
GregCr 0:deaafdfde3bb 330 pktStatus->packetType = this -> GetPacketType( );
GregCr 0:deaafdfde3bb 331 switch( pktStatus->packetType )
GregCr 0:deaafdfde3bb 332 {
GregCr 0:deaafdfde3bb 333 case PACKET_TYPE_GFSK:
GregCr 0:deaafdfde3bb 334 pktStatus->Gfsk.RxStatus = status[0];
GregCr 0:deaafdfde3bb 335 pktStatus->Gfsk.RssiSync = -status[1] / 2;
GregCr 0:deaafdfde3bb 336 pktStatus->Gfsk.RssiAvg = -status[2] / 2;
GregCr 0:deaafdfde3bb 337 break;
GregCr 0:deaafdfde3bb 338
GregCr 0:deaafdfde3bb 339 case PACKET_TYPE_LORA:
GregCr 0:deaafdfde3bb 340 pktStatus->LoRa.RssiPkt = -status[0] / 2;
GregCr 0:deaafdfde3bb 341 ( status[1] < 128 ) ? ( pktStatus->LoRa.SnrPkt = status[1] / 4 ) : ( pktStatus->LoRa.SnrPkt = ( ( status[1] - 256 ) /4 ) );
GregCr 0:deaafdfde3bb 342 pktStatus->LoRa.SignalRssiPkt = -status[2] / 2;
GregCr 0:deaafdfde3bb 343 break;
GregCr 0:deaafdfde3bb 344
GregCr 3:7e3595a9ebe0 345 case PACKET_TYPE_RESERVED:
GregCr 0:deaafdfde3bb 346 // In that specific case, we set everything in the pktStatus to zeros
GregCr 0:deaafdfde3bb 347 // and reset the packet type accordingly
GregCr 0:deaafdfde3bb 348 memset( pktStatus, 0, sizeof( PacketStatus_t ) );
GregCr 3:7e3595a9ebe0 349 pktStatus->packetType = PACKET_TYPE_RESERVED;
GregCr 0:deaafdfde3bb 350 break;
GregCr 0:deaafdfde3bb 351 }
GregCr 0:deaafdfde3bb 352 }
GregCr 0:deaafdfde3bb 353
GregCr 2:4ff11ea92fbe 354 int8_t SX126x::GetRssiInst( void )
GregCr 0:deaafdfde3bb 355 {
GregCr 0:deaafdfde3bb 356 int8_t rssi;
GregCr 0:deaafdfde3bb 357
GregCr 0:deaafdfde3bb 358 ReadCommand( RADIO_GET_RSSIINST, ( uint8_t* )&rssi, 1 );
GregCr 0:deaafdfde3bb 359 return -rssi / 2;
GregCr 0:deaafdfde3bb 360 }
GregCr 0:deaafdfde3bb 361
GregCr 2:4ff11ea92fbe 362 void SX126x::GetStats( RxCounter_t *rxCounter )
GregCr 0:deaafdfde3bb 363 {
GregCr 0:deaafdfde3bb 364 uint8_t status[6];
GregCr 0:deaafdfde3bb 365
GregCr 0:deaafdfde3bb 366
GregCr 0:deaafdfde3bb 367 rxCounter->packetType = this -> GetPacketType( );
GregCr 0:deaafdfde3bb 368 ReadCommand( RADIO_GET_STATS, status, 6 );
GregCr 0:deaafdfde3bb 369 rxCounter->NbPktReceived = ( status[0] << 8 ) | status[1];
GregCr 0:deaafdfde3bb 370 rxCounter->NbPktCrcOk = ( status[2] << 8 ) | status[3];
GregCr 0:deaafdfde3bb 371 rxCounter->NbPktLengthError = ( status[4] << 8 ) | status[4];
GregCr 0:deaafdfde3bb 372 }
GregCr 0:deaafdfde3bb 373
GregCr 2:4ff11ea92fbe 374 void SX126x::ResetStats( )
GregCr 0:deaafdfde3bb 375 {
GregCr 0:deaafdfde3bb 376 uint8_t status[6];
GregCr 0:deaafdfde3bb 377
GregCr 0:deaafdfde3bb 378 memset( status, 0, sizeof( status ) );
GregCr 0:deaafdfde3bb 379 WriteCommand( RADIO_RESET_STATS, status, 6 );
GregCr 0:deaafdfde3bb 380 }
GregCr 0:deaafdfde3bb 381
GregCr 2:4ff11ea92fbe 382 uint8_t SX126x::GetError()
GregCr 0:deaafdfde3bb 383 {
GregCr 0:deaafdfde3bb 384 uint8_t error;
GregCr 0:deaafdfde3bb 385
GregCr 0:deaafdfde3bb 386 ReadCommand( RADIO_GET_ERROR, &error, 1 );
GregCr 0:deaafdfde3bb 387 return error;
GregCr 0:deaafdfde3bb 388 }
GregCr 0:deaafdfde3bb 389
GregCr 0:deaafdfde3bb 390
GregCr 2:4ff11ea92fbe 391 void SX126x::SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask )
GregCr 0:deaafdfde3bb 392 {
GregCr 0:deaafdfde3bb 393 uint8_t buf[8];
GregCr 0:deaafdfde3bb 394
GregCr 0:deaafdfde3bb 395 buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF );
GregCr 0:deaafdfde3bb 396 buf[1] = ( uint8_t )( irqMask & 0x00FF );
GregCr 0:deaafdfde3bb 397 buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF );
GregCr 0:deaafdfde3bb 398 buf[3] = ( uint8_t )( dio1Mask & 0x00FF );
GregCr 0:deaafdfde3bb 399 buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF );
GregCr 0:deaafdfde3bb 400 buf[5] = ( uint8_t )( dio2Mask & 0x00FF );
GregCr 0:deaafdfde3bb 401 buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF );
GregCr 0:deaafdfde3bb 402 buf[7] = ( uint8_t )( dio3Mask & 0x00FF );
GregCr 0:deaafdfde3bb 403 WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 );
GregCr 0:deaafdfde3bb 404 }
GregCr 0:deaafdfde3bb 405
GregCr 2:4ff11ea92fbe 406 uint16_t SX126x::GetIrqStatus( void )
GregCr 0:deaafdfde3bb 407 {
GregCr 0:deaafdfde3bb 408 uint8_t irqStatus[2];
GregCr 0:deaafdfde3bb 409 ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 );
GregCr 0:deaafdfde3bb 410 return ( irqStatus[0] << 8 ) | irqStatus[1];
GregCr 0:deaafdfde3bb 411 }
GregCr 0:deaafdfde3bb 412
GregCr 2:4ff11ea92fbe 413 void SX126x::ClearIrqStatus( uint16_t irq )
GregCr 0:deaafdfde3bb 414 {
GregCr 0:deaafdfde3bb 415 uint8_t buf[2];
GregCr 0:deaafdfde3bb 416
GregCr 0:deaafdfde3bb 417 buf[0] = ( uint8_t )( ( ( uint16_t )irq >> 8 ) & 0x00FF );
GregCr 0:deaafdfde3bb 418 buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF );
GregCr 0:deaafdfde3bb 419 WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 );
GregCr 0:deaafdfde3bb 420 }
GregCr 0:deaafdfde3bb 421
GregCr 2:4ff11ea92fbe 422 void SX126x::Calibrate( CalibrationParams_t calibParam )
GregCr 0:deaafdfde3bb 423 {
GregCr 0:deaafdfde3bb 424 WriteCommand( RADIO_CALIBRATE, &calibParam.Value, 1 );
GregCr 0:deaafdfde3bb 425 }
GregCr 0:deaafdfde3bb 426
GregCr 2:4ff11ea92fbe 427 void SX126x::SetRegulatorMode( uint8_t mode )
GregCr 0:deaafdfde3bb 428 {
GregCr 0:deaafdfde3bb 429 WriteCommand( RADIO_SET_REGULATORMODE, &mode, 1 );
GregCr 0:deaafdfde3bb 430 }
GregCr 0:deaafdfde3bb 431
GregCr 0:deaafdfde3bb 432
GregCr 2:4ff11ea92fbe 433 void SX126x::SetLongPreamble( uint8_t enable )
GregCr 0:deaafdfde3bb 434 {
GregCr 0:deaafdfde3bb 435 WriteCommand( RADIO_SET_LONGPREAMBLE, &enable, 1 );
GregCr 0:deaafdfde3bb 436 }
GregCr 0:deaafdfde3bb 437
GregCr 2:4ff11ea92fbe 438 void SX126x::SetPayload( uint8_t *buffer, uint8_t size )
GregCr 0:deaafdfde3bb 439 {
GregCr 0:deaafdfde3bb 440 WriteBuffer( 0x00, buffer, size );
GregCr 0:deaafdfde3bb 441 }
GregCr 0:deaafdfde3bb 442
GregCr 2:4ff11ea92fbe 443 uint8_t SX126x::GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize )
GregCr 0:deaafdfde3bb 444 {
GregCr 0:deaafdfde3bb 445 uint8_t offset;
GregCr 0:deaafdfde3bb 446
GregCr 0:deaafdfde3bb 447 GetRxBufferStatus( size, &offset );
GregCr 0:deaafdfde3bb 448 if(*size > maxSize)
GregCr 0:deaafdfde3bb 449 {
GregCr 0:deaafdfde3bb 450 return 1;
GregCr 0:deaafdfde3bb 451 }
GregCr 0:deaafdfde3bb 452 ReadBuffer( offset, buffer, *size );
GregCr 0:deaafdfde3bb 453 return 0;
GregCr 0:deaafdfde3bb 454 }
GregCr 0:deaafdfde3bb 455
GregCr 2:4ff11ea92fbe 456 void SX126x::SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout )
GregCr 0:deaafdfde3bb 457 {
GregCr 0:deaafdfde3bb 458 SetPayload( payload, size );
GregCr 0:deaafdfde3bb 459 SetTx( timeout );
GregCr 0:deaafdfde3bb 460 }
GregCr 0:deaafdfde3bb 461
GregCr 2:4ff11ea92fbe 462 uint8_t SX126x::SetSyncWord( uint8_t *syncWord )
GregCr 0:deaafdfde3bb 463 {
GregCr 3:7e3595a9ebe0 464 WriteRegister( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 );
GregCr 0:deaafdfde3bb 465 return 0;
GregCr 0:deaafdfde3bb 466 }
GregCr 0:deaafdfde3bb 467
GregCr 3:7e3595a9ebe0 468 void SX126x::SetCrcSeed( uint16_t seed )
GregCr 0:deaafdfde3bb 469 {
GregCr 3:7e3595a9ebe0 470 uint8_t buf[2];
GregCr 3:7e3595a9ebe0 471 buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF );
GregCr 3:7e3595a9ebe0 472 buf[1] = ( uint8_t )( seed & 0xFF );
GregCr 3:7e3595a9ebe0 473
GregCr 0:deaafdfde3bb 474 switch( GetPacketType( ) )
GregCr 0:deaafdfde3bb 475 {
GregCr 0:deaafdfde3bb 476 case PACKET_TYPE_GFSK:
GregCr 3:7e3595a9ebe0 477 WriteRegister( REG_LR_CRCSEEDBASEADDR, buf, 2 );
GregCr 0:deaafdfde3bb 478 break;
GregCr 0:deaafdfde3bb 479 default:
GregCr 0:deaafdfde3bb 480 break;
GregCr 0:deaafdfde3bb 481 }
GregCr 0:deaafdfde3bb 482 }
GregCr 0:deaafdfde3bb 483
GregCr 3:7e3595a9ebe0 484 void SX126x::SetCrcPolynomial( uint16_t polynomial )
GregCr 0:deaafdfde3bb 485 {
GregCr 3:7e3595a9ebe0 486 uint8_t buf[2];
GregCr 3:7e3595a9ebe0 487 buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF );
GregCr 3:7e3595a9ebe0 488 buf[1] = ( uint8_t )( polynomial & 0xFF );
GregCr 3:7e3595a9ebe0 489
GregCr 0:deaafdfde3bb 490 switch( GetPacketType( ) )
GregCr 0:deaafdfde3bb 491 {
GregCr 0:deaafdfde3bb 492 case PACKET_TYPE_GFSK:
GregCr 3:7e3595a9ebe0 493 WriteRegister( REG_LR_CRCPOLYBASEADDR, buf, 2 );
GregCr 0:deaafdfde3bb 494 break;
GregCr 0:deaafdfde3bb 495 default:
GregCr 0:deaafdfde3bb 496 break;
GregCr 0:deaafdfde3bb 497 }
GregCr 0:deaafdfde3bb 498 }
GregCr 0:deaafdfde3bb 499
GregCr 2:4ff11ea92fbe 500 void SX126x::SetWhiteningSeed( uint8_t seed )
GregCr 0:deaafdfde3bb 501 {
GregCr 0:deaafdfde3bb 502 switch( GetPacketType( ) )
GregCr 0:deaafdfde3bb 503 {
GregCr 0:deaafdfde3bb 504 case PACKET_TYPE_GFSK:
GregCr 0:deaafdfde3bb 505 WriteRegister( REG_LR_WHITSEEDBASEADDR, seed );
GregCr 0:deaafdfde3bb 506 break;
GregCr 0:deaafdfde3bb 507 default:
GregCr 0:deaafdfde3bb 508 break;
GregCr 0:deaafdfde3bb 509 }
GregCr 0:deaafdfde3bb 510 }
GregCr 0:deaafdfde3bb 511
GregCr 2:4ff11ea92fbe 512 int8_t SX126x::ParseHexFileLine( char* line )
GregCr 0:deaafdfde3bb 513 {
GregCr 0:deaafdfde3bb 514 uint16_t addr;
GregCr 0:deaafdfde3bb 515 uint16_t n;
GregCr 0:deaafdfde3bb 516 uint8_t code;
GregCr 0:deaafdfde3bb 517 uint8_t bytes[256];
GregCr 0:deaafdfde3bb 518
GregCr 0:deaafdfde3bb 519 if( GetHexFileLineFields( line, bytes, &addr, &n, &code ) != 0 )
GregCr 0:deaafdfde3bb 520 {
GregCr 0:deaafdfde3bb 521 if( code == 0 )
GregCr 0:deaafdfde3bb 522 {
GregCr 0:deaafdfde3bb 523 WriteRegister( addr, bytes, n );
GregCr 0:deaafdfde3bb 524 }
GregCr 0:deaafdfde3bb 525 if( code == 1 )
GregCr 0:deaafdfde3bb 526 { // end of file
GregCr 0:deaafdfde3bb 527 //return 2;
GregCr 0:deaafdfde3bb 528 }
GregCr 0:deaafdfde3bb 529 if( code == 2 )
GregCr 0:deaafdfde3bb 530 { // begin of file
GregCr 0:deaafdfde3bb 531 //return 3;
GregCr 0:deaafdfde3bb 532 }
GregCr 0:deaafdfde3bb 533 }
GregCr 0:deaafdfde3bb 534 else
GregCr 0:deaafdfde3bb 535 {
GregCr 0:deaafdfde3bb 536 return 0;
GregCr 0:deaafdfde3bb 537 }
GregCr 0:deaafdfde3bb 538 return 1;
GregCr 0:deaafdfde3bb 539 }
GregCr 0:deaafdfde3bb 540
GregCr 2:4ff11ea92fbe 541 int8_t SX126x::GetHexFileLineFields( char* line, uint8_t *bytes, uint16_t *addr, uint16_t *num, uint8_t *code )
GregCr 0:deaafdfde3bb 542 {
GregCr 0:deaafdfde3bb 543 uint16_t sum, len, cksum;
GregCr 0:deaafdfde3bb 544 char *ptr;
GregCr 0:deaafdfde3bb 545
GregCr 0:deaafdfde3bb 546 *num = 0;
GregCr 0:deaafdfde3bb 547 if( line[0] != ':' )
GregCr 0:deaafdfde3bb 548 {
GregCr 0:deaafdfde3bb 549 return 0;
GregCr 0:deaafdfde3bb 550 }
GregCr 0:deaafdfde3bb 551 if( strlen( line ) < 11 )
GregCr 0:deaafdfde3bb 552 {
GregCr 0:deaafdfde3bb 553 return 0;
GregCr 0:deaafdfde3bb 554 }
GregCr 0:deaafdfde3bb 555 ptr = line + 1;
GregCr 0:deaafdfde3bb 556 if( !sscanf( ptr, "%02hx", &len ) )
GregCr 0:deaafdfde3bb 557 {
GregCr 0:deaafdfde3bb 558 return 0;
GregCr 0:deaafdfde3bb 559 }
GregCr 0:deaafdfde3bb 560 ptr += 2;
GregCr 0:deaafdfde3bb 561 if( strlen( line ) < ( 11 + ( len * 2 ) ) )
GregCr 0:deaafdfde3bb 562 {
GregCr 0:deaafdfde3bb 563 return 0;
GregCr 0:deaafdfde3bb 564 }
GregCr 0:deaafdfde3bb 565 if( !sscanf( ptr, "%04hx", addr ) )
GregCr 0:deaafdfde3bb 566 {
GregCr 0:deaafdfde3bb 567 return 0;
GregCr 0:deaafdfde3bb 568 }
GregCr 0:deaafdfde3bb 569 ptr += 4;
GregCr 0:deaafdfde3bb 570 if( !sscanf( ptr, "%02hhx", code ) )
GregCr 0:deaafdfde3bb 571 {
GregCr 0:deaafdfde3bb 572 return 0;
GregCr 0:deaafdfde3bb 573 }
GregCr 0:deaafdfde3bb 574 ptr += 2;
GregCr 0:deaafdfde3bb 575 sum = ( len & 255 ) + ( ( *addr >> 8 ) & 255 ) + ( *addr & 255 ) + ( ( *code >> 8 ) & 255 ) + ( *code & 255 );
GregCr 0:deaafdfde3bb 576 while( *num != len )
GregCr 0:deaafdfde3bb 577 {
GregCr 0:deaafdfde3bb 578 if( !sscanf( ptr, "%02hhx", &bytes[*num] ) )
GregCr 0:deaafdfde3bb 579 {
GregCr 0:deaafdfde3bb 580 return 0;
GregCr 0:deaafdfde3bb 581 }
GregCr 0:deaafdfde3bb 582 ptr += 2;
GregCr 0:deaafdfde3bb 583 sum += bytes[*num] & 255;
GregCr 0:deaafdfde3bb 584 ( *num )++;
GregCr 0:deaafdfde3bb 585 if( *num >= 256 )
GregCr 0:deaafdfde3bb 586 {
GregCr 0:deaafdfde3bb 587 return 0;
GregCr 0:deaafdfde3bb 588 }
GregCr 0:deaafdfde3bb 589 }
GregCr 0:deaafdfde3bb 590 if( !sscanf( ptr, "%02hx", &cksum ) )
GregCr 0:deaafdfde3bb 591 {
GregCr 0:deaafdfde3bb 592 return 0;
GregCr 0:deaafdfde3bb 593 }
GregCr 0:deaafdfde3bb 594 if( ( ( sum & 255 ) + ( cksum & 255 ) ) & 255 )
GregCr 0:deaafdfde3bb 595 {
GregCr 0:deaafdfde3bb 596 return 0; // checksum error
GregCr 0:deaafdfde3bb 597 }
GregCr 0:deaafdfde3bb 598
GregCr 0:deaafdfde3bb 599 return 1;
GregCr 0:deaafdfde3bb 600 }
GregCr 0:deaafdfde3bb 601
GregCr 2:4ff11ea92fbe 602 void SX126x::OnDioIrq( void )
GregCr 0:deaafdfde3bb 603 {
GregCr 3:7e3595a9ebe0 604 if( onCustomDioIrq != NULL )
GregCr 0:deaafdfde3bb 605 {
GregCr 0:deaafdfde3bb 606 onCustomDioIrq();
GregCr 0:deaafdfde3bb 607 return;
GregCr 0:deaafdfde3bb 608 }
GregCr 3:7e3595a9ebe0 609
GregCr 0:deaafdfde3bb 610 uint16_t irqRegs = GetIrqStatus( );
GregCr 0:deaafdfde3bb 611 LastIrqs = irqRegs;
GregCr 3:7e3595a9ebe0 612 // printf("0x%04x\n\r", irqRegs );
GregCr 0:deaafdfde3bb 613 ClearIrqStatus( IRQ_RADIO_ALL );
GregCr 0:deaafdfde3bb 614
GregCr 0:deaafdfde3bb 615
GregCr 2:4ff11ea92fbe 616 #if( SX126x_DEBUG == 1 )
GregCr 0:deaafdfde3bb 617 DigitalOut TEST_PIN_1( D14 );
GregCr 0:deaafdfde3bb 618 DigitalOut TEST_PIN_2( D15 );
GregCr 0:deaafdfde3bb 619 for( int i = 0x8000; i != 0; i >>= 1 )
GregCr 0:deaafdfde3bb 620 {
GregCr 0:deaafdfde3bb 621 TEST_PIN_2 = 0;
GregCr 0:deaafdfde3bb 622 TEST_PIN_1 = ( ( irqRegs & i ) != 0 ) ? 1 : 0;
GregCr 0:deaafdfde3bb 623 TEST_PIN_2 = 1;
GregCr 0:deaafdfde3bb 624 }
GregCr 0:deaafdfde3bb 625 TEST_PIN_1 = 0;
GregCr 0:deaafdfde3bb 626 TEST_PIN_2 = 0;
GregCr 0:deaafdfde3bb 627 #endif
GregCr 0:deaafdfde3bb 628
GregCr 3:7e3595a9ebe0 629 if( ( irqRegs & IRQ_TX_DONE ) == IRQ_TX_DONE )
GregCr 0:deaafdfde3bb 630 {
GregCr 0:deaafdfde3bb 631 if( txDone != NULL )
GregCr 0:deaafdfde3bb 632 {
GregCr 0:deaafdfde3bb 633 txDone( );
GregCr 0:deaafdfde3bb 634 }
GregCr 0:deaafdfde3bb 635 }
GregCr 0:deaafdfde3bb 636
GregCr 3:7e3595a9ebe0 637 if( ( irqRegs & IRQ_RX_DONE ) == IRQ_RX_DONE )
GregCr 0:deaafdfde3bb 638 {
GregCr 3:7e3595a9ebe0 639 if( ( irqRegs & IRQ_CRC_ERROR ) == IRQ_CRC_ERROR )
GregCr 0:deaafdfde3bb 640 {
GregCr 3:7e3595a9ebe0 641 if( rxError != NULL )
GregCr 3:7e3595a9ebe0 642 {
GregCr 3:7e3595a9ebe0 643 rxError( IRQ_CRC_ERROR_CODE );
GregCr 3:7e3595a9ebe0 644 }
GregCr 3:7e3595a9ebe0 645 }
GregCr 3:7e3595a9ebe0 646 else
GregCr 3:7e3595a9ebe0 647 {
GregCr 3:7e3595a9ebe0 648 if( rxDone != NULL )
GregCr 3:7e3595a9ebe0 649 {
GregCr 3:7e3595a9ebe0 650 rxDone( );
GregCr 3:7e3595a9ebe0 651 }
GregCr 0:deaafdfde3bb 652 }
GregCr 0:deaafdfde3bb 653 }
GregCr 0:deaafdfde3bb 654
GregCr 3:7e3595a9ebe0 655 if( ( irqRegs & IRQ_RX_TX_TIMEOUT ) == IRQ_RX_TX_TIMEOUT )
GregCr 3:7e3595a9ebe0 656 {
GregCr 3:7e3595a9ebe0 657 if( ( rxTxTimeout != NULL ) && ( OperatingMode == MODE_TX ) )
GregCr 3:7e3595a9ebe0 658 {
GregCr 3:7e3595a9ebe0 659 rxTxTimeout( IRQ_TX_TIMEOUT );
GregCr 3:7e3595a9ebe0 660 }
GregCr 3:7e3595a9ebe0 661 else if( ( rxTxTimeout != NULL ) && ( OperatingMode == MODE_RX ) )
GregCr 3:7e3595a9ebe0 662 {
GregCr 3:7e3595a9ebe0 663 rxTxTimeout( IRQ_RX_TIMEOUT );
GregCr 3:7e3595a9ebe0 664 }
GregCr 3:7e3595a9ebe0 665 else
GregCr 3:7e3595a9ebe0 666 {
GregCr 3:7e3595a9ebe0 667 rxTxTimeout( IRQ_XYZ );
GregCr 3:7e3595a9ebe0 668 }
GregCr 3:7e3595a9ebe0 669 }
GregCr 3:7e3595a9ebe0 670
GregCr 3:7e3595a9ebe0 671 /*
GregCr 0:deaafdfde3bb 672 //IRQ_PREAMBLE_DETECTED = 0x0004,
GregCr 0:deaafdfde3bb 673 if( irqRegs & IRQ_PREAMBLE_DETECTED )
GregCr 0:deaafdfde3bb 674 {
GregCr 0:deaafdfde3bb 675 if( rxPblSyncWordHeader != NULL )
GregCr 0:deaafdfde3bb 676 {
GregCr 0:deaafdfde3bb 677 rxPblSyncWordHeader( IRQ_PBL_DETECT_CODE);
GregCr 3:7e3595a9ebe0 678
GregCr 0:deaafdfde3bb 679 }
GregCr 0:deaafdfde3bb 680 }
GregCr 0:deaafdfde3bb 681
GregCr 0:deaafdfde3bb 682 //IRQ_SYNCWORD_VALID = 0x0008,
GregCr 0:deaafdfde3bb 683 if( irqRegs & IRQ_SYNCWORD_VALID )
GregCr 0:deaafdfde3bb 684 {
GregCr 0:deaafdfde3bb 685 if( rxPblSyncWordHeader != NULL )
GregCr 0:deaafdfde3bb 686 {
GregCr 0:deaafdfde3bb 687 rxPblSyncWordHeader( IRQ_SYNCWORD_VALID_CODE );
GregCr 0:deaafdfde3bb 688 }
GregCr 0:deaafdfde3bb 689 }
GregCr 0:deaafdfde3bb 690
GregCr 0:deaafdfde3bb 691 //IRQ_HEADER_VALID = 0x0010,
GregCr 0:deaafdfde3bb 692 if ( irqRegs & IRQ_HEADER_VALID )
GregCr 0:deaafdfde3bb 693 {
GregCr 0:deaafdfde3bb 694 if( rxPblSyncWordHeader != NULL )
GregCr 0:deaafdfde3bb 695 {
GregCr 3:7e3595a9ebe0 696 rxPblSyncWordHeader( IRQ_HEADER_VALID_CODE );
GregCr 0:deaafdfde3bb 697 }
GregCr 0:deaafdfde3bb 698 }
GregCr 0:deaafdfde3bb 699
GregCr 0:deaafdfde3bb 700 //IRQ_HEADER_ERROR = 0x0020,
GregCr 0:deaafdfde3bb 701 if( irqRegs & IRQ_HEADER_ERROR )
GregCr 0:deaafdfde3bb 702 {
GregCr 0:deaafdfde3bb 703 if( rxError != NULL )
GregCr 0:deaafdfde3bb 704 {
GregCr 0:deaafdfde3bb 705 rxError( IRQ_HEADER_ERROR_CODE );
GregCr 0:deaafdfde3bb 706 }
GregCr 0:deaafdfde3bb 707 }
GregCr 0:deaafdfde3bb 708
GregCr 0:deaafdfde3bb 709 //IRQ_CAD_DONE = 0x0080,
GregCr 0:deaafdfde3bb 710 //IRQ_CAD_ACTIVITY_DETECTED = 0x0100,
GregCr 0:deaafdfde3bb 711 if( irqRegs & IRQ_CAD_DONE )
GregCr 0:deaafdfde3bb 712 {
GregCr 0:deaafdfde3bb 713 bool detected = ( ( irqRegs & IRQ_CAD_ACTIVITY_DETECTED ) == IRQ_CAD_ACTIVITY_DETECTED );
GregCr 0:deaafdfde3bb 714
GregCr 0:deaafdfde3bb 715 if( cadDone != NULL )
GregCr 0:deaafdfde3bb 716 {
GregCr 0:deaafdfde3bb 717 cadDone( detected );
GregCr 0:deaafdfde3bb 718 }
GregCr 0:deaafdfde3bb 719
GregCr 3:7e3595a9ebe0 720 }*/
GregCr 0:deaafdfde3bb 721 }
GregCr 0:deaafdfde3bb 722
GregCr 0:deaafdfde3bb 723
GregCr 0:deaafdfde3bb 724