ST / X_NUCLEO_CCA01M1

Library to handle the X-NUCLEO-CCA01M1 Sound Terminal Expansion Board.

Dependencies:   ST_I2S X_NUCLEO_COMMON

Dependents:   HelloWorld_CCA01M1 HelloWorld_CCA01M1_mbedOS HelloWorld_CCA01M1_mbedOS Karaoke_CCA01M1_CCA02M1_mbedOS ... more

Fork of X_NUCLEO_CCA01M1 by ST Expansion SW Team

Sound Terminal Library

Library to handle the X-NUCLEO-CCA01M1 Sound Terminal Expansion Board based on the STA350BW Sound Terminal device. A single board allows the output of a standard 2-channel stereo signal, while two boards stacked up realize a 4-channel audio system.


Power supply

The X-NUCLEO-CCA01M1 Sound Terminal Expansion Board has to be powered with at least 5V DC. You can connect the VCC terminal to an external power supplier or directly to the +5V pin of the CN6 Arduino connector.


Platform compatibility

  • This board can be currently used with the Nucleo F4 Family only, please see the ST_I2S library compatibility for further information.
  • The library is compatible both with mbed OS 5.x and mbed classic 2.x (to work with mbed classic, the main application has to import the "events" library, which is not included into the "mbed" library).


I2S Peripheral Usage

This board makes use of an I2S peripheral available on Nucleo boards, and when stacked up two times on the same Nucleo board each expansion board have to be configured to use a different I2S peripheral.

By default it comes with solder bridges configured to use the I2S1 peripheral, as depicted here below:

/media/uploads/Davidroid/solder_bridges_i2s1.png

And can be set to use the I2S2 peripheral by configuring the solder bridges this way:

/media/uploads/Davidroid/solder_bridges_i2s2.png


Components/sta350bw/sta350bw.h@0:542c79e7e0ef, 2017-02-10 (annotated)

Committer:
davide.aliprandi@st.com
Date:
Fri Feb 10 17:29:23 2017 +0100
Revision:
0:542c79e7e0ef
Child:
3:c688a4acb4bf
First version of the library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
davide.aliprandi@st.com 0:542c79e7e0ef 1 /**
davide.aliprandi@st.com 0:542c79e7e0ef 2 ******************************************************************************
davide.aliprandi@st.com 0:542c79e7e0ef 3 * @file STA350BW.h
davide.aliprandi@st.com 0:542c79e7e0ef 4 * @author Central Labs
davide.aliprandi@st.com 0:542c79e7e0ef 5 * @version V1.0.0
davide.aliprandi@st.com 0:542c79e7e0ef 6 * @date 18-August-2015
davide.aliprandi@st.com 0:542c79e7e0ef 7 * @brief This file contains definitions for STA350BW.c
davide.aliprandi@st.com 0:542c79e7e0ef 8 * firmware driver.
davide.aliprandi@st.com 0:542c79e7e0ef 9 ******************************************************************************
davide.aliprandi@st.com 0:542c79e7e0ef 10 * @attention
davide.aliprandi@st.com 0:542c79e7e0ef 11 *
davide.aliprandi@st.com 0:542c79e7e0ef 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
davide.aliprandi@st.com 0:542c79e7e0ef 13 *
davide.aliprandi@st.com 0:542c79e7e0ef 14 * Redistribution and use in source and binary forms, with or without modification,
davide.aliprandi@st.com 0:542c79e7e0ef 15 * are permitted provided that the following conditions are met:
davide.aliprandi@st.com 0:542c79e7e0ef 16 * 1. Redistributions of source code must retain the above copyright notice,
davide.aliprandi@st.com 0:542c79e7e0ef 17 * this list of conditions and the following disclaimer.
davide.aliprandi@st.com 0:542c79e7e0ef 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
davide.aliprandi@st.com 0:542c79e7e0ef 19 * this list of conditions and the following disclaimer in the documentation
davide.aliprandi@st.com 0:542c79e7e0ef 20 * and/or other materials provided with the distribution.
davide.aliprandi@st.com 0:542c79e7e0ef 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
davide.aliprandi@st.com 0:542c79e7e0ef 22 * may be used to endorse or promote products derived from this software
davide.aliprandi@st.com 0:542c79e7e0ef 23 * without specific prior written permission.
davide.aliprandi@st.com 0:542c79e7e0ef 24 *
davide.aliprandi@st.com 0:542c79e7e0ef 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
davide.aliprandi@st.com 0:542c79e7e0ef 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
davide.aliprandi@st.com 0:542c79e7e0ef 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
davide.aliprandi@st.com 0:542c79e7e0ef 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
davide.aliprandi@st.com 0:542c79e7e0ef 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
davide.aliprandi@st.com 0:542c79e7e0ef 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
davide.aliprandi@st.com 0:542c79e7e0ef 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
davide.aliprandi@st.com 0:542c79e7e0ef 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
davide.aliprandi@st.com 0:542c79e7e0ef 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
davide.aliprandi@st.com 0:542c79e7e0ef 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
davide.aliprandi@st.com 0:542c79e7e0ef 35 *
davide.aliprandi@st.com 0:542c79e7e0ef 36 ******************************************************************************
davide.aliprandi@st.com 0:542c79e7e0ef 37 */
davide.aliprandi@st.com 0:542c79e7e0ef 38
davide.aliprandi@st.com 0:542c79e7e0ef 39
davide.aliprandi@st.com 0:542c79e7e0ef 40 /* Define to prevent recursive inclusion -------------------------------------*/
davide.aliprandi@st.com 0:542c79e7e0ef 41
davide.aliprandi@st.com 0:542c79e7e0ef 42 #ifndef __STA350BW_H
davide.aliprandi@st.com 0:542c79e7e0ef 43 #define __STA350BW_H
davide.aliprandi@st.com 0:542c79e7e0ef 44
davide.aliprandi@st.com 0:542c79e7e0ef 45 #ifdef __cplusplus
davide.aliprandi@st.com 0:542c79e7e0ef 46 extern "C" {
davide.aliprandi@st.com 0:542c79e7e0ef 47 #endif
davide.aliprandi@st.com 0:542c79e7e0ef 48
davide.aliprandi@st.com 0:542c79e7e0ef 49
davide.aliprandi@st.com 0:542c79e7e0ef 50 /* Includes ------------------------------------------------------------------*/
davide.aliprandi@st.com 0:542c79e7e0ef 51
davide.aliprandi@st.com 0:542c79e7e0ef 52 #include "../Common/sound_terminal.h"
davide.aliprandi@st.com 0:542c79e7e0ef 53
davide.aliprandi@st.com 0:542c79e7e0ef 54 /** @addtogroup BSP
davide.aliprandi@st.com 0:542c79e7e0ef 55 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 56 */
davide.aliprandi@st.com 0:542c79e7e0ef 57
davide.aliprandi@st.com 0:542c79e7e0ef 58 /** @addtogroup Components
davide.aliprandi@st.com 0:542c79e7e0ef 59 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 60 */
davide.aliprandi@st.com 0:542c79e7e0ef 61
davide.aliprandi@st.com 0:542c79e7e0ef 62 /** @addtogroup STA350BW
davide.aliprandi@st.com 0:542c79e7e0ef 63 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 64 */
davide.aliprandi@st.com 0:542c79e7e0ef 65
davide.aliprandi@st.com 0:542c79e7e0ef 66
davide.aliprandi@st.com 0:542c79e7e0ef 67 /** @defgroup STA350BW_Exported_Constants
davide.aliprandi@st.com 0:542c79e7e0ef 68 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 69 */
davide.aliprandi@st.com 0:542c79e7e0ef 70
davide.aliprandi@st.com 0:542c79e7e0ef 71 /** @defgroup STA350BW_Registers_Mapping
davide.aliprandi@st.com 0:542c79e7e0ef 72 * @brief STA350BW register mapping
davide.aliprandi@st.com 0:542c79e7e0ef 73 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 74 */
davide.aliprandi@st.com 0:542c79e7e0ef 75
davide.aliprandi@st.com 0:542c79e7e0ef 76 #define STA350BW_MAX_REGISTERS ((uint8_t)0x56)
davide.aliprandi@st.com 0:542c79e7e0ef 77
davide.aliprandi@st.com 0:542c79e7e0ef 78 /**
davide.aliprandi@st.com 0:542c79e7e0ef 79 * @brief Configuration Register A
davide.aliprandi@st.com 0:542c79e7e0ef 80 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 81 * Read/Write
davide.aliprandi@st.com 0:542c79e7e0ef 82 * Default value: 0x63
davide.aliprandi@st.com 0:542c79e7e0ef 83 * 7 FAULT detect recovery bypass
davide.aliprandi@st.com 0:542c79e7e0ef 84 * 6 TWAB Thermal warning adjustable bypass
davide.aliprandi@st.com 0:542c79e7e0ef 85 * 5 TWRB Thermal warning recovery bypass
davide.aliprandi@st.com 0:542c79e7e0ef 86 * 4,3 IR Interpolatio ratio
davide.aliprandi@st.com 0:542c79e7e0ef 87 * [2:0] MCS Master clock selection
davide.aliprandi@st.com 0:542c79e7e0ef 88 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 89 */
davide.aliprandi@st.com 0:542c79e7e0ef 90 #define STA350BW_CONF_REGA ((uint8_t)0x00) /*Configuration Register A*/
davide.aliprandi@st.com 0:542c79e7e0ef 91
davide.aliprandi@st.com 0:542c79e7e0ef 92 /**
davide.aliprandi@st.com 0:542c79e7e0ef 93 * @brief Configuration Register B
davide.aliprandi@st.com 0:542c79e7e0ef 94 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 95 * Read/Write
davide.aliprandi@st.com 0:542c79e7e0ef 96 * Default value: 0x80
davide.aliprandi@st.com 0:542c79e7e0ef 97 * 7 C2IM channel 2 input mapping
davide.aliprandi@st.com 0:542c79e7e0ef 98 * 6 C2IM channel 1 input mapping
davide.aliprandi@st.com 0:542c79e7e0ef 99 * 5 DSCKE Delay serial clock enable
davide.aliprandi@st.com 0:542c79e7e0ef 100 * 4 SAIFB Serial data first bit
davide.aliprandi@st.com 0:542c79e7e0ef 101 * [3:0] Serial Input interface format
davide.aliprandi@st.com 0:542c79e7e0ef 102 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 103 */
davide.aliprandi@st.com 0:542c79e7e0ef 104 #define STA350BW_CONF_REGB ((uint8_t)0x01) /*Configuration Register B*/
davide.aliprandi@st.com 0:542c79e7e0ef 105
davide.aliprandi@st.com 0:542c79e7e0ef 106
davide.aliprandi@st.com 0:542c79e7e0ef 107 /**
davide.aliprandi@st.com 0:542c79e7e0ef 108 * @brief Configuration Register C
davide.aliprandi@st.com 0:542c79e7e0ef 109 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 110 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 111 * Default value: 0x09F
davide.aliprandi@st.com 0:542c79e7e0ef 112 * 7 OCRB Overcurrent warning adjustment bypass
davide.aliprandi@st.com 0:542c79e7e0ef 113 * [5:2] CSZx: FFX compensating pulse size
davide.aliprandi@st.com 0:542c79e7e0ef 114 * [1:0] OMx: FFX Output mode
davide.aliprandi@st.com 0:542c79e7e0ef 115 * 0 Clk_Out: Enable HSE on MCO. 0: MCO disable. 1: MCO enable
davide.aliprandi@st.com 0:542c79e7e0ef 116 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 117 */
davide.aliprandi@st.com 0:542c79e7e0ef 118 #define STA350BW_CONF_REGC ((uint8_t)0x02) /*Configuration Register C*/
davide.aliprandi@st.com 0:542c79e7e0ef 119
davide.aliprandi@st.com 0:542c79e7e0ef 120 /**
davide.aliprandi@st.com 0:542c79e7e0ef 121 * @brief I2C address Configuration Register D
davide.aliprandi@st.com 0:542c79e7e0ef 122 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 123 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 124 * Default value: 0x40
davide.aliprandi@st.com 0:542c79e7e0ef 125 * 7 SME soft mute enable
davide.aliprandi@st.com 0:542c79e7e0ef 126 * 6 ZDE zero detect enable
davide.aliprandi@st.com 0:542c79e7e0ef 127 * 5 DRC DRC or anti-clipping mode
davide.aliprandi@st.com 0:542c79e7e0ef 128 * 4 BQL Biquad Link
davide.aliprandi@st.com 0:542c79e7e0ef 129 * 3 PSL Post scale Link
davide.aliprandi@st.com 0:542c79e7e0ef 130 * 2 DSPB DSP bypass
davide.aliprandi@st.com 0:542c79e7e0ef 131 * 1 DEMP De-Emphasys filter
davide.aliprandi@st.com 0:542c79e7e0ef 132 * 0 HPB High pass filter bypass
davide.aliprandi@st.com 0:542c79e7e0ef 133 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 134 */
davide.aliprandi@st.com 0:542c79e7e0ef 135 #define STA350BW_CONF_REGD ((uint8_t)0x03) /*Configuration Register D*/
davide.aliprandi@st.com 0:542c79e7e0ef 136
davide.aliprandi@st.com 0:542c79e7e0ef 137 /**
davide.aliprandi@st.com 0:542c79e7e0ef 138 * @brief I2C address Configuration Register E
davide.aliprandi@st.com 0:542c79e7e0ef 139 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 140 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 141 * Default value: 0xC2
davide.aliprandi@st.com 0:542c79e7e0ef 142 * 7 SVE soft volume enable
davide.aliprandi@st.com 0:542c79e7e0ef 143 * 6 ZCE zero crossing enable
davide.aliprandi@st.com 0:542c79e7e0ef 144 * 5 DCCV variable distorsion compensation
davide.aliprandi@st.com 0:542c79e7e0ef 145 * 4 PWMS PWM speed
davide.aliprandi@st.com 0:542c79e7e0ef 146 * 3 AME AM noise reduction enable
davide.aliprandi@st.com 0:542c79e7e0ef 147 * 2 NSBW Noise shaper bandwidth
davide.aliprandi@st.com 0:542c79e7e0ef 148 * 1 MPC Max Power correction
davide.aliprandi@st.com 0:542c79e7e0ef 149 * 0 MPCV Variable ax power correction
davide.aliprandi@st.com 0:542c79e7e0ef 150 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 151 */
davide.aliprandi@st.com 0:542c79e7e0ef 152 #define STA350BW_CONF_REGE ((uint8_t)0x04) /*Configuration Register E*/
davide.aliprandi@st.com 0:542c79e7e0ef 153
davide.aliprandi@st.com 0:542c79e7e0ef 154 /**
davide.aliprandi@st.com 0:542c79e7e0ef 155 * @brief I2C address Configuration Register F
davide.aliprandi@st.com 0:542c79e7e0ef 156 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 157 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 158 * Default value: 0x5C
davide.aliprandi@st.com 0:542c79e7e0ef 159 * 7 EAPD External Amplifier Power Down
davide.aliprandi@st.com 0:542c79e7e0ef 160 * 6 PWDN device power down
davide.aliprandi@st.com 0:542c79e7e0ef 161 * 5 ECLE Auto EAPD on clock loss
davide.aliprandi@st.com 0:542c79e7e0ef 162 * 4 LDTE LRCK double trigger protection
davide.aliprandi@st.com 0:542c79e7e0ef 163 * 3 BCLE Binary out mode clock loss detection
davide.aliprandi@st.com 0:542c79e7e0ef 164 * 2 IDE Invalid Input Detect
davide.aliprandi@st.com 0:542c79e7e0ef 165 * 1,0 OCFG Output configuration
davide.aliprandi@st.com 0:542c79e7e0ef 166 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 167 */
davide.aliprandi@st.com 0:542c79e7e0ef 168 #define STA350BW_CONF_REGF ((uint8_t)0x05) /*Configuration Register F*/
davide.aliprandi@st.com 0:542c79e7e0ef 169
davide.aliprandi@st.com 0:542c79e7e0ef 170 /**
davide.aliprandi@st.com 0:542c79e7e0ef 171 * @brief I2C address MUTE/Line Out configuration
davide.aliprandi@st.com 0:542c79e7e0ef 172 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 173 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 174 * Default value: 0x10
davide.aliprandi@st.com 0:542c79e7e0ef 175 * [7:6] LOC line out configuration
davide.aliprandi@st.com 0:542c79e7e0ef 176 * [5:4] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 177 * 3 C3M Channel 3 MUTE
davide.aliprandi@st.com 0:542c79e7e0ef 178 * 2 C2M Channel 2 MUTE
davide.aliprandi@st.com 0:542c79e7e0ef 179 * 1 C1M Channel 1 MUTE
davide.aliprandi@st.com 0:542c79e7e0ef 180 * 0 MMUTE Master Mute
davide.aliprandi@st.com 0:542c79e7e0ef 181 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 182 */
davide.aliprandi@st.com 0:542c79e7e0ef 183 #define STA350BW_MUTE ((uint8_t)0x06) /* MUTE / Lineout configuration */
davide.aliprandi@st.com 0:542c79e7e0ef 184
davide.aliprandi@st.com 0:542c79e7e0ef 185 /**
davide.aliprandi@st.com 0:542c79e7e0ef 186 * @brief I2C address Master Volume
davide.aliprandi@st.com 0:542c79e7e0ef 187 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 188 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 189 * Default value: 0xFF
davide.aliprandi@st.com 0:542c79e7e0ef 190 * [7:0] Master volume (default -127.5dB)
davide.aliprandi@st.com 0:542c79e7e0ef 191 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 192 */
davide.aliprandi@st.com 0:542c79e7e0ef 193 #define STA350BW_MVOL ((uint8_t)0x07) /* Master Volume */
davide.aliprandi@st.com 0:542c79e7e0ef 194
davide.aliprandi@st.com 0:542c79e7e0ef 195 /**
davide.aliprandi@st.com 0:542c79e7e0ef 196 * @brief I2C address Channel 1 Volume
davide.aliprandi@st.com 0:542c79e7e0ef 197 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 198 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 199 * Default value: 0x60
davide.aliprandi@st.com 0:542c79e7e0ef 200 * [7:0] Master volume (default 0.0dB)
davide.aliprandi@st.com 0:542c79e7e0ef 201 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 202 */
davide.aliprandi@st.com 0:542c79e7e0ef 203 #define STA350BW_C1VOL ((uint8_t)0x08) /* Channel 1 volume */
davide.aliprandi@st.com 0:542c79e7e0ef 204
davide.aliprandi@st.com 0:542c79e7e0ef 205 /**
davide.aliprandi@st.com 0:542c79e7e0ef 206 * @brief I2C address Channel 2 Volume
davide.aliprandi@st.com 0:542c79e7e0ef 207 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 208 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 209 * Default value: 0x60
davide.aliprandi@st.com 0:542c79e7e0ef 210 * [7:0] Master volume (default 0.0dB)
davide.aliprandi@st.com 0:542c79e7e0ef 211 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 212 */
davide.aliprandi@st.com 0:542c79e7e0ef 213 #define STA350BW_C2VOL ((uint8_t)0x09) /* Channel 2 volume */
davide.aliprandi@st.com 0:542c79e7e0ef 214
davide.aliprandi@st.com 0:542c79e7e0ef 215 /**
davide.aliprandi@st.com 0:542c79e7e0ef 216 * @brief I2C address Channel 3 Volume
davide.aliprandi@st.com 0:542c79e7e0ef 217 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 218 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 219 * Default value: 0x60
davide.aliprandi@st.com 0:542c79e7e0ef 220 * [7:0] Master volume (default 0.0dB)
davide.aliprandi@st.com 0:542c79e7e0ef 221 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 222 */
davide.aliprandi@st.com 0:542c79e7e0ef 223 #define STA350BW_C3VOL ((uint8_t)0x0A) /* Channel 3 volume */
davide.aliprandi@st.com 0:542c79e7e0ef 224
davide.aliprandi@st.com 0:542c79e7e0ef 225 /**
davide.aliprandi@st.com 0:542c79e7e0ef 226 * @brief I2C address AUTO MODE 1
davide.aliprandi@st.com 0:542c79e7e0ef 227 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 228 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 229 * Default value: 0x80
davide.aliprandi@st.com 0:542c79e7e0ef 230 * [7:6] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 231 * [5:4] AMGC Audio Preset Gain compression
davide.aliprandi@st.com 0:542c79e7e0ef 232 * [3:0] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 233 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 234 */
davide.aliprandi@st.com 0:542c79e7e0ef 235 #define STA350BW_AUTO1 ((uint8_t)0x0B) /* Audio Preset 1 register */
davide.aliprandi@st.com 0:542c79e7e0ef 236
davide.aliprandi@st.com 0:542c79e7e0ef 237 /**
davide.aliprandi@st.com 0:542c79e7e0ef 238 * @brief I2C address AUTO MODE 2
davide.aliprandi@st.com 0:542c79e7e0ef 239 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 240 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 241 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 242 * [7:4] XO preset crossover filter
davide.aliprandi@st.com 0:542c79e7e0ef 243 * [3:1] AMAMx AM atomode settings
davide.aliprandi@st.com 0:542c79e7e0ef 244 * 0 AMAME AM automode enable
davide.aliprandi@st.com 0:542c79e7e0ef 245 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 246 */
davide.aliprandi@st.com 0:542c79e7e0ef 247 #define STA350BW_AUTO2 ((uint8_t)0x0C) /* Audio Preset 2 register */
davide.aliprandi@st.com 0:542c79e7e0ef 248
davide.aliprandi@st.com 0:542c79e7e0ef 249 /**
davide.aliprandi@st.com 0:542c79e7e0ef 250 * @brief I2C address Channel 1 configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 251 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 252 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 253 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 254 * 7,6 C1OM Channel 1 output mapping
davide.aliprandi@st.com 0:542c79e7e0ef 255 * 5,4 C1LS Channel 1 limiter mapping
davide.aliprandi@st.com 0:542c79e7e0ef 256 * 3 C1BO Channel 1 Binary output
davide.aliprandi@st.com 0:542c79e7e0ef 257 * 2 C1VPB Channel 1 volume bypass
davide.aliprandi@st.com 0:542c79e7e0ef 258 * 1 C1EQBP Channel 1 Equalization Bypass
davide.aliprandi@st.com 0:542c79e7e0ef 259 * 0 C1TCB Channel 1 Tone/Control Bypass
davide.aliprandi@st.com 0:542c79e7e0ef 260 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 261 */
davide.aliprandi@st.com 0:542c79e7e0ef 262 #define STA350BW_C1CFG ((uint8_t)0x0E) /* Channel 1 configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 263
davide.aliprandi@st.com 0:542c79e7e0ef 264 /**
davide.aliprandi@st.com 0:542c79e7e0ef 265 * @brief I2C address Channel 2 configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 266 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 267 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 268 * Default value: 0x40
davide.aliprandi@st.com 0:542c79e7e0ef 269 * 7,6 C2OM Channel 2 output mapping
davide.aliprandi@st.com 0:542c79e7e0ef 270 * 5,4 C2LS Channel 2 limiter mapping
davide.aliprandi@st.com 0:542c79e7e0ef 271 * 3 C2BO Channel 2 Binary output
davide.aliprandi@st.com 0:542c79e7e0ef 272 * 2 C2VPB Channel 2 volume bypass
davide.aliprandi@st.com 0:542c79e7e0ef 273 * 1 C2EQBP Channel 2 Equalization Bypass
davide.aliprandi@st.com 0:542c79e7e0ef 274 * 0 C2TCB Channel 2 Tone/Control Bypass
davide.aliprandi@st.com 0:542c79e7e0ef 275 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 276 */
davide.aliprandi@st.com 0:542c79e7e0ef 277 #define STA350BW_C2CFG ((uint8_t)0x0F) /* Channel 2 configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 278
davide.aliprandi@st.com 0:542c79e7e0ef 279 /**
davide.aliprandi@st.com 0:542c79e7e0ef 280 * @brief I2C address Channel 3 configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 281 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 282 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 283 * Default value: 0x80
davide.aliprandi@st.com 0:542c79e7e0ef 284 * 7,6 C2OM Channel 3 output mapping
davide.aliprandi@st.com 0:542c79e7e0ef 285 * 5,4 C2LS Channel 3 limiter mapping
davide.aliprandi@st.com 0:542c79e7e0ef 286 * 3 C2BO Channel 3 Binary output
davide.aliprandi@st.com 0:542c79e7e0ef 287 * 2 C2VPB Channel 3 volume bypass
davide.aliprandi@st.com 0:542c79e7e0ef 288 * 1,0 RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 289 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 290 */
davide.aliprandi@st.com 0:542c79e7e0ef 291 #define STA350BW_C3CFG ((uint8_t)0x10) /* Channel 3 configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 292
davide.aliprandi@st.com 0:542c79e7e0ef 293 /**
davide.aliprandi@st.com 0:542c79e7e0ef 294 * @brief I2C address Tone control register
davide.aliprandi@st.com 0:542c79e7e0ef 295 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 296 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 297 * Default value: 0x77
davide.aliprandi@st.com 0:542c79e7e0ef 298 * [7:4] Treble
davide.aliprandi@st.com 0:542c79e7e0ef 299 * [3:0] Bass
davide.aliprandi@st.com 0:542c79e7e0ef 300 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 301 */
davide.aliprandi@st.com 0:542c79e7e0ef 302 #define STA350BW_TONE ((uint8_t)0x11) /* Tone control register */
davide.aliprandi@st.com 0:542c79e7e0ef 303
davide.aliprandi@st.com 0:542c79e7e0ef 304 /**
davide.aliprandi@st.com 0:542c79e7e0ef 305 * @brief I2C address Limiter 1 Attack/Release rate register
davide.aliprandi@st.com 0:542c79e7e0ef 306 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 307 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 308 * Default value: 0x6A
davide.aliprandi@st.com 0:542c79e7e0ef 309 * [7:4] Limiter 1 Attack rate
davide.aliprandi@st.com 0:542c79e7e0ef 310 * [3:0] Limiter 1 release rate
davide.aliprandi@st.com 0:542c79e7e0ef 311 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 312 */
davide.aliprandi@st.com 0:542c79e7e0ef 313 #define STA350BW_L1AR ((uint8_t)0x12) /* Limiter 1 Attack/Release rate register */
davide.aliprandi@st.com 0:542c79e7e0ef 314
davide.aliprandi@st.com 0:542c79e7e0ef 315 /**
davide.aliprandi@st.com 0:542c79e7e0ef 316 * @brief I2C address Limiter 1 Attack/Release threshold register
davide.aliprandi@st.com 0:542c79e7e0ef 317 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 318 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 319 * Default value: 0x69
davide.aliprandi@st.com 0:542c79e7e0ef 320 * [7:4] Limiter 1 Attack threshold
davide.aliprandi@st.com 0:542c79e7e0ef 321 * [3:0] Limiter 1 release threshold
davide.aliprandi@st.com 0:542c79e7e0ef 322 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 323 */
davide.aliprandi@st.com 0:542c79e7e0ef 324 #define STA350BW_L1ATR ((uint8_t)0x13) /* Limiter 1 Attack/Release threshold register */
davide.aliprandi@st.com 0:542c79e7e0ef 325
davide.aliprandi@st.com 0:542c79e7e0ef 326 /**
davide.aliprandi@st.com 0:542c79e7e0ef 327 * @brief I2C address Limiter 2 Attack/Release rate register
davide.aliprandi@st.com 0:542c79e7e0ef 328 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 329 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 330 * Default value: 0x6A
davide.aliprandi@st.com 0:542c79e7e0ef 331 * [7:4] Limiter 2 Attack rate
davide.aliprandi@st.com 0:542c79e7e0ef 332 * [3:0] Limiter 2 Release rate
davide.aliprandi@st.com 0:542c79e7e0ef 333 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 334 */
davide.aliprandi@st.com 0:542c79e7e0ef 335 #define STA350BW_L2AR ((uint8_t)0x14) /* Limiter 2 Attack/Release rate register */
davide.aliprandi@st.com 0:542c79e7e0ef 336
davide.aliprandi@st.com 0:542c79e7e0ef 337 /**
davide.aliprandi@st.com 0:542c79e7e0ef 338 * @brief I2C address Limiter 2 Attack/Release threshold register
davide.aliprandi@st.com 0:542c79e7e0ef 339 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 340 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 341 * Default value: 0x69
davide.aliprandi@st.com 0:542c79e7e0ef 342 * [7:4] Limiter 2 Attack threshold
davide.aliprandi@st.com 0:542c79e7e0ef 343 * [3:0] Limiter 2 release threshold
davide.aliprandi@st.com 0:542c79e7e0ef 344 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 345 */
davide.aliprandi@st.com 0:542c79e7e0ef 346 #define STA350BW_L2ATR ((uint8_t)0x15) /* Limiter 2 Attack/Release threshold register */
davide.aliprandi@st.com 0:542c79e7e0ef 347
davide.aliprandi@st.com 0:542c79e7e0ef 348 /* RAM download*/
davide.aliprandi@st.com 0:542c79e7e0ef 349
davide.aliprandi@st.com 0:542c79e7e0ef 350 /**
davide.aliprandi@st.com 0:542c79e7e0ef 351 * @brief I2C address Coefficient address register
davide.aliprandi@st.com 0:542c79e7e0ef 352 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 353 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 354 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 355 * [7:6] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 356 * [5:0] RAM address
davide.aliprandi@st.com 0:542c79e7e0ef 357 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 358 */
davide.aliprandi@st.com 0:542c79e7e0ef 359 #define STA350BW_CFADDR ((uint8_t)0x16) /* Coefficient address register */
davide.aliprandi@st.com 0:542c79e7e0ef 360
davide.aliprandi@st.com 0:542c79e7e0ef 361 /**
davide.aliprandi@st.com 0:542c79e7e0ef 362 * @brief I2C address Coefficient b1 data register bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 363 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 364 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 365 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 366 * [7:0] coefficient b1 bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 367 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 368 */
davide.aliprandi@st.com 0:542c79e7e0ef 369 #define STA350BW_B1CF1 ((uint8_t)0x17) /* Coefficient b1 data register bits 23:16 */
davide.aliprandi@st.com 0:542c79e7e0ef 370
davide.aliprandi@st.com 0:542c79e7e0ef 371 /**
davide.aliprandi@st.com 0:542c79e7e0ef 372 * @brief I2C address Coefficient b1 data register bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 373 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 374 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 375 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 376 * [7:0] coefficient b1 bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 377 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 378 */
davide.aliprandi@st.com 0:542c79e7e0ef 379 #define STA350BW_B1CF2 ((uint8_t)0x18) /* Coefficient b1 data register bits 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 380
davide.aliprandi@st.com 0:542c79e7e0ef 381 /**
davide.aliprandi@st.com 0:542c79e7e0ef 382 * @brief I2C address Coefficient b1 data register bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 383 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 384 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 385 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 386 * [7:0] coefficient b1 bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 387 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 388 */
davide.aliprandi@st.com 0:542c79e7e0ef 389 #define STA350BW_B1CF3 ((uint8_t)0x19) /* Coefficient b1 data register bits 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 390
davide.aliprandi@st.com 0:542c79e7e0ef 391 /**
davide.aliprandi@st.com 0:542c79e7e0ef 392 * @brief I2C address Coefficient b2 data register bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 393 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 394 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 395 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 396 * [7:0] coefficient b2 bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 397 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 398 */
davide.aliprandi@st.com 0:542c79e7e0ef 399 #define STA350BW_B2CF1 ((uint8_t)0x1A) /* Coefficient b2 data register bits 23:16 */
davide.aliprandi@st.com 0:542c79e7e0ef 400
davide.aliprandi@st.com 0:542c79e7e0ef 401 /**
davide.aliprandi@st.com 0:542c79e7e0ef 402 * @brief I2C address Coefficient b2 data register bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 403 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 404 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 405 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 406 * [7:0] coefficient b2 bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 407 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 408 */
davide.aliprandi@st.com 0:542c79e7e0ef 409 #define STA350BW_B2CF2 ((uint8_t)0x1B) /* Coefficient b2 data register bits 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 410
davide.aliprandi@st.com 0:542c79e7e0ef 411 /**
davide.aliprandi@st.com 0:542c79e7e0ef 412 * @brief I2C address Coefficient b2 data register bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 413 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 414 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 415 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 416 * [7:0] Coefficient b2 data bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 417 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 418 */
davide.aliprandi@st.com 0:542c79e7e0ef 419 #define STA350BW_B2CF3 ((uint8_t)0x1C) /* Coefficient b2 data register bits 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 420
davide.aliprandi@st.com 0:542c79e7e0ef 421 /**
davide.aliprandi@st.com 0:542c79e7e0ef 422 * @brief I2C address Coefficient a1 data register bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 423 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 424 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 425 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 426 * [7:0] Coefficient a1 data bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 427 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 428 */
davide.aliprandi@st.com 0:542c79e7e0ef 429 #define STA350BW_A1CF1 ((uint8_t)0x1D) /* Coefficient a1 data register bits 23:16 */
davide.aliprandi@st.com 0:542c79e7e0ef 430
davide.aliprandi@st.com 0:542c79e7e0ef 431 /**
davide.aliprandi@st.com 0:542c79e7e0ef 432 * @brief I2C address Coefficient a1 data register bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 433 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 434 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 435 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 436 * [7:0] Coefficient a1 data bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 437 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 438 */
davide.aliprandi@st.com 0:542c79e7e0ef 439 #define STA350BW_A1CF2 ((uint8_t)0x1E) /* Coefficient a1 data register bits 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 440
davide.aliprandi@st.com 0:542c79e7e0ef 441 /**
davide.aliprandi@st.com 0:542c79e7e0ef 442 * @brief I2C address Coefficient a1 data register bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 443 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 444 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 445 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 446 * [7:0] Coefficient a1 data bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 447 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 448 */
davide.aliprandi@st.com 0:542c79e7e0ef 449 #define STA350BW_A1CF3 ((uint8_t)0x1F) /* Coefficient a1 data register bits 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 450
davide.aliprandi@st.com 0:542c79e7e0ef 451 /**
davide.aliprandi@st.com 0:542c79e7e0ef 452 * @brief I2C address Coefficient a2 data register bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 453 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 454 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 455 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 456 * [7:0] Coefficient a2 data bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 457 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 458 */
davide.aliprandi@st.com 0:542c79e7e0ef 459 #define STA350BW_A2CF1 ((uint8_t)0x20) /* Coefficient a2 data register bits 23:16 */
davide.aliprandi@st.com 0:542c79e7e0ef 460
davide.aliprandi@st.com 0:542c79e7e0ef 461 /**
davide.aliprandi@st.com 0:542c79e7e0ef 462 * @brief I2C address Coefficient a2 data register bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 463 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 464 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 465 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 466 * [7:0] Coefficient a2 data bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 467 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 468 */
davide.aliprandi@st.com 0:542c79e7e0ef 469 #define STA350BW_A2CF2 ((uint8_t)0x21) /* Coefficient a2 data register bits 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 470
davide.aliprandi@st.com 0:542c79e7e0ef 471 /**
davide.aliprandi@st.com 0:542c79e7e0ef 472 * @brief I2C address Coefficient a2 data register bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 473 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 474 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 475 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 476 * [7:0] Coefficient a2 data bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 477 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 478 */
davide.aliprandi@st.com 0:542c79e7e0ef 479 #define STA350BW_A2CF3 ((uint8_t)0x22) /* Coefficient a2 data register bits 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 480
davide.aliprandi@st.com 0:542c79e7e0ef 481 /**
davide.aliprandi@st.com 0:542c79e7e0ef 482 * @brief I2C address Coefficient b0 data register bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 483 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 484 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 485 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 486 * [7:0] coefficient b0 bits 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 487 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 488 */
davide.aliprandi@st.com 0:542c79e7e0ef 489 #define STA350BW_B0CF1 ((uint8_t)0x23) /* Coefficient b0 data register bits 23:16 */
davide.aliprandi@st.com 0:542c79e7e0ef 490
davide.aliprandi@st.com 0:542c79e7e0ef 491 /**
davide.aliprandi@st.com 0:542c79e7e0ef 492 * @brief I2C address Coefficient b0 data register bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 493 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 494 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 495 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 496 * [7:0] Coefficient b0 data bits 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 497 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 498 */
davide.aliprandi@st.com 0:542c79e7e0ef 499 #define STA350BW_B0CF2 ((uint8_t)0x24) /* Coefficient b0 data register bits 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 500
davide.aliprandi@st.com 0:542c79e7e0ef 501 /**
davide.aliprandi@st.com 0:542c79e7e0ef 502 * @brief I2C address Coefficient b0 data register bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 503 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 504 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 505 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 506 * [7:0] Coefficient b0 data bits 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 507 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 508 */
davide.aliprandi@st.com 0:542c79e7e0ef 509 #define STA350BW_B0CF3 ((uint8_t)0x25) /* Coefficient b0 data register bits 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 510
davide.aliprandi@st.com 0:542c79e7e0ef 511 /**
davide.aliprandi@st.com 0:542c79e7e0ef 512 * @brief I2C address Coefficient write/read control register
davide.aliprandi@st.com 0:542c79e7e0ef 513 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 514 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 515 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 516 * [7:4] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 517 * 3 RA read a complete set of coefficient
davide.aliprandi@st.com 0:542c79e7e0ef 518 * 2 R1 read only one coefficient
davide.aliprandi@st.com 0:542c79e7e0ef 519 * 1 WA write a complete set of coefficient
davide.aliprandi@st.com 0:542c79e7e0ef 520 * 0 W1 write only one coefficient
davide.aliprandi@st.com 0:542c79e7e0ef 521 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 522 */
davide.aliprandi@st.com 0:542c79e7e0ef 523 #define STA350BW_CFUD ((uint8_t)0x26) /* Coefficient write/read control register */
davide.aliprandi@st.com 0:542c79e7e0ef 524
davide.aliprandi@st.com 0:542c79e7e0ef 525
davide.aliprandi@st.com 0:542c79e7e0ef 526 /**
davide.aliprandi@st.com 0:542c79e7e0ef 527 * @brief I2C address Variable max power correction 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 528 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 529 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 530 * Default value: 0x1A
davide.aliprandi@st.com 0:542c79e7e0ef 531 * [7:0] Coefficient for Variable max power correction 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 532 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 533 */
davide.aliprandi@st.com 0:542c79e7e0ef 534 #define STA350BW_MPCC1 ((uint8_t)0x27) /* Variable max power correction 15:8 register*/
davide.aliprandi@st.com 0:542c79e7e0ef 535
davide.aliprandi@st.com 0:542c79e7e0ef 536 /**
davide.aliprandi@st.com 0:542c79e7e0ef 537 * @brief I2C address Variable max power correction 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 538 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 539 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 540 * Default value: 0x30
davide.aliprandi@st.com 0:542c79e7e0ef 541 * [7:0] Coefficient for Variable max power correction 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 542 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 543 */
davide.aliprandi@st.com 0:542c79e7e0ef 544 #define STA350BW_MPCC2 ((uint8_t)0x28) /* Variable max power correction 7:0 register*/
davide.aliprandi@st.com 0:542c79e7e0ef 545
davide.aliprandi@st.com 0:542c79e7e0ef 546 /**
davide.aliprandi@st.com 0:542c79e7e0ef 547 * @brief I2C address Variable distortion compensation 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 548 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 549 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 550 * Default value: 0xF3
davide.aliprandi@st.com 0:542c79e7e0ef 551 * [7:0] Coefficient for Variable distortion compensation 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 552 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 553 */
davide.aliprandi@st.com 0:542c79e7e0ef 554 #define STA350BW_DCC1 ((uint8_t)0x29) /* Variable distortion compensation 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 555
davide.aliprandi@st.com 0:542c79e7e0ef 556 /**
davide.aliprandi@st.com 0:542c79e7e0ef 557 * @brief I2C address Variable distortion compensation 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 558 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 559 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 560 * Default value: 0x33
davide.aliprandi@st.com 0:542c79e7e0ef 561 * [7:0] Coefficient for Variable distortion compensation 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 562 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 563 */
davide.aliprandi@st.com 0:542c79e7e0ef 564 #define STA350BW_DCC2 ((uint8_t)0x2A) /* Variable distortion compensation 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 565
davide.aliprandi@st.com 0:542c79e7e0ef 566 /**
davide.aliprandi@st.com 0:542c79e7e0ef 567 * @brief I2C address Fault detect recovery constant register 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 568 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 569 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 570 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 571 * [7:0] Fault detect recovery constant 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 572 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 573 */
davide.aliprandi@st.com 0:542c79e7e0ef 574 #define STA350BW_FDRC1 ((uint8_t)0x2B) /* Fault detect recovery constant register 15:8 */
davide.aliprandi@st.com 0:542c79e7e0ef 575
davide.aliprandi@st.com 0:542c79e7e0ef 576 /**
davide.aliprandi@st.com 0:542c79e7e0ef 577 * @brief I2C address Fault detect recovery constant register 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 578 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 579 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 580 * Default value: 0xC0
davide.aliprandi@st.com 0:542c79e7e0ef 581 * [7:0] Fault detect recovery constant 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 582 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 583 */
davide.aliprandi@st.com 0:542c79e7e0ef 584 #define STA350BW_FDRC2 ((uint8_t)0x2C) /* Fault detect recovery constant register 7:0 */
davide.aliprandi@st.com 0:542c79e7e0ef 585
davide.aliprandi@st.com 0:542c79e7e0ef 586 /**
davide.aliprandi@st.com 0:542c79e7e0ef 587 * @brief I2C address Status Register
davide.aliprandi@st.com 0:542c79e7e0ef 588 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 589 * Read
davide.aliprandi@st.com 0:542c79e7e0ef 590 * Default value: 0x7F
davide.aliprandi@st.com 0:542c79e7e0ef 591 * 7 PLLUL PLL unlock
davide.aliprandi@st.com 0:542c79e7e0ef 592 * 6 FAULT Fault detected on bridge
davide.aliprandi@st.com 0:542c79e7e0ef 593 * 5 UVFAULT undervoltage fault
davide.aliprandi@st.com 0:542c79e7e0ef 594 * 4 OVFAULT overvoltage fault
davide.aliprandi@st.com 0:542c79e7e0ef 595 * 3 OCFAULT overcurrent fault
davide.aliprandi@st.com 0:542c79e7e0ef 596 * 2 OCWARN overcurrent warning
davide.aliprandi@st.com 0:542c79e7e0ef 597 * 1 TFAULT Thermal fault
davide.aliprandi@st.com 0:542c79e7e0ef 598 * 0 TWARN thermal warning
davide.aliprandi@st.com 0:542c79e7e0ef 599 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 600 */
davide.aliprandi@st.com 0:542c79e7e0ef 601 #define STA350BW_STATUS ((uint8_t)0x2D) /* Status Register */
davide.aliprandi@st.com 0:542c79e7e0ef 602
davide.aliprandi@st.com 0:542c79e7e0ef 603 /**
davide.aliprandi@st.com 0:542c79e7e0ef 604 * @brief I2C address EQ coefficients and DRC configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 605 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 606 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 607 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 608 * 7 XOB Crossover filter bypass
davide.aliprandi@st.com 0:542c79e7e0ef 609 * [6:5] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 610 * [4:3] AMGC Anti-clipping and DRC preset
davide.aliprandi@st.com 0:542c79e7e0ef 611 * 2 RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 612 * [1:0] EQ RAM bank selector
davide.aliprandi@st.com 0:542c79e7e0ef 613 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 614 */
davide.aliprandi@st.com 0:542c79e7e0ef 615 #define STA350BW_EQCFG ((uint8_t)0x31) /* EQ coefficients and DRC configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 616
davide.aliprandi@st.com 0:542c79e7e0ef 617 /**
davide.aliprandi@st.com 0:542c79e7e0ef 618 * @brief I2C address Limiter 1 extended attack threshold register
davide.aliprandi@st.com 0:542c79e7e0ef 619 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 620 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 621 * Default value: 0x30
davide.aliprandi@st.com 0:542c79e7e0ef 622 * 7 EATHEN1 Limiter 1 Extended Attack threshold enable
davide.aliprandi@st.com 0:542c79e7e0ef 623 * [6:0] EATH1 Limiter 1 Extended Attack threshold
davide.aliprandi@st.com 0:542c79e7e0ef 624 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 625 */
davide.aliprandi@st.com 0:542c79e7e0ef 626 #define STA350BW_EATH1 ((uint8_t)0x32) /* Limiter 1 extended attack threshold register */
davide.aliprandi@st.com 0:542c79e7e0ef 627
davide.aliprandi@st.com 0:542c79e7e0ef 628 /**
davide.aliprandi@st.com 0:542c79e7e0ef 629 * @brief I2C address Limiter 1 extended release threshold register
davide.aliprandi@st.com 0:542c79e7e0ef 630 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 631 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 632 * Default value: 0x30
davide.aliprandi@st.com 0:542c79e7e0ef 633 * 7 ERTHEN1 Limiter 1 Extended Release threshold enable
davide.aliprandi@st.com 0:542c79e7e0ef 634 * [6:0] ERTH1 Limiter 1 Extended Release threshold
davide.aliprandi@st.com 0:542c79e7e0ef 635 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 636 */
davide.aliprandi@st.com 0:542c79e7e0ef 637 #define STA350BW_ERTH1 ((uint8_t)0x33) /* Limiter 1 extended release threshold register */
davide.aliprandi@st.com 0:542c79e7e0ef 638
davide.aliprandi@st.com 0:542c79e7e0ef 639 /**
davide.aliprandi@st.com 0:542c79e7e0ef 640 * @brief I2C address Limiter 2 extended attack threshold register
davide.aliprandi@st.com 0:542c79e7e0ef 641 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 642 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 643 * Default value: 0x30
davide.aliprandi@st.com 0:542c79e7e0ef 644 * 7 EATHEN2 Limiter 2 Extended Attack threshold enable
davide.aliprandi@st.com 0:542c79e7e0ef 645 * [6:0] EATH2 Limiter 2 Extended Attack threshold
davide.aliprandi@st.com 0:542c79e7e0ef 646 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 647 */
davide.aliprandi@st.com 0:542c79e7e0ef 648 #define STA350BW_EATH2 ((uint8_t)0x34) /* Limiter 2 extended attack threshold register */
davide.aliprandi@st.com 0:542c79e7e0ef 649
davide.aliprandi@st.com 0:542c79e7e0ef 650 /**
davide.aliprandi@st.com 0:542c79e7e0ef 651 * @brief I2C address Limiter 2 extended release threshold register
davide.aliprandi@st.com 0:542c79e7e0ef 652 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 653 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 654 * Default value: 0x30
davide.aliprandi@st.com 0:542c79e7e0ef 655 * 7 ERTHEN2 Limiter 2 Extended Release threshold enable
davide.aliprandi@st.com 0:542c79e7e0ef 656 * [6:0] ERTH2 Limiter 2 Extended Release threshold
davide.aliprandi@st.com 0:542c79e7e0ef 657 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 658 */
davide.aliprandi@st.com 0:542c79e7e0ef 659 #define STA350BW_ERTH2 ((uint8_t)0x35) /* Limiter 2 extended release threshold register */
davide.aliprandi@st.com 0:542c79e7e0ef 660
davide.aliprandi@st.com 0:542c79e7e0ef 661 /**
davide.aliprandi@st.com 0:542c79e7e0ef 662 * @brief I2C address Extended configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 663 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 664 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 665 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 666 * [7:6] MDRC MDRC or EQ DRC selector
davide.aliprandi@st.com 0:542c79e7e0ef 667 * 5 PS48DB Extended post-scale range
davide.aliprandi@st.com 0:542c79e7e0ef 668 * 4 Extended attack rate Limiter 1
davide.aliprandi@st.com 0:542c79e7e0ef 669 * 3 Extended attack rate Limiter 2
davide.aliprandi@st.com 0:542c79e7e0ef 670 * 2 Biquad 5 enable
davide.aliprandi@st.com 0:542c79e7e0ef 671 * 1 Biquad 6 enable
davide.aliprandi@st.com 0:542c79e7e0ef 672 * 0 Biquad 7 enable
davide.aliprandi@st.com 0:542c79e7e0ef 673 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 674 */
davide.aliprandi@st.com 0:542c79e7e0ef 675 #define STA350BW_CONFX ((uint8_t)0x36) /* Extended configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 676
davide.aliprandi@st.com 0:542c79e7e0ef 677 /**
davide.aliprandi@st.com 0:542c79e7e0ef 678 * @brief I2C address soft-volume up configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 679 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 680 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 681 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 682 * [7:6] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 683 * 5 SVUPE Soft volume up enable
davide.aliprandi@st.com 0:542c79e7e0ef 684 * [4:0] SVUP Soft volume up coefficient
davide.aliprandi@st.com 0:542c79e7e0ef 685 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 686 */
davide.aliprandi@st.com 0:542c79e7e0ef 687 #define STA350BW_SVCA ((uint8_t)0x37) /* soft-volume up configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 688
davide.aliprandi@st.com 0:542c79e7e0ef 689 /**
davide.aliprandi@st.com 0:542c79e7e0ef 690 * @brief I2C address soft-volume down configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 691 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 692 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 693 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 694 * [7:6] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 695 * 5 SVDWE Soft volume down enable
davide.aliprandi@st.com 0:542c79e7e0ef 696 * [4:0] SVDW Soft volume down coefficient
davide.aliprandi@st.com 0:542c79e7e0ef 697 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 698 */
davide.aliprandi@st.com 0:542c79e7e0ef 699 #define STA350BW_SVCB ((uint8_t)0x38) /* soft-volume down configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 700
davide.aliprandi@st.com 0:542c79e7e0ef 701
davide.aliprandi@st.com 0:542c79e7e0ef 702 /**
davide.aliprandi@st.com 0:542c79e7e0ef 703 * @brief I2C address DRC RMS filter coefficient c0 23:16 register
davide.aliprandi@st.com 0:542c79e7e0ef 704 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 705 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 706 * Default value: 0x01
davide.aliprandi@st.com 0:542c79e7e0ef 707 * [7:0] R_C0 DRC RMS filter coefficient c0 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 708 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 709 */
davide.aliprandi@st.com 0:542c79e7e0ef 710 #define STA350BW_RMS0A ((uint8_t)0x39) /* DRC RMS filter coefficient c0 23:16 register */
davide.aliprandi@st.com 0:542c79e7e0ef 711
davide.aliprandi@st.com 0:542c79e7e0ef 712 /**
davide.aliprandi@st.com 0:542c79e7e0ef 713 * @brief I2C address DRC RMS filter coefficient c0 15:8 register
davide.aliprandi@st.com 0:542c79e7e0ef 714 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 715 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 716 * Default value: 0xEE
davide.aliprandi@st.com 0:542c79e7e0ef 717 * [7:0] R_C0 DRC RMS filter coefficient c0 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 718 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 719 */
davide.aliprandi@st.com 0:542c79e7e0ef 720 #define STA350BW_RMS0B ((uint8_t)0x3A) /* DRC RMS filter coefficient c0 15:8 register */
davide.aliprandi@st.com 0:542c79e7e0ef 721
davide.aliprandi@st.com 0:542c79e7e0ef 722 /**
davide.aliprandi@st.com 0:542c79e7e0ef 723 * @brief I2C address DRC RMS filter coefficient c0 7:0 register
davide.aliprandi@st.com 0:542c79e7e0ef 724 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 725 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 726 * Default value: 0xFF
davide.aliprandi@st.com 0:542c79e7e0ef 727 * [7:0] R_C0 DRC RMS filter coefficient c0 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 728 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 729 */
davide.aliprandi@st.com 0:542c79e7e0ef 730 #define STA350BW_RMS0C ((uint8_t)0x3B) /* DRC RMS filter coefficient c0 7:0 register */
davide.aliprandi@st.com 0:542c79e7e0ef 731
davide.aliprandi@st.com 0:542c79e7e0ef 732 /**
davide.aliprandi@st.com 0:542c79e7e0ef 733 * @brief I2C address DRC RMS filter coefficient c1 23:16 register
davide.aliprandi@st.com 0:542c79e7e0ef 734 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 735 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 736 * Default value: 0x7E
davide.aliprandi@st.com 0:542c79e7e0ef 737 * [7:0] R_C1 DRC RMS filter coefficient c0 23:16
davide.aliprandi@st.com 0:542c79e7e0ef 738 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 739 */
davide.aliprandi@st.com 0:542c79e7e0ef 740 #define STA350BW_RMS1A ((uint8_t)0x3C) /* DRC RMS filter coefficient c1 23:16 register */
davide.aliprandi@st.com 0:542c79e7e0ef 741
davide.aliprandi@st.com 0:542c79e7e0ef 742 /**
davide.aliprandi@st.com 0:542c79e7e0ef 743 * @brief I2C address DRC RMS filter coefficient c1 15:8 register
davide.aliprandi@st.com 0:542c79e7e0ef 744 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 745 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 746 * Default value: 0xC0
davide.aliprandi@st.com 0:542c79e7e0ef 747 * [7:0] R_C1 DRC RMS filter coefficient c1 15:8
davide.aliprandi@st.com 0:542c79e7e0ef 748 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 749 */
davide.aliprandi@st.com 0:542c79e7e0ef 750 #define STA350BW_RMS1B ((uint8_t)0x3D) /* DRC RMS filter coefficient c1 15:8 register */
davide.aliprandi@st.com 0:542c79e7e0ef 751
davide.aliprandi@st.com 0:542c79e7e0ef 752 /**
davide.aliprandi@st.com 0:542c79e7e0ef 753 * @brief I2C address DRC RMS filter coefficient c1 7:0 register
davide.aliprandi@st.com 0:542c79e7e0ef 754 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 755 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 756 * Default value: 0x26
davide.aliprandi@st.com 0:542c79e7e0ef 757 * [7:0] R_C0 DRC RMS filter coefficient c1 7:0
davide.aliprandi@st.com 0:542c79e7e0ef 758 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 759 */
davide.aliprandi@st.com 0:542c79e7e0ef 760 #define STA350BW_RMS1C ((uint8_t)0x3E) /* DRC RMS filter coefficient c1 7:0 register */
davide.aliprandi@st.com 0:542c79e7e0ef 761
davide.aliprandi@st.com 0:542c79e7e0ef 762 /**
davide.aliprandi@st.com 0:542c79e7e0ef 763 * @brief I2C address Extra volume resolution configuration register
davide.aliprandi@st.com 0:542c79e7e0ef 764 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 765 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 766 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 767 * 7 VRESEN Extra volume resolution enable
davide.aliprandi@st.com 0:542c79e7e0ef 768 * 6 VRESTG Extra volume resolution update
davide.aliprandi@st.com 0:542c79e7e0ef 769 * [5:4] C3VR Channel 3 extra volume value
davide.aliprandi@st.com 0:542c79e7e0ef 770 * [3:2] C2VR Channel 2 extra volume value
davide.aliprandi@st.com 0:542c79e7e0ef 771 * [1:0] C1VR Channel 1 extra volume value
davide.aliprandi@st.com 0:542c79e7e0ef 772 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 773 */
davide.aliprandi@st.com 0:542c79e7e0ef 774 #define STA350BW_EVOLRES ((uint8_t)0x3F) /* Extra volume resolution configuration register */
davide.aliprandi@st.com 0:542c79e7e0ef 775
davide.aliprandi@st.com 0:542c79e7e0ef 776 /**
davide.aliprandi@st.com 0:542c79e7e0ef 777 * @brief I2C address Quantization error noise correction register
davide.aliprandi@st.com 0:542c79e7e0ef 778 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 779 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 780 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 781 * 7 Quntization Noise shaping enable
davide.aliprandi@st.com 0:542c79e7e0ef 782 * 6 Quntization Noise shaping on biquad 7
davide.aliprandi@st.com 0:542c79e7e0ef 783 * 5 Quntization Noise shaping on biquad 6
davide.aliprandi@st.com 0:542c79e7e0ef 784 * 4 Quntization Noise shaping on biquad 5
davide.aliprandi@st.com 0:542c79e7e0ef 785 * 3 Quntization Noise shaping on biquad 4
davide.aliprandi@st.com 0:542c79e7e0ef 786 * 2 Quntization Noise shaping on biquad 3
davide.aliprandi@st.com 0:542c79e7e0ef 787 * 1 Quntization Noise shaping on biquad 2
davide.aliprandi@st.com 0:542c79e7e0ef 788 * 0 Quntization Noise shaping on biquad 1
davide.aliprandi@st.com 0:542c79e7e0ef 789 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 790 */
davide.aliprandi@st.com 0:542c79e7e0ef 791 #define STA350BW_NSHAPE ((uint8_t)0x48) /* Quantization error noise correction register */
davide.aliprandi@st.com 0:542c79e7e0ef 792
davide.aliprandi@st.com 0:542c79e7e0ef 793 /**
davide.aliprandi@st.com 0:542c79e7e0ef 794 * @brief I2C address Extended coefficient range up to -4...4 biquad 1-4 register
davide.aliprandi@st.com 0:542c79e7e0ef 795 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 796 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 797 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 798 * [7:6] CXTB4 Extended coefficient on biquad 4
davide.aliprandi@st.com 0:542c79e7e0ef 799 * [5:4] CXTB3 Extended coefficient on biquad 3
davide.aliprandi@st.com 0:542c79e7e0ef 800 * [3:2] CXTB2 Extended coefficient on biquad 2
davide.aliprandi@st.com 0:542c79e7e0ef 801 * [1:0] CXTB1 Extended coefficient on biquad 1
davide.aliprandi@st.com 0:542c79e7e0ef 802 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 803 */
davide.aliprandi@st.com 0:542c79e7e0ef 804 #define STA350BW_CXT_B4B1 ((uint8_t)0x49) /* Extended coefficient range up to -4...4 biquad 1-4 register */
davide.aliprandi@st.com 0:542c79e7e0ef 805
davide.aliprandi@st.com 0:542c79e7e0ef 806 /**
davide.aliprandi@st.com 0:542c79e7e0ef 807 * @brief I2C address Extended coefficient range up to -4...4 biquad 5-7 register
davide.aliprandi@st.com 0:542c79e7e0ef 808 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 809 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 810 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 811 * [7:6] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 812 * [5:4] CXTB7 Extended coefficient on biquad 7
davide.aliprandi@st.com 0:542c79e7e0ef 813 * [3:2] CXTB6 Extended coefficient on biquad 6
davide.aliprandi@st.com 0:542c79e7e0ef 814 * [1:0] CXTB5 Extended coefficient on biquad 5
davide.aliprandi@st.com 0:542c79e7e0ef 815 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 816 */
davide.aliprandi@st.com 0:542c79e7e0ef 817 #define STA350BW_CXT_B7B5 ((uint8_t)0x4A) /* Extended coefficient range up to -4...4 biquad 5-7 register */
davide.aliprandi@st.com 0:542c79e7e0ef 818
davide.aliprandi@st.com 0:542c79e7e0ef 819 /**
davide.aliprandi@st.com 0:542c79e7e0ef 820 * @brief I2C address Miscellaneous register 1
davide.aliprandi@st.com 0:542c79e7e0ef 821 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 822 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 823 * Default value: 0x04
davide.aliprandi@st.com 0:542c79e7e0ef 824 * 7 RPDNEN Rate powerdown enable
davide.aliprandi@st.com 0:542c79e7e0ef 825 * 6 NSHHPEN Noise shaping feature enable
davide.aliprandi@st.com 0:542c79e7e0ef 826 * 5 BRIDGOFF Bridge immediate OFF
davide.aliprandi@st.com 0:542c79e7e0ef 827 * [4:3] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 828 * 2 CPWMEN Channel PWM enable
davide.aliprandi@st.com 0:542c79e7e0ef 829 * [1:0] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 830 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 831 */
davide.aliprandi@st.com 0:542c79e7e0ef 832 #define STA350BW_MISC1 ((uint8_t)0x4B) /* Miscellaneous register 1 */
davide.aliprandi@st.com 0:542c79e7e0ef 833
davide.aliprandi@st.com 0:542c79e7e0ef 834 /**
davide.aliprandi@st.com 0:542c79e7e0ef 835 * @brief I2C address Miscellaneous register 2
davide.aliprandi@st.com 0:542c79e7e0ef 836 * \code
davide.aliprandi@st.com 0:542c79e7e0ef 837 * Read/write
davide.aliprandi@st.com 0:542c79e7e0ef 838 * Default value: 0x00
davide.aliprandi@st.com 0:542c79e7e0ef 839 * [7:5] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 840 * [4:2] PNDLSL Power-down delay selector
davide.aliprandi@st.com 0:542c79e7e0ef 841 * [1:0] RESERVED
davide.aliprandi@st.com 0:542c79e7e0ef 842 * \endcode
davide.aliprandi@st.com 0:542c79e7e0ef 843 */
davide.aliprandi@st.com 0:542c79e7e0ef 844 #define STA350BW_MISC2 ((uint8_t)0x4C) /* Miscellaneous register 2 */
davide.aliprandi@st.com 0:542c79e7e0ef 845
davide.aliprandi@st.com 0:542c79e7e0ef 846 /**
davide.aliprandi@st.com 0:542c79e7e0ef 847 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 848 */
davide.aliprandi@st.com 0:542c79e7e0ef 849
davide.aliprandi@st.com 0:542c79e7e0ef 850
davide.aliprandi@st.com 0:542c79e7e0ef 851
davide.aliprandi@st.com 0:542c79e7e0ef 852 /** @defgroup STA350BW_Main_parameter
davide.aliprandi@st.com 0:542c79e7e0ef 853 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 854 */
davide.aliprandi@st.com 0:542c79e7e0ef 855 #define STA350BW_EAPD_ON ((uint8_t)0x80)
davide.aliprandi@st.com 0:542c79e7e0ef 856 #define STA350BW_EAPD_OFF ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 857 #define STA350BW_PWDN_OFF ((uint8_t)0x40)
davide.aliprandi@st.com 0:542c79e7e0ef 858 #define STA350BW_PWDN_ON ((uint8_t)0x00) /* low power consumption */
davide.aliprandi@st.com 0:542c79e7e0ef 859
davide.aliprandi@st.com 0:542c79e7e0ef 860 #define STA350BW_MVOL_0dB ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 861 #define STA350BW_MVOL_MUTE ((uint8_t)0xFF)
davide.aliprandi@st.com 0:542c79e7e0ef 862 /**
davide.aliprandi@st.com 0:542c79e7e0ef 863 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 864 */
davide.aliprandi@st.com 0:542c79e7e0ef 865
davide.aliprandi@st.com 0:542c79e7e0ef 866
davide.aliprandi@st.com 0:542c79e7e0ef 867 /** @defgroup STA350BW_Input_frequency_selection
davide.aliprandi@st.com 0:542c79e7e0ef 868 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 869 */
davide.aliprandi@st.com 0:542c79e7e0ef 870 #define STA350BW_Fs_32000 ((uint32_t)32000)
davide.aliprandi@st.com 0:542c79e7e0ef 871 #define STA350BW_Fs_44100 ((uint32_t)44100)
davide.aliprandi@st.com 0:542c79e7e0ef 872 #define STA350BW_Fs_48000 ((uint32_t)48000)
davide.aliprandi@st.com 0:542c79e7e0ef 873 #define STA350BW_Fs_88200 ((uint32_t)88200)
davide.aliprandi@st.com 0:542c79e7e0ef 874 #define STA350BW_Fs_96000 ((uint32_t)96000)
davide.aliprandi@st.com 0:542c79e7e0ef 875
davide.aliprandi@st.com 0:542c79e7e0ef 876 #define STA350BW_MCLK_256_LR_48K ((uint8_t)0x03)
davide.aliprandi@st.com 0:542c79e7e0ef 877 #define STA350BW_MCLK_128_LR_48K ((uint8_t)0x04)
davide.aliprandi@st.com 0:542c79e7e0ef 878 #define STA350BW_MCLK_256_LR_96K ((uint8_t)0x09)
davide.aliprandi@st.com 0:542c79e7e0ef 879 #define STA350BW_MCLK_128_LR_96K ((uint8_t)0x0B)
davide.aliprandi@st.com 0:542c79e7e0ef 880 /**
davide.aliprandi@st.com 0:542c79e7e0ef 881 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 882 */
davide.aliprandi@st.com 0:542c79e7e0ef 883
davide.aliprandi@st.com 0:542c79e7e0ef 884
davide.aliprandi@st.com 0:542c79e7e0ef 885
davide.aliprandi@st.com 0:542c79e7e0ef 886
davide.aliprandi@st.com 0:542c79e7e0ef 887
davide.aliprandi@st.com 0:542c79e7e0ef 888 /** @defgroup STA350BW_mode_selection
davide.aliprandi@st.com 0:542c79e7e0ef 889 * @brief STA350BW mode configuration constants
davide.aliprandi@st.com 0:542c79e7e0ef 890 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 891 */
davide.aliprandi@st.com 0:542c79e7e0ef 892 #define STA350BW_STEREO_CONF ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 893 #define STA350BW_2SE_1BTL_CONF ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 894 #define STA350BW_STEREO_EXT_BRIDGE_CONF ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 895 #define STA350BW_MONOBTL_CONF ((uint8_t)0x11)
davide.aliprandi@st.com 0:542c79e7e0ef 896 #define STA350BW_BINARY_CONF ((uint8_t)0x80) /* on registers 0E, 0F, 10 */
davide.aliprandi@st.com 0:542c79e7e0ef 897 /**
davide.aliprandi@st.com 0:542c79e7e0ef 898 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 899 */
davide.aliprandi@st.com 0:542c79e7e0ef 900
davide.aliprandi@st.com 0:542c79e7e0ef 901 /** @defgroup STA350BW_DSP_option_selection
davide.aliprandi@st.com 0:542c79e7e0ef 902 * @brief STA350BW constants related to data path management
davide.aliprandi@st.com 0:542c79e7e0ef 903 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 904 */
davide.aliprandi@st.com 0:542c79e7e0ef 905 #define STA350BW_DSPB ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 906 #define STA350BW_C1EQBP ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 907 #define STA350BW_C2EQBP ((uint8_t)0x02)
davide.aliprandi@st.com 0:542c79e7e0ef 908 #define STA350BW_C1TCB ((uint8_t)0x03)
davide.aliprandi@st.com 0:542c79e7e0ef 909 #define STA350BW_C2TCB ((uint8_t)0x04)
davide.aliprandi@st.com 0:542c79e7e0ef 910 #define STA350BW_C1VBP ((uint8_t)0x05)
davide.aliprandi@st.com 0:542c79e7e0ef 911 #define STA350BW_C2VBP ((uint8_t)0x06)
davide.aliprandi@st.com 0:542c79e7e0ef 912 #define STA350BW_HPB ((uint8_t)0x07)
davide.aliprandi@st.com 0:542c79e7e0ef 913 #define STA350BW_DEMP ((uint8_t)0x08)
davide.aliprandi@st.com 0:542c79e7e0ef 914 #define STA350BW_BQL ((uint8_t)0x09)
davide.aliprandi@st.com 0:542c79e7e0ef 915 #define STA350BW_BQ5 ((uint8_t)0x0A)
davide.aliprandi@st.com 0:542c79e7e0ef 916 #define STA350BW_BQ6 ((uint8_t)0x0B)
davide.aliprandi@st.com 0:542c79e7e0ef 917 #define STA350BW_BQ7 ((uint8_t)0x0C)
davide.aliprandi@st.com 0:542c79e7e0ef 918 #define STA350BW_EXT_RANGE_BQ1 ((uint8_t)0x0D)
davide.aliprandi@st.com 0:542c79e7e0ef 919 #define STA350BW_EXT_RANGE_BQ2 ((uint8_t)0x0E)
davide.aliprandi@st.com 0:542c79e7e0ef 920 #define STA350BW_EXT_RANGE_BQ3 ((uint8_t)0x0F)
davide.aliprandi@st.com 0:542c79e7e0ef 921 #define STA350BW_EXT_RANGE_BQ4 ((uint8_t)0x10)
davide.aliprandi@st.com 0:542c79e7e0ef 922 #define STA350BW_EXT_RANGE_BQ5 ((uint8_t)0x11)
davide.aliprandi@st.com 0:542c79e7e0ef 923 #define STA350BW_EXT_RANGE_BQ6 ((uint8_t)0x12)
davide.aliprandi@st.com 0:542c79e7e0ef 924 #define STA350BW_EXT_RANGE_BQ7 ((uint8_t)0x13)
davide.aliprandi@st.com 0:542c79e7e0ef 925 #define STA350BW_RAM_BANK_SELECT ((uint8_t)0x14)
davide.aliprandi@st.com 0:542c79e7e0ef 926 /**
davide.aliprandi@st.com 0:542c79e7e0ef 927 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 928 */
davide.aliprandi@st.com 0:542c79e7e0ef 929
davide.aliprandi@st.com 0:542c79e7e0ef 930
davide.aliprandi@st.com 0:542c79e7e0ef 931
davide.aliprandi@st.com 0:542c79e7e0ef 932 #define STA350BW_ERROR ((int32_t)-1)
davide.aliprandi@st.com 0:542c79e7e0ef 933 #define STA350BW_OK ((int32_t)0)
davide.aliprandi@st.com 0:542c79e7e0ef 934
davide.aliprandi@st.com 0:542c79e7e0ef 935
davide.aliprandi@st.com 0:542c79e7e0ef 936 /** @defgroup STA350BW_state_define STA350BW state define
davide.aliprandi@st.com 0:542c79e7e0ef 937 * @brief STA350BW state definitions
davide.aliprandi@st.com 0:542c79e7e0ef 938 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 939 */
davide.aliprandi@st.com 0:542c79e7e0ef 940 #define STA350BW_ENABLE ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 941 #define STA350BW_DISABLE ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 942 #define STA350BW_RANGE_ONE ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 943 #define STA350BW_RANGE_TWO ((uint8_t)0x02)
davide.aliprandi@st.com 0:542c79e7e0ef 944 #define STA350BW_RANGE_FOUR ((uint8_t)0x04)
davide.aliprandi@st.com 0:542c79e7e0ef 945 /**
davide.aliprandi@st.com 0:542c79e7e0ef 946 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 947 */
davide.aliprandi@st.com 0:542c79e7e0ef 948
davide.aliprandi@st.com 0:542c79e7e0ef 949 /** @defgroup STA350BW_channel_define STA350BW channel define
davide.aliprandi@st.com 0:542c79e7e0ef 950 * @brief STA350BW channels definitions
davide.aliprandi@st.com 0:542c79e7e0ef 951 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 952 */
davide.aliprandi@st.com 0:542c79e7e0ef 953 #define STA350BW_CHANNEL_MASTER ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 954 #define STA350BW_CHANNEL_1 ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 955 #define STA350BW_CHANNEL_2 ((uint8_t)0x02)
davide.aliprandi@st.com 0:542c79e7e0ef 956 #define STA350BW_CHANNEL_3 ((uint8_t)0x03)
davide.aliprandi@st.com 0:542c79e7e0ef 957 /**
davide.aliprandi@st.com 0:542c79e7e0ef 958 * @}
davide.aliprandi@st.com 0:542c79e7e0ef 959 */
davide.aliprandi@st.com 0:542c79e7e0ef 960
davide.aliprandi@st.com 0:542c79e7e0ef 961 /** @defgroup STA350BW_channel_define STA350BW Biq define
davide.aliprandi@st.com 0:542c79e7e0ef 962 * @brief STA350BW Biq definitions
davide.aliprandi@st.com 0:542c79e7e0ef 963 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 964 */
davide.aliprandi@st.com 0:542c79e7e0ef 965 #define STA350BW_RAM_BANK_FIRST ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 966 #define STA350BW_RAM_BANK_SECOND ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 967 #define STA350BW_RAM_BANK_THIRD ((uint8_t)0x02)
davide.aliprandi@st.com 0:542c79e7e0ef 968 #define STA350BW_CH1_BQ1 ((uint8_t)0x00)
davide.aliprandi@st.com 0:542c79e7e0ef 969 #define STA350BW_CH1_BQ2 ((uint8_t)0x01)
davide.aliprandi@st.com 0:542c79e7e0ef 970 #define STA350BW_CH1_BQ3 ((uint8_t)0x02)
davide.aliprandi@st.com 0:542c79e7e0ef 971 #define STA350BW_CH1_BQ4 ((uint8_t)0x03)
davide.aliprandi@st.com 0:542c79e7e0ef 972 #define STA350BW_CH2_BQ1 ((uint8_t)0x04)
davide.aliprandi@st.com 0:542c79e7e0ef 973 #define STA350BW_CH2_BQ2 ((uint8_t)0x05)
davide.aliprandi@st.com 0:542c79e7e0ef 974 #define STA350BW_CH2_BQ3 ((uint8_t)0x06)
davide.aliprandi@st.com 0:542c79e7e0ef 975 #define STA350BW_CH2_BQ4 ((uint8_t)0x07)
davide.aliprandi@st.com 0:542c79e7e0ef 976
davide.aliprandi@st.com 0:542c79e7e0ef 977 /** @defgroup STA350BW_adsress_define STA350BW address define
davide.aliprandi@st.com 0:542c79e7e0ef 978 * @brief STA350BW address definitions
davide.aliprandi@st.com 0:542c79e7e0ef 979 * @{
davide.aliprandi@st.com 0:542c79e7e0ef 980 */
davide.aliprandi@st.com 0:542c79e7e0ef 981 #define STA350BW_ADDRESS_1 ((uint8_t)0x38) /* To be used when using I2S1. */
davide.aliprandi@st.com 0:542c79e7e0ef 982 #define STA350BW_ADDRESS_2 ((uint8_t)0x3A) /* To be used when using I2S2. */
davide.aliprandi@st.com 0:542c79e7e0ef 983
davide.aliprandi@st.com 0:542c79e7e0ef 984 /* Audio processor initialization structure. */
davide.aliprandi@st.com 0:542c79e7e0ef 985 typedef struct
davide.aliprandi@st.com 0:542c79e7e0ef 986 {
davide.aliprandi@st.com 0:542c79e7e0ef 987 uint32_t frequency; /* Allowed frequency: 32000, 44100, 48000, 88200, 96000. */
davide.aliprandi@st.com 0:542c79e7e0ef 988 uint16_t volume; /* Allowed volume: [0..128]. */
davide.aliprandi@st.com 0:542c79e7e0ef 989 } STA350BW_Init_t;
davide.aliprandi@st.com 0:542c79e7e0ef 990
davide.aliprandi@st.com 0:542c79e7e0ef 991 /* Audio processor extern functions. */
davide.aliprandi@st.com 0:542c79e7e0ef 992 extern uint8_t STA350BW_IO_Init(void);
davide.aliprandi@st.com 0:542c79e7e0ef 993 extern uint8_t STA350BW_IO_Read(uint8_t reg, uint8_t *value);
davide.aliprandi@st.com 0:542c79e7e0ef 994 extern uint8_t STA350BW_IO_Write(uint8_t reg, uint8_t value);
davide.aliprandi@st.com 0:542c79e7e0ef 995 extern uint8_t STA350BW_IO_ReadMulti(uint8_t *pBuffer, uint8_t reg, uint16_t length);
davide.aliprandi@st.com 0:542c79e7e0ef 996 extern uint8_t STA350BW_IO_WriteMulti(uint8_t *pBuffer, uint8_t reg, uint16_t length);
davide.aliprandi@st.com 0:542c79e7e0ef 997 extern uint8_t STA350BW_IO_Delay(uint32_t delay_ms);
davide.aliprandi@st.com 0:542c79e7e0ef 998
davide.aliprandi@st.com 0:542c79e7e0ef 999 #ifdef __cplusplus
davide.aliprandi@st.com 0:542c79e7e0ef 1000 }
davide.aliprandi@st.com 0:542c79e7e0ef 1001 #endif
davide.aliprandi@st.com 0:542c79e7e0ef 1002
davide.aliprandi@st.com 0:542c79e7e0ef 1003 #endif /*__STA350BW_H*/
davide.aliprandi@st.com 0:542c79e7e0ef 1004
davide.aliprandi@st.com 0:542c79e7e0ef 1005 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/