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LSM6DSOX
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
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lsm6dsox_reg.h
00001 /* 00002 ****************************************************************************** 00003 * @file lsm6dsox_reg.h 00004 * @author Sensors Software Solution Team 00005 * @brief This file contains all the functions prototypes for the 00006 * lsm6dsox_reg.c driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 00011 * All rights reserved.</center></h2> 00012 * 00013 * This software component is licensed by ST under BSD 3-Clause license, 00014 * the "License"; You may not use this file except in compliance with the 00015 * License. You may obtain a copy of the License at: 00016 * opensource.org/licenses/BSD-3-Clause 00017 * 00018 ****************************************************************************** 00019 */ 00020 00021 /* Define to prevent recursive inclusion -------------------------------------*/ 00022 #ifndef LSM6DSOX_REGS_H 00023 #define LSM6DSOX_REGS_H 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include <stdint.h> 00031 #include <stddef.h> 00032 #include <math.h> 00033 00034 /** @addtogroup LSM6DSOX 00035 * @{ 00036 * 00037 */ 00038 00039 /** @defgroup STMicroelectronics sensors common types 00040 * @{ 00041 * 00042 */ 00043 00044 #ifndef MEMS_SHARED_TYPES 00045 #define MEMS_SHARED_TYPES 00046 00047 /** 00048 * @defgroup axisXbitXX_t 00049 * @brief These unions are useful to represent different sensors data type. 00050 * These unions are not need by the driver. 00051 * 00052 * REMOVING the unions you are compliant with: 00053 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 00054 * 00055 * @{ 00056 * 00057 */ 00058 00059 typedef union { 00060 int16_t i16bit[3]; 00061 uint8_t u8bit[6]; 00062 } axis3bit16_t; 00063 00064 typedef union { 00065 int16_t i16bit; 00066 uint8_t u8bit[2]; 00067 } axis1bit16_t; 00068 00069 typedef union { 00070 int32_t i32bit[3]; 00071 uint8_t u8bit[12]; 00072 } axis3bit32_t; 00073 00074 typedef union { 00075 int32_t i32bit; 00076 uint8_t u8bit[4]; 00077 } axis1bit32_t; 00078 00079 /** 00080 * @} 00081 * 00082 */ 00083 00084 typedef struct { 00085 uint8_t bit0 : 1; 00086 uint8_t bit1 : 1; 00087 uint8_t bit2 : 1; 00088 uint8_t bit3 : 1; 00089 uint8_t bit4 : 1; 00090 uint8_t bit5 : 1; 00091 uint8_t bit6 : 1; 00092 uint8_t bit7 : 1; 00093 } bitwise_t; 00094 00095 #define PROPERTY_DISABLE (0U) 00096 #define PROPERTY_ENABLE (1U) 00097 00098 #endif /* MEMS_SHARED_TYPES */ 00099 00100 #ifndef MEMS_UCF_SHARED_TYPES 00101 #define MEMS_UCF_SHARED_TYPES 00102 00103 /** @defgroup Generic address-data structure definition 00104 * @brief This structure is useful to load a predefined configuration 00105 * of a sensor. 00106 * You can create a sensor configuration by your own or using 00107 * Unico / Unicleo tools available on STMicroelectronics 00108 * web site. 00109 * 00110 * @{ 00111 * 00112 */ 00113 00114 typedef struct { 00115 uint8_t address; 00116 uint8_t data; 00117 } ucf_line_t; 00118 00119 /** 00120 * @} 00121 * 00122 */ 00123 00124 #endif /* MEMS_UCF_SHARED_TYPES */ 00125 00126 /** 00127 * @} 00128 * 00129 */ 00130 00131 /** @addtogroup LSM6DSOX_Interfaces_Functions 00132 * @brief This section provide a set of functions used to read and 00133 * write a generic register of the device. 00134 * MANDATORY: return 0 -> no Error. 00135 * @{ 00136 * 00137 */ 00138 00139 typedef int32_t (*lsm6dsox_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); 00140 typedef int32_t (*lsm6dsox_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 00141 00142 typedef struct { 00143 /** Component mandatory fields **/ 00144 lsm6dsox_write_ptr write_reg; 00145 lsm6dsox_read_ptr read_reg; 00146 /** Customizable optional pointer **/ 00147 void *handle; 00148 } lsm6dsox_ctx_t; 00149 00150 /** 00151 * @} 00152 * 00153 */ 00154 00155 /** @defgroup LSM6DSOX_Infos 00156 * @{ 00157 * 00158 */ 00159 00160 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 00161 #define LSM6DSOX_I2C_ADD_L 0xD5U 00162 #define LSM6DSOX_I2C_ADD_H 0xD7U 00163 00164 /** Device Identification (Who am I) **/ 00165 #define LSM6DSOX_ID 0x6CU 00166 00167 /** 00168 * @} 00169 * 00170 */ 00171 00172 #define LSM6DSOX_FUNC_CFG_ACCESS 0x01U 00173 typedef struct { 00174 uint8_t ois_ctrl_from_ui : 1; 00175 uint8_t not_used_01 : 5; 00176 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 00177 } lsm6dsox_func_cfg_access_t; 00178 00179 #define LSM6DSOX_PIN_CTRL 0x02U 00180 typedef struct { 00181 uint8_t not_used_01 : 6; 00182 uint8_t sdo_pu_en : 1; 00183 uint8_t ois_pu_dis : 1; 00184 } lsm6dsox_pin_ctrl_t; 00185 00186 #define LSM6DSOX_S4S_TPH_L 0x04U 00187 typedef struct { 00188 uint8_t tph_l : 7; 00189 uint8_t tph_h_sel : 1; 00190 } lsm6dsox_s4s_tph_l_t; 00191 00192 #define LSM6DSOX_S4S_TPH_H 0x05U 00193 typedef struct { 00194 uint8_t tph_h : 8; 00195 } lsm6dsox_s4s_tph_h_t; 00196 00197 #define LSM6DSOX_S4S_RR 0x06U 00198 typedef struct { 00199 uint8_t rr : 2; 00200 uint8_t not_used_01 : 6; 00201 } lsm6dsox_s4s_rr_t; 00202 00203 #define LSM6DSOX_FIFO_CTRL1 0x07U 00204 typedef struct { 00205 uint8_t wtm : 8; 00206 } lsm6dsox_fifo_ctrl1_t; 00207 00208 #define LSM6DSOX_FIFO_CTRL2 0x08U 00209 typedef struct { 00210 uint8_t wtm : 1; 00211 uint8_t uncoptr_rate : 2; 00212 uint8_t not_used_01 : 1; 00213 uint8_t odrchg_en : 1; 00214 uint8_t not_used_02 : 1; 00215 uint8_t fifo_compr_rt_en : 1; 00216 uint8_t stop_on_wtm : 1; 00217 } lsm6dsox_fifo_ctrl2_t; 00218 00219 #define LSM6DSOX_FIFO_CTRL3 0x09U 00220 typedef struct { 00221 uint8_t bdr_xl : 4; 00222 uint8_t bdr_gy : 4; 00223 } lsm6dsox_fifo_ctrl3_t; 00224 00225 #define LSM6DSOX_FIFO_CTRL4 0x0AU 00226 typedef struct { 00227 uint8_t fifo_mode : 3; 00228 uint8_t not_used_01 : 1; 00229 uint8_t odr_t_batch : 2; 00230 uint8_t odr_ts_batch : 2; 00231 } lsm6dsox_fifo_ctrl4_t; 00232 00233 #define LSM6DSOX_COUNTER_BDR_REG1 0x0BU 00234 typedef struct { 00235 uint8_t cnt_bdr_th : 3; 00236 uint8_t not_used_01 : 2; 00237 uint8_t trig_counter_bdr : 1; 00238 uint8_t rst_counter_bdr : 1; 00239 uint8_t dataready_pulsed : 1; 00240 } lsm6dsox_counter_bdr_reg1_t; 00241 00242 #define LSM6DSOX_COUNTER_BDR_REG2 0x0CU 00243 typedef struct { 00244 uint8_t cnt_bdr_th : 8; 00245 } lsm6dsox_counter_bdr_reg2_t; 00246 00247 #define LSM6DSOX_INT1_CTRL 0x0D 00248 typedef struct { 00249 uint8_t int1_drdy_xl : 1; 00250 uint8_t int1_drdy_g : 1; 00251 uint8_t int1_boot : 1; 00252 uint8_t int1_fifo_th : 1; 00253 uint8_t int1_fifo_ovr : 1; 00254 uint8_t int1_fifo_full : 1; 00255 uint8_t int1_cnt_bdr : 1; 00256 uint8_t den_drdy_flag : 1; 00257 } lsm6dsox_int1_ctrl_t; 00258 00259 #define LSM6DSOX_INT2_CTRL 0x0EU 00260 typedef struct { 00261 uint8_t int2_drdy_xl : 1; 00262 uint8_t int2_drdy_g : 1; 00263 uint8_t int2_drdy_temp : 1; 00264 uint8_t int2_fifo_th : 1; 00265 uint8_t int2_fifo_ovr : 1; 00266 uint8_t int2_fifo_full : 1; 00267 uint8_t int2_cnt_bdr : 1; 00268 uint8_t not_used_01 : 1; 00269 } lsm6dsox_int2_ctrl_t; 00270 00271 #define LSM6DSOX_WHO_AM_I 0x0FU 00272 #define LSM6DSOX_CTRL1_XL 0x10U 00273 typedef struct { 00274 uint8_t not_used_01 : 1; 00275 uint8_t lpf2_xl_en : 1; 00276 uint8_t fs_xl : 2; 00277 uint8_t odr_xl : 4; 00278 } lsm6dsox_ctrl1_xl_t; 00279 00280 #define LSM6DSOX_CTRL2_G 0x11U 00281 typedef struct { 00282 uint8_t not_used_01 : 1; 00283 uint8_t fs_g : 3; /* fs_125 + fs_g */ 00284 uint8_t odr_g : 4; 00285 } lsm6dsox_ctrl2_g_t; 00286 00287 #define LSM6DSOX_CTRL3_C 0x12U 00288 typedef struct { 00289 uint8_t sw_reset : 1; 00290 uint8_t not_used_01 : 1; 00291 uint8_t if_inc : 1; 00292 uint8_t sim : 1; 00293 uint8_t pp_od : 1; 00294 uint8_t h_lactive : 1; 00295 uint8_t bdu : 1; 00296 uint8_t boot : 1; 00297 } lsm6dsox_ctrl3_c_t; 00298 00299 #define LSM6DSOX_CTRL4_C 0x13U 00300 typedef struct { 00301 uint8_t not_used_01 : 1; 00302 uint8_t lpf1_sel_g : 1; 00303 uint8_t i2c_disable : 1; 00304 uint8_t drdy_mask : 1; 00305 uint8_t not_used_02 : 1; 00306 uint8_t int2_on_int1 : 1; 00307 uint8_t sleep_g : 1; 00308 uint8_t not_used_03 : 1; 00309 } lsm6dsox_ctrl4_c_t; 00310 00311 #define LSM6DSOX_CTRL5_C 0x14U 00312 typedef struct { 00313 uint8_t st_xl : 2; 00314 uint8_t st_g : 2; 00315 uint8_t rounding_status : 1; 00316 uint8_t rounding : 2; 00317 uint8_t xl_ulp_en : 1; 00318 } lsm6dsox_ctrl5_c_t; 00319 00320 #define LSM6DSOX_CTRL6_C 0x15U 00321 typedef struct { 00322 uint8_t ftype : 3; 00323 uint8_t usr_off_w : 1; 00324 uint8_t xl_hm_mode : 1; 00325 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 00326 } lsm6dsox_ctrl6_c_t; 00327 00328 #define LSM6DSOX_CTRL7_G 0x16U 00329 typedef struct { 00330 uint8_t ois_on : 1; 00331 uint8_t usr_off_on_out : 1; 00332 uint8_t ois_on_en : 1; 00333 uint8_t not_used_01 : 1; 00334 uint8_t hpm_g : 2; 00335 uint8_t hp_en_g : 1; 00336 uint8_t g_hm_mode : 1; 00337 } lsm6dsox_ctrl7_g_t; 00338 00339 #define LSM6DSOX_CTRL8_XL 0x17U 00340 typedef struct { 00341 uint8_t low_pass_on_6d : 1; 00342 uint8_t xl_fs_mode : 1; 00343 uint8_t hp_slope_xl_en : 1; 00344 uint8_t fastsettl_mode_xl : 1; 00345 uint8_t hp_ref_mode_xl : 1; 00346 uint8_t hpcf_xl : 3; 00347 } lsm6dsox_ctrl8_xl_t; 00348 00349 #define LSM6DSOX_CTRL9_XL 0x18U 00350 typedef struct { 00351 uint8_t not_used_01 : 1; 00352 uint8_t i3c_disable : 1; 00353 uint8_t den_lh : 1; 00354 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 00355 uint8_t den_z : 1; 00356 uint8_t den_y : 1; 00357 uint8_t den_x : 1; 00358 } lsm6dsox_ctrl9_xl_t; 00359 00360 #define LSM6DSOX_CTRL10_C 0x19U 00361 typedef struct { 00362 uint8_t not_used_01 : 5; 00363 uint8_t timestamp_en : 1; 00364 uint8_t not_used_02 : 2; 00365 } lsm6dsox_ctrl10_c_t; 00366 00367 #define LSM6DSOX_ALL_INT_SRC 0x1AU 00368 typedef struct { 00369 uint8_t ff_ia : 1; 00370 uint8_t wu_ia : 1; 00371 uint8_t single_tap : 1; 00372 uint8_t double_tap : 1; 00373 uint8_t d6d_ia : 1; 00374 uint8_t sleep_change_ia : 1; 00375 uint8_t not_used_01 : 1; 00376 uint8_t timestamp_endcount : 1; 00377 } lsm6dsox_all_int_src_t; 00378 00379 #define LSM6DSOX_WAKE_UP_SRC 0x1BU 00380 typedef struct { 00381 uint8_t z_wu : 1; 00382 uint8_t y_wu : 1; 00383 uint8_t x_wu : 1; 00384 uint8_t wu_ia : 1; 00385 uint8_t sleep_state : 1; 00386 uint8_t ff_ia : 1; 00387 uint8_t sleep_change_ia : 2; 00388 } lsm6dsox_wake_up_src_t; 00389 00390 #define LSM6DSOX_TAP_SRC 0x1CU 00391 typedef struct { 00392 uint8_t z_tap : 1; 00393 uint8_t y_tap : 1; 00394 uint8_t x_tap : 1; 00395 uint8_t tap_sign : 1; 00396 uint8_t double_tap : 1; 00397 uint8_t single_tap : 1; 00398 uint8_t tap_ia : 1; 00399 uint8_t not_used_02 : 1; 00400 } lsm6dsox_tap_src_t; 00401 00402 #define LSM6DSOX_D6D_SRC 0x1DU 00403 typedef struct { 00404 uint8_t xl : 1; 00405 uint8_t xh : 1; 00406 uint8_t yl : 1; 00407 uint8_t yh : 1; 00408 uint8_t zl : 1; 00409 uint8_t zh : 1; 00410 uint8_t d6d_ia : 1; 00411 uint8_t den_drdy : 1; 00412 } lsm6dsox_d6d_src_t; 00413 00414 #define LSM6DSOX_STATUS_REG 0x1EU 00415 typedef struct { 00416 uint8_t xlda : 1; 00417 uint8_t gda : 1; 00418 uint8_t tda : 1; 00419 uint8_t not_used_01 : 5; 00420 } lsm6dsox_status_reg_t; 00421 00422 #define LSM6DSOX_OUT_TEMP_L 0x20U 00423 #define LSM6DSOX_OUT_TEMP_H 0x21U 00424 #define LSM6DSOX_OUTX_L_G 0x22U 00425 #define LSM6DSOX_OUTX_H_G 0x23U 00426 #define LSM6DSOX_OUTY_L_G 0x24U 00427 #define LSM6DSOX_OUTY_H_G 0x25U 00428 #define LSM6DSOX_OUTZ_L_G 0x26U 00429 #define LSM6DSOX_OUTZ_H_G 0x27U 00430 #define LSM6DSOX_OUTX_L_A 0x28U 00431 #define LSM6DSOX_OUTX_H_A 0x29U 00432 #define LSM6DSOX_OUTY_L_A 0x2AU 00433 #define LSM6DSOX_OUTY_H_A 0x2BU 00434 #define LSM6DSOX_OUTZ_L_A 0x2CU 00435 #define LSM6DSOX_OUTZ_H_A 0x2DU 00436 #define LSM6DSOX_EMB_FUNC_STATUS_MAINPAGE 0x35U 00437 typedef struct { 00438 uint8_t not_used_01 : 3; 00439 uint8_t is_step_det : 1; 00440 uint8_t is_tilt : 1; 00441 uint8_t is_sigmot : 1; 00442 uint8_t not_used_02 : 1; 00443 uint8_t is_fsm_lc : 1; 00444 } lsm6dsox_emb_func_status_mainpage_t; 00445 00446 #define LSM6DSOX_FSM_STATUS_A_MAINPAGE 0x36U 00447 typedef struct { 00448 uint8_t is_fsm1 : 1; 00449 uint8_t is_fsm2 : 1; 00450 uint8_t is_fsm3 : 1; 00451 uint8_t is_fsm4 : 1; 00452 uint8_t is_fsm5 : 1; 00453 uint8_t is_fsm6 : 1; 00454 uint8_t is_fsm7 : 1; 00455 uint8_t is_fsm8 : 1; 00456 } lsm6dsox_fsm_status_a_mainpage_t; 00457 00458 #define LSM6DSOX_FSM_STATUS_B_MAINPAGE 0x37U 00459 typedef struct { 00460 uint8_t is_fsm9 : 1; 00461 uint8_t is_fsm10 : 1; 00462 uint8_t is_fsm11 : 1; 00463 uint8_t is_fsm12 : 1; 00464 uint8_t is_fsm13 : 1; 00465 uint8_t is_fsm14 : 1; 00466 uint8_t is_fsm15 : 1; 00467 uint8_t is_fsm16 : 1; 00468 } lsm6dsox_fsm_status_b_mainpage_t; 00469 00470 #define LSM6DSOX_MLC_STATUS_MAINPAGE 0x38U 00471 typedef struct { 00472 uint8_t is_mlc1 : 1; 00473 uint8_t is_mlc2 : 1; 00474 uint8_t is_mlc3 : 1; 00475 uint8_t is_mlc4 : 1; 00476 uint8_t is_mlc5 : 1; 00477 uint8_t is_mlc6 : 1; 00478 uint8_t is_mlc7 : 1; 00479 uint8_t is_mlc8 : 1; 00480 } lsm6dsox_mlc_status_mainpage_t; 00481 00482 #define LSM6DSOX_STATUS_MASTER_MAINPAGE 0x39U 00483 typedef struct { 00484 uint8_t sens_hub_endop : 1; 00485 uint8_t not_used_01 : 2; 00486 uint8_t slave0_nack : 1; 00487 uint8_t slave1_nack : 1; 00488 uint8_t slave2_nack : 1; 00489 uint8_t slave3_nack : 1; 00490 uint8_t wr_once_done : 1; 00491 } lsm6dsox_status_master_mainpage_t; 00492 00493 #define LSM6DSOX_FIFO_STATUS1 0x3AU 00494 typedef struct { 00495 uint8_t diff_fifo : 8; 00496 } lsm6dsox_fifo_status1_t; 00497 00498 #define LSM6DSOX_FIFO_STATUS2 0x3B 00499 typedef struct { 00500 uint8_t diff_fifo : 2; 00501 uint8_t not_used_01 : 1; 00502 uint8_t over_run_latched : 1; 00503 uint8_t counter_bdr_ia : 1; 00504 uint8_t fifo_full_ia : 1; 00505 uint8_t fifo_ovr_ia : 1; 00506 uint8_t fifo_wtm_ia : 1; 00507 } lsm6dsox_fifo_status2_t; 00508 00509 #define LSM6DSOX_TIMESTAMP0 0x40U 00510 #define LSM6DSOX_TIMESTAMP1 0x41U 00511 #define LSM6DSOX_TIMESTAMP2 0x42U 00512 #define LSM6DSOX_TIMESTAMP3 0x43U 00513 #define LSM6DSOX_UI_STATUS_REG_OIS 0x49U 00514 typedef struct { 00515 uint8_t xlda : 1; 00516 uint8_t gda : 1; 00517 uint8_t gyro_settling : 1; 00518 uint8_t not_used_01 : 5; 00519 } lsm6dsox_ui_status_reg_ois_t; 00520 00521 #define LSM6DSOX_UI_OUTX_L_G_OIS 0x4AU 00522 #define LSM6DSOX_UI_OUTX_H_G_OIS 0x4BU 00523 #define LSM6DSOX_UI_OUTY_L_G_OIS 0x4CU 00524 #define LSM6DSOX_UI_OUTY_H_G_OIS 0x4DU 00525 #define LSM6DSOX_UI_OUTZ_L_G_OIS 0x4EU 00526 #define LSM6DSOX_UI_OUTZ_H_G_OIS 0x4FU 00527 #define LSM6DSOX_UI_OUTX_L_A_OIS 0x50U 00528 #define LSM6DSOX_UI_OUTX_H_A_OIS 0x51U 00529 #define LSM6DSOX_UI_OUTY_L_A_OIS 0x52U 00530 #define LSM6DSOX_UI_OUTY_H_A_OIS 0x53U 00531 #define LSM6DSOX_UI_OUTZ_L_A_OIS 0x54U 00532 #define LSM6DSOX_UI_OUTZ_H_A_OIS 0x55U 00533 00534 #define LSM6DSOX_TAP_CFG0 0x56U 00535 typedef struct { 00536 uint8_t lir : 1; 00537 uint8_t tap_z_en : 1; 00538 uint8_t tap_y_en : 1; 00539 uint8_t tap_x_en : 1; 00540 uint8_t slope_fds : 1; 00541 uint8_t sleep_status_on_int : 1; 00542 uint8_t int_clr_on_read : 1; 00543 uint8_t not_used_01 : 1; 00544 } lsm6dsox_tap_cfg0_t; 00545 00546 #define LSM6DSOX_TAP_CFG1 0x57U 00547 typedef struct { 00548 uint8_t tap_ths_x : 5; 00549 uint8_t tap_priority : 3; 00550 } lsm6dsox_tap_cfg1_t; 00551 00552 #define LSM6DSOX_TAP_CFG2 0x58U 00553 typedef struct { 00554 uint8_t tap_ths_y : 5; 00555 uint8_t inact_en : 2; 00556 uint8_t interrupts_enable : 1; 00557 } lsm6dsox_tap_cfg2_t; 00558 00559 #define LSM6DSOX_TAP_THS_6D 0x59U 00560 typedef struct { 00561 uint8_t tap_ths_z : 5; 00562 uint8_t sixd_ths : 2; 00563 uint8_t d4d_en : 1; 00564 } lsm6dsox_tap_ths_6d_t; 00565 00566 #define LSM6DSOX_INT_DUR2 0x5AU 00567 typedef struct { 00568 uint8_t shock : 2; 00569 uint8_t quiet : 2; 00570 uint8_t dur : 4; 00571 } lsm6dsox_int_dur2_t; 00572 00573 #define LSM6DSOX_WAKE_UP_THS 0x5BU 00574 typedef struct { 00575 uint8_t wk_ths : 6; 00576 uint8_t usr_off_on_wu : 1; 00577 uint8_t single_double_tap : 1; 00578 } lsm6dsox_wake_up_ths_t; 00579 00580 #define LSM6DSOX_WAKE_UP_DUR 0x5CU 00581 typedef struct { 00582 uint8_t sleep_dur : 4; 00583 uint8_t wake_ths_w : 1; 00584 uint8_t wake_dur : 2; 00585 uint8_t ff_dur : 1; 00586 } lsm6dsox_wake_up_dur_t; 00587 00588 #define LSM6DSOX_FREE_FALL 0x5DU 00589 typedef struct { 00590 uint8_t ff_ths : 3; 00591 uint8_t ff_dur : 5; 00592 } lsm6dsox_free_fall_t; 00593 00594 #define LSM6DSOX_MD1_CFG 0x5EU 00595 typedef struct { 00596 uint8_t int1_shub : 1; 00597 uint8_t int1_emb_func : 1; 00598 uint8_t int1_6d : 1; 00599 uint8_t int1_double_tap : 1; 00600 uint8_t int1_ff : 1; 00601 uint8_t int1_wu : 1; 00602 uint8_t int1_single_tap : 1; 00603 uint8_t int1_sleep_change : 1; 00604 } lsm6dsox_md1_cfg_t; 00605 00606 #define LSM6DSOX_MD2_CFG 0x5FU 00607 typedef struct { 00608 uint8_t int2_timestamp : 1; 00609 uint8_t int2_emb_func : 1; 00610 uint8_t int2_6d : 1; 00611 uint8_t int2_double_tap : 1; 00612 uint8_t int2_ff : 1; 00613 uint8_t int2_wu : 1; 00614 uint8_t int2_single_tap : 1; 00615 uint8_t int2_sleep_change : 1; 00616 } lsm6dsox_md2_cfg_t; 00617 00618 #define LSM6DSOX_S4S_ST_CMD_CODE 0x60U 00619 typedef struct { 00620 uint8_t s4s_st_cmd_code : 8; 00621 } lsm6dsox_s4s_st_cmd_code_t; 00622 00623 #define LSM6DSOX_S4S_DT_REG 0x61U 00624 typedef struct { 00625 uint8_t dt : 8; 00626 } lsm6dsox_s4s_dt_reg_t; 00627 00628 #define LSM6DSOX_I3C_BUS_AVB 0x62U 00629 typedef struct { 00630 uint8_t pd_dis_int1 : 1; 00631 uint8_t not_used_01 : 2; 00632 uint8_t i3c_bus_avb_sel : 2; 00633 uint8_t not_used_02 : 3; 00634 } lsm6dsox_i3c_bus_avb_t; 00635 00636 #define LSM6DSOX_INTERNAL_FREQ_FINE 0x63U 00637 typedef struct { 00638 uint8_t freq_fine : 8; 00639 } lsm6dsox_internal_freq_fine_t; 00640 00641 #define LSM6DSOX_UI_INT_OIS 0x6F 00642 typedef struct { 00643 uint8_t not_used_01 : 3; 00644 uint8_t spi2_read_en : 1; 00645 uint8_t not_used_02 : 1; 00646 uint8_t den_lh_ois : 1; 00647 uint8_t lvl2_ois : 1; 00648 uint8_t int2_drdy_ois : 1; 00649 } lsm6dsox_ui_int_ois_t; 00650 00651 #define LSM6DSOX_UI_CTRL1_OIS 0x70U 00652 typedef struct { 00653 uint8_t ois_en_spi2 : 1; 00654 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 00655 uint8_t mode4_en : 1; 00656 uint8_t sim_ois : 1; 00657 uint8_t lvl1_ois : 1; 00658 uint8_t not_used_01 : 1; 00659 } lsm6dsox_ui_ctrl1_ois_t; 00660 00661 #define LSM6DSOX_UI_CTRL2_OIS 0x71U 00662 typedef struct { 00663 uint8_t hp_en_ois : 1; 00664 uint8_t ftype_ois : 2; 00665 uint8_t not_used_01 : 1; 00666 uint8_t hpm_ois : 2; 00667 uint8_t not_used_02 : 2; 00668 } lsm6dsox_ui_ctrl2_ois_t; 00669 00670 #define LSM6DSOX_UI_CTRL3_OIS 0x72U 00671 typedef struct { 00672 uint8_t st_ois_clampdis : 1; 00673 uint8_t not_used_01 : 2; 00674 uint8_t filter_xl_conf_ois : 3; 00675 uint8_t fs_xl_ois : 2; 00676 } lsm6dsox_ui_ctrl3_ois_t; 00677 00678 #define LSM6DSOX_X_OFS_USR 0x73U 00679 #define LSM6DSOX_Y_OFS_USR 0x74U 00680 #define LSM6DSOX_Z_OFS_USR 0x75U 00681 #define LSM6DSOX_FIFO_DATA_OUT_TAG 0x78U 00682 typedef struct { 00683 uint8_t tag_parity : 1; 00684 uint8_t tag_cnt : 2; 00685 uint8_t tag_sensor : 5; 00686 } lsm6dsox_fifo_data_out_tag_t; 00687 00688 #define LSM6DSOX_FIFO_DATA_OUT_X_L 0x79 00689 #define LSM6DSOX_FIFO_DATA_OUT_X_H 0x7A 00690 #define LSM6DSOX_FIFO_DATA_OUT_Y_L 0x7B 00691 #define LSM6DSOX_FIFO_DATA_OUT_Y_H 0x7C 00692 #define LSM6DSOX_FIFO_DATA_OUT_Z_L 0x7D 00693 #define LSM6DSOX_FIFO_DATA_OUT_Z_H 0x7E 00694 00695 #define LSM6DSOX_SPI2_WHO_AM_I 0x0F 00696 #define LSM6DSOX_SPI2_STATUS_REG_OIS 0x1E 00697 typedef struct { 00698 uint8_t xlda : 1; 00699 uint8_t gda : 1; 00700 uint8_t gyro_settling : 1; 00701 uint8_t not_used_01 : 5; 00702 } lsm6dsox_spi2_status_reg_ois_t; 00703 00704 #define LSM6DSOX_SPI2_OUT_TEMP_L 0x20 00705 #define LSM6DSOX_SPI2_OUT_TEMP_H 0x21 00706 #define LSM6DSOX_SPI2_OUTX_L_G_OIS 0x22 00707 #define LSM6DSOX_SPI2_OUTX_H_G_OIS 0x23 00708 #define LSM6DSOX_SPI2_OUTY_L_G_OIS 0x24 00709 #define LSM6DSOX_SPI2_OUTY_H_G_OIS 0x25 00710 #define LSM6DSOX_SPI2_OUTZ_L_G_OIS 0x26 00711 #define LSM6DSOX_SPI2_OUTZ_H_G_OIS 0x27 00712 #define LSM6DSOX_SPI2_OUTX_L_A_OIS 0x28 00713 #define LSM6DSOX_SPI2_OUTX_H_A_OIS 0x29 00714 #define LSM6DSOX_SPI2_OUTY_L_A_OIS 0x2A 00715 #define LSM6DSOX_SPI2_OUTY_H_A_OIS 0x2B 00716 #define LSM6DSOX_SPI2_OUTZ_L_A_OIS 0x2C 00717 #define LSM6DSOX_SPI2_OUTZ_H_A_OIS 0x2D 00718 #define LSM6DSOX_SPI2_INT_OIS 0x6F 00719 typedef struct { 00720 uint8_t st_xl_ois : 2; 00721 uint8_t not_used_01 : 3; 00722 uint8_t den_lh_ois : 1; 00723 uint8_t lvl2_ois : 1; 00724 uint8_t int2_drdy_ois : 1; 00725 } lsm6dsox_spi2_int_ois_t; 00726 00727 #define LSM6DSOX_SPI2_CTRL1_OIS 0x70U 00728 typedef struct { 00729 uint8_t ois_en_spi2 : 1; 00730 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 00731 uint8_t mode4_en : 1; 00732 uint8_t sim_ois : 1; 00733 uint8_t lvl1_ois : 1; 00734 uint8_t not_used_01 : 1; 00735 } lsm6dsox_spi2_ctrl1_ois_t; 00736 00737 #define LSM6DSOX_SPI2_CTRL2_OIS 0x71U 00738 typedef struct { 00739 uint8_t hp_en_ois : 1; 00740 uint8_t ftype_ois : 2; 00741 uint8_t not_used_01 : 1; 00742 uint8_t hpm_ois : 2; 00743 uint8_t not_used_02 : 2; 00744 } lsm6dsox_spi2_ctrl2_ois_t; 00745 00746 #define LSM6DSOX_SPI2_CTRL3_OIS 0x72U 00747 typedef struct { 00748 uint8_t st_ois_clampdis : 1; 00749 uint8_t st_ois : 2; 00750 uint8_t filter_xl_conf_ois : 3; 00751 uint8_t fs_xl_ois : 2; 00752 } lsm6dsox_spi2_ctrl3_ois_t; 00753 00754 #define LSM6DSOX_PAGE_SEL 0x02U 00755 typedef struct { 00756 uint8_t not_used_01 : 4; 00757 uint8_t page_sel : 4; 00758 } lsm6dsox_page_sel_t; 00759 00760 #define LSM6DSOX_EMB_FUNC_EN_A 0x04U 00761 typedef struct { 00762 uint8_t not_used_01 : 3; 00763 uint8_t pedo_en : 1; 00764 uint8_t tilt_en : 1; 00765 uint8_t sign_motion_en : 1; 00766 uint8_t not_used_02 : 2; 00767 } lsm6dsox_emb_func_en_a_t; 00768 00769 #define LSM6DSOX_EMB_FUNC_EN_B 0x05U 00770 typedef struct { 00771 uint8_t fsm_en : 1; 00772 uint8_t not_used_01 : 2; 00773 uint8_t fifo_compr_en : 1; 00774 uint8_t mlc_en : 1; 00775 uint8_t not_used_02 : 3; 00776 } lsm6dsox_emb_func_en_b_t; 00777 00778 #define LSM6DSOX_PAGE_ADDRESS 0x08U 00779 typedef struct { 00780 uint8_t page_addr : 8; 00781 } lsm6dsox_page_address_t; 00782 00783 #define LSM6DSOX_PAGE_VALUE 0x09U 00784 typedef struct { 00785 uint8_t page_value : 8; 00786 } lsm6dsox_page_value_t; 00787 00788 #define LSM6DSOX_EMB_FUNC_INT1 0x0AU 00789 typedef struct { 00790 uint8_t not_used_01 : 3; 00791 uint8_t int1_step_detector : 1; 00792 uint8_t int1_tilt : 1; 00793 uint8_t int1_sig_mot : 1; 00794 uint8_t not_used_02 : 1; 00795 uint8_t int1_fsm_lc : 1; 00796 } lsm6dsox_emb_func_int1_t; 00797 00798 #define LSM6DSOX_FSM_INT1_A 0x0BU 00799 typedef struct { 00800 uint8_t int1_fsm1 : 1; 00801 uint8_t int1_fsm2 : 1; 00802 uint8_t int1_fsm3 : 1; 00803 uint8_t int1_fsm4 : 1; 00804 uint8_t int1_fsm5 : 1; 00805 uint8_t int1_fsm6 : 1; 00806 uint8_t int1_fsm7 : 1; 00807 uint8_t int1_fsm8 : 1; 00808 } lsm6dsox_fsm_int1_a_t; 00809 00810 #define LSM6DSOX_FSM_INT1_B 0x0CU 00811 typedef struct { 00812 uint8_t int1_fsm9 : 1; 00813 uint8_t int1_fsm10 : 1; 00814 uint8_t int1_fsm11 : 1; 00815 uint8_t int1_fsm12 : 1; 00816 uint8_t int1_fsm13 : 1; 00817 uint8_t int1_fsm14 : 1; 00818 uint8_t int1_fsm15 : 1; 00819 uint8_t int1_fsm16 : 1; 00820 } lsm6dsox_fsm_int1_b_t; 00821 00822 #define LSM6DSOX_MLC_INT1 0x0DU 00823 typedef struct { 00824 uint8_t int1_mlc1 : 1; 00825 uint8_t int1_mlc2 : 1; 00826 uint8_t int1_mlc3 : 1; 00827 uint8_t int1_mlc4 : 1; 00828 uint8_t int1_mlc5 : 1; 00829 uint8_t int1_mlc6 : 1; 00830 uint8_t int1_mlc7 : 1; 00831 uint8_t int1_mlc8 : 1; 00832 } lsm6dsox_mlc_int1_t; 00833 00834 #define LSM6DSOX_EMB_FUNC_INT2 0x0EU 00835 typedef struct { 00836 uint8_t not_used_01 : 3; 00837 uint8_t int2_step_detector : 1; 00838 uint8_t int2_tilt : 1; 00839 uint8_t int2_sig_mot : 1; 00840 uint8_t not_used_02 : 1; 00841 uint8_t int2_fsm_lc : 1; 00842 } lsm6dsox_emb_func_int2_t; 00843 00844 #define LSM6DSOX_FSM_INT2_A 0x0FU 00845 typedef struct { 00846 uint8_t int2_fsm1 : 1; 00847 uint8_t int2_fsm2 : 1; 00848 uint8_t int2_fsm3 : 1; 00849 uint8_t int2_fsm4 : 1; 00850 uint8_t int2_fsm5 : 1; 00851 uint8_t int2_fsm6 : 1; 00852 uint8_t int2_fsm7 : 1; 00853 uint8_t int2_fsm8 : 1; 00854 } lsm6dsox_fsm_int2_a_t; 00855 00856 #define LSM6DSOX_FSM_INT2_B 0x10U 00857 typedef struct { 00858 uint8_t int2_fsm9 : 1; 00859 uint8_t int2_fsm10 : 1; 00860 uint8_t int2_fsm11 : 1; 00861 uint8_t int2_fsm12 : 1; 00862 uint8_t int2_fsm13 : 1; 00863 uint8_t int2_fsm14 : 1; 00864 uint8_t int2_fsm15 : 1; 00865 uint8_t int2_fsm16 : 1; 00866 } lsm6dsox_fsm_int2_b_t; 00867 00868 #define LSM6DSOX_MLC_INT2 0x11U 00869 typedef struct { 00870 uint8_t int2_mlc1 : 1; 00871 uint8_t int2_mlc2 : 1; 00872 uint8_t int2_mlc3 : 1; 00873 uint8_t int2_mlc4 : 1; 00874 uint8_t int2_mlc5 : 1; 00875 uint8_t int2_mlc6 : 1; 00876 uint8_t int2_mlc7 : 1; 00877 uint8_t int2_mlc8 : 1; 00878 } lsm6dsox_mlc_int2_t; 00879 00880 #define LSM6DSOX_EMB_FUNC_STATUS 0x12U 00881 typedef struct { 00882 uint8_t not_used_01 : 3; 00883 uint8_t is_step_det : 1; 00884 uint8_t is_tilt : 1; 00885 uint8_t is_sigmot : 1; 00886 uint8_t not_used_02 : 1; 00887 uint8_t is_fsm_lc : 1; 00888 } lsm6dsox_emb_func_status_t; 00889 00890 #define LSM6DSOX_FSM_STATUS_A 0x13U 00891 typedef struct { 00892 uint8_t is_fsm1 : 1; 00893 uint8_t is_fsm2 : 1; 00894 uint8_t is_fsm3 : 1; 00895 uint8_t is_fsm4 : 1; 00896 uint8_t is_fsm5 : 1; 00897 uint8_t is_fsm6 : 1; 00898 uint8_t is_fsm7 : 1; 00899 uint8_t is_fsm8 : 1; 00900 } lsm6dsox_fsm_status_a_t; 00901 00902 #define LSM6DSOX_FSM_STATUS_B 0x14U 00903 typedef struct { 00904 uint8_t is_fsm9 : 1; 00905 uint8_t is_fsm10 : 1; 00906 uint8_t is_fsm11 : 1; 00907 uint8_t is_fsm12 : 1; 00908 uint8_t is_fsm13 : 1; 00909 uint8_t is_fsm14 : 1; 00910 uint8_t is_fsm15 : 1; 00911 uint8_t is_fsm16 : 1; 00912 } lsm6dsox_fsm_status_b_t; 00913 00914 #define LSM6DSOX_MLC_STATUS 0x15U 00915 typedef struct { 00916 uint8_t is_mlc1 : 1; 00917 uint8_t is_mlc2 : 1; 00918 uint8_t is_mlc3 : 1; 00919 uint8_t is_mlc4 : 1; 00920 uint8_t is_mlc5 : 1; 00921 uint8_t is_mlc6 : 1; 00922 uint8_t is_mlc7 : 1; 00923 uint8_t is_mlc8 : 1; 00924 } lsm6dsox_mlc_status_t; 00925 00926 #define LSM6DSOX_PAGE_RW 0x17U 00927 typedef struct { 00928 uint8_t not_used_01 : 5; 00929 uint8_t page_rw : 2; /* page_write + page_read */ 00930 uint8_t emb_func_lir : 1; 00931 } lsm6dsox_page_rw_t; 00932 00933 #define LSM6DSOX_EMB_FUNC_FIFO_CFG 0x44U 00934 typedef struct { 00935 uint8_t not_used_00 : 6; 00936 uint8_t pedo_fifo_en : 1; 00937 uint8_t not_used_01 : 1; 00938 } lsm6dsox_emb_func_fifo_cfg_t; 00939 00940 #define LSM6DSOX_FSM_ENABLE_A 0x46U 00941 typedef struct { 00942 uint8_t fsm1_en : 1; 00943 uint8_t fsm2_en : 1; 00944 uint8_t fsm3_en : 1; 00945 uint8_t fsm4_en : 1; 00946 uint8_t fsm5_en : 1; 00947 uint8_t fsm6_en : 1; 00948 uint8_t fsm7_en : 1; 00949 uint8_t fsm8_en : 1; 00950 } lsm6dsox_fsm_enable_a_t; 00951 00952 #define LSM6DSOX_FSM_ENABLE_B 0x47U 00953 typedef struct { 00954 uint8_t fsm9_en : 1; 00955 uint8_t fsm10_en : 1; 00956 uint8_t fsm11_en : 1; 00957 uint8_t fsm12_en : 1; 00958 uint8_t fsm13_en : 1; 00959 uint8_t fsm14_en : 1; 00960 uint8_t fsm15_en : 1; 00961 uint8_t fsm16_en : 1; 00962 } lsm6dsox_fsm_enable_b_t; 00963 00964 #define LSM6DSOX_FSM_LONG_COUNTER_L 0x48U 00965 #define LSM6DSOX_FSM_LONG_COUNTER_H 0x49U 00966 #define LSM6DSOX_FSM_LONG_COUNTER_CLEAR 0x4AU 00967 typedef struct { 00968 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 00969 uint8_t not_used_01 : 6; 00970 } lsm6dsox_fsm_long_counter_clear_t; 00971 00972 #define LSM6DSOX_FSM_OUTS1 0x4CU 00973 typedef struct { 00974 uint8_t n_v : 1; 00975 uint8_t p_v : 1; 00976 uint8_t n_z : 1; 00977 uint8_t p_z : 1; 00978 uint8_t n_y : 1; 00979 uint8_t p_y : 1; 00980 uint8_t n_x : 1; 00981 uint8_t p_x : 1; 00982 } lsm6dsox_fsm_outs1_t; 00983 00984 #define LSM6DSOX_FSM_OUTS2 0x4DU 00985 typedef struct { 00986 uint8_t n_v : 1; 00987 uint8_t p_v : 1; 00988 uint8_t n_z : 1; 00989 uint8_t p_z : 1; 00990 uint8_t n_y : 1; 00991 uint8_t p_y : 1; 00992 uint8_t n_x : 1; 00993 uint8_t p_x : 1; 00994 } lsm6dsox_fsm_outs2_t; 00995 00996 #define LSM6DSOX_FSM_OUTS3 0x4EU 00997 typedef struct { 00998 uint8_t n_v : 1; 00999 uint8_t p_v : 1; 01000 uint8_t n_z : 1; 01001 uint8_t p_z : 1; 01002 uint8_t n_y : 1; 01003 uint8_t p_y : 1; 01004 uint8_t n_x : 1; 01005 uint8_t p_x : 1; 01006 } lsm6dsox_fsm_outs3_t; 01007 01008 #define LSM6DSOX_FSM_OUTS4 0x4FU 01009 typedef struct { 01010 uint8_t n_v : 1; 01011 uint8_t p_v : 1; 01012 uint8_t n_z : 1; 01013 uint8_t p_z : 1; 01014 uint8_t n_y : 1; 01015 uint8_t p_y : 1; 01016 uint8_t n_x : 1; 01017 uint8_t p_x : 1; 01018 } lsm6dsox_fsm_outs4_t; 01019 01020 #define LSM6DSOX_FSM_OUTS5 0x50U 01021 typedef struct { 01022 uint8_t n_v : 1; 01023 uint8_t p_v : 1; 01024 uint8_t n_z : 1; 01025 uint8_t p_z : 1; 01026 uint8_t n_y : 1; 01027 uint8_t p_y : 1; 01028 uint8_t n_x : 1; 01029 uint8_t p_x : 1; 01030 } lsm6dsox_fsm_outs5_t; 01031 01032 #define LSM6DSOX_FSM_OUTS6 0x51U 01033 typedef struct { 01034 uint8_t n_v : 1; 01035 uint8_t p_v : 1; 01036 uint8_t n_z : 1; 01037 uint8_t p_z : 1; 01038 uint8_t n_y : 1; 01039 uint8_t p_y : 1; 01040 uint8_t n_x : 1; 01041 uint8_t p_x : 1; 01042 } lsm6dsox_fsm_outs6_t; 01043 01044 #define LSM6DSOX_FSM_OUTS7 0x52U 01045 typedef struct { 01046 uint8_t n_v : 1; 01047 uint8_t p_v : 1; 01048 uint8_t n_z : 1; 01049 uint8_t p_z : 1; 01050 uint8_t n_y : 1; 01051 uint8_t p_y : 1; 01052 uint8_t n_x : 1; 01053 uint8_t p_x : 1; 01054 } lsm6dsox_fsm_outs7_t; 01055 01056 #define LSM6DSOX_FSM_OUTS8 0x53U 01057 typedef struct { 01058 uint8_t n_v : 1; 01059 uint8_t p_v : 1; 01060 uint8_t n_z : 1; 01061 uint8_t p_z : 1; 01062 uint8_t n_y : 1; 01063 uint8_t p_y : 1; 01064 uint8_t n_x : 1; 01065 uint8_t p_x : 1; 01066 } lsm6dsox_fsm_outs8_t; 01067 01068 #define LSM6DSOX_FSM_OUTS9 0x54U 01069 typedef struct { 01070 uint8_t n_v : 1; 01071 uint8_t p_v : 1; 01072 uint8_t n_z : 1; 01073 uint8_t p_z : 1; 01074 uint8_t n_y : 1; 01075 uint8_t p_y : 1; 01076 uint8_t n_x : 1; 01077 uint8_t p_x : 1; 01078 } lsm6dsox_fsm_outs9_t; 01079 01080 #define LSM6DSOX_FSM_OUTS10 0x55U 01081 typedef struct { 01082 uint8_t n_v : 1; 01083 uint8_t p_v : 1; 01084 uint8_t n_z : 1; 01085 uint8_t p_z : 1; 01086 uint8_t n_y : 1; 01087 uint8_t p_y : 1; 01088 uint8_t n_x : 1; 01089 uint8_t p_x : 1; 01090 } lsm6dsox_fsm_outs10_t; 01091 01092 #define LSM6DSOX_FSM_OUTS11 0x56U 01093 typedef struct { 01094 uint8_t n_v : 1; 01095 uint8_t p_v : 1; 01096 uint8_t n_z : 1; 01097 uint8_t p_z : 1; 01098 uint8_t n_y : 1; 01099 uint8_t p_y : 1; 01100 uint8_t n_x : 1; 01101 uint8_t p_x : 1; 01102 } lsm6dsox_fsm_outs11_t; 01103 01104 #define LSM6DSOX_FSM_OUTS12 0x57U 01105 typedef struct { 01106 uint8_t n_v : 1; 01107 uint8_t p_v : 1; 01108 uint8_t n_z : 1; 01109 uint8_t p_z : 1; 01110 uint8_t n_y : 1; 01111 uint8_t p_y : 1; 01112 uint8_t n_x : 1; 01113 uint8_t p_x : 1; 01114 } lsm6dsox_fsm_outs12_t; 01115 01116 #define LSM6DSOX_FSM_OUTS13 0x58U 01117 typedef struct { 01118 uint8_t n_v : 1; 01119 uint8_t p_v : 1; 01120 uint8_t n_z : 1; 01121 uint8_t p_z : 1; 01122 uint8_t n_y : 1; 01123 uint8_t p_y : 1; 01124 uint8_t n_x : 1; 01125 uint8_t p_x : 1; 01126 } lsm6dsox_fsm_outs13_t; 01127 01128 #define LSM6DSOX_FSM_OUTS14 0x59U 01129 typedef struct { 01130 uint8_t n_v : 1; 01131 uint8_t p_v : 1; 01132 uint8_t n_z : 1; 01133 uint8_t p_z : 1; 01134 uint8_t n_y : 1; 01135 uint8_t p_y : 1; 01136 uint8_t n_x : 1; 01137 uint8_t p_x : 1; 01138 } lsm6dsox_fsm_outs14_t; 01139 01140 #define LSM6DSOX_FSM_OUTS15 0x5AU 01141 typedef struct { 01142 uint8_t n_v : 1; 01143 uint8_t p_v : 1; 01144 uint8_t n_z : 1; 01145 uint8_t p_z : 1; 01146 uint8_t n_y : 1; 01147 uint8_t p_y : 1; 01148 uint8_t n_x : 1; 01149 uint8_t p_x : 1; 01150 } lsm6dsox_fsm_outs15_t; 01151 01152 #define LSM6DSOX_FSM_OUTS16 0x5BU 01153 typedef struct { 01154 uint8_t n_v : 1; 01155 uint8_t p_v : 1; 01156 uint8_t n_z : 1; 01157 uint8_t p_z : 1; 01158 uint8_t n_y : 1; 01159 uint8_t p_y : 1; 01160 uint8_t n_x : 1; 01161 uint8_t p_x : 1; 01162 } lsm6dsox_fsm_outs16_t; 01163 01164 #define LSM6DSOX_EMB_FUNC_ODR_CFG_B 0x5FU 01165 typedef struct { 01166 uint8_t not_used_01 : 3; 01167 uint8_t fsm_odr : 2; 01168 uint8_t not_used_02 : 3; 01169 } lsm6dsox_emb_func_odr_cfg_b_t; 01170 01171 #define LSM6DSOX_EMB_FUNC_ODR_CFG_C 0x60U 01172 typedef struct { 01173 uint8_t not_used_01 : 4; 01174 uint8_t mlc_odr : 2; 01175 uint8_t not_used_02 : 2; 01176 } lsm6dsox_emb_func_odr_cfg_c_t; 01177 01178 #define LSM6DSOX_STEP_COUNTER_L 0x62U 01179 #define LSM6DSOX_STEP_COUNTER_H 0x63U 01180 #define LSM6DSOX_EMB_FUNC_SRC 0x64U 01181 typedef struct { 01182 uint8_t not_used_01 : 2; 01183 uint8_t stepcounter_bit_set : 1; 01184 uint8_t step_overflow : 1; 01185 uint8_t step_count_delta_ia : 1; 01186 uint8_t step_detected : 1; 01187 uint8_t not_used_02 : 1; 01188 uint8_t pedo_rst_step : 1; 01189 } lsm6dsox_emb_func_src_t; 01190 01191 #define LSM6DSOX_EMB_FUNC_INIT_A 0x66U 01192 typedef struct { 01193 uint8_t not_used_01 : 3; 01194 uint8_t step_det_init : 1; 01195 uint8_t tilt_init : 1; 01196 uint8_t sig_mot_init : 1; 01197 uint8_t not_used_02 : 2; 01198 } lsm6dsox_emb_func_init_a_t; 01199 01200 #define LSM6DSOX_EMB_FUNC_INIT_B 0x67U 01201 typedef struct { 01202 uint8_t fsm_init : 1; 01203 uint8_t not_used_01 : 2; 01204 uint8_t fifo_compr_init : 1; 01205 uint8_t mlc_init : 1; 01206 uint8_t not_used_02 : 3; 01207 } lsm6dsox_emb_func_init_b_t; 01208 01209 #define LSM6DSOX_MLC0_SRC 0x70U 01210 #define LSM6DSOX_MLC1_SRC 0x71U 01211 #define LSM6DSOX_MLC2_SRC 0x72U 01212 #define LSM6DSOX_MLC3_SRC 0x73U 01213 #define LSM6DSOX_MLC4_SRC 0x74U 01214 #define LSM6DSOX_MLC5_SRC 0x75U 01215 #define LSM6DSOX_MLC6_SRC 0x76U 01216 #define LSM6DSOX_MLC7_SRC 0x77U 01217 #define LSM6DSOX_MAG_SENSITIVITY_L 0xBAU 01218 #define LSM6DSOX_MAG_SENSITIVITY_H 0xBBU 01219 #define LSM6DSOX_MAG_OFFX_L 0xC0U 01220 #define LSM6DSOX_MAG_OFFX_H 0xC1U 01221 #define LSM6DSOX_MAG_OFFY_L 0xC2U 01222 #define LSM6DSOX_MAG_OFFY_H 0xC3U 01223 #define LSM6DSOX_MAG_OFFZ_L 0xC4U 01224 #define LSM6DSOX_MAG_OFFZ_H 0xC5U 01225 #define LSM6DSOX_MAG_SI_XX_L 0xC6U 01226 #define LSM6DSOX_MAG_SI_XX_H 0xC7U 01227 #define LSM6DSOX_MAG_SI_XY_L 0xC8U 01228 #define LSM6DSOX_MAG_SI_XY_H 0xC9U 01229 #define LSM6DSOX_MAG_SI_XZ_L 0xCAU 01230 #define LSM6DSOX_MAG_SI_XZ_H 0xCBU 01231 #define LSM6DSOX_MAG_SI_YY_L 0xCCU 01232 #define LSM6DSOX_MAG_SI_YY_H 0xCDU 01233 #define LSM6DSOX_MAG_SI_YZ_L 0xCEU 01234 #define LSM6DSOX_MAG_SI_YZ_H 0xCFU 01235 #define LSM6DSOX_MAG_SI_ZZ_L 0xD0U 01236 #define LSM6DSOX_MAG_SI_ZZ_H 0xD1U 01237 #define LSM6DSOX_MAG_CFG_A 0xD4U 01238 typedef struct { 01239 uint8_t mag_z_axis : 3; 01240 uint8_t not_used_01 : 1; 01241 uint8_t mag_y_axis : 3; 01242 uint8_t not_used_02 : 1; 01243 } lsm6dsox_mag_cfg_a_t; 01244 01245 #define LSM6DSOX_MAG_CFG_B 0xD5U 01246 typedef struct { 01247 uint8_t mag_x_axis : 3; 01248 uint8_t not_used_01 : 5; 01249 } lsm6dsox_mag_cfg_b_t; 01250 01251 #define LSM6DSOX_FSM_LC_TIMEOUT_L 0x17AU 01252 #define LSM6DSOX_FSM_LC_TIMEOUT_H 0x17BU 01253 #define LSM6DSOX_FSM_PROGRAMS 0x17CU 01254 #define LSM6DSOX_FSM_START_ADD_L 0x17EU 01255 #define LSM6DSOX_FSM_START_ADD_H 0x17FU 01256 #define LSM6DSOX_PEDO_CMD_REG 0x183U 01257 typedef struct { 01258 uint8_t ad_det_en : 1; 01259 uint8_t not_used_01 : 1; 01260 uint8_t fp_rejection_en : 1; 01261 uint8_t carry_count_en : 1; 01262 uint8_t not_used_02 : 4; 01263 } lsm6dsox_pedo_cmd_reg_t; 01264 01265 #define LSM6DSOX_PEDO_DEB_STEPS_CONF 0x184U 01266 #define LSM6DSOX_PEDO_SC_DELTAT_L 0x1D0U 01267 #define LSM6DSOX_PEDO_SC_DELTAT_H 0x1D1U 01268 01269 #define LSM6DSOX_MLC_MAG_SENSITIVITY_L 0x1E8U 01270 #define LSM6DSOX_MLC_MAG_SENSITIVITY_H 0x1E9U 01271 01272 #define LSM6DSOX_SENSOR_HUB_1 0x02U 01273 typedef struct { 01274 uint8_t bit0 : 1; 01275 uint8_t bit1 : 1; 01276 uint8_t bit2 : 1; 01277 uint8_t bit3 : 1; 01278 uint8_t bit4 : 1; 01279 uint8_t bit5 : 1; 01280 uint8_t bit6 : 1; 01281 uint8_t bit7 : 1; 01282 } lsm6dsox_sensor_hub_1_t; 01283 01284 #define LSM6DSOX_SENSOR_HUB_2 0x03U 01285 typedef struct { 01286 uint8_t bit0 : 1; 01287 uint8_t bit1 : 1; 01288 uint8_t bit2 : 1; 01289 uint8_t bit3 : 1; 01290 uint8_t bit4 : 1; 01291 uint8_t bit5 : 1; 01292 uint8_t bit6 : 1; 01293 uint8_t bit7 : 1; 01294 } lsm6dsox_sensor_hub_2_t; 01295 01296 #define LSM6DSOX_SENSOR_HUB_3 0x04U 01297 typedef struct { 01298 uint8_t bit0 : 1; 01299 uint8_t bit1 : 1; 01300 uint8_t bit2 : 1; 01301 uint8_t bit3 : 1; 01302 uint8_t bit4 : 1; 01303 uint8_t bit5 : 1; 01304 uint8_t bit6 : 1; 01305 uint8_t bit7 : 1; 01306 } lsm6dsox_sensor_hub_3_t; 01307 01308 #define LSM6DSOX_SENSOR_HUB_4 0x05U 01309 typedef struct { 01310 uint8_t bit0 : 1; 01311 uint8_t bit1 : 1; 01312 uint8_t bit2 : 1; 01313 uint8_t bit3 : 1; 01314 uint8_t bit4 : 1; 01315 uint8_t bit5 : 1; 01316 uint8_t bit6 : 1; 01317 uint8_t bit7 : 1; 01318 } lsm6dsox_sensor_hub_4_t; 01319 01320 #define LSM6DSOX_SENSOR_HUB_5 0x06U 01321 typedef struct { 01322 uint8_t bit0 : 1; 01323 uint8_t bit1 : 1; 01324 uint8_t bit2 : 1; 01325 uint8_t bit3 : 1; 01326 uint8_t bit4 : 1; 01327 uint8_t bit5 : 1; 01328 uint8_t bit6 : 1; 01329 uint8_t bit7 : 1; 01330 } lsm6dsox_sensor_hub_5_t; 01331 01332 #define LSM6DSOX_SENSOR_HUB_6 0x07U 01333 typedef struct { 01334 uint8_t bit0 : 1; 01335 uint8_t bit1 : 1; 01336 uint8_t bit2 : 1; 01337 uint8_t bit3 : 1; 01338 uint8_t bit4 : 1; 01339 uint8_t bit5 : 1; 01340 uint8_t bit6 : 1; 01341 uint8_t bit7 : 1; 01342 } lsm6dsox_sensor_hub_6_t; 01343 01344 #define LSM6DSOX_SENSOR_HUB_7 0x08U 01345 typedef struct { 01346 uint8_t bit0 : 1; 01347 uint8_t bit1 : 1; 01348 uint8_t bit2 : 1; 01349 uint8_t bit3 : 1; 01350 uint8_t bit4 : 1; 01351 uint8_t bit5 : 1; 01352 uint8_t bit6 : 1; 01353 uint8_t bit7 : 1; 01354 } lsm6dsox_sensor_hub_7_t; 01355 01356 #define LSM6DSOX_SENSOR_HUB_8 0x09U 01357 typedef struct { 01358 uint8_t bit0 : 1; 01359 uint8_t bit1 : 1; 01360 uint8_t bit2 : 1; 01361 uint8_t bit3 : 1; 01362 uint8_t bit4 : 1; 01363 uint8_t bit5 : 1; 01364 uint8_t bit6 : 1; 01365 uint8_t bit7 : 1; 01366 } lsm6dsox_sensor_hub_8_t; 01367 01368 #define LSM6DSOX_SENSOR_HUB_9 0x0AU 01369 typedef struct { 01370 uint8_t bit0 : 1; 01371 uint8_t bit1 : 1; 01372 uint8_t bit2 : 1; 01373 uint8_t bit3 : 1; 01374 uint8_t bit4 : 1; 01375 uint8_t bit5 : 1; 01376 uint8_t bit6 : 1; 01377 uint8_t bit7 : 1; 01378 } lsm6dsox_sensor_hub_9_t; 01379 01380 #define LSM6DSOX_SENSOR_HUB_10 0x0BU 01381 typedef struct { 01382 uint8_t bit0 : 1; 01383 uint8_t bit1 : 1; 01384 uint8_t bit2 : 1; 01385 uint8_t bit3 : 1; 01386 uint8_t bit4 : 1; 01387 uint8_t bit5 : 1; 01388 uint8_t bit6 : 1; 01389 uint8_t bit7 : 1; 01390 } lsm6dsox_sensor_hub_10_t; 01391 01392 #define LSM6DSOX_SENSOR_HUB_11 0x0CU 01393 typedef struct { 01394 uint8_t bit0 : 1; 01395 uint8_t bit1 : 1; 01396 uint8_t bit2 : 1; 01397 uint8_t bit3 : 1; 01398 uint8_t bit4 : 1; 01399 uint8_t bit5 : 1; 01400 uint8_t bit6 : 1; 01401 uint8_t bit7 : 1; 01402 } lsm6dsox_sensor_hub_11_t; 01403 01404 #define LSM6DSOX_SENSOR_HUB_12 0x0DU 01405 typedef struct { 01406 uint8_t bit0 : 1; 01407 uint8_t bit1 : 1; 01408 uint8_t bit2 : 1; 01409 uint8_t bit3 : 1; 01410 uint8_t bit4 : 1; 01411 uint8_t bit5 : 1; 01412 uint8_t bit6 : 1; 01413 uint8_t bit7 : 1; 01414 } lsm6dsox_sensor_hub_12_t; 01415 01416 #define LSM6DSOX_SENSOR_HUB_13 0x0EU 01417 typedef struct { 01418 uint8_t bit0 : 1; 01419 uint8_t bit1 : 1; 01420 uint8_t bit2 : 1; 01421 uint8_t bit3 : 1; 01422 uint8_t bit4 : 1; 01423 uint8_t bit5 : 1; 01424 uint8_t bit6 : 1; 01425 uint8_t bit7 : 1; 01426 } lsm6dsox_sensor_hub_13_t; 01427 01428 #define LSM6DSOX_SENSOR_HUB_14 0x0FU 01429 typedef struct { 01430 uint8_t bit0 : 1; 01431 uint8_t bit1 : 1; 01432 uint8_t bit2 : 1; 01433 uint8_t bit3 : 1; 01434 uint8_t bit4 : 1; 01435 uint8_t bit5 : 1; 01436 uint8_t bit6 : 1; 01437 uint8_t bit7 : 1; 01438 } lsm6dsox_sensor_hub_14_t; 01439 01440 #define LSM6DSOX_SENSOR_HUB_15 0x10U 01441 typedef struct { 01442 uint8_t bit0 : 1; 01443 uint8_t bit1 : 1; 01444 uint8_t bit2 : 1; 01445 uint8_t bit3 : 1; 01446 uint8_t bit4 : 1; 01447 uint8_t bit5 : 1; 01448 uint8_t bit6 : 1; 01449 uint8_t bit7 : 1; 01450 } lsm6dsox_sensor_hub_15_t; 01451 01452 #define LSM6DSOX_SENSOR_HUB_16 0x11U 01453 typedef struct { 01454 uint8_t bit0 : 1; 01455 uint8_t bit1 : 1; 01456 uint8_t bit2 : 1; 01457 uint8_t bit3 : 1; 01458 uint8_t bit4 : 1; 01459 uint8_t bit5 : 1; 01460 uint8_t bit6 : 1; 01461 uint8_t bit7 : 1; 01462 } lsm6dsox_sensor_hub_16_t; 01463 01464 #define LSM6DSOX_SENSOR_HUB_17 0x12U 01465 typedef struct { 01466 uint8_t bit0 : 1; 01467 uint8_t bit1 : 1; 01468 uint8_t bit2 : 1; 01469 uint8_t bit3 : 1; 01470 uint8_t bit4 : 1; 01471 uint8_t bit5 : 1; 01472 uint8_t bit6 : 1; 01473 uint8_t bit7 : 1; 01474 } lsm6dsox_sensor_hub_17_t; 01475 01476 #define LSM6DSOX_SENSOR_HUB_18 0x13U 01477 typedef struct { 01478 uint8_t bit0 : 1; 01479 uint8_t bit1 : 1; 01480 uint8_t bit2 : 1; 01481 uint8_t bit3 : 1; 01482 uint8_t bit4 : 1; 01483 uint8_t bit5 : 1; 01484 uint8_t bit6 : 1; 01485 uint8_t bit7 : 1; 01486 } lsm6dsox_sensor_hub_18_t; 01487 01488 #define LSM6DSOX_MASTER_CONFIG 0x14U 01489 typedef struct { 01490 uint8_t aux_sens_on : 2; 01491 uint8_t master_on : 1; 01492 uint8_t shub_pu_en : 1; 01493 uint8_t pass_through_mode : 1; 01494 uint8_t start_config : 1; 01495 uint8_t write_once : 1; 01496 uint8_t rst_master_regs : 1; 01497 } lsm6dsox_master_config_t; 01498 01499 #define LSM6DSOX_SLV0_ADD 0x15U 01500 typedef struct { 01501 uint8_t rw_0 : 1; 01502 uint8_t slave0 : 7; 01503 } lsm6dsox_slv0_add_t; 01504 01505 #define LSM6DSOX_SLV0_SUBADD 0x16U 01506 typedef struct { 01507 uint8_t slave0_reg : 8; 01508 } lsm6dsox_slv0_subadd_t; 01509 01510 #define LSM6DSOX_SLV0_CONFIG 0x17U 01511 typedef struct { 01512 uint8_t slave0_numop : 3; 01513 uint8_t batch_ext_sens_0_en : 1; 01514 uint8_t not_used_01 : 2; 01515 uint8_t shub_odr : 2; 01516 } lsm6dsox_slv0_config_t; 01517 01518 #define LSM6DSOX_SLV1_ADD 0x18U 01519 typedef struct { 01520 uint8_t r_1 : 1; 01521 uint8_t slave1_add : 7; 01522 } lsm6dsox_slv1_add_t; 01523 01524 #define LSM6DSOX_SLV1_SUBADD 0x19U 01525 typedef struct { 01526 uint8_t slave1_reg : 8; 01527 } lsm6dsox_slv1_subadd_t; 01528 01529 #define LSM6DSOX_SLV1_CONFIG 0x1AU 01530 typedef struct { 01531 uint8_t slave1_numop : 3; 01532 uint8_t batch_ext_sens_1_en : 1; 01533 uint8_t not_used_01 : 4; 01534 } lsm6dsox_slv1_config_t; 01535 01536 #define LSM6DSOX_SLV2_ADD 0x1BU 01537 typedef struct { 01538 uint8_t r_2 : 1; 01539 uint8_t slave2_add : 7; 01540 } lsm6dsox_slv2_add_t; 01541 01542 #define LSM6DSOX_SLV2_SUBADD 0x1CU 01543 typedef struct { 01544 uint8_t slave2_reg : 8; 01545 } lsm6dsox_slv2_subadd_t; 01546 01547 #define LSM6DSOX_SLV2_CONFIG 0x1DU 01548 typedef struct { 01549 uint8_t slave2_numop : 3; 01550 uint8_t batch_ext_sens_2_en : 1; 01551 uint8_t not_used_01 : 4; 01552 } lsm6dsox_slv2_config_t; 01553 01554 #define LSM6DSOX_SLV3_ADD 0x1EU 01555 typedef struct { 01556 uint8_t r_3 : 1; 01557 uint8_t slave3_add : 7; 01558 } lsm6dsox_slv3_add_t; 01559 01560 #define LSM6DSOX_SLV3_SUBADD 0x1FU 01561 typedef struct { 01562 uint8_t slave3_reg : 8; 01563 } lsm6dsox_slv3_subadd_t; 01564 01565 #define LSM6DSOX_SLV3_CONFIG 0x20U 01566 typedef struct { 01567 uint8_t slave3_numop : 3; 01568 uint8_t batch_ext_sens_3_en : 1; 01569 uint8_t not_used_01 : 4; 01570 } lsm6dsox_slv3_config_t; 01571 01572 #define LSM6DSOX_DATAWRITE_SLV0 0x21U 01573 typedef struct { 01574 uint8_t slave0_dataw : 8; 01575 } lsm6dsox_datawrite_slv0_t; 01576 01577 #define LSM6DSOX_STATUS_MASTER 0x22U 01578 typedef struct { 01579 uint8_t sens_hub_endop : 1; 01580 uint8_t not_used_01 : 2; 01581 uint8_t slave0_nack : 1; 01582 uint8_t slave1_nack : 1; 01583 uint8_t slave2_nack : 1; 01584 uint8_t slave3_nack : 1; 01585 uint8_t wr_once_done : 1; 01586 } lsm6dsox_status_master_t; 01587 01588 #define LSM6DSOX_START_FSM_ADD 0x0400U 01589 01590 /** 01591 * @defgroup LSM6DSOX_Register_Union 01592 * @brief This union group all the registers that has a bitfield 01593 * description. 01594 * This union is useful but not need by the driver. 01595 * 01596 * REMOVING this union you are compliant with: 01597 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 01598 * 01599 * @{ 01600 * 01601 */ 01602 typedef union{ 01603 lsm6dsox_func_cfg_access_t func_cfg_access; 01604 lsm6dsox_pin_ctrl_t pin_ctrl; 01605 lsm6dsox_s4s_tph_l_t s4s_tph_l; 01606 lsm6dsox_s4s_tph_h_t s4s_tph_h; 01607 lsm6dsox_s4s_rr_t s4s_rr; 01608 lsm6dsox_fifo_ctrl1_t fifo_ctrl1; 01609 lsm6dsox_fifo_ctrl2_t fifo_ctrl2; 01610 lsm6dsox_fifo_ctrl3_t fifo_ctrl3; 01611 lsm6dsox_fifo_ctrl4_t fifo_ctrl4; 01612 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; 01613 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; 01614 lsm6dsox_int1_ctrl_t int1_ctrl; 01615 lsm6dsox_int2_ctrl_t int2_ctrl; 01616 lsm6dsox_ctrl1_xl_t ctrl1_xl; 01617 lsm6dsox_ctrl2_g_t ctrl2_g; 01618 lsm6dsox_ctrl3_c_t ctrl3_c; 01619 lsm6dsox_ctrl4_c_t ctrl4_c; 01620 lsm6dsox_ctrl5_c_t ctrl5_c; 01621 lsm6dsox_ctrl6_c_t ctrl6_c; 01622 lsm6dsox_ctrl7_g_t ctrl7_g; 01623 lsm6dsox_ctrl8_xl_t ctrl8_xl; 01624 lsm6dsox_ctrl9_xl_t ctrl9_xl; 01625 lsm6dsox_ctrl10_c_t ctrl10_c; 01626 lsm6dsox_all_int_src_t all_int_src; 01627 lsm6dsox_wake_up_src_t wake_up_src; 01628 lsm6dsox_tap_src_t tap_src; 01629 lsm6dsox_d6d_src_t d6d_src; 01630 lsm6dsox_status_reg_t status_reg; 01631 lsm6dsox_fifo_status1_t fifo_status1; 01632 lsm6dsox_fifo_status2_t fifo_status2; 01633 lsm6dsox_ui_status_reg_ois_t ui_status_reg_ois; 01634 lsm6dsox_tap_cfg0_t tap_cfg0; 01635 lsm6dsox_tap_cfg1_t tap_cfg1; 01636 lsm6dsox_tap_cfg2_t tap_cfg2; 01637 lsm6dsox_tap_ths_6d_t tap_ths_6d; 01638 lsm6dsox_int_dur2_t int_dur2; 01639 lsm6dsox_wake_up_ths_t wake_up_ths; 01640 lsm6dsox_wake_up_dur_t wake_up_dur; 01641 lsm6dsox_free_fall_t free_fall; 01642 lsm6dsox_md1_cfg_t md1_cfg; 01643 lsm6dsox_md2_cfg_t md2_cfg; 01644 lsm6dsox_s4s_st_cmd_code_t s4s_st_cmd_code; 01645 lsm6dsox_s4s_dt_reg_t s4s_dt_reg; 01646 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 01647 lsm6dsox_internal_freq_fine_t internal_freq_fine; 01648 lsm6dsox_ui_int_ois_t ui_int_ois; 01649 lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois; 01650 lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois; 01651 lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois; 01652 lsm6dsox_fifo_data_out_tag_t fifo_data_out_tag; 01653 lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois; 01654 lsm6dsox_spi2_int_ois_t spi2_int_ois; 01655 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; 01656 lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois; 01657 lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois; 01658 lsm6dsox_page_sel_t page_sel; 01659 lsm6dsox_emb_func_en_a_t emb_func_en_a; 01660 lsm6dsox_emb_func_en_b_t emb_func_en_b; 01661 lsm6dsox_page_address_t page_address; 01662 lsm6dsox_page_value_t page_value; 01663 lsm6dsox_emb_func_int1_t emb_func_int1; 01664 lsm6dsox_fsm_int1_a_t fsm_int1_a; 01665 lsm6dsox_fsm_int1_b_t fsm_int1_b; 01666 lsm6dsox_emb_func_int2_t emb_func_int2; 01667 lsm6dsox_fsm_int2_a_t fsm_int2_a; 01668 lsm6dsox_fsm_int2_b_t fsm_int2_b; 01669 lsm6dsox_emb_func_status_t emb_func_status; 01670 lsm6dsox_fsm_status_a_t fsm_status_a; 01671 lsm6dsox_fsm_status_b_t fsm_status_b; 01672 lsm6dsox_page_rw_t page_rw; 01673 lsm6dsox_emb_func_fifo_cfg_t emb_func_fifo_cfg; 01674 lsm6dsox_fsm_enable_a_t fsm_enable_a; 01675 lsm6dsox_fsm_enable_b_t fsm_enable_b; 01676 lsm6dsox_fsm_long_counter_clear_t fsm_long_counter_clear; 01677 lsm6dsox_fsm_outs1_t fsm_outs1; 01678 lsm6dsox_fsm_outs2_t fsm_outs2; 01679 lsm6dsox_fsm_outs3_t fsm_outs3; 01680 lsm6dsox_fsm_outs4_t fsm_outs4; 01681 lsm6dsox_fsm_outs5_t fsm_outs5; 01682 lsm6dsox_fsm_outs6_t fsm_outs6; 01683 lsm6dsox_fsm_outs7_t fsm_outs7; 01684 lsm6dsox_fsm_outs8_t fsm_outs8; 01685 lsm6dsox_fsm_outs9_t fsm_outs9; 01686 lsm6dsox_fsm_outs10_t fsm_outs10; 01687 lsm6dsox_fsm_outs11_t fsm_outs11; 01688 lsm6dsox_fsm_outs12_t fsm_outs12; 01689 lsm6dsox_fsm_outs13_t fsm_outs13; 01690 lsm6dsox_fsm_outs14_t fsm_outs14; 01691 lsm6dsox_fsm_outs15_t fsm_outs15; 01692 lsm6dsox_fsm_outs16_t fsm_outs16; 01693 lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 01694 lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 01695 lsm6dsox_emb_func_src_t emb_func_src; 01696 lsm6dsox_emb_func_init_a_t emb_func_init_a; 01697 lsm6dsox_emb_func_init_b_t emb_func_init_b; 01698 lsm6dsox_mag_cfg_a_t mag_cfg_a; 01699 lsm6dsox_mag_cfg_b_t mag_cfg_b; 01700 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; 01701 lsm6dsox_sensor_hub_1_t sensor_hub_1; 01702 lsm6dsox_sensor_hub_2_t sensor_hub_2; 01703 lsm6dsox_sensor_hub_3_t sensor_hub_3; 01704 lsm6dsox_sensor_hub_4_t sensor_hub_4; 01705 lsm6dsox_sensor_hub_5_t sensor_hub_5; 01706 lsm6dsox_sensor_hub_6_t sensor_hub_6; 01707 lsm6dsox_sensor_hub_7_t sensor_hub_7; 01708 lsm6dsox_sensor_hub_8_t sensor_hub_8; 01709 lsm6dsox_sensor_hub_9_t sensor_hub_9; 01710 lsm6dsox_sensor_hub_10_t sensor_hub_10; 01711 lsm6dsox_sensor_hub_11_t sensor_hub_11; 01712 lsm6dsox_sensor_hub_12_t sensor_hub_12; 01713 lsm6dsox_sensor_hub_13_t sensor_hub_13; 01714 lsm6dsox_sensor_hub_14_t sensor_hub_14; 01715 lsm6dsox_sensor_hub_15_t sensor_hub_15; 01716 lsm6dsox_sensor_hub_16_t sensor_hub_16; 01717 lsm6dsox_sensor_hub_17_t sensor_hub_17; 01718 lsm6dsox_sensor_hub_18_t sensor_hub_18; 01719 lsm6dsox_master_config_t master_config; 01720 lsm6dsox_slv0_add_t slv0_add; 01721 lsm6dsox_slv0_subadd_t slv0_subadd; 01722 lsm6dsox_slv0_config_t slv0_config; 01723 lsm6dsox_slv1_add_t slv1_add; 01724 lsm6dsox_slv1_subadd_t slv1_subadd; 01725 lsm6dsox_slv1_config_t slv1_config; 01726 lsm6dsox_slv2_add_t slv2_add; 01727 lsm6dsox_slv2_subadd_t slv2_subadd; 01728 lsm6dsox_slv2_config_t slv2_config; 01729 lsm6dsox_slv3_add_t slv3_add; 01730 lsm6dsox_slv3_subadd_t slv3_subadd; 01731 lsm6dsox_slv3_config_t slv3_config; 01732 lsm6dsox_datawrite_slv0_t datawrite_slv0; 01733 lsm6dsox_status_master_t status_master; 01734 bitwise_t bitwise; 01735 uint8_t byte; 01736 } lsm6dsox_reg_t; 01737 01738 /** 01739 * @} 01740 * 01741 */ 01742 01743 int32_t lsm6dsox_read_reg(lsm6dsox_ctx_t *ctx, uint8_t reg, uint8_t* data, 01744 uint16_t len); 01745 int32_t lsm6dsox_write_reg(lsm6dsox_ctx_t *ctx, uint8_t reg, uint8_t* data, 01746 uint16_t len); 01747 01748 extern float_t lsm6dsox_from_fs2_to_mg(int16_t lsb); 01749 extern float_t lsm6dsox_from_fs4_to_mg(int16_t lsb); 01750 extern float_t lsm6dsox_from_fs8_to_mg(int16_t lsb); 01751 extern float_t lsm6dsox_from_fs16_to_mg(int16_t lsb); 01752 extern float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb); 01753 extern float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb); 01754 extern float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb); 01755 extern float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb); 01756 extern float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb); 01757 extern float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb); 01758 extern float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb); 01759 01760 typedef enum { 01761 LSM6DSOX_2g = 0, 01762 LSM6DSOX_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSOX_2g */ 01763 LSM6DSOX_4g = 2, 01764 LSM6DSOX_8g = 3, 01765 } lsm6dsox_fs_xl_t; 01766 int32_t lsm6dsox_xl_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t val); 01767 int32_t lsm6dsox_xl_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t *val); 01768 01769 typedef enum { 01770 LSM6DSOX_XL_ODR_OFF = 0, 01771 LSM6DSOX_XL_ODR_12Hz5 = 1, 01772 LSM6DSOX_XL_ODR_26Hz = 2, 01773 LSM6DSOX_XL_ODR_52Hz = 3, 01774 LSM6DSOX_XL_ODR_104Hz = 4, 01775 LSM6DSOX_XL_ODR_208Hz = 5, 01776 LSM6DSOX_XL_ODR_417Hz = 6, 01777 LSM6DSOX_XL_ODR_833Hz = 7, 01778 LSM6DSOX_XL_ODR_1667Hz = 8, 01779 LSM6DSOX_XL_ODR_3333Hz = 9, 01780 LSM6DSOX_XL_ODR_6667Hz = 10, 01781 LSM6DSOX_XL_ODR_1Hz6 = 11, /* (low power only) */ 01782 } lsm6dsox_odr_xl_t; 01783 int32_t lsm6dsox_xl_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t val); 01784 int32_t lsm6dsox_xl_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t *val); 01785 01786 typedef enum { 01787 LSM6DSOX_250dps = 0, 01788 LSM6DSOX_125dps = 1, 01789 LSM6DSOX_500dps = 2, 01790 LSM6DSOX_1000dps = 4, 01791 LSM6DSOX_2000dps = 6, 01792 } lsm6dsox_fs_g_t; 01793 int32_t lsm6dsox_gy_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t val); 01794 int32_t lsm6dsox_gy_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t *val); 01795 01796 typedef enum { 01797 LSM6DSOX_GY_ODR_OFF = 0, 01798 LSM6DSOX_GY_ODR_12Hz5 = 1, 01799 LSM6DSOX_GY_ODR_26Hz = 2, 01800 LSM6DSOX_GY_ODR_52Hz = 3, 01801 LSM6DSOX_GY_ODR_104Hz = 4, 01802 LSM6DSOX_GY_ODR_208Hz = 5, 01803 LSM6DSOX_GY_ODR_417Hz = 6, 01804 LSM6DSOX_GY_ODR_833Hz = 7, 01805 LSM6DSOX_GY_ODR_1667Hz = 8, 01806 LSM6DSOX_GY_ODR_3333Hz = 9, 01807 LSM6DSOX_GY_ODR_6667Hz = 10, 01808 } lsm6dsox_odr_g_t; 01809 int32_t lsm6dsox_gy_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t val); 01810 int32_t lsm6dsox_gy_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t *val); 01811 01812 int32_t lsm6dsox_block_data_update_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01813 int32_t lsm6dsox_block_data_update_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01814 01815 typedef enum { 01816 LSM6DSOX_LSb_1mg = 0, 01817 LSM6DSOX_LSb_16mg = 1, 01818 } lsm6dsox_usr_off_w_t; 01819 int32_t lsm6dsox_xl_offset_weight_set(lsm6dsox_ctx_t *ctx, 01820 lsm6dsox_usr_off_w_t val); 01821 int32_t lsm6dsox_xl_offset_weight_get(lsm6dsox_ctx_t *ctx, 01822 lsm6dsox_usr_off_w_t *val); 01823 01824 typedef enum { 01825 LSM6DSOX_HIGH_PERFORMANCE_MD = 0, 01826 LSM6DSOX_LOW_NORMAL_POWER_MD = 1, 01827 LSM6DSOX_ULTRA_LOW_POWER_MD = 2, 01828 } lsm6dsox_xl_hm_mode_t; 01829 int32_t lsm6dsox_xl_power_mode_set(lsm6dsox_ctx_t *ctx, 01830 lsm6dsox_xl_hm_mode_t val); 01831 int32_t lsm6dsox_xl_power_mode_get(lsm6dsox_ctx_t *ctx, 01832 lsm6dsox_xl_hm_mode_t *val); 01833 01834 typedef enum { 01835 LSM6DSOX_GY_HIGH_PERFORMANCE = 0, 01836 LSM6DSOX_GY_NORMAL = 1, 01837 } lsm6dsox_g_hm_mode_t; 01838 int32_t lsm6dsox_gy_power_mode_set(lsm6dsox_ctx_t *ctx, 01839 lsm6dsox_g_hm_mode_t val); 01840 int32_t lsm6dsox_gy_power_mode_get(lsm6dsox_ctx_t *ctx, 01841 lsm6dsox_g_hm_mode_t *val); 01842 01843 int32_t lsm6dsox_status_reg_get(lsm6dsox_ctx_t *ctx, 01844 lsm6dsox_status_reg_t *val); 01845 01846 int32_t lsm6dsox_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01847 01848 int32_t lsm6dsox_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01849 01850 int32_t lsm6dsox_temp_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01851 01852 int32_t lsm6dsox_xl_usr_offset_x_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01853 int32_t lsm6dsox_xl_usr_offset_x_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01854 01855 int32_t lsm6dsox_xl_usr_offset_y_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01856 int32_t lsm6dsox_xl_usr_offset_y_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01857 01858 int32_t lsm6dsox_xl_usr_offset_z_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01859 int32_t lsm6dsox_xl_usr_offset_z_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01860 01861 int32_t lsm6dsox_xl_usr_offset_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01862 int32_t lsm6dsox_xl_usr_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01863 01864 int32_t lsm6dsox_timestamp_rst(lsm6dsox_ctx_t *ctx); 01865 01866 int32_t lsm6dsox_timestamp_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01867 int32_t lsm6dsox_timestamp_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01868 01869 int32_t lsm6dsox_timestamp_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01870 01871 typedef enum { 01872 LSM6DSOX_NO_ROUND = 0, 01873 LSM6DSOX_ROUND_XL = 1, 01874 LSM6DSOX_ROUND_GY = 2, 01875 LSM6DSOX_ROUND_GY_XL = 3, 01876 } lsm6dsox_rounding_t; 01877 int32_t lsm6dsox_rounding_mode_set(lsm6dsox_ctx_t *ctx, 01878 lsm6dsox_rounding_t val); 01879 int32_t lsm6dsox_rounding_mode_get(lsm6dsox_ctx_t *ctx, 01880 lsm6dsox_rounding_t *val); 01881 01882 typedef enum { 01883 LSM6DSOX_STAT_RND_DISABLE = 0, 01884 LSM6DSOX_STAT_RND_ENABLE = 1, 01885 } lsm6dsox_rounding_status_t; 01886 int32_t lsm6dsox_rounding_on_status_set(lsm6dsox_ctx_t *ctx, 01887 lsm6dsox_rounding_status_t val); 01888 int32_t lsm6dsox_rounding_on_status_get(lsm6dsox_ctx_t *ctx, 01889 lsm6dsox_rounding_status_t *val); 01890 01891 int32_t lsm6dsox_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01892 01893 int32_t lsm6dsox_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01894 01895 int32_t lsm6dsox_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01896 01897 int32_t lsm6dsox_fifo_out_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01898 01899 int32_t lsm6dsox_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01900 01901 int32_t lsm6dsox_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01902 01903 int32_t lsm6dsox_aux_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01904 01905 int32_t lsm6dsox_aux_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01906 01907 int32_t lsm6dsox_aux_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01908 01909 int32_t lsm6dsox_number_of_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01910 01911 int32_t lsm6dsox_steps_reset(lsm6dsox_ctx_t *ctx); 01912 01913 int32_t lsm6dsox_mlc_out_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01914 01915 int32_t lsm6dsox_odr_cal_reg_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01916 int32_t lsm6dsox_odr_cal_reg_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01917 01918 typedef enum { 01919 LSM6DSOX_USER_BANK = 0, 01920 LSM6DSOX_SENSOR_HUB_BANK = 1, 01921 LSM6DSOX_EMBEDDED_FUNC_BANK = 2, 01922 } lsm6dsox_reg_access_t; 01923 int32_t lsm6dsox_mem_bank_set(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t val); 01924 int32_t lsm6dsox_mem_bank_get(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t *val); 01925 01926 int32_t lsm6dsox_ln_pg_write_byte(lsm6dsox_ctx_t *ctx, uint16_t address, 01927 uint8_t *val); 01928 int32_t lsm6dsox_ln_pg_read_byte(lsm6dsox_ctx_t *ctx, uint16_t address, 01929 uint8_t *val); 01930 01931 int32_t lsm6dsox_ln_pg_write(lsm6dsox_ctx_t *ctx, uint16_t address, 01932 uint8_t *buf, uint8_t len); 01933 int32_t lsm6dsox_ln_pg_read(lsm6dsox_ctx_t *ctx, uint16_t address, 01934 uint8_t *val); 01935 01936 typedef enum { 01937 LSM6DSOX_DRDY_LATCHED = 0, 01938 LSM6DSOX_DRDY_PULSED = 1, 01939 } lsm6dsox_dataready_pulsed_t; 01940 int32_t lsm6dsox_data_ready_mode_set(lsm6dsox_ctx_t *ctx, 01941 lsm6dsox_dataready_pulsed_t val); 01942 int32_t lsm6dsox_data_ready_mode_get(lsm6dsox_ctx_t *ctx, 01943 lsm6dsox_dataready_pulsed_t *val); 01944 01945 int32_t lsm6dsox_device_id_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 01946 01947 int32_t lsm6dsox_reset_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01948 int32_t lsm6dsox_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01949 01950 int32_t lsm6dsox_auto_increment_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01951 int32_t lsm6dsox_auto_increment_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01952 01953 int32_t lsm6dsox_boot_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01954 int32_t lsm6dsox_boot_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01955 01956 typedef enum { 01957 LSM6DSOX_XL_ST_DISABLE = 0, 01958 LSM6DSOX_XL_ST_POSITIVE = 1, 01959 LSM6DSOX_XL_ST_NEGATIVE = 2, 01960 } lsm6dsox_st_xl_t; 01961 int32_t lsm6dsox_xl_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t val); 01962 int32_t lsm6dsox_xl_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t *val); 01963 01964 typedef enum { 01965 LSM6DSOX_GY_ST_DISABLE = 0, 01966 LSM6DSOX_GY_ST_POSITIVE = 1, 01967 LSM6DSOX_GY_ST_NEGATIVE = 3, 01968 } lsm6dsox_st_g_t; 01969 int32_t lsm6dsox_gy_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t val); 01970 int32_t lsm6dsox_gy_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t *val); 01971 01972 int32_t lsm6dsox_xl_filter_lp2_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01973 int32_t lsm6dsox_xl_filter_lp2_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01974 01975 int32_t lsm6dsox_gy_filter_lp1_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01976 int32_t lsm6dsox_gy_filter_lp1_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 01977 01978 int32_t lsm6dsox_filter_settling_mask_set(lsm6dsox_ctx_t *ctx, 01979 uint8_t val); 01980 int32_t lsm6dsox_filter_settling_mask_get(lsm6dsox_ctx_t *ctx, 01981 uint8_t *val); 01982 01983 typedef enum { 01984 LSM6DSOX_ULTRA_LIGHT = 0, 01985 LSM6DSOX_VERY_LIGHT = 1, 01986 LSM6DSOX_LIGHT = 2, 01987 LSM6DSOX_MEDIUM = 3, 01988 LSM6DSOX_STRONG = 4, 01989 LSM6DSOX_VERY_STRONG = 5, 01990 LSM6DSOX_AGGRESSIVE = 6, 01991 LSM6DSOX_XTREME = 7, 01992 } lsm6dsox_ftype_t; 01993 int32_t lsm6dsox_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, 01994 lsm6dsox_ftype_t val); 01995 int32_t lsm6dsox_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, 01996 lsm6dsox_ftype_t *val); 01997 01998 int32_t lsm6dsox_xl_lp2_on_6d_set(lsm6dsox_ctx_t *ctx, uint8_t val); 01999 int32_t lsm6dsox_xl_lp2_on_6d_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02000 02001 typedef enum { 02002 LSM6DSOX_HP_PATH_DISABLE_ON_OUT = 0x00, 02003 LSM6DSOX_SLOPE_ODR_DIV_4 = 0x10, 02004 LSM6DSOX_HP_ODR_DIV_10 = 0x11, 02005 LSM6DSOX_HP_ODR_DIV_20 = 0x12, 02006 LSM6DSOX_HP_ODR_DIV_45 = 0x13, 02007 LSM6DSOX_HP_ODR_DIV_100 = 0x14, 02008 LSM6DSOX_HP_ODR_DIV_200 = 0x15, 02009 LSM6DSOX_HP_ODR_DIV_400 = 0x16, 02010 LSM6DSOX_HP_ODR_DIV_800 = 0x17, 02011 LSM6DSOX_HP_REF_MD_ODR_DIV_10 = 0x31, 02012 LSM6DSOX_HP_REF_MD_ODR_DIV_20 = 0x32, 02013 LSM6DSOX_HP_REF_MD_ODR_DIV_45 = 0x33, 02014 LSM6DSOX_HP_REF_MD_ODR_DIV_100 = 0x34, 02015 LSM6DSOX_HP_REF_MD_ODR_DIV_200 = 0x35, 02016 LSM6DSOX_HP_REF_MD_ODR_DIV_400 = 0x36, 02017 LSM6DSOX_HP_REF_MD_ODR_DIV_800 = 0x37, 02018 LSM6DSOX_LP_ODR_DIV_10 = 0x01, 02019 LSM6DSOX_LP_ODR_DIV_20 = 0x02, 02020 LSM6DSOX_LP_ODR_DIV_45 = 0x03, 02021 LSM6DSOX_LP_ODR_DIV_100 = 0x04, 02022 LSM6DSOX_LP_ODR_DIV_200 = 0x05, 02023 LSM6DSOX_LP_ODR_DIV_400 = 0x06, 02024 LSM6DSOX_LP_ODR_DIV_800 = 0x07, 02025 } lsm6dsox_hp_slope_xl_en_t; 02026 int32_t lsm6dsox_xl_hp_path_on_out_set(lsm6dsox_ctx_t *ctx, 02027 lsm6dsox_hp_slope_xl_en_t val); 02028 int32_t lsm6dsox_xl_hp_path_on_out_get(lsm6dsox_ctx_t *ctx, 02029 lsm6dsox_hp_slope_xl_en_t *val); 02030 02031 int32_t lsm6dsox_xl_fast_settling_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02032 int32_t lsm6dsox_xl_fast_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02033 02034 typedef enum { 02035 LSM6DSOX_USE_SLOPE = 0, 02036 LSM6DSOX_USE_HPF = 1, 02037 } lsm6dsox_slope_fds_t; 02038 int32_t lsm6dsox_xl_hp_path_internal_set(lsm6dsox_ctx_t *ctx, 02039 lsm6dsox_slope_fds_t val); 02040 int32_t lsm6dsox_xl_hp_path_internal_get(lsm6dsox_ctx_t *ctx, 02041 lsm6dsox_slope_fds_t *val); 02042 02043 typedef enum { 02044 LSM6DSOX_HP_FILTER_NONE = 0x00, 02045 LSM6DSOX_HP_FILTER_16mHz = 0x80, 02046 LSM6DSOX_HP_FILTER_65mHz = 0x81, 02047 LSM6DSOX_HP_FILTER_260mHz = 0x82, 02048 LSM6DSOX_HP_FILTER_1Hz04 = 0x83, 02049 } lsm6dsox_hpm_g_t; 02050 int32_t lsm6dsox_gy_hp_path_internal_set(lsm6dsox_ctx_t *ctx, 02051 lsm6dsox_hpm_g_t val); 02052 int32_t lsm6dsox_gy_hp_path_internal_get(lsm6dsox_ctx_t *ctx, 02053 lsm6dsox_hpm_g_t *val); 02054 02055 typedef enum { 02056 LSM6DSOX_OIS_CTRL_AUX_DATA_UI = 0x00, 02057 LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX = 0x01, 02058 LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI = 0x02, 02059 LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX = 0x03, 02060 } lsm6dsox_spi2_read_en_t; 02061 int32_t lsm6dsox_ois_mode_set(lsm6dsox_ctx_t *ctx, 02062 lsm6dsox_spi2_read_en_t val); 02063 int32_t lsm6dsox_ois_mode_get(lsm6dsox_ctx_t *ctx, 02064 lsm6dsox_spi2_read_en_t *val); 02065 02066 typedef enum { 02067 LSM6DSOX_AUX_PULL_UP_DISC = 0, 02068 LSM6DSOX_AUX_PULL_UP_CONNECT = 1, 02069 } lsm6dsox_ois_pu_dis_t; 02070 int32_t lsm6dsox_aux_sdo_ocs_mode_set(lsm6dsox_ctx_t *ctx, 02071 lsm6dsox_ois_pu_dis_t val); 02072 int32_t lsm6dsox_aux_sdo_ocs_mode_get(lsm6dsox_ctx_t *ctx, 02073 lsm6dsox_ois_pu_dis_t *val); 02074 02075 typedef enum { 02076 LSM6DSOX_AUX_ON = 1, 02077 LSM6DSOX_AUX_ON_BY_AUX_INTERFACE = 0, 02078 } lsm6dsox_ois_on_t; 02079 int32_t lsm6dsox_aux_pw_on_ctrl_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t val); 02080 int32_t lsm6dsox_aux_pw_on_ctrl_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t *val); 02081 02082 typedef enum { 02083 LSM6DSOX_USE_SAME_XL_FS = 0, 02084 LSM6DSOX_USE_DIFFERENT_XL_FS = 1, 02085 } lsm6dsox_xl_fs_mode_t; 02086 int32_t lsm6dsox_aux_xl_fs_mode_set(lsm6dsox_ctx_t *ctx, 02087 lsm6dsox_xl_fs_mode_t val); 02088 int32_t lsm6dsox_aux_xl_fs_mode_get(lsm6dsox_ctx_t *ctx, 02089 lsm6dsox_xl_fs_mode_t *val); 02090 02091 int32_t lsm6dsox_aux_status_reg_get(lsm6dsox_ctx_t *ctx, 02092 lsm6dsox_spi2_status_reg_ois_t *val); 02093 02094 int32_t lsm6dsox_aux_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02095 02096 int32_t lsm6dsox_aux_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02097 02098 int32_t lsm6dsox_aux_gy_flag_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02099 02100 typedef enum { 02101 LSM6DSOX_AUX_DEN_ACTIVE_LOW = 0, 02102 LSM6DSOX_AUX_DEN_ACTIVE_HIGH = 1, 02103 } lsm6dsox_den_lh_ois_t; 02104 int32_t lsm6dsox_aux_den_polarity_set(lsm6dsox_ctx_t *ctx, 02105 lsm6dsox_den_lh_ois_t val); 02106 int32_t lsm6dsox_aux_den_polarity_get(lsm6dsox_ctx_t *ctx, 02107 lsm6dsox_den_lh_ois_t *val); 02108 02109 typedef enum { 02110 LSM6DSOX_AUX_DEN_DISABLE = 0, 02111 LSM6DSOX_AUX_DEN_LEVEL_LATCH = 3, 02112 LSM6DSOX_AUX_DEN_LEVEL_TRIG = 2, 02113 } lsm6dsox_lvl2_ois_t; 02114 int32_t lsm6dsox_aux_den_mode_set(lsm6dsox_ctx_t *ctx, 02115 lsm6dsox_lvl2_ois_t val); 02116 int32_t lsm6dsox_aux_den_mode_get(lsm6dsox_ctx_t *ctx, 02117 lsm6dsox_lvl2_ois_t *val); 02118 02119 int32_t lsm6dsox_aux_drdy_on_int2_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02120 int32_t lsm6dsox_aux_drdy_on_int2_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02121 02122 typedef enum { 02123 LSM6DSOX_AUX_DISABLE = 0, 02124 LSM6DSOX_MODE_3_GY = 1, 02125 LSM6DSOX_MODE_4_GY_XL = 3, 02126 } lsm6dsox_ois_en_spi2_t; 02127 int32_t lsm6dsox_aux_mode_set(lsm6dsox_ctx_t *ctx, 02128 lsm6dsox_ois_en_spi2_t val); 02129 int32_t lsm6dsox_aux_mode_get(lsm6dsox_ctx_t *ctx, 02130 lsm6dsox_ois_en_spi2_t *val); 02131 02132 typedef enum { 02133 LSM6DSOX_250dps_AUX = 0, 02134 LSM6DSOX_125dps_AUX = 1, 02135 LSM6DSOX_500dps_AUX = 2, 02136 LSM6DSOX_1000dps_AUX = 4, 02137 LSM6DSOX_2000dps_AUX = 6, 02138 } lsm6dsox_fs_g_ois_t; 02139 int32_t lsm6dsox_aux_gy_full_scale_set(lsm6dsox_ctx_t *ctx, 02140 lsm6dsox_fs_g_ois_t val); 02141 int32_t lsm6dsox_aux_gy_full_scale_get(lsm6dsox_ctx_t *ctx, 02142 lsm6dsox_fs_g_ois_t *val); 02143 02144 typedef enum { 02145 LSM6DSOX_AUX_SPI_4_WIRE = 0, 02146 LSM6DSOX_AUX_SPI_3_WIRE = 1, 02147 } lsm6dsox_sim_ois_t; 02148 int32_t lsm6dsox_aux_spi_mode_set(lsm6dsox_ctx_t *ctx, 02149 lsm6dsox_sim_ois_t val); 02150 int32_t lsm6dsox_aux_spi_mode_get(lsm6dsox_ctx_t *ctx, 02151 lsm6dsox_sim_ois_t *val); 02152 02153 typedef enum { 02154 LSM6DSOX_351Hz39 = 0, 02155 LSM6DSOX_236Hz63 = 1, 02156 LSM6DSOX_172Hz70 = 2, 02157 LSM6DSOX_937Hz91 = 3, 02158 } lsm6dsox_ftype_ois_t; 02159 int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, 02160 lsm6dsox_ftype_ois_t val); 02161 int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, 02162 lsm6dsox_ftype_ois_t *val); 02163 02164 typedef enum { 02165 LSM6DSOX_AUX_HP_DISABLE = 0x00, 02166 LSM6DSOX_AUX_HP_Hz016 = 0x10, 02167 LSM6DSOX_AUX_HP_Hz065 = 0x11, 02168 LSM6DSOX_AUX_HP_Hz260 = 0x12, 02169 LSM6DSOX_AUX_HP_1Hz040 = 0x13, 02170 } lsm6dsox_hpm_ois_t; 02171 int32_t lsm6dsox_aux_gy_hp_bandwidth_set(lsm6dsox_ctx_t *ctx, 02172 lsm6dsox_hpm_ois_t val); 02173 int32_t lsm6dsox_aux_gy_hp_bandwidth_get(lsm6dsox_ctx_t *ctx, 02174 lsm6dsox_hpm_ois_t *val); 02175 02176 typedef enum { 02177 LSM6DSOX_ENABLE_CLAMP = 0, 02178 LSM6DSOX_DISABLE_CLAMP = 1, 02179 } lsm6dsox_st_ois_clampdis_t; 02180 int32_t lsm6dsox_aux_gy_clamp_set(lsm6dsox_ctx_t *ctx, 02181 lsm6dsox_st_ois_clampdis_t val); 02182 int32_t lsm6dsox_aux_gy_clamp_get(lsm6dsox_ctx_t *ctx, 02183 lsm6dsox_st_ois_clampdis_t *val); 02184 02185 typedef enum { 02186 LSM6DSOX_289Hz = 0, 02187 LSM6DSOX_258Hz = 1, 02188 LSM6DSOX_120Hz = 2, 02189 LSM6DSOX_65Hz2 = 3, 02190 LSM6DSOX_33Hz2 = 4, 02191 LSM6DSOX_16Hz6 = 5, 02192 LSM6DSOX_8Hz30 = 6, 02193 LSM6DSOX_4Hz15 = 7, 02194 } lsm6dsox_filter_xl_conf_ois_t; 02195 int32_t lsm6dsox_aux_xl_bandwidth_set(lsm6dsox_ctx_t *ctx, 02196 lsm6dsox_filter_xl_conf_ois_t val); 02197 int32_t lsm6dsox_aux_xl_bandwidth_get(lsm6dsox_ctx_t *ctx, 02198 lsm6dsox_filter_xl_conf_ois_t *val); 02199 02200 typedef enum { 02201 LSM6DSOX_AUX_2g = 0, 02202 LSM6DSOX_AUX_16g = 1, 02203 LSM6DSOX_AUX_4g = 2, 02204 LSM6DSOX_AUX_8g = 3, 02205 } lsm6dsox_fs_xl_ois_t; 02206 int32_t lsm6dsox_aux_xl_full_scale_set(lsm6dsox_ctx_t *ctx, 02207 lsm6dsox_fs_xl_ois_t val); 02208 int32_t lsm6dsox_aux_xl_full_scale_get(lsm6dsox_ctx_t *ctx, 02209 lsm6dsox_fs_xl_ois_t *val); 02210 02211 typedef enum { 02212 LSM6DSOX_PULL_UP_DISC = 0, 02213 LSM6DSOX_PULL_UP_CONNECT = 1, 02214 } lsm6dsox_sdo_pu_en_t; 02215 int32_t lsm6dsox_sdo_sa0_mode_set(lsm6dsox_ctx_t *ctx, 02216 lsm6dsox_sdo_pu_en_t val); 02217 int32_t lsm6dsox_sdo_sa0_mode_get(lsm6dsox_ctx_t *ctx, 02218 lsm6dsox_sdo_pu_en_t *val); 02219 02220 typedef enum { 02221 LSM6DSOX_SPI_4_WIRE = 0, 02222 LSM6DSOX_SPI_3_WIRE = 1, 02223 } lsm6dsox_sim_t; 02224 int32_t lsm6dsox_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t val); 02225 int32_t lsm6dsox_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t *val); 02226 02227 typedef enum { 02228 LSM6DSOX_I2C_ENABLE = 0, 02229 LSM6DSOX_I2C_DISABLE = 1, 02230 } lsm6dsox_i2c_disable_t; 02231 int32_t lsm6dsox_i2c_interface_set(lsm6dsox_ctx_t *ctx, 02232 lsm6dsox_i2c_disable_t val); 02233 int32_t lsm6dsox_i2c_interface_get(lsm6dsox_ctx_t *ctx, 02234 lsm6dsox_i2c_disable_t *val); 02235 02236 typedef enum { 02237 LSM6DSOX_I3C_DISABLE = 0x80, 02238 LSM6DSOX_I3C_ENABLE_T_50us = 0x00, 02239 LSM6DSOX_I3C_ENABLE_T_2us = 0x01, 02240 LSM6DSOX_I3C_ENABLE_T_1ms = 0x02, 02241 LSM6DSOX_I3C_ENABLE_T_25ms = 0x03, 02242 } lsm6dsox_i3c_disable_t; 02243 int32_t lsm6dsox_i3c_disable_set(lsm6dsox_ctx_t *ctx, 02244 lsm6dsox_i3c_disable_t val); 02245 int32_t lsm6dsox_i3c_disable_get(lsm6dsox_ctx_t *ctx, 02246 lsm6dsox_i3c_disable_t *val); 02247 02248 typedef enum { 02249 LSM6DSOX_PUSH_PULL = 0x00, 02250 LSM6DSOX_OPEN_DRAIN = 0x01, 02251 LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, 02252 LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, 02253 } lsm6dsox_pp_od_t; 02254 int32_t lsm6dsox_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t val); 02255 int32_t lsm6dsox_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t *val); 02256 02257 typedef enum { 02258 LSM6DSOX_ACTIVE_HIGH = 0, 02259 LSM6DSOX_ACTIVE_LOW = 1, 02260 } lsm6dsox_h_lactive_t; 02261 int32_t lsm6dsox_pin_polarity_set(lsm6dsox_ctx_t *ctx, 02262 lsm6dsox_h_lactive_t val); 02263 int32_t lsm6dsox_pin_polarity_get(lsm6dsox_ctx_t *ctx, 02264 lsm6dsox_h_lactive_t *val); 02265 02266 int32_t lsm6dsox_all_on_int1_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02267 int32_t lsm6dsox_all_on_int1_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02268 02269 typedef enum { 02270 LSM6DSOX_ALL_INT_PULSED = 0, 02271 LSM6DSOX_BASE_LATCHED_EMB_PULSED = 1, 02272 LSM6DSOX_BASE_PULSED_EMB_LATCHED = 2, 02273 LSM6DSOX_ALL_INT_LATCHED = 3, 02274 } lsm6dsox_lir_t; 02275 int32_t lsm6dsox_int_notification_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t val); 02276 int32_t lsm6dsox_int_notification_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t *val); 02277 02278 typedef enum { 02279 LSM6DSOX_LSb_FS_DIV_64 = 0, 02280 LSM6DSOX_LSb_FS_DIV_256 = 1, 02281 } lsm6dsox_wake_ths_w_t; 02282 int32_t lsm6dsox_wkup_ths_weight_set(lsm6dsox_ctx_t *ctx, 02283 lsm6dsox_wake_ths_w_t val); 02284 int32_t lsm6dsox_wkup_ths_weight_get(lsm6dsox_ctx_t *ctx, 02285 lsm6dsox_wake_ths_w_t *val); 02286 02287 int32_t lsm6dsox_wkup_threshold_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02288 int32_t lsm6dsox_wkup_threshold_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02289 02290 int32_t lsm6dsox_xl_usr_offset_on_wkup_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02291 int32_t lsm6dsox_xl_usr_offset_on_wkup_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02292 02293 int32_t lsm6dsox_wkup_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02294 int32_t lsm6dsox_wkup_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02295 02296 int32_t lsm6dsox_gy_sleep_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02297 int32_t lsm6dsox_gy_sleep_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02298 02299 typedef enum { 02300 LSM6DSOX_DRIVE_SLEEP_CHG_EVENT = 0, 02301 LSM6DSOX_DRIVE_SLEEP_STATUS = 1, 02302 } lsm6dsox_sleep_status_on_int_t; 02303 int32_t lsm6dsox_act_pin_notification_set(lsm6dsox_ctx_t *ctx, 02304 lsm6dsox_sleep_status_on_int_t val); 02305 int32_t lsm6dsox_act_pin_notification_get(lsm6dsox_ctx_t *ctx, 02306 lsm6dsox_sleep_status_on_int_t *val); 02307 02308 typedef enum { 02309 LSM6DSOX_XL_AND_GY_NOT_AFFECTED = 0, 02310 LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED = 1, 02311 LSM6DSOX_XL_12Hz5_GY_SLEEP = 2, 02312 LSM6DSOX_XL_12Hz5_GY_PD = 3, 02313 } lsm6dsox_inact_en_t; 02314 int32_t lsm6dsox_act_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t val); 02315 int32_t lsm6dsox_act_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t *val); 02316 02317 int32_t lsm6dsox_act_sleep_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02318 int32_t lsm6dsox_act_sleep_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02319 02320 int32_t lsm6dsox_tap_detection_on_z_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02321 int32_t lsm6dsox_tap_detection_on_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02322 02323 int32_t lsm6dsox_tap_detection_on_y_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02324 int32_t lsm6dsox_tap_detection_on_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02325 02326 int32_t lsm6dsox_tap_detection_on_x_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02327 int32_t lsm6dsox_tap_detection_on_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02328 02329 int32_t lsm6dsox_tap_threshold_x_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02330 int32_t lsm6dsox_tap_threshold_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02331 02332 typedef enum { 02333 LSM6DSOX_XYZ = 0, 02334 LSM6DSOX_YXZ = 1, 02335 LSM6DSOX_XZY = 2, 02336 LSM6DSOX_ZYX = 3, 02337 LSM6DSOX_YZX = 5, 02338 LSM6DSOX_ZXY = 6, 02339 } lsm6dsox_tap_priority_t; 02340 int32_t lsm6dsox_tap_axis_priority_set(lsm6dsox_ctx_t *ctx, 02341 lsm6dsox_tap_priority_t val); 02342 int32_t lsm6dsox_tap_axis_priority_get(lsm6dsox_ctx_t *ctx, 02343 lsm6dsox_tap_priority_t *val); 02344 02345 int32_t lsm6dsox_tap_threshold_y_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02346 int32_t lsm6dsox_tap_threshold_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02347 02348 int32_t lsm6dsox_tap_threshold_z_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02349 int32_t lsm6dsox_tap_threshold_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02350 02351 int32_t lsm6dsox_tap_shock_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02352 int32_t lsm6dsox_tap_shock_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02353 02354 int32_t lsm6dsox_tap_quiet_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02355 int32_t lsm6dsox_tap_quiet_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02356 02357 int32_t lsm6dsox_tap_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02358 int32_t lsm6dsox_tap_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02359 02360 typedef enum { 02361 LSM6DSOX_ONLY_SINGLE = 0, 02362 LSM6DSOX_BOTH_SINGLE_DOUBLE = 1, 02363 } lsm6dsox_single_double_tap_t; 02364 int32_t lsm6dsox_tap_mode_set(lsm6dsox_ctx_t *ctx, 02365 lsm6dsox_single_double_tap_t val); 02366 int32_t lsm6dsox_tap_mode_get(lsm6dsox_ctx_t *ctx, 02367 lsm6dsox_single_double_tap_t *val); 02368 02369 typedef enum { 02370 LSM6DSOX_DEG_80 = 0, 02371 LSM6DSOX_DEG_70 = 1, 02372 LSM6DSOX_DEG_60 = 2, 02373 LSM6DSOX_DEG_50 = 3, 02374 } lsm6dsox_sixd_ths_t; 02375 int32_t lsm6dsox_6d_threshold_set(lsm6dsox_ctx_t *ctx, 02376 lsm6dsox_sixd_ths_t val); 02377 int32_t lsm6dsox_6d_threshold_get(lsm6dsox_ctx_t *ctx, 02378 lsm6dsox_sixd_ths_t *val); 02379 02380 int32_t lsm6dsox_4d_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02381 int32_t lsm6dsox_4d_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02382 02383 typedef enum { 02384 LSM6DSOX_FF_TSH_156mg = 0, 02385 LSM6DSOX_FF_TSH_219mg = 1, 02386 LSM6DSOX_FF_TSH_250mg = 2, 02387 LSM6DSOX_FF_TSH_312mg = 3, 02388 LSM6DSOX_FF_TSH_344mg = 4, 02389 LSM6DSOX_FF_TSH_406mg = 5, 02390 LSM6DSOX_FF_TSH_469mg = 6, 02391 LSM6DSOX_FF_TSH_500mg = 7, 02392 } lsm6dsox_ff_ths_t; 02393 int32_t lsm6dsox_ff_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t val); 02394 int32_t lsm6dsox_ff_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t *val); 02395 02396 int32_t lsm6dsox_ff_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02397 int32_t lsm6dsox_ff_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02398 02399 int32_t lsm6dsox_fifo_watermark_set(lsm6dsox_ctx_t *ctx, uint16_t val); 02400 int32_t lsm6dsox_fifo_watermark_get(lsm6dsox_ctx_t *ctx, uint16_t *val); 02401 02402 int32_t lsm6dsox_compression_algo_init_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02403 int32_t lsm6dsox_compression_algo_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02404 02405 typedef enum { 02406 LSM6DSOX_CMP_DISABLE = 0x00, 02407 LSM6DSOX_CMP_ALWAYS = 0x04, 02408 LSM6DSOX_CMP_8_TO_1 = 0x05, 02409 LSM6DSOX_CMP_16_TO_1 = 0x06, 02410 LSM6DSOX_CMP_32_TO_1 = 0x07, 02411 } lsm6dsox_uncoptr_rate_t; 02412 int32_t lsm6dsox_compression_algo_set(lsm6dsox_ctx_t *ctx, 02413 lsm6dsox_uncoptr_rate_t val); 02414 int32_t lsm6dsox_compression_algo_get(lsm6dsox_ctx_t *ctx, 02415 lsm6dsox_uncoptr_rate_t *val); 02416 02417 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(lsm6dsox_ctx_t *ctx, 02418 uint8_t val); 02419 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(lsm6dsox_ctx_t *ctx, 02420 uint8_t *val); 02421 02422 int32_t lsm6dsox_compression_algo_real_time_set(lsm6dsox_ctx_t *ctx, 02423 uint8_t val); 02424 int32_t lsm6dsox_compression_algo_real_time_get(lsm6dsox_ctx_t *ctx, 02425 uint8_t *val); 02426 02427 int32_t lsm6dsox_fifo_stop_on_wtm_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02428 int32_t lsm6dsox_fifo_stop_on_wtm_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02429 02430 typedef enum { 02431 LSM6DSOX_XL_NOT_BATCHED = 0, 02432 LSM6DSOX_XL_BATCHED_AT_12Hz5 = 1, 02433 LSM6DSOX_XL_BATCHED_AT_26Hz = 2, 02434 LSM6DSOX_XL_BATCHED_AT_52Hz = 3, 02435 LSM6DSOX_XL_BATCHED_AT_104Hz = 4, 02436 LSM6DSOX_XL_BATCHED_AT_208Hz = 5, 02437 LSM6DSOX_XL_BATCHED_AT_417Hz = 6, 02438 LSM6DSOX_XL_BATCHED_AT_833Hz = 7, 02439 LSM6DSOX_XL_BATCHED_AT_1667Hz = 8, 02440 LSM6DSOX_XL_BATCHED_AT_3333Hz = 9, 02441 LSM6DSOX_XL_BATCHED_AT_6667Hz = 10, 02442 LSM6DSOX_XL_BATCHED_AT_6Hz5 = 11, 02443 } lsm6dsox_bdr_xl_t; 02444 int32_t lsm6dsox_fifo_xl_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t val); 02445 int32_t lsm6dsox_fifo_xl_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t *val); 02446 02447 typedef enum { 02448 LSM6DSOX_GY_NOT_BATCHED = 0, 02449 LSM6DSOX_GY_BATCHED_AT_12Hz5 = 1, 02450 LSM6DSOX_GY_BATCHED_AT_26Hz = 2, 02451 LSM6DSOX_GY_BATCHED_AT_52Hz = 3, 02452 LSM6DSOX_GY_BATCHED_AT_104Hz = 4, 02453 LSM6DSOX_GY_BATCHED_AT_208Hz = 5, 02454 LSM6DSOX_GY_BATCHED_AT_417Hz = 6, 02455 LSM6DSOX_GY_BATCHED_AT_833Hz = 7, 02456 LSM6DSOX_GY_BATCHED_AT_1667Hz = 8, 02457 LSM6DSOX_GY_BATCHED_AT_3333Hz = 9, 02458 LSM6DSOX_GY_BATCHED_AT_6667Hz = 10, 02459 LSM6DSOX_GY_BATCHED_AT_6Hz5 = 11, 02460 } lsm6dsox_bdr_gy_t; 02461 int32_t lsm6dsox_fifo_gy_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t val); 02462 int32_t lsm6dsox_fifo_gy_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t *val); 02463 02464 typedef enum { 02465 LSM6DSOX_BYPASS_MODE = 0, 02466 LSM6DSOX_FIFO_MODE = 1, 02467 LSM6DSOX_STREAM_TO_FIFO_MODE = 3, 02468 LSM6DSOX_BYPASS_TO_STREAM_MODE = 4, 02469 LSM6DSOX_STREAM_MODE = 6, 02470 LSM6DSOX_BYPASS_TO_FIFO_MODE = 7, 02471 } lsm6dsox_fifo_mode_t; 02472 int32_t lsm6dsox_fifo_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t val); 02473 int32_t lsm6dsox_fifo_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t *val); 02474 02475 typedef enum { 02476 LSM6DSOX_TEMP_NOT_BATCHED = 0, 02477 LSM6DSOX_TEMP_BATCHED_AT_1Hz6 = 1, 02478 LSM6DSOX_TEMP_BATCHED_AT_12Hz5 = 2, 02479 LSM6DSOX_TEMP_BATCHED_AT_52Hz = 3, 02480 } lsm6dsox_odr_t_batch_t; 02481 int32_t lsm6dsox_fifo_temp_batch_set(lsm6dsox_ctx_t *ctx, 02482 lsm6dsox_odr_t_batch_t val); 02483 int32_t lsm6dsox_fifo_temp_batch_get(lsm6dsox_ctx_t *ctx, 02484 lsm6dsox_odr_t_batch_t *val); 02485 02486 typedef enum { 02487 LSM6DSOX_NO_DECIMATION = 0, 02488 LSM6DSOX_DEC_1 = 1, 02489 LSM6DSOX_DEC_8 = 2, 02490 LSM6DSOX_DEC_32 = 3, 02491 } lsm6dsox_odr_ts_batch_t; 02492 int32_t lsm6dsox_fifo_timestamp_decimation_set(lsm6dsox_ctx_t *ctx, 02493 lsm6dsox_odr_ts_batch_t val); 02494 int32_t lsm6dsox_fifo_timestamp_decimation_get(lsm6dsox_ctx_t *ctx, 02495 lsm6dsox_odr_ts_batch_t *val); 02496 02497 typedef enum { 02498 LSM6DSOX_XL_BATCH_EVENT = 0, 02499 LSM6DSOX_GYRO_BATCH_EVENT = 1, 02500 } lsm6dsox_trig_counter_bdr_t; 02501 02502 typedef enum { 02503 LSM6DSOX_GYRO_NC_TAG = 1, 02504 LSM6DSOX_XL_NC_TAG, 02505 LSM6DSOX_TEMPERATURE_TAG, 02506 LSM6DSOX_TIMESTAMP_TAG, 02507 LSM6DSOX_CFG_CHANGE_TAG, 02508 LSM6DSOX_XL_NC_T_2_TAG, 02509 LSM6DSOX_XL_NC_T_1_TAG, 02510 LSM6DSOX_XL_2XC_TAG, 02511 LSM6DSOX_XL_3XC_TAG, 02512 LSM6DSOX_GYRO_NC_T_2_TAG, 02513 LSM6DSOX_GYRO_NC_T_1_TAG, 02514 LSM6DSOX_GYRO_2XC_TAG, 02515 LSM6DSOX_GYRO_3XC_TAG, 02516 LSM6DSOX_SENSORHUB_SLAVE0_TAG, 02517 LSM6DSOX_SENSORHUB_SLAVE1_TAG, 02518 LSM6DSOX_SENSORHUB_SLAVE2_TAG, 02519 LSM6DSOX_SENSORHUB_SLAVE3_TAG, 02520 LSM6DSOX_STEP_CPUNTER_TAG, 02521 LSM6DSOX_GAME_ROTATION_TAG, 02522 LSM6DSOX_GEOMAG_ROTATION_TAG, 02523 LSM6DSOX_ROTATION_TAG, 02524 LSM6DSOX_SENSORHUB_NACK_TAG = 0x19, 02525 } lsm6dsox_fifo_tag_t; 02526 int32_t lsm6dsox_fifo_cnt_event_batch_set(lsm6dsox_ctx_t *ctx, 02527 lsm6dsox_trig_counter_bdr_t val); 02528 int32_t lsm6dsox_fifo_cnt_event_batch_get(lsm6dsox_ctx_t *ctx, 02529 lsm6dsox_trig_counter_bdr_t *val); 02530 02531 int32_t lsm6dsox_rst_batch_counter_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02532 int32_t lsm6dsox_rst_batch_counter_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02533 02534 int32_t lsm6dsox_batch_counter_threshold_set(lsm6dsox_ctx_t *ctx, 02535 uint16_t val); 02536 int32_t lsm6dsox_batch_counter_threshold_get(lsm6dsox_ctx_t *ctx, 02537 uint16_t *val); 02538 02539 int32_t lsm6dsox_fifo_data_level_get(lsm6dsox_ctx_t *ctx, uint16_t *val); 02540 02541 int32_t lsm6dsox_fifo_status_get(lsm6dsox_ctx_t *ctx, 02542 lsm6dsox_fifo_status2_t *val); 02543 02544 int32_t lsm6dsox_fifo_full_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02545 02546 int32_t lsm6dsox_fifo_ovr_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02547 02548 int32_t lsm6dsox_fifo_wtm_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02549 02550 int32_t lsm6dsox_fifo_sensor_tag_get(lsm6dsox_ctx_t *ctx, 02551 lsm6dsox_fifo_tag_t *val); 02552 02553 int32_t lsm6dsox_fifo_pedo_batch_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02554 int32_t lsm6dsox_fifo_pedo_batch_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02555 02556 int32_t lsm6dsox_sh_batch_slave_0_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02557 int32_t lsm6dsox_sh_batch_slave_0_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02558 02559 int32_t lsm6dsox_sh_batch_slave_1_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02560 int32_t lsm6dsox_sh_batch_slave_1_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02561 02562 int32_t lsm6dsox_sh_batch_slave_2_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02563 int32_t lsm6dsox_sh_batch_slave_2_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02564 02565 int32_t lsm6dsox_sh_batch_slave_3_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02566 int32_t lsm6dsox_sh_batch_slave_3_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02567 02568 typedef enum { 02569 LSM6DSOX_DEN_DISABLE = 0, 02570 LSM6DSOX_LEVEL_FIFO = 6, 02571 LSM6DSOX_LEVEL_LETCHED = 3, 02572 LSM6DSOX_LEVEL_TRIGGER = 2, 02573 LSM6DSOX_EDGE_TRIGGER = 4, 02574 } lsm6dsox_den_mode_t; 02575 int32_t lsm6dsox_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t val); 02576 int32_t lsm6dsox_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t *val); 02577 02578 typedef enum { 02579 LSM6DSOX_DEN_ACT_LOW = 0, 02580 LSM6DSOX_DEN_ACT_HIGH = 1, 02581 } lsm6dsox_den_lh_t; 02582 int32_t lsm6dsox_den_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t val); 02583 int32_t lsm6dsox_den_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t *val); 02584 02585 typedef enum { 02586 LSM6DSOX_STAMP_IN_GY_DATA = 0, 02587 LSM6DSOX_STAMP_IN_XL_DATA = 1, 02588 LSM6DSOX_STAMP_IN_GY_XL_DATA = 2, 02589 } lsm6dsox_den_xl_g_t; 02590 int32_t lsm6dsox_den_enable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t val); 02591 int32_t lsm6dsox_den_enable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t *val); 02592 02593 int32_t lsm6dsox_den_mark_axis_x_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02594 int32_t lsm6dsox_den_mark_axis_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02595 02596 int32_t lsm6dsox_den_mark_axis_y_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02597 int32_t lsm6dsox_den_mark_axis_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02598 02599 int32_t lsm6dsox_den_mark_axis_z_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02600 int32_t lsm6dsox_den_mark_axis_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02601 02602 typedef enum { 02603 LSM6DSOX_PEDO_BASE_MODE = 0x00, 02604 LSM6DSOX_FALSE_STEP_REJ = 0x10, 02605 LSM6DSOX_FALSE_STEP_REJ_ADV_MODE = 0x30, 02606 } lsm6dsox_pedo_md_t; 02607 int32_t lsm6dsox_pedo_sens_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t val); 02608 int32_t lsm6dsox_pedo_sens_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t *val); 02609 02610 int32_t lsm6dsox_pedo_step_detect_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02611 02612 int32_t lsm6dsox_pedo_debounce_steps_set(lsm6dsox_ctx_t *ctx, 02613 uint8_t *buff); 02614 int32_t lsm6dsox_pedo_debounce_steps_get(lsm6dsox_ctx_t *ctx, 02615 uint8_t *buff); 02616 02617 int32_t lsm6dsox_pedo_steps_period_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02618 int32_t lsm6dsox_pedo_steps_period_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02619 02620 int32_t lsm6dsox_pedo_adv_detection_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02621 int32_t lsm6dsox_pedo_adv_detection_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02622 02623 int32_t lsm6dsox_pedo_false_step_rejection_set(lsm6dsox_ctx_t *ctx, 02624 uint8_t val); 02625 int32_t lsm6dsox_pedo_false_step_rejection_get(lsm6dsox_ctx_t *ctx, 02626 uint8_t *val); 02627 02628 typedef enum { 02629 LSM6DSOX_EVERY_STEP = 0, 02630 LSM6DSOX_COUNT_OVERFLOW = 1, 02631 } lsm6dsox_carry_count_en_t; 02632 int32_t lsm6dsox_pedo_int_mode_set(lsm6dsox_ctx_t *ctx, 02633 lsm6dsox_carry_count_en_t val); 02634 int32_t lsm6dsox_pedo_int_mode_get(lsm6dsox_ctx_t *ctx, 02635 lsm6dsox_carry_count_en_t *val); 02636 02637 int32_t lsm6dsox_motion_flag_data_ready_get(lsm6dsox_ctx_t *ctx, 02638 uint8_t *val); 02639 02640 int32_t lsm6dsox_tilt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, 02641 uint8_t *val); 02642 02643 int32_t lsm6dsox_sh_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02644 int32_t lsm6dsox_sh_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02645 02646 int32_t lsm6dsox_mlc_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02647 int32_t lsm6dsox_mlc_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02648 02649 int32_t lsm6dsox_mag_offset_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02650 int32_t lsm6dsox_mag_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02651 02652 int32_t lsm6dsox_mag_soft_iron_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02653 int32_t lsm6dsox_mag_soft_iron_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02654 02655 typedef enum { 02656 LSM6DSOX_Z_EQ_Y = 0, 02657 LSM6DSOX_Z_EQ_MIN_Y = 1, 02658 LSM6DSOX_Z_EQ_X = 2, 02659 LSM6DSOX_Z_EQ_MIN_X = 3, 02660 LSM6DSOX_Z_EQ_MIN_Z = 4, 02661 LSM6DSOX_Z_EQ_Z = 5, 02662 } lsm6dsox_mag_z_axis_t; 02663 int32_t lsm6dsox_mag_z_orient_set(lsm6dsox_ctx_t *ctx, 02664 lsm6dsox_mag_z_axis_t val); 02665 int32_t lsm6dsox_mag_z_orient_get(lsm6dsox_ctx_t *ctx, 02666 lsm6dsox_mag_z_axis_t *val); 02667 02668 typedef enum { 02669 LSM6DSOX_Y_EQ_Y = 0, 02670 LSM6DSOX_Y_EQ_MIN_Y = 1, 02671 LSM6DSOX_Y_EQ_X = 2, 02672 LSM6DSOX_Y_EQ_MIN_X = 3, 02673 LSM6DSOX_Y_EQ_MIN_Z = 4, 02674 LSM6DSOX_Y_EQ_Z = 5, 02675 } lsm6dsox_mag_y_axis_t; 02676 int32_t lsm6dsox_mag_y_orient_set(lsm6dsox_ctx_t *ctx, 02677 lsm6dsox_mag_y_axis_t val); 02678 int32_t lsm6dsox_mag_y_orient_get(lsm6dsox_ctx_t *ctx, 02679 lsm6dsox_mag_y_axis_t *val); 02680 02681 typedef enum { 02682 LSM6DSOX_X_EQ_Y = 0, 02683 LSM6DSOX_X_EQ_MIN_Y = 1, 02684 LSM6DSOX_X_EQ_X = 2, 02685 LSM6DSOX_X_EQ_MIN_X = 3, 02686 LSM6DSOX_X_EQ_MIN_Z = 4, 02687 LSM6DSOX_X_EQ_Z = 5, 02688 } lsm6dsox_mag_x_axis_t; 02689 int32_t lsm6dsox_mag_x_orient_set(lsm6dsox_ctx_t *ctx, 02690 lsm6dsox_mag_x_axis_t val); 02691 int32_t lsm6dsox_mag_x_orient_get(lsm6dsox_ctx_t *ctx, 02692 lsm6dsox_mag_x_axis_t *val); 02693 02694 int32_t lsm6dsox_long_cnt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, 02695 uint8_t *val); 02696 02697 typedef struct { 02698 lsm6dsox_fsm_enable_a_t fsm_enable_a; 02699 lsm6dsox_fsm_enable_b_t fsm_enable_b; 02700 } lsm6dsox_emb_fsm_enable_t; 02701 int32_t lsm6dsox_fsm_enable_set(lsm6dsox_ctx_t *ctx, 02702 lsm6dsox_emb_fsm_enable_t *val); 02703 int32_t lsm6dsox_fsm_enable_get(lsm6dsox_ctx_t *ctx, 02704 lsm6dsox_emb_fsm_enable_t *val); 02705 02706 int32_t lsm6dsox_long_cnt_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02707 int32_t lsm6dsox_long_cnt_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); 02708 02709 typedef enum { 02710 LSM6DSOX_LC_NORMAL = 0, 02711 LSM6DSOX_LC_CLEAR = 1, 02712 LSM6DSOX_LC_CLEAR_DONE = 2, 02713 } lsm6dsox_fsm_lc_clr_t; 02714 int32_t lsm6dsox_long_clr_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val); 02715 int32_t lsm6dsox_long_clr_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val); 02716 02717 typedef struct { 02718 lsm6dsox_fsm_outs1_t fsm_outs1; 02719 lsm6dsox_fsm_outs2_t fsm_outs2; 02720 lsm6dsox_fsm_outs3_t fsm_outs3; 02721 lsm6dsox_fsm_outs4_t fsm_outs4; 02722 lsm6dsox_fsm_outs5_t fsm_outs5; 02723 lsm6dsox_fsm_outs6_t fsm_outs6; 02724 lsm6dsox_fsm_outs7_t fsm_outs7; 02725 lsm6dsox_fsm_outs8_t fsm_outs8; 02726 lsm6dsox_fsm_outs1_t fsm_outs9; 02727 lsm6dsox_fsm_outs2_t fsm_outs10; 02728 lsm6dsox_fsm_outs3_t fsm_outs11; 02729 lsm6dsox_fsm_outs4_t fsm_outs12; 02730 lsm6dsox_fsm_outs5_t fsm_outs13; 02731 lsm6dsox_fsm_outs6_t fsm_outs14; 02732 lsm6dsox_fsm_outs7_t fsm_outs15; 02733 lsm6dsox_fsm_outs8_t fsm_outs16; 02734 } lsm6dsox_fsm_out_t; 02735 int32_t lsm6dsox_fsm_out_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_out_t *val); 02736 02737 typedef enum { 02738 LSM6DSOX_ODR_FSM_12Hz5 = 0, 02739 LSM6DSOX_ODR_FSM_26Hz = 1, 02740 LSM6DSOX_ODR_FSM_52Hz = 2, 02741 LSM6DSOX_ODR_FSM_104Hz = 3, 02742 } lsm6dsox_fsm_odr_t; 02743 int32_t lsm6dsox_fsm_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t val); 02744 int32_t lsm6dsox_fsm_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t *val); 02745 02746 int32_t lsm6dsox_fsm_init_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02747 int32_t lsm6dsox_fsm_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02748 02749 int32_t lsm6dsox_long_cnt_int_value_set(lsm6dsox_ctx_t *ctx, uint16_t val); 02750 int32_t lsm6dsox_long_cnt_int_value_get(lsm6dsox_ctx_t *ctx, uint16_t *val); 02751 02752 int32_t lsm6dsox_fsm_number_of_programs_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02753 int32_t lsm6dsox_fsm_number_of_programs_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02754 02755 int32_t lsm6dsox_fsm_start_address_set(lsm6dsox_ctx_t *ctx, uint16_t val); 02756 int32_t lsm6dsox_fsm_start_address_get(lsm6dsox_ctx_t *ctx, uint16_t *val); 02757 02758 int32_t lsm6dsox_mlc_status_get(lsm6dsox_ctx_t *ctx, 02759 lsm6dsox_mlc_status_mainpage_t *val); 02760 02761 typedef enum { 02762 LSM6DSOX_ODR_PRGS_12Hz5 = 0, 02763 LSM6DSOX_ODR_PRGS_26Hz = 1, 02764 LSM6DSOX_ODR_PRGS_52Hz = 2, 02765 LSM6DSOX_ODR_PRGS_104Hz = 3, 02766 } lsm6dsox_mlc_odr_t; 02767 int32_t lsm6dsox_mlc_data_rate_set(lsm6dsox_ctx_t *ctx, 02768 lsm6dsox_mlc_odr_t val); 02769 int32_t lsm6dsox_mlc_data_rate_get(lsm6dsox_ctx_t *ctx, 02770 lsm6dsox_mlc_odr_t *val); 02771 02772 typedef struct { 02773 lsm6dsox_sensor_hub_1_t sh_byte_1; 02774 lsm6dsox_sensor_hub_2_t sh_byte_2; 02775 lsm6dsox_sensor_hub_3_t sh_byte_3; 02776 lsm6dsox_sensor_hub_4_t sh_byte_4; 02777 lsm6dsox_sensor_hub_5_t sh_byte_5; 02778 lsm6dsox_sensor_hub_6_t sh_byte_6; 02779 lsm6dsox_sensor_hub_7_t sh_byte_7; 02780 lsm6dsox_sensor_hub_8_t sh_byte_8; 02781 lsm6dsox_sensor_hub_9_t sh_byte_9; 02782 lsm6dsox_sensor_hub_10_t sh_byte_10; 02783 lsm6dsox_sensor_hub_11_t sh_byte_11; 02784 lsm6dsox_sensor_hub_12_t sh_byte_12; 02785 lsm6dsox_sensor_hub_13_t sh_byte_13; 02786 lsm6dsox_sensor_hub_14_t sh_byte_14; 02787 lsm6dsox_sensor_hub_15_t sh_byte_15; 02788 lsm6dsox_sensor_hub_16_t sh_byte_16; 02789 lsm6dsox_sensor_hub_17_t sh_byte_17; 02790 lsm6dsox_sensor_hub_18_t sh_byte_18; 02791 } lsm6dsox_emb_sh_read_t; 02792 int32_t lsm6dsox_sh_read_data_raw_get(lsm6dsox_ctx_t *ctx, 02793 lsm6dsox_emb_sh_read_t *val, 02794 uint8_t len); 02795 02796 typedef enum { 02797 LSM6DSOX_SLV_0 = 0, 02798 LSM6DSOX_SLV_0_1 = 1, 02799 LSM6DSOX_SLV_0_1_2 = 2, 02800 LSM6DSOX_SLV_0_1_2_3 = 3, 02801 } lsm6dsox_aux_sens_on_t; 02802 int32_t lsm6dsox_sh_slave_connected_set(lsm6dsox_ctx_t *ctx, 02803 lsm6dsox_aux_sens_on_t val); 02804 int32_t lsm6dsox_sh_slave_connected_get(lsm6dsox_ctx_t *ctx, 02805 lsm6dsox_aux_sens_on_t *val); 02806 02807 int32_t lsm6dsox_sh_master_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02808 int32_t lsm6dsox_sh_master_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02809 02810 typedef enum { 02811 LSM6DSOX_EXT_PULL_UP = 0, 02812 LSM6DSOX_INTERNAL_PULL_UP = 1, 02813 } lsm6dsox_shub_pu_en_t; 02814 int32_t lsm6dsox_sh_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t val); 02815 int32_t lsm6dsox_sh_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t *val); 02816 02817 int32_t lsm6dsox_sh_pass_through_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02818 int32_t lsm6dsox_sh_pass_through_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02819 02820 typedef enum { 02821 LSM6DSOX_EXT_ON_INT2_PIN = 1, 02822 LSM6DSOX_XL_GY_DRDY = 0, 02823 } lsm6dsox_start_config_t; 02824 int32_t lsm6dsox_sh_syncro_mode_set(lsm6dsox_ctx_t *ctx, 02825 lsm6dsox_start_config_t val); 02826 int32_t lsm6dsox_sh_syncro_mode_get(lsm6dsox_ctx_t *ctx, 02827 lsm6dsox_start_config_t *val); 02828 02829 typedef enum { 02830 LSM6DSOX_EACH_SH_CYCLE = 0, 02831 LSM6DSOX_ONLY_FIRST_CYCLE = 1, 02832 } lsm6dsox_write_once_t; 02833 int32_t lsm6dsox_sh_write_mode_set(lsm6dsox_ctx_t *ctx, 02834 lsm6dsox_write_once_t val); 02835 int32_t lsm6dsox_sh_write_mode_get(lsm6dsox_ctx_t *ctx, 02836 lsm6dsox_write_once_t *val); 02837 02838 int32_t lsm6dsox_sh_reset_set(lsm6dsox_ctx_t *ctx); 02839 int32_t lsm6dsox_sh_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02840 02841 typedef enum { 02842 LSM6DSOX_SH_ODR_104Hz = 0, 02843 LSM6DSOX_SH_ODR_52Hz = 1, 02844 LSM6DSOX_SH_ODR_26Hz = 2, 02845 LSM6DSOX_SH_ODR_13Hz = 3, 02846 } lsm6dsox_shub_odr_t; 02847 int32_t lsm6dsox_sh_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t val); 02848 int32_t lsm6dsox_sh_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t *val); 02849 02850 typedef struct{ 02851 uint8_t slv0_add; 02852 uint8_t slv0_subadd; 02853 uint8_t slv0_data; 02854 } lsm6dsox_sh_cfg_write_t; 02855 int32_t lsm6dsox_sh_cfg_write(lsm6dsox_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val); 02856 02857 typedef struct{ 02858 uint8_t slv_add; 02859 uint8_t slv_subadd; 02860 uint8_t slv_len; 02861 } lsm6dsox_sh_cfg_read_t; 02862 int32_t lsm6dsox_sh_slv0_cfg_read(lsm6dsox_ctx_t *ctx, 02863 lsm6dsox_sh_cfg_read_t *val); 02864 int32_t lsm6dsox_sh_slv1_cfg_read(lsm6dsox_ctx_t *ctx, 02865 lsm6dsox_sh_cfg_read_t *val); 02866 int32_t lsm6dsox_sh_slv2_cfg_read(lsm6dsox_ctx_t *ctx, 02867 lsm6dsox_sh_cfg_read_t *val); 02868 int32_t lsm6dsox_sh_slv3_cfg_read(lsm6dsox_ctx_t *ctx, 02869 lsm6dsox_sh_cfg_read_t *val); 02870 02871 int32_t lsm6dsox_sh_status_get(lsm6dsox_ctx_t *ctx, 02872 lsm6dsox_status_master_t *val); 02873 typedef enum { 02874 LSM6DSOX_S4S_TPH_7bit = 0, 02875 LSM6DSOX_S4S_TPH_15bit = 1, 02876 } lsm6dsox_s4s_tph_res_t; 02877 int32_t lsm6dsox_s4s_tph_res_set(lsm6dsox_ctx_t *ctx, 02878 lsm6dsox_s4s_tph_res_t val); 02879 int32_t lsm6dsox_s4s_tph_res_get(lsm6dsox_ctx_t *ctx, 02880 lsm6dsox_s4s_tph_res_t *val); 02881 02882 int32_t lsm6dsox_s4s_tph_val_set(lsm6dsox_ctx_t *ctx, uint16_t val); 02883 int32_t lsm6dsox_s4s_tph_val_get(lsm6dsox_ctx_t *ctx, uint16_t *val); 02884 02885 typedef enum { 02886 LSM6DSOX_S4S_DT_RES_11 = 0, 02887 LSM6DSOX_S4S_DT_RES_12 = 1, 02888 LSM6DSOX_S4S_DT_RES_13 = 2, 02889 LSM6DSOX_S4S_DT_RES_14 = 3, 02890 } lsm6dsox_s4s_res_ratio_t; 02891 int32_t lsm6dsox_s4s_res_ratio_set(lsm6dsox_ctx_t *ctx, 02892 lsm6dsox_s4s_res_ratio_t val); 02893 int32_t lsm6dsox_s4s_res_ratio_get(lsm6dsox_ctx_t *ctx, 02894 lsm6dsox_s4s_res_ratio_t *val); 02895 02896 int32_t lsm6dsox_s4s_command_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02897 int32_t lsm6dsox_s4s_command_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02898 02899 int32_t lsm6dsox_s4s_dt_set(lsm6dsox_ctx_t *ctx, uint8_t val); 02900 int32_t lsm6dsox_s4s_dt_get(lsm6dsox_ctx_t *ctx, uint8_t *val); 02901 02902 typedef struct { 02903 uint8_t ui; 02904 uint8_t aux; 02905 } lsm6dsox_id_t; 02906 int32_t lsm6dsox_id_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 02907 lsm6dsox_id_t *val); 02908 02909 typedef struct { 02910 enum { 02911 LSM6DSOX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 02912 LSM6DSOX_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 02913 LSM6DSOX_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 02914 LSM6DSOX_I2C = 0x04, /* Only I2C */ 02915 LSM6DSOX_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ 02916 LSM6DSOX_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ 02917 LSM6DSOX_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 02918 LSM6DSOX_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 02919 } ui_bus_md; 02920 enum { 02921 LSM6DSOX_SPI_4W_AUX = 0x00, 02922 LSM6DSOX_SPI_3W_AUX = 0x01, 02923 } aux_bus_md; 02924 } lsm6dsox_bus_mode_t; 02925 int32_t lsm6dsox_bus_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 02926 lsm6dsox_bus_mode_t val); 02927 int32_t lsm6dsox_bus_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 02928 lsm6dsox_bus_mode_t *val); 02929 02930 typedef enum { 02931 LSM6DSOX_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 02932 LSM6DSOX_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 02933 LSM6DSOX_RESET = 0x02, /* Reset configuration registers */ 02934 LSM6DSOX_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 02935 LSM6DSOX_FSM = 0x08, /* Finite State Machine initialization request */ 02936 LSM6DSOX_MLC = 0x10, /* Machine Learning Core initialization request */ 02937 LSM6DSOX_PEDO = 0x20, /* Pedometer algo initialization request. */ 02938 LSM6DSOX_TILT = 0x40, /* Tilt algo initialization request */ 02939 LSM6DSOX_SMOTION = 0x80, /* Significant Motion initialization request */ 02940 } lsm6dsox_init_t; 02941 int32_t lsm6dsox_init_set(lsm6dsox_ctx_t *ctx, lsm6dsox_init_t val); 02942 02943 typedef struct { 02944 uint8_t sw_reset : 1; /* Restoring configuration registers */ 02945 uint8_t boot : 1; /* Restoring calibration parameters */ 02946 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 02947 uint8_t drdy_g : 1; /* Gyroscope data ready */ 02948 uint8_t drdy_temp : 1; /* Temperature data ready */ 02949 uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */ 02950 uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */ 02951 uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */ 02952 } lsm6dsox_status_t; 02953 int32_t lsm6dsox_status_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 02954 lsm6dsox_status_t *val); 02955 02956 typedef struct { 02957 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 02958 uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 02959 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 02960 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 02961 } lsm6dsox_pin_conf_t; 02962 int32_t lsm6dsox_pin_conf_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pin_conf_t val); 02963 int32_t lsm6dsox_pin_conf_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pin_conf_t *val); 02964 02965 typedef struct { 02966 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 02967 uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 02968 uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 02969 } lsm6dsox_int_mode_t; 02970 int32_t lsm6dsox_interrupt_mode_set(lsm6dsox_ctx_t *ctx, 02971 lsm6dsox_int_mode_t val); 02972 int32_t lsm6dsox_interrupt_mode_get(lsm6dsox_ctx_t *ctx, 02973 lsm6dsox_int_mode_t *val); 02974 02975 typedef struct { 02976 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 02977 uint8_t drdy_g : 1; /* Gyroscope data ready */ 02978 uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */ 02979 uint8_t boot : 1; /* Restoring calibration parameters */ 02980 uint8_t fifo_th : 1; /* FIFO threshold reached */ 02981 uint8_t fifo_ovr : 1; /* FIFO overrun */ 02982 uint8_t fifo_full : 1; /* FIFO full */ 02983 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 02984 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 02985 uint8_t sh_endop : 1; /* sensor hub end operation */ 02986 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 02987 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 02988 uint8_t double_tap : 1; /* double-tap event */ 02989 uint8_t free_fall : 1; /* free fall event */ 02990 uint8_t wake_up : 1; /* wake up event */ 02991 uint8_t single_tap : 1; /* single-tap event */ 02992 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 02993 uint8_t step_detector : 1; /* Step detected */ 02994 uint8_t tilt : 1; /* Relative tilt event detected */ 02995 uint8_t sig_mot : 1; /* "significant motion" event detected */ 02996 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 02997 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 02998 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 02999 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 03000 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 03001 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 03002 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 03003 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 03004 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 03005 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 03006 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 03007 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 03008 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 03009 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 03010 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 03011 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 03012 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 03013 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 03014 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 03015 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 03016 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 03017 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 03018 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 03019 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 03020 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 03021 } lsm6dsox_pin_int1_route_t; 03022 03023 int32_t lsm6dsox_pin_int1_route_set(lsm6dsox_ctx_t *ctx, 03024 lsm6dsox_pin_int1_route_t val); 03025 int32_t lsm6dsox_pin_int1_route_get(lsm6dsox_ctx_t *ctx, 03026 lsm6dsox_pin_int1_route_t *val); 03027 03028 typedef struct { 03029 uint8_t drdy_ois : 1; /* OIS chain data ready */ 03030 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 03031 uint8_t drdy_g : 1; /* Gyroscope data ready */ 03032 uint8_t drdy_temp : 1; /* Temperature data ready */ 03033 uint8_t fifo_th : 1; /* FIFO threshold reached */ 03034 uint8_t fifo_ovr : 1; /* FIFO overrun */ 03035 uint8_t fifo_full : 1; /* FIFO full */ 03036 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 03037 uint8_t timestamp : 1; /* timestamp overflow */ 03038 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 03039 uint8_t double_tap : 1; /* double-tap event */ 03040 uint8_t free_fall : 1; /* free fall event */ 03041 uint8_t wake_up : 1; /* wake up event */ 03042 uint8_t single_tap : 1; /* single-tap event */ 03043 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 03044 uint8_t step_detector : 1; /* Step detected */ 03045 uint8_t tilt : 1; /* Relative tilt event detected */ 03046 uint8_t sig_mot : 1; /* "significant motion" event detected */ 03047 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 03048 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 03049 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 03050 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 03051 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 03052 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 03053 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 03054 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 03055 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 03056 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 03057 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 03058 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 03059 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 03060 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 03061 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 03062 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 03063 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 03064 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 03065 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 03066 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 03067 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 03068 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 03069 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 03070 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 03071 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 03072 } lsm6dsox_pin_int2_route_t; 03073 03074 int32_t lsm6dsox_pin_int2_route_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 03075 lsm6dsox_pin_int2_route_t val); 03076 int32_t lsm6dsox_pin_int2_route_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 03077 lsm6dsox_pin_int2_route_t *val); 03078 03079 typedef struct { 03080 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 03081 uint8_t drdy_g : 1; /* Gyroscope data ready */ 03082 uint8_t drdy_temp : 1; /* Temperature data ready */ 03083 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 03084 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 03085 uint8_t free_fall : 1; /* free fall event */ 03086 uint8_t wake_up : 1; /* wake up event */ 03087 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 03088 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 03089 uint8_t wake_up_x : 1; /* wake up on X axis event */ 03090 uint8_t single_tap : 1; /* single-tap event */ 03091 uint8_t double_tap : 1; /* double-tap event */ 03092 uint8_t tap_z : 1; /* single-tap on Z axis event */ 03093 uint8_t tap_y : 1; /* single-tap on Y axis event */ 03094 uint8_t tap_x : 1; /* single-tap on X axis event */ 03095 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 03096 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 03097 uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ 03098 uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ 03099 uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ 03100 uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ 03101 uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ 03102 uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ 03103 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 03104 uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 03105 uint8_t step_detector : 1; /* Step detected */ 03106 uint8_t tilt : 1; /* Relative tilt event detected */ 03107 uint8_t sig_mot : 1; /* "significant motion" event detected */ 03108 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 03109 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 03110 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 03111 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 03112 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 03113 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 03114 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 03115 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 03116 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 03117 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 03118 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 03119 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 03120 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 03121 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 03122 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 03123 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 03124 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 03125 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 03126 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 03127 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 03128 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 03129 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 03130 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 03131 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 03132 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 03133 uint8_t sh_endop : 1; /* sensor hub end operation */ 03134 uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */ 03135 uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */ 03136 uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */ 03137 uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */ 03138 uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 03139 uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/ 03140 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 03141 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 03142 uint8_t fifo_full : 1; /* FIFO full */ 03143 uint8_t fifo_ovr : 1; /* FIFO overrun */ 03144 uint8_t fifo_th : 1; /* FIFO threshold reached */ 03145 } lsm6dsox_all_sources_t; 03146 int32_t lsm6dsox_all_sources_get(lsm6dsox_ctx_t *ctx, 03147 lsm6dsox_all_sources_t *val); 03148 03149 typedef struct{ 03150 uint8_t odr_fine_tune; 03151 } lsm6dsox_dev_cal_t; 03152 int32_t lsm6dsox_calibration_get(lsm6dsox_ctx_t *ctx, lsm6dsox_dev_cal_t *val); 03153 03154 typedef struct { 03155 struct { 03156 struct { 03157 enum { 03158 LSM6DSOX_XL_UI_OFF = 0x00, /* in power down */ 03159 LSM6DSOX_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 03160 LSM6DSOX_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ 03161 LSM6DSOX_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 03162 LSM6DSOX_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 03163 LSM6DSOX_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ 03164 LSM6DSOX_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 03165 LSM6DSOX_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 03166 LSM6DSOX_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ 03167 LSM6DSOX_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 03168 LSM6DSOX_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 03169 LSM6DSOX_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ 03170 LSM6DSOX_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 03171 LSM6DSOX_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 03172 LSM6DSOX_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ 03173 LSM6DSOX_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 03174 LSM6DSOX_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 03175 LSM6DSOX_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ 03176 LSM6DSOX_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 03177 LSM6DSOX_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 03178 LSM6DSOX_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 03179 LSM6DSOX_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 03180 LSM6DSOX_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 03181 } odr; 03182 enum { 03183 LSM6DSOX_XL_UI_2g = 0, 03184 LSM6DSOX_XL_UI_4g = 2, 03185 LSM6DSOX_XL_UI_8g = 3, 03186 LSM6DSOX_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ 03187 } fs; 03188 } xl; 03189 struct { 03190 enum { 03191 LSM6DSOX_GY_UI_OFF = 0x00, /* gy in power down */ 03192 LSM6DSOX_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 03193 LSM6DSOX_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 03194 LSM6DSOX_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 03195 LSM6DSOX_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 03196 LSM6DSOX_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 03197 LSM6DSOX_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 03198 LSM6DSOX_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 03199 LSM6DSOX_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 03200 LSM6DSOX_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 03201 LSM6DSOX_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 03202 LSM6DSOX_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 03203 LSM6DSOX_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 03204 LSM6DSOX_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 03205 LSM6DSOX_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 03206 LSM6DSOX_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 03207 } odr; 03208 enum { 03209 LSM6DSOX_GY_UI_250dps = 0, 03210 LSM6DSOX_GY_UI_125dps = 1, 03211 LSM6DSOX_GY_UI_500dps = 2, 03212 LSM6DSOX_GY_UI_1000dps = 4, 03213 LSM6DSOX_GY_UI_2000dps = 6, 03214 } fs; 03215 }gy; 03216 } ui; 03217 struct { 03218 enum { 03219 LSM6DSOX_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ 03220 LSM6DSOX_OIS_ONLY_UI = 0x02, /* Primary interface full control */ 03221 LSM6DSOX_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ 03222 } ctrl_md; 03223 struct { 03224 enum { 03225 LSM6DSOX_XL_OIS_OFF = 0x00, /* in power down */ 03226 LSM6DSOX_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ 03227 } odr; 03228 enum { 03229 LSM6DSOX_XL_OIS_2g = 0, 03230 LSM6DSOX_XL_OIS_4g = 2, 03231 LSM6DSOX_XL_OIS_8g = 3, 03232 LSM6DSOX_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ 03233 } fs; 03234 } xl; 03235 struct { 03236 enum { 03237 LSM6DSOX_GY_OIS_OFF = 0x00, /* in power down */ 03238 LSM6DSOX_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ 03239 } odr; 03240 enum { 03241 LSM6DSOX_GY_OIS_250dps = 0, 03242 LSM6DSOX_GY_OIS_125dps = 1, 03243 LSM6DSOX_GY_OIS_500dps = 2, 03244 LSM6DSOX_GY_OIS_1000dps = 4, 03245 LSM6DSOX_GY_OIS_2000dps = 6, 03246 } fs; 03247 } gy; 03248 } ois; 03249 struct { 03250 enum { 03251 LSM6DSOX_FSM_DISABLE = 0x00, 03252 LSM6DSOX_FSM_XL = 0x01, 03253 LSM6DSOX_FSM_GY = 0x02, 03254 LSM6DSOX_FSM_XL_GY = 0x03, 03255 } sens; 03256 enum { 03257 LSM6DSOX_FSM_12Hz5 = 0x00, 03258 LSM6DSOX_FSM_26Hz = 0x01, 03259 LSM6DSOX_FSM_52Hz = 0x02, 03260 LSM6DSOX_FSM_104Hz = 0x03, 03261 } odr; 03262 } fsm; 03263 struct { 03264 enum { 03265 LSM6DSOX_MLC_DISABLE = 0x00, 03266 LSM6DSOX_MLC_XL = 0x01, 03267 LSM6DSOX_MLC_XL_GY = 0x03, 03268 } sens; 03269 enum { 03270 LSM6DSOX_MLC_12Hz5 = 0x00, 03271 LSM6DSOX_MLC_26Hz = 0x01, 03272 LSM6DSOX_MLC_52Hz = 0x02, 03273 LSM6DSOX_MLC_104Hz = 0x03, 03274 } odr; 03275 } mlc; 03276 } lsm6dsox_md_t; 03277 int32_t lsm6dsox_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 03278 lsm6dsox_md_t *val); 03279 int32_t lsm6dsox_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 03280 lsm6dsox_md_t *val); 03281 03282 typedef struct { 03283 struct { 03284 struct { 03285 float mg[3]; 03286 int16_t raw[3]; 03287 }xl; 03288 struct { 03289 float mdps[3]; 03290 int16_t raw[3]; 03291 }gy; 03292 struct { 03293 float deg_c; 03294 int16_t raw; 03295 }heat; 03296 } ui; 03297 struct { 03298 struct { 03299 float mg[3]; 03300 int16_t raw[3]; 03301 }xl; 03302 struct { 03303 float mdps[3]; 03304 int16_t raw[3]; 03305 }gy; 03306 } ois; 03307 } lsm6dsox_data_t; 03308 int32_t lsm6dsox_data_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 03309 lsm6dsox_md_t *md, lsm6dsox_data_t *data); 03310 03311 typedef struct { 03312 uint8_t sig_mot : 1; /* significant motion */ 03313 uint8_t tilt : 1; /* tilt detection */ 03314 uint8_t step : 1; /* step counter/detector */ 03315 uint8_t mlc : 1; /* machine learning core */ 03316 uint8_t fsm : 1; /* finite state machine */ 03317 uint8_t fifo_compr : 1; /* mlc 8 interrupt event */ 03318 } lsm6dsox_emb_sens_t; 03319 int32_t lsm6dsox_embedded_sens_set(lsm6dsox_ctx_t *ctx, 03320 lsm6dsox_emb_sens_t *emb_sens); 03321 int32_t lsm6dsox_embedded_sens_get(lsm6dsox_ctx_t *ctx, 03322 lsm6dsox_emb_sens_t *emb_sens); 03323 int32_t lsm6dsox_embedded_sens_off(lsm6dsox_ctx_t *ctx); 03324 03325 /** 03326 * @} 03327 * 03328 */ 03329 03330 #ifdef __cplusplus 03331 } 03332 #endif 03333 03334 #endif /*LSM6DSOX_DRIVER_H */ 03335 03336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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