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LSM6DSOX
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
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lsm6dsox_reg.c
00001 /* 00002 ****************************************************************************** 00003 * @file lsm6dsox_reg.c 00004 * @author Sensors Software Solution Team 00005 * @brief LSM6DSOX driver file 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 #include "lsm6dsox_reg.h" 00021 00022 /** 00023 * @defgroup LSM6DSOX 00024 * @brief This file provides a set of functions needed to drive the 00025 * lsm6dsox enhanced inertial module. 00026 * @{ 00027 * 00028 */ 00029 00030 /** 00031 * @defgroup LSM6DSOX_Interfaces_Functions 00032 * @brief This section provide a set of functions used to read and 00033 * write a generic register of the device. 00034 * MANDATORY: return 0 -> no Error. 00035 * @{ 00036 * 00037 */ 00038 00039 /** 00040 * @brief Read generic device register 00041 * 00042 * @param ctx communication interface handler.(ptr) 00043 * @param reg first register address to read. 00044 * @param data buffer for data read.(ptr) 00045 * @param len number of consecutive register to read. 00046 * @retval interface status (MANDATORY: return 0 -> no Error). 00047 * 00048 */ 00049 int32_t lsm6dsox_read_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data, 00050 uint16_t len) 00051 { 00052 int32_t ret; 00053 ret = ctx->read_reg(ctx->handle, reg, data, len); 00054 return ret; 00055 } 00056 00057 /** 00058 * @brief Write generic device register 00059 * 00060 * @param ctx communication interface handler.(ptr) 00061 * @param reg first register address to write. 00062 * @param data the buffer contains data to be written.(ptr) 00063 * @param len number of consecutive register to write. 00064 * @retval interface status (MANDATORY: return 0 -> no Error). 00065 * 00066 */ 00067 int32_t lsm6dsox_write_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data, 00068 uint16_t len) 00069 { 00070 int32_t ret; 00071 ret = ctx->write_reg(ctx->handle, reg, data, len); 00072 return ret; 00073 } 00074 00075 /** 00076 * @} 00077 * 00078 */ 00079 00080 /** 00081 * @defgroup LSM6DSOX_Private_functions 00082 * @brief Section collect all the utility functions needed by APIs. 00083 * @{ 00084 * 00085 */ 00086 00087 static void bytecpy(uint8_t *target, uint8_t *source) 00088 { 00089 if ( (target != NULL) && (source != NULL) ) { 00090 *target = *source; 00091 } 00092 } 00093 00094 /** 00095 * @} 00096 * 00097 */ 00098 00099 /** 00100 * @defgroup LSM6DSOX_Sensitivity 00101 * @brief These functions convert raw-data into engineering units. 00102 * @{ 00103 * 00104 */ 00105 float_t lsm6dsox_from_fs2_to_mg(int16_t lsb) 00106 { 00107 return ((float_t)lsb) * 0.061f; 00108 } 00109 00110 float_t lsm6dsox_from_fs4_to_mg(int16_t lsb) 00111 { 00112 return ((float_t)lsb) * 0.122f; 00113 } 00114 00115 float_t lsm6dsox_from_fs8_to_mg(int16_t lsb) 00116 { 00117 return ((float_t)lsb) * 0.244f; 00118 } 00119 00120 float_t lsm6dsox_from_fs16_to_mg(int16_t lsb) 00121 { 00122 return ((float_t)lsb) *0.488f; 00123 } 00124 00125 float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb) 00126 { 00127 return ((float_t)lsb) *4.375f; 00128 } 00129 00130 float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb) 00131 { 00132 return ((float_t)lsb) *17.50f; 00133 } 00134 00135 float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb) 00136 { 00137 return ((float_t)lsb) *8.750f; 00138 } 00139 00140 float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb) 00141 { 00142 return ((float_t)lsb) *35.0f; 00143 } 00144 00145 float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb) 00146 { 00147 return ((float_t)lsb) *70.0f; 00148 } 00149 00150 float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb) 00151 { 00152 return (((float_t)lsb / 256.0f) + 25.0f); 00153 } 00154 00155 float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb) 00156 { 00157 return ((float_t)lsb * 25000.0f); 00158 } 00159 00160 /** 00161 * @} 00162 * 00163 */ 00164 00165 /** 00166 * @defgroup LSM6DSOX_Data_Generation 00167 * @brief This section groups all the functions concerning 00168 * data generation. 00169 * 00170 */ 00171 00172 /** 00173 * @brief Accelerometer full-scale selection.[set] 00174 * 00175 * @param ctx read / write interface definitions 00176 * @param val change the values of fs_xl in reg CTRL1_XL 00177 * 00178 */ 00179 int32_t lsm6dsox_xl_full_scale_set(lsm6dsox_ctx_t *ctx, 00180 lsm6dsox_fs_xl_t val) 00181 { 00182 lsm6dsox_ctrl1_xl_t reg; 00183 int32_t ret; 00184 00185 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 00186 if (ret == 0) { 00187 reg.fs_xl = (uint8_t) val; 00188 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 00189 } 00190 return ret; 00191 } 00192 00193 /** 00194 * @brief Accelerometer full-scale selection.[get] 00195 * 00196 * @param ctx read / write interface definitions 00197 * @param val Get the values of fs_xl in reg CTRL1_XL 00198 * 00199 */ 00200 int32_t lsm6dsox_xl_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t *val) 00201 { 00202 lsm6dsox_ctrl1_xl_t reg; 00203 int32_t ret; 00204 00205 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 00206 switch (reg.fs_xl) { 00207 case LSM6DSOX_2g: 00208 *val = LSM6DSOX_2g; 00209 break; 00210 case LSM6DSOX_16g: 00211 *val = LSM6DSOX_16g; 00212 break; 00213 case LSM6DSOX_4g: 00214 *val = LSM6DSOX_4g; 00215 break; 00216 case LSM6DSOX_8g: 00217 *val = LSM6DSOX_8g; 00218 break; 00219 default: 00220 *val = LSM6DSOX_2g; 00221 break; 00222 } 00223 00224 return ret; 00225 } 00226 00227 /** 00228 * @brief Accelerometer UI data rate selection.[set] 00229 * 00230 * @param ctx read / write interface definitions 00231 * @param val change the values of odr_xl in reg CTRL1_XL 00232 * 00233 */ 00234 int32_t lsm6dsox_xl_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t val) 00235 { 00236 lsm6dsox_odr_xl_t odr_xl = val; 00237 lsm6dsox_emb_fsm_enable_t fsm_enable; 00238 lsm6dsox_fsm_odr_t fsm_odr; 00239 lsm6dsox_emb_sens_t emb_sens; 00240 lsm6dsox_mlc_odr_t mlc_odr; 00241 lsm6dsox_ctrl1_xl_t reg; 00242 int32_t ret; 00243 00244 /* Check the Finite State Machine data rate constraints */ 00245 ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable); 00246 if (ret == 0) { 00247 if ( (fsm_enable.fsm_enable_a.fsm1_en | 00248 fsm_enable.fsm_enable_a.fsm2_en | 00249 fsm_enable.fsm_enable_a.fsm3_en | 00250 fsm_enable.fsm_enable_a.fsm4_en | 00251 fsm_enable.fsm_enable_a.fsm5_en | 00252 fsm_enable.fsm_enable_a.fsm6_en | 00253 fsm_enable.fsm_enable_a.fsm7_en | 00254 fsm_enable.fsm_enable_a.fsm8_en | 00255 fsm_enable.fsm_enable_b.fsm9_en | 00256 fsm_enable.fsm_enable_b.fsm10_en | 00257 fsm_enable.fsm_enable_b.fsm11_en | 00258 fsm_enable.fsm_enable_b.fsm12_en | 00259 fsm_enable.fsm_enable_b.fsm13_en | 00260 fsm_enable.fsm_enable_b.fsm14_en | 00261 fsm_enable.fsm_enable_b.fsm15_en | 00262 fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){ 00263 00264 ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr); 00265 if (ret == 0) { 00266 switch (fsm_odr) { 00267 case LSM6DSOX_ODR_FSM_12Hz5: 00268 00269 if (val == LSM6DSOX_XL_ODR_OFF){ 00270 odr_xl = LSM6DSOX_XL_ODR_12Hz5; 00271 00272 } else { 00273 odr_xl = val; 00274 } 00275 break; 00276 case LSM6DSOX_ODR_FSM_26Hz: 00277 00278 if (val == LSM6DSOX_XL_ODR_OFF){ 00279 odr_xl = LSM6DSOX_XL_ODR_26Hz; 00280 00281 } else if (val == LSM6DSOX_XL_ODR_12Hz5){ 00282 odr_xl = LSM6DSOX_XL_ODR_26Hz; 00283 00284 } else { 00285 odr_xl = val; 00286 } 00287 break; 00288 case LSM6DSOX_ODR_FSM_52Hz: 00289 00290 if (val == LSM6DSOX_XL_ODR_OFF){ 00291 odr_xl = LSM6DSOX_XL_ODR_52Hz; 00292 00293 } else if (val == LSM6DSOX_XL_ODR_12Hz5){ 00294 odr_xl = LSM6DSOX_XL_ODR_52Hz; 00295 00296 } else if (val == LSM6DSOX_XL_ODR_26Hz){ 00297 odr_xl = LSM6DSOX_XL_ODR_52Hz; 00298 00299 } else { 00300 odr_xl = val; 00301 } 00302 break; 00303 case LSM6DSOX_ODR_FSM_104Hz: 00304 00305 if (val == LSM6DSOX_XL_ODR_OFF){ 00306 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00307 00308 } else if (val == LSM6DSOX_XL_ODR_12Hz5){ 00309 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00310 00311 } else if (val == LSM6DSOX_XL_ODR_26Hz){ 00312 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00313 00314 } else if (val == LSM6DSOX_XL_ODR_52Hz){ 00315 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00316 00317 } else { 00318 odr_xl = val; 00319 } 00320 break; 00321 default: 00322 odr_xl = val; 00323 break; 00324 } 00325 } 00326 } 00327 } 00328 00329 /* Check the Machine Learning Core data rate constraints */ 00330 emb_sens.mlc = PROPERTY_DISABLE; 00331 if (ret == 0) { 00332 lsm6dsox_embedded_sens_get(ctx, &emb_sens); 00333 if ( emb_sens.mlc == PROPERTY_ENABLE ){ 00334 00335 ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr); 00336 if (ret == 0) { 00337 switch (mlc_odr) { 00338 case LSM6DSOX_ODR_PRGS_12Hz5: 00339 00340 if (val == LSM6DSOX_XL_ODR_OFF){ 00341 odr_xl = LSM6DSOX_XL_ODR_12Hz5; 00342 00343 } else { 00344 odr_xl = val; 00345 } 00346 break; 00347 case LSM6DSOX_ODR_PRGS_26Hz: 00348 if (val == LSM6DSOX_XL_ODR_OFF){ 00349 odr_xl = LSM6DSOX_XL_ODR_26Hz; 00350 00351 } else if (val == LSM6DSOX_XL_ODR_12Hz5){ 00352 odr_xl = LSM6DSOX_XL_ODR_26Hz; 00353 00354 } else { 00355 odr_xl = val; 00356 } 00357 break; 00358 case LSM6DSOX_ODR_PRGS_52Hz: 00359 00360 if (val == LSM6DSOX_XL_ODR_OFF){ 00361 odr_xl = LSM6DSOX_XL_ODR_52Hz; 00362 00363 } else if (val == LSM6DSOX_XL_ODR_12Hz5){ 00364 odr_xl = LSM6DSOX_XL_ODR_52Hz; 00365 00366 } else if (val == LSM6DSOX_XL_ODR_26Hz){ 00367 odr_xl = LSM6DSOX_XL_ODR_52Hz; 00368 00369 } else { 00370 odr_xl = val; 00371 } 00372 break; 00373 case LSM6DSOX_ODR_PRGS_104Hz: 00374 if (val == LSM6DSOX_XL_ODR_OFF){ 00375 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00376 00377 } else if (val == LSM6DSOX_XL_ODR_12Hz5){ 00378 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00379 00380 } else if (val == LSM6DSOX_XL_ODR_26Hz){ 00381 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00382 00383 } else if (val == LSM6DSOX_XL_ODR_52Hz){ 00384 odr_xl = LSM6DSOX_XL_ODR_104Hz; 00385 00386 } else { 00387 odr_xl = val; 00388 } 00389 break; 00390 default: 00391 odr_xl = val; 00392 break; 00393 } 00394 } 00395 } 00396 } 00397 if (ret == 0) { 00398 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 00399 } 00400 if (ret == 0) { 00401 reg.odr_xl = (uint8_t) odr_xl; 00402 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 00403 } 00404 return ret; 00405 } 00406 00407 /** 00408 * @brief Accelerometer UI data rate selection.[get] 00409 * 00410 * @param ctx read / write interface definitions 00411 * @param val Get the values of odr_xl in reg CTRL1_XL 00412 * 00413 */ 00414 int32_t lsm6dsox_xl_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t *val) 00415 { 00416 lsm6dsox_ctrl1_xl_t reg; 00417 int32_t ret; 00418 00419 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 00420 00421 switch (reg.odr_xl) { 00422 case LSM6DSOX_XL_ODR_OFF: 00423 *val = LSM6DSOX_XL_ODR_OFF; 00424 break; 00425 case LSM6DSOX_XL_ODR_12Hz5: 00426 *val = LSM6DSOX_XL_ODR_12Hz5; 00427 break; 00428 case LSM6DSOX_XL_ODR_26Hz: 00429 *val = LSM6DSOX_XL_ODR_26Hz; 00430 break; 00431 case LSM6DSOX_XL_ODR_52Hz: 00432 *val = LSM6DSOX_XL_ODR_52Hz; 00433 break; 00434 case LSM6DSOX_XL_ODR_104Hz: 00435 *val = LSM6DSOX_XL_ODR_104Hz; 00436 break; 00437 case LSM6DSOX_XL_ODR_208Hz: 00438 *val = LSM6DSOX_XL_ODR_208Hz; 00439 break; 00440 case LSM6DSOX_XL_ODR_417Hz: 00441 *val = LSM6DSOX_XL_ODR_417Hz; 00442 break; 00443 case LSM6DSOX_XL_ODR_833Hz: 00444 *val = LSM6DSOX_XL_ODR_833Hz; 00445 break; 00446 case LSM6DSOX_XL_ODR_1667Hz: 00447 *val = LSM6DSOX_XL_ODR_1667Hz; 00448 break; 00449 case LSM6DSOX_XL_ODR_3333Hz: 00450 *val = LSM6DSOX_XL_ODR_3333Hz; 00451 break; 00452 case LSM6DSOX_XL_ODR_6667Hz: 00453 *val = LSM6DSOX_XL_ODR_6667Hz; 00454 break; 00455 case LSM6DSOX_XL_ODR_1Hz6: 00456 *val = LSM6DSOX_XL_ODR_1Hz6; 00457 break; 00458 default: 00459 *val = LSM6DSOX_XL_ODR_OFF; 00460 break; 00461 } 00462 return ret; 00463 } 00464 00465 /** 00466 * @brief Gyroscope UI chain full-scale selection.[set] 00467 * 00468 * @param ctx read / write interface definitions 00469 * @param val change the values of fs_g in reg CTRL2_G 00470 * 00471 */ 00472 int32_t lsm6dsox_gy_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t val) 00473 { 00474 lsm6dsox_ctrl2_g_t reg; 00475 int32_t ret; 00476 00477 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); 00478 if (ret == 0) { 00479 reg.fs_g = (uint8_t) val; 00480 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); 00481 } 00482 00483 return ret; 00484 } 00485 00486 /** 00487 * @brief Gyroscope UI chain full-scale selection.[get] 00488 * 00489 * @param ctx read / write interface definitions 00490 * @param val Get the values of fs_g in reg CTRL2_G 00491 * 00492 */ 00493 int32_t lsm6dsox_gy_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t *val) 00494 { 00495 lsm6dsox_ctrl2_g_t reg; 00496 int32_t ret; 00497 00498 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); 00499 switch (reg.fs_g) { 00500 case LSM6DSOX_250dps: 00501 *val = LSM6DSOX_250dps; 00502 break; 00503 case LSM6DSOX_125dps: 00504 *val = LSM6DSOX_125dps; 00505 break; 00506 case LSM6DSOX_500dps: 00507 *val = LSM6DSOX_500dps; 00508 break; 00509 case LSM6DSOX_1000dps: 00510 *val = LSM6DSOX_1000dps; 00511 break; 00512 case LSM6DSOX_2000dps: 00513 *val = LSM6DSOX_2000dps; 00514 break; 00515 default: 00516 *val = LSM6DSOX_250dps; 00517 break; 00518 } 00519 00520 return ret; 00521 } 00522 00523 /** 00524 * @brief Gyroscope UI data rate selection.[set] 00525 * 00526 * @param ctx read / write interface definitions 00527 * @param val change the values of odr_g in reg CTRL2_G 00528 * 00529 */ 00530 int32_t lsm6dsox_gy_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t val) 00531 { 00532 lsm6dsox_odr_g_t odr_gy = val; 00533 lsm6dsox_emb_fsm_enable_t fsm_enable; 00534 lsm6dsox_fsm_odr_t fsm_odr; 00535 lsm6dsox_emb_sens_t emb_sens; 00536 lsm6dsox_mlc_odr_t mlc_odr; 00537 lsm6dsox_ctrl2_g_t reg; 00538 int32_t ret; 00539 00540 /* Check the Finite State Machine data rate constraints */ 00541 ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable); 00542 if (ret == 0) { 00543 if ( (fsm_enable.fsm_enable_a.fsm1_en | 00544 fsm_enable.fsm_enable_a.fsm2_en | 00545 fsm_enable.fsm_enable_a.fsm3_en | 00546 fsm_enable.fsm_enable_a.fsm4_en | 00547 fsm_enable.fsm_enable_a.fsm5_en | 00548 fsm_enable.fsm_enable_a.fsm6_en | 00549 fsm_enable.fsm_enable_a.fsm7_en | 00550 fsm_enable.fsm_enable_a.fsm8_en | 00551 fsm_enable.fsm_enable_b.fsm9_en | 00552 fsm_enable.fsm_enable_b.fsm10_en | 00553 fsm_enable.fsm_enable_b.fsm11_en | 00554 fsm_enable.fsm_enable_b.fsm12_en | 00555 fsm_enable.fsm_enable_b.fsm13_en | 00556 fsm_enable.fsm_enable_b.fsm14_en | 00557 fsm_enable.fsm_enable_b.fsm15_en | 00558 fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){ 00559 00560 ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr); 00561 if (ret == 0) { 00562 switch (fsm_odr) { 00563 case LSM6DSOX_ODR_FSM_12Hz5: 00564 00565 if (val == LSM6DSOX_GY_ODR_OFF){ 00566 odr_gy = LSM6DSOX_GY_ODR_12Hz5; 00567 00568 } else { 00569 odr_gy = val; 00570 } 00571 break; 00572 case LSM6DSOX_ODR_FSM_26Hz: 00573 00574 if (val == LSM6DSOX_GY_ODR_OFF){ 00575 odr_gy = LSM6DSOX_GY_ODR_26Hz; 00576 00577 } else if (val == LSM6DSOX_GY_ODR_12Hz5){ 00578 odr_gy = LSM6DSOX_GY_ODR_26Hz; 00579 00580 } else { 00581 odr_gy = val; 00582 } 00583 break; 00584 case LSM6DSOX_ODR_FSM_52Hz: 00585 00586 if (val == LSM6DSOX_GY_ODR_OFF){ 00587 odr_gy = LSM6DSOX_GY_ODR_52Hz; 00588 00589 } else if (val == LSM6DSOX_GY_ODR_12Hz5){ 00590 odr_gy = LSM6DSOX_GY_ODR_52Hz; 00591 00592 } else if (val == LSM6DSOX_GY_ODR_26Hz){ 00593 odr_gy = LSM6DSOX_GY_ODR_52Hz; 00594 00595 } else { 00596 odr_gy = val; 00597 } 00598 break; 00599 case LSM6DSOX_ODR_FSM_104Hz: 00600 00601 if (val == LSM6DSOX_GY_ODR_OFF){ 00602 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00603 00604 } else if (val == LSM6DSOX_GY_ODR_12Hz5){ 00605 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00606 00607 } else if (val == LSM6DSOX_GY_ODR_26Hz){ 00608 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00609 00610 } else if (val == LSM6DSOX_GY_ODR_52Hz){ 00611 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00612 00613 } else { 00614 odr_gy = val; 00615 } 00616 break; 00617 default: 00618 odr_gy = val; 00619 break; 00620 } 00621 } 00622 } 00623 } 00624 00625 /* Check the Machine Learning Core data rate constraints */ 00626 emb_sens.mlc = PROPERTY_DISABLE; 00627 if (ret == 0) { 00628 ret = lsm6dsox_embedded_sens_get(ctx, &emb_sens); 00629 if ( emb_sens.mlc == PROPERTY_ENABLE ){ 00630 00631 ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr); 00632 if (ret == 0) { 00633 switch (mlc_odr) { 00634 case LSM6DSOX_ODR_PRGS_12Hz5: 00635 00636 if (val == LSM6DSOX_GY_ODR_OFF){ 00637 odr_gy = LSM6DSOX_GY_ODR_12Hz5; 00638 00639 } else { 00640 odr_gy = val; 00641 } 00642 break; 00643 case LSM6DSOX_ODR_PRGS_26Hz: 00644 00645 if (val == LSM6DSOX_GY_ODR_OFF){ 00646 odr_gy = LSM6DSOX_GY_ODR_26Hz; 00647 00648 } else if (val == LSM6DSOX_GY_ODR_12Hz5){ 00649 odr_gy = LSM6DSOX_GY_ODR_26Hz; 00650 00651 } else { 00652 odr_gy = val; 00653 } 00654 break; 00655 case LSM6DSOX_ODR_PRGS_52Hz: 00656 00657 if (val == LSM6DSOX_GY_ODR_OFF){ 00658 odr_gy = LSM6DSOX_GY_ODR_52Hz; 00659 00660 } else if (val == LSM6DSOX_GY_ODR_12Hz5){ 00661 odr_gy = LSM6DSOX_GY_ODR_52Hz; 00662 00663 } else if (val == LSM6DSOX_GY_ODR_26Hz){ 00664 odr_gy = LSM6DSOX_GY_ODR_52Hz; 00665 00666 } else { 00667 odr_gy = val; 00668 } 00669 break; 00670 case LSM6DSOX_ODR_PRGS_104Hz: 00671 00672 if (val == LSM6DSOX_GY_ODR_OFF){ 00673 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00674 00675 } else if (val == LSM6DSOX_GY_ODR_12Hz5){ 00676 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00677 00678 } else if (val == LSM6DSOX_GY_ODR_26Hz){ 00679 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00680 00681 } else if (val == LSM6DSOX_GY_ODR_52Hz){ 00682 odr_gy = LSM6DSOX_GY_ODR_104Hz; 00683 00684 } else { 00685 odr_gy = val; 00686 } 00687 break; 00688 default: 00689 odr_gy = val; 00690 break; 00691 } 00692 } 00693 } 00694 } 00695 if (ret == 0) { 00696 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); 00697 } 00698 if (ret == 0) { 00699 reg.odr_g = (uint8_t) odr_gy; 00700 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); 00701 } 00702 00703 return ret; 00704 } 00705 00706 /** 00707 * @brief Gyroscope UI data rate selection.[get] 00708 * 00709 * @param ctx read / write interface definitions 00710 * @param val Get the values of odr_g in reg CTRL2_G 00711 * 00712 */ 00713 int32_t lsm6dsox_gy_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t *val) 00714 { 00715 lsm6dsox_ctrl2_g_t reg; 00716 int32_t ret; 00717 00718 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); 00719 switch (reg.odr_g) { 00720 case LSM6DSOX_GY_ODR_OFF: 00721 *val = LSM6DSOX_GY_ODR_OFF; 00722 break; 00723 case LSM6DSOX_GY_ODR_12Hz5: 00724 *val = LSM6DSOX_GY_ODR_12Hz5; 00725 break; 00726 case LSM6DSOX_GY_ODR_26Hz: 00727 *val = LSM6DSOX_GY_ODR_26Hz; 00728 break; 00729 case LSM6DSOX_GY_ODR_52Hz: 00730 *val = LSM6DSOX_GY_ODR_52Hz; 00731 break; 00732 case LSM6DSOX_GY_ODR_104Hz: 00733 *val = LSM6DSOX_GY_ODR_104Hz; 00734 break; 00735 case LSM6DSOX_GY_ODR_208Hz: 00736 *val = LSM6DSOX_GY_ODR_208Hz; 00737 break; 00738 case LSM6DSOX_GY_ODR_417Hz: 00739 *val = LSM6DSOX_GY_ODR_417Hz; 00740 break; 00741 case LSM6DSOX_GY_ODR_833Hz: 00742 *val = LSM6DSOX_GY_ODR_833Hz; 00743 break; 00744 case LSM6DSOX_GY_ODR_1667Hz: 00745 *val = LSM6DSOX_GY_ODR_1667Hz; 00746 break; 00747 case LSM6DSOX_GY_ODR_3333Hz: 00748 *val = LSM6DSOX_GY_ODR_3333Hz; 00749 break; 00750 case LSM6DSOX_GY_ODR_6667Hz: 00751 *val = LSM6DSOX_GY_ODR_6667Hz; 00752 break; 00753 default: 00754 *val = LSM6DSOX_GY_ODR_OFF; 00755 break; 00756 } 00757 return ret; 00758 } 00759 00760 /** 00761 * @brief Block data update.[set] 00762 * 00763 * @param ctx read / write interface definitions 00764 * @param val change the values of bdu in reg CTRL3_C 00765 * 00766 */ 00767 int32_t lsm6dsox_block_data_update_set(lsm6dsox_ctx_t *ctx, uint8_t val) 00768 { 00769 lsm6dsox_ctrl3_c_t reg; 00770 int32_t ret; 00771 00772 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 00773 if (ret == 0) { 00774 reg.bdu = val; 00775 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 00776 } 00777 return ret; 00778 } 00779 00780 /** 00781 * @brief Block data update.[get] 00782 * 00783 * @param ctx read / write interface definitions 00784 * @param val change the values of bdu in reg CTRL3_C 00785 * 00786 */ 00787 int32_t lsm6dsox_block_data_update_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 00788 { 00789 lsm6dsox_ctrl3_c_t reg; 00790 int32_t ret; 00791 00792 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 00793 *val = reg.bdu; 00794 00795 return ret; 00796 } 00797 00798 /** 00799 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), 00800 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] 00801 * 00802 * @param ctx read / write interface definitions 00803 * @param val change the values of usr_off_w in reg CTRL6_C 00804 * 00805 */ 00806 int32_t lsm6dsox_xl_offset_weight_set(lsm6dsox_ctx_t *ctx, 00807 lsm6dsox_usr_off_w_t val) 00808 { 00809 lsm6dsox_ctrl6_c_t reg; 00810 int32_t ret; 00811 00812 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 00813 if (ret == 0) { 00814 reg.usr_off_w = (uint8_t)val; 00815 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 00816 } 00817 return ret; 00818 } 00819 00820 /** 00821 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), 00822 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] 00823 * 00824 * @param ctx read / write interface definitions 00825 * @param val Get the values of usr_off_w in reg CTRL6_C 00826 * 00827 */ 00828 int32_t lsm6dsox_xl_offset_weight_get(lsm6dsox_ctx_t *ctx, 00829 lsm6dsox_usr_off_w_t *val) 00830 { 00831 lsm6dsox_ctrl6_c_t reg; 00832 int32_t ret; 00833 00834 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 00835 00836 switch (reg.usr_off_w) { 00837 case LSM6DSOX_LSb_1mg: 00838 *val = LSM6DSOX_LSb_1mg; 00839 break; 00840 case LSM6DSOX_LSb_16mg: 00841 *val = LSM6DSOX_LSb_16mg; 00842 break; 00843 default: 00844 *val = LSM6DSOX_LSb_1mg; 00845 break; 00846 } 00847 return ret; 00848 } 00849 00850 /** 00851 * @brief Accelerometer power mode.[set] 00852 * 00853 * @param ctx read / write interface definitions 00854 * @param val change the values of xl_hm_mode in 00855 * reg CTRL6_C 00856 * 00857 */ 00858 int32_t lsm6dsox_xl_power_mode_set(lsm6dsox_ctx_t *ctx, 00859 lsm6dsox_xl_hm_mode_t val) 00860 { 00861 lsm6dsox_ctrl5_c_t ctrl5_c; 00862 lsm6dsox_ctrl6_c_t ctrl6_c; 00863 int32_t ret; 00864 00865 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1); 00866 if (ret == 0) { 00867 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1; 00868 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1); 00869 } 00870 if (ret == 0) { 00871 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1); 00872 } 00873 if (ret == 0) { 00874 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; 00875 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1); 00876 } 00877 return ret; 00878 } 00879 00880 /** 00881 * @brief Accelerometer power mode.[get] 00882 * 00883 * @param ctx read / write interface definitions 00884 * @param val Get the values of xl_hm_mode in reg CTRL6_C 00885 * 00886 */ 00887 int32_t lsm6dsox_xl_power_mode_get(lsm6dsox_ctx_t *ctx, 00888 lsm6dsox_xl_hm_mode_t *val) 00889 { 00890 lsm6dsox_ctrl5_c_t ctrl5_c; 00891 lsm6dsox_ctrl6_c_t ctrl6_c; 00892 int32_t ret; 00893 00894 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1); 00895 if (ret == 0) { 00896 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1); 00897 switch ( (ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) { 00898 case LSM6DSOX_HIGH_PERFORMANCE_MD: 00899 *val = LSM6DSOX_HIGH_PERFORMANCE_MD; 00900 break; 00901 case LSM6DSOX_LOW_NORMAL_POWER_MD: 00902 *val = LSM6DSOX_LOW_NORMAL_POWER_MD; 00903 break; 00904 case LSM6DSOX_ULTRA_LOW_POWER_MD: 00905 *val = LSM6DSOX_ULTRA_LOW_POWER_MD; 00906 break; 00907 default: 00908 *val = LSM6DSOX_HIGH_PERFORMANCE_MD; 00909 break; 00910 } 00911 } 00912 return ret; 00913 } 00914 00915 /** 00916 * @brief Operating mode for gyroscope.[set] 00917 * 00918 * @param ctx read / write interface definitions 00919 * @param val change the values of g_hm_mode in reg CTRL7_G 00920 * 00921 */ 00922 int32_t lsm6dsox_gy_power_mode_set(lsm6dsox_ctx_t *ctx, 00923 lsm6dsox_g_hm_mode_t val) 00924 { 00925 lsm6dsox_ctrl7_g_t reg; 00926 int32_t ret; 00927 00928 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 00929 if (ret == 0) { 00930 reg.g_hm_mode = (uint8_t)val; 00931 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 00932 } 00933 return ret; 00934 } 00935 00936 /** 00937 * @brief Operating mode for gyroscope.[get] 00938 * 00939 * @param ctx read / write interface definitions 00940 * @param val Get the values of g_hm_mode in reg CTRL7_G 00941 * 00942 */ 00943 int32_t lsm6dsox_gy_power_mode_get(lsm6dsox_ctx_t *ctx, 00944 lsm6dsox_g_hm_mode_t *val) 00945 { 00946 lsm6dsox_ctrl7_g_t reg; 00947 int32_t ret; 00948 00949 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 00950 switch (reg.g_hm_mode) { 00951 case LSM6DSOX_GY_HIGH_PERFORMANCE: 00952 *val = LSM6DSOX_GY_HIGH_PERFORMANCE; 00953 break; 00954 case LSM6DSOX_GY_NORMAL: 00955 *val = LSM6DSOX_GY_NORMAL; 00956 break; 00957 default: 00958 *val = LSM6DSOX_GY_HIGH_PERFORMANCE; 00959 break; 00960 } 00961 return ret; 00962 } 00963 00964 /** 00965 * @brief The STATUS_REG register is read by the primary interface.[get] 00966 * 00967 * @param ctx read / write interface definitions 00968 * @param val register STATUS_REG 00969 * 00970 */ 00971 int32_t lsm6dsox_status_reg_get(lsm6dsox_ctx_t *ctx, lsm6dsox_status_reg_t *val) 00972 { 00973 int32_t ret; 00974 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*) val, 1); 00975 return ret; 00976 } 00977 00978 /** 00979 * @brief Accelerometer new data available.[get] 00980 * 00981 * @param ctx read / write interface definitions 00982 * @param val change the values of xlda in reg STATUS_REG 00983 * 00984 */ 00985 int32_t lsm6dsox_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 00986 { 00987 lsm6dsox_status_reg_t reg; 00988 int32_t ret; 00989 00990 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1); 00991 *val = reg.xlda; 00992 00993 return ret; 00994 } 00995 00996 /** 00997 * @brief Gyroscope new data available.[get] 00998 * 00999 * @param ctx read / write interface definitions 01000 * @param val change the values of gda in reg STATUS_REG 01001 * 01002 */ 01003 int32_t lsm6dsox_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 01004 { 01005 lsm6dsox_status_reg_t reg; 01006 int32_t ret; 01007 01008 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1); 01009 *val = reg.gda; 01010 01011 return ret; 01012 } 01013 01014 /** 01015 * @brief Temperature new data available.[get] 01016 * 01017 * @param ctx read / write interface definitions 01018 * @param val change the values of tda in reg STATUS_REG 01019 * 01020 */ 01021 int32_t lsm6dsox_temp_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 01022 { 01023 lsm6dsox_status_reg_t reg; 01024 int32_t ret; 01025 01026 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1); 01027 *val = reg.tda; 01028 01029 return ret; 01030 } 01031 01032 /** 01033 * @brief Accelerometer X-axis user offset correction expressed in 01034 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). 01035 * The value must be in the range [-127 127].[set] 01036 * 01037 * @param ctx read / write interface definitions 01038 * @param buff buffer that contains data to write 01039 * 01040 */ 01041 int32_t lsm6dsox_xl_usr_offset_x_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01042 { 01043 int32_t ret; 01044 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1); 01045 return ret; 01046 } 01047 01048 /** 01049 * @brief Accelerometer X-axis user offset correction expressed in two’s 01050 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 01051 * The value must be in the range [-127 127].[get] 01052 * 01053 * @param ctx read / write interface definitions 01054 * @param buff buffer that stores data read 01055 * 01056 */ 01057 int32_t lsm6dsox_xl_usr_offset_x_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01058 { 01059 int32_t ret; 01060 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1); 01061 return ret; 01062 } 01063 01064 /** 01065 * @brief Accelerometer Y-axis user offset correction expressed in two’s 01066 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 01067 * The value must be in the range [-127 127].[set] 01068 * 01069 * @param ctx read / write interface definitions 01070 * @param buff buffer that contains data to write 01071 * 01072 */ 01073 int32_t lsm6dsox_xl_usr_offset_y_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01074 { 01075 int32_t ret; 01076 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1); 01077 return ret; 01078 } 01079 01080 /** 01081 * @brief Accelerometer Y-axis user offset correction expressed in two’s 01082 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 01083 * The value must be in the range [-127 127].[get] 01084 * 01085 * @param ctx read / write interface definitions 01086 * @param buff buffer that stores data read 01087 * 01088 */ 01089 int32_t lsm6dsox_xl_usr_offset_y_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01090 { 01091 int32_t ret; 01092 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1); 01093 return ret; 01094 } 01095 01096 /** 01097 * @brief Accelerometer Z-axis user offset correction expressed in two’s 01098 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 01099 * The value must be in the range [-127 127].[set] 01100 * 01101 * @param ctx read / write interface definitions 01102 * @param buff buffer that contains data to write 01103 * 01104 */ 01105 int32_t lsm6dsox_xl_usr_offset_z_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01106 { 01107 int32_t ret; 01108 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1); 01109 return ret; 01110 } 01111 01112 /** 01113 * @brief Accelerometer Z-axis user offset correction expressed in two’s 01114 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 01115 * The value must be in the range [-127 127].[get] 01116 * 01117 * @param ctx read / write interface definitions 01118 * @param buff buffer that stores data read 01119 * 01120 */ 01121 int32_t lsm6dsox_xl_usr_offset_z_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01122 { 01123 int32_t ret; 01124 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1); 01125 return ret; 01126 } 01127 01128 /** 01129 * @brief Enables user offset on out.[set] 01130 * 01131 * @param ctx read / write interface definitions 01132 * @param val change the values of usr_off_on_out in reg CTRL7_G 01133 * 01134 */ 01135 int32_t lsm6dsox_xl_usr_offset_set(lsm6dsox_ctx_t *ctx, uint8_t val) 01136 { 01137 lsm6dsox_ctrl7_g_t reg; 01138 int32_t ret; 01139 01140 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 01141 if (ret == 0) { 01142 reg.usr_off_on_out = val; 01143 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 01144 } 01145 return ret; 01146 } 01147 01148 /** 01149 * @brief User offset on out flag.[get] 01150 * 01151 * @param ctx read / write interface definitions 01152 * @param val values of usr_off_on_out in reg CTRL7_G 01153 * 01154 */ 01155 int32_t lsm6dsox_xl_usr_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 01156 { 01157 lsm6dsox_ctrl7_g_t reg; 01158 int32_t ret; 01159 01160 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 01161 *val = reg.usr_off_on_out; 01162 01163 return ret; 01164 } 01165 01166 /** 01167 * @} 01168 * 01169 */ 01170 01171 /** 01172 * @defgroup LSM6DSOX_Timestamp 01173 * @brief This section groups all the functions that manage the 01174 * timestamp generation. 01175 * @{ 01176 * 01177 */ 01178 01179 /** 01180 * @brief Reset timestamp counter.[set] 01181 * 01182 * @param ctx Read / write interface definitions.(ptr) 01183 * @retval Interface status (MANDATORY: return 0 -> no Error). 01184 * 01185 */ 01186 int32_t lsm6dsox_timestamp_rst(lsm6dsox_ctx_t *ctx) 01187 { 01188 uint8_t rst_val = 0xAA; 01189 01190 return lsm6dsox_write_reg(ctx, LSM6DSOX_TIMESTAMP2, &rst_val, 1); 01191 } 01192 01193 /** 01194 * @brief Enables timestamp counter.[set] 01195 * 01196 * @param ctx read / write interface definitions 01197 * @param val change the values of timestamp_en in reg CTRL10_C 01198 * 01199 */ 01200 int32_t lsm6dsox_timestamp_set(lsm6dsox_ctx_t *ctx, uint8_t val) 01201 { 01202 lsm6dsox_ctrl10_c_t reg; 01203 int32_t ret; 01204 01205 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1); 01206 if (ret == 0) { 01207 reg.timestamp_en = val; 01208 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1); 01209 } 01210 return ret; 01211 } 01212 01213 /** 01214 * @brief Enables timestamp counter.[get] 01215 * 01216 * @param ctx read / write interface definitions 01217 * @param val change the values of timestamp_en in reg CTRL10_C 01218 * 01219 */ 01220 int32_t lsm6dsox_timestamp_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 01221 { 01222 lsm6dsox_ctrl10_c_t reg; 01223 int32_t ret; 01224 01225 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1); 01226 *val = reg.timestamp_en; 01227 01228 return ret; 01229 } 01230 01231 /** 01232 * @brief Timestamp first data output register (r). 01233 * The value is expressed as a 32-bit word and the bit 01234 * resolution is 25 μs.[get] 01235 * 01236 * @param ctx read / write interface definitions 01237 * @param buff buffer that stores data read 01238 * 01239 */ 01240 int32_t lsm6dsox_timestamp_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01241 { 01242 int32_t ret; 01243 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4); 01244 return ret; 01245 } 01246 01247 /** 01248 * @} 01249 * 01250 */ 01251 01252 /** 01253 * @defgroup LSM6DSOX_Data output 01254 * @brief This section groups all the data output functions. 01255 * @{ 01256 * 01257 */ 01258 01259 /** 01260 * @brief Circular burst-mode (rounding) read of the output 01261 * registers.[set] 01262 * 01263 * @param ctx read / write interface definitions 01264 * @param val change the values of rounding in reg CTRL5_C 01265 * 01266 */ 01267 int32_t lsm6dsox_rounding_mode_set(lsm6dsox_ctx_t *ctx, 01268 lsm6dsox_rounding_t val) 01269 { 01270 lsm6dsox_ctrl5_c_t reg; 01271 int32_t ret; 01272 01273 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 01274 if (ret == 0) { 01275 reg.rounding = (uint8_t)val; 01276 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 01277 } 01278 return ret; 01279 } 01280 01281 /** 01282 * @brief Gyroscope UI chain full-scale selection.[get] 01283 * 01284 * @param ctx read / write interface definitions 01285 * @param val Get the values of rounding in reg CTRL5_C 01286 * 01287 */ 01288 int32_t lsm6dsox_rounding_mode_get(lsm6dsox_ctx_t *ctx, 01289 lsm6dsox_rounding_t *val) 01290 { 01291 lsm6dsox_ctrl5_c_t reg; 01292 int32_t ret; 01293 01294 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 01295 switch (reg.rounding) { 01296 case LSM6DSOX_NO_ROUND: 01297 *val = LSM6DSOX_NO_ROUND; 01298 break; 01299 case LSM6DSOX_ROUND_XL: 01300 *val = LSM6DSOX_ROUND_XL; 01301 break; 01302 case LSM6DSOX_ROUND_GY: 01303 *val = LSM6DSOX_ROUND_GY; 01304 break; 01305 case LSM6DSOX_ROUND_GY_XL: 01306 *val = LSM6DSOX_ROUND_GY_XL; 01307 break; 01308 default: 01309 *val = LSM6DSOX_NO_ROUND; 01310 break; 01311 } 01312 return ret; 01313 } 01314 01315 /** 01316 * @brief rounding_on_status: [set] Source register rounding function in 01317 * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh), 01318 * TAP_SRC (1Ch), D6D_SRC (1Dh), 01319 * STATUS_REG (1Eh) and 01320 * EMB_FUNC_STATUS_MAINPAGE(35h), 01321 * FSM_STATUS_A_MAINPAGE (36h), 01322 * FSM_STATUS_B_MAINPAGE (37h), 01323 * MLC_STATUS_MAINPAGE (38h), 01324 * STATUS_MASTER_MAINPAGE (39h), 01325 * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh). 01326 * 01327 * @param ctx read / write interface definitions 01328 * @param lsm6dsox_rounding_status_t: change the values of rounding_status 01329 * in reg CTRL7_G 01330 * 01331 */ 01332 int32_t lsm6dsox_rounding_on_status_set(lsm6dsox_ctx_t *ctx, 01333 lsm6dsox_rounding_status_t val) 01334 { 01335 lsm6dsox_ctrl5_c_t reg; 01336 int32_t ret; 01337 01338 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 01339 if (ret == 0) { 01340 reg.rounding_status = (uint8_t)val; 01341 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 01342 } 01343 01344 return ret; 01345 } 01346 01347 /** 01348 * @brief rounding_on_status: [get] Source register rounding function in 01349 * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh), 01350 * TAP_SRC (1Ch), D6D_SRC (1Dh), 01351 * STATUS_REG (1Eh) and 01352 * EMB_FUNC_STATUS_MAINPAGE(35h), 01353 * FSM_STATUS_A_MAINPAGE (36h), 01354 * FSM_STATUS_B_MAINPAGE (37h), 01355 * MLC_STATUS_MAINPAGE (38h), 01356 * STATUS_MASTER_MAINPAGE (39h), 01357 * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh). 01358 * 01359 * @param ctx read / write interface definitions 01360 * @param lsm6dsox_rounding_status_t: Get the values of rounding_status 01361 * in reg CTRL7_G 01362 * 01363 */ 01364 int32_t lsm6dsox_rounding_on_status_get(lsm6dsox_ctx_t *ctx, 01365 lsm6dsox_rounding_status_t *val) 01366 { 01367 lsm6dsox_ctrl5_c_t reg; 01368 int32_t ret; 01369 01370 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 01371 switch (reg.rounding_status) { 01372 case LSM6DSOX_STAT_RND_DISABLE: 01373 *val = LSM6DSOX_STAT_RND_DISABLE; 01374 break; 01375 case LSM6DSOX_STAT_RND_ENABLE: 01376 *val = LSM6DSOX_STAT_RND_ENABLE; 01377 break; 01378 default: 01379 *val = LSM6DSOX_STAT_RND_DISABLE; 01380 break; 01381 } 01382 return ret; 01383 } 01384 01385 /** 01386 * @brief Temperature data output register (r). 01387 * L and H registers together express a 16-bit word in two’s 01388 * complement.[get] 01389 * 01390 * @param ctx read / write interface definitions 01391 * @param buff buffer that stores data read 01392 * 01393 */ 01394 int32_t lsm6dsox_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01395 { 01396 int32_t ret; 01397 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2); 01398 return ret; 01399 } 01400 01401 /** 01402 * @brief Angular rate sensor. The value is expressed as a 16-bit 01403 * word in two’s complement.[get] 01404 * 01405 * @param ctx read / write interface definitions 01406 * @param buff buffer that stores data read 01407 * 01408 */ 01409 int32_t lsm6dsox_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01410 { 01411 int32_t ret; 01412 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6); 01413 return ret; 01414 } 01415 01416 /** 01417 * @brief Linear acceleration output register. 01418 * The value is expressed as a 16-bit word in two’s complement.[get] 01419 * 01420 * @param ctx read / write interface definitions 01421 * @param buff buffer that stores data read 01422 * 01423 */ 01424 int32_t lsm6dsox_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01425 { 01426 int32_t ret; 01427 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6); 01428 return ret; 01429 } 01430 01431 /** 01432 * @brief FIFO data output [get] 01433 * 01434 * @param ctx read / write interface definitions 01435 * @param buff buffer that stores data read 01436 * 01437 */ 01438 int32_t lsm6dsox_fifo_out_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01439 { 01440 int32_t ret; 01441 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, buff, 6); 01442 return ret; 01443 } 01444 01445 /** 01446 * @brief ois_angular_rate_raw: [get] OIS angular rate sensor. 01447 * The value is expressed as a 01448 * 16-bit word in two’s complement. 01449 * 01450 * @param ctx read / write interface definitions 01451 * @param uint8_t * : buffer that stores data read 01452 * 01453 */ 01454 int32_t lsm6dsox_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01455 { 01456 return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6); 01457 } 01458 01459 /** 01460 * @brief ois_acceleration_raw: [get] OIS Linear acceleration output register. 01461 * The value is expressed as a 01462 * 16-bit word in two’s complement. 01463 * 01464 * @param ctx read / write interface definitions 01465 * @param uint8_t * : buffer that stores data read 01466 * 01467 */ 01468 int32_t lsm6dsox_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01469 { 01470 return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6); 01471 } 01472 01473 /** 01474 * @brief aux_temperature_raw: [get] Temperature from auxiliary 01475 * interface. 01476 * The value is expressed as a 01477 * 16-bit word in two’s complement. 01478 * 01479 * @param ctx read / write interface definitions 01480 * @param uint8_t * : buffer that stores data read 01481 * 01482 */ 01483 int32_t lsm6dsox_aux_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01484 { 01485 return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2); 01486 } 01487 01488 /** 01489 * @brief aux_ois_angular_rate_raw: [get] OIS angular rate sensor from 01490 * auxiliary interface. 01491 * The value is expressed as a 01492 * 16-bit word in two’s complement. 01493 * 01494 * @param ctx read / write interface definitions 01495 * @param uint8_t * : buffer that stores data read 01496 * 01497 */ 01498 int32_t lsm6dsox_aux_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01499 { 01500 return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6); 01501 } 01502 01503 /** 01504 * @brief aux_ois_acceleration_raw: [get] OIS linear acceleration output 01505 * register from auxiliary interface. 01506 * The value is expressed as a 01507 * 16-bit word in two’s complement. 01508 * 01509 * @param ctx read / write interface definitions 01510 * @param uint8_t * : buffer that stores data read 01511 * 01512 */ 01513 int32_t lsm6dsox_aux_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01514 { 01515 return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6); 01516 } 01517 01518 /** 01519 * @brief Step counter output register.[get] 01520 * 01521 * @param ctx read / write interface definitions 01522 * @param buff buffer that stores data read 01523 * 01524 */ 01525 int32_t lsm6dsox_number_of_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01526 { 01527 int32_t ret; 01528 01529 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 01530 if (ret == 0) { 01531 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2); 01532 } 01533 if (ret == 0) { 01534 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 01535 } 01536 return ret; 01537 } 01538 01539 /** 01540 * @brief Reset step counter register.[get] 01541 * 01542 * @param ctx read / write interface definitions 01543 * 01544 */ 01545 int32_t lsm6dsox_steps_reset(lsm6dsox_ctx_t *ctx) 01546 { 01547 lsm6dsox_emb_func_src_t reg; 01548 int32_t ret; 01549 01550 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 01551 if (ret == 0) { 01552 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)®, 1); 01553 } 01554 if (ret == 0) { 01555 reg.pedo_rst_step = PROPERTY_ENABLE; 01556 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)®, 1); 01557 } 01558 if (ret == 0) { 01559 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 01560 } 01561 return ret; 01562 } 01563 01564 /** 01565 * @brief prgsens_out: [get] Output value of all MLCx decision trees. 01566 * 01567 * @param ctx_t *ctx: read / write interface definitions 01568 * @param uint8_t * : buffer that stores data read 01569 * 01570 */ 01571 int32_t lsm6dsox_mlc_out_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01572 { 01573 int32_t ret; 01574 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 01575 if (ret == 0) { 01576 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8); 01577 } 01578 if (ret == 0) { 01579 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 01580 } 01581 return ret; 01582 } 01583 01584 /** 01585 * @} 01586 * 01587 */ 01588 01589 /** 01590 * @defgroup LSM6DSOX_common 01591 * @brief This section groups common usefull functions. 01592 * @{ 01593 * 01594 */ 01595 01596 /** 01597 * @brief Difference in percentage of the effective ODR(and timestamp rate) 01598 * with respect to the typical. 01599 * Step: 0.15%. 8-bit format, 2's complement.[set] 01600 * 01601 * @param ctx read / write interface definitions 01602 * @param val change the values of freq_fine in reg 01603 * INTERNAL_FREQ_FINE 01604 * 01605 */ 01606 int32_t lsm6dsox_odr_cal_reg_set(lsm6dsox_ctx_t *ctx, uint8_t val) 01607 { 01608 lsm6dsox_internal_freq_fine_t reg; 01609 int32_t ret; 01610 01611 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)®, 1); 01612 if (ret == 0) { 01613 reg.freq_fine = val; 01614 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, 01615 (uint8_t*)®, 1); 01616 } 01617 return ret; 01618 } 01619 01620 /** 01621 * @brief Difference in percentage of the effective ODR(and timestamp rate) 01622 * with respect to the typical. 01623 * Step: 0.15%. 8-bit format, 2's complement.[get] 01624 * 01625 * @param ctx read / write interface definitions 01626 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE 01627 * 01628 */ 01629 int32_t lsm6dsox_odr_cal_reg_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 01630 { 01631 lsm6dsox_internal_freq_fine_t reg; 01632 int32_t ret; 01633 01634 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)®, 1); 01635 *val = reg.freq_fine; 01636 01637 return ret; 01638 } 01639 01640 01641 /** 01642 * @brief Enable access to the embedded functions/sensor 01643 * hub configuration registers.[set] 01644 * 01645 * @param ctx read / write interface definitions 01646 * @param val change the values of reg_access in 01647 * reg FUNC_CFG_ACCESS 01648 * 01649 */ 01650 int32_t lsm6dsox_mem_bank_set(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t val) 01651 { 01652 lsm6dsox_func_cfg_access_t reg; 01653 int32_t ret; 01654 01655 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1); 01656 if (ret == 0) { 01657 reg.reg_access = (uint8_t)val; 01658 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1); 01659 } 01660 return ret; 01661 } 01662 01663 /** 01664 * @brief Enable access to the embedded functions/sensor 01665 * hub configuration registers.[get] 01666 * 01667 * @param ctx read / write interface definitions 01668 * @param val Get the values of reg_access in 01669 * reg FUNC_CFG_ACCESS 01670 * 01671 */ 01672 int32_t lsm6dsox_mem_bank_get(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t *val) 01673 { 01674 lsm6dsox_func_cfg_access_t reg; 01675 int32_t ret; 01676 01677 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1); 01678 switch (reg.reg_access) { 01679 case LSM6DSOX_USER_BANK: 01680 *val = LSM6DSOX_USER_BANK; 01681 break; 01682 case LSM6DSOX_SENSOR_HUB_BANK: 01683 *val = LSM6DSOX_SENSOR_HUB_BANK; 01684 break; 01685 case LSM6DSOX_EMBEDDED_FUNC_BANK: 01686 *val = LSM6DSOX_EMBEDDED_FUNC_BANK; 01687 break; 01688 default: 01689 *val = LSM6DSOX_USER_BANK; 01690 break; 01691 } 01692 return ret; 01693 } 01694 01695 /** 01696 * @brief Write a line(byte) in a page.[set] 01697 * 01698 * @param ctx read / write interface definitions 01699 * @param uint8_t address: page line address 01700 * @param val value to write 01701 * 01702 */ 01703 int32_t lsm6dsox_ln_pg_write_byte(lsm6dsox_ctx_t *ctx, uint16_t address, 01704 uint8_t *val) 01705 { 01706 lsm6dsox_page_rw_t page_rw; 01707 lsm6dsox_page_sel_t page_sel; 01708 lsm6dsox_page_address_t page_address; 01709 int32_t ret; 01710 01711 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 01712 01713 if (ret == 0) { 01714 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01715 } 01716 if (ret == 0) { 01717 page_rw.page_rw = 0x02; /* page_write enable */ 01718 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01719 } 01720 if (ret == 0) { 01721 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01722 } 01723 01724 if (ret == 0) { 01725 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); 01726 page_sel.not_used_01 = 1; 01727 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01728 } 01729 if (ret == 0) { 01730 page_address.page_addr = (uint8_t)address & 0xFFU; 01731 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, 01732 (uint8_t*)&page_address, 1); 01733 } 01734 if (ret == 0) { 01735 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1); 01736 } 01737 if (ret == 0) { 01738 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01739 } 01740 if (ret == 0) { 01741 page_rw.page_rw = 0x00; /* page_write disable */ 01742 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01743 } 01744 if (ret == 0) { 01745 01746 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 01747 } 01748 return ret; 01749 } 01750 01751 /** 01752 * @brief Write buffer in a page.[set] 01753 * 01754 * @param ctx read / write interface definitions 01755 * @param uint8_t address: page line address 01756 * @param uint8_t *buf: buffer to write 01757 * @param uint8_t len: buffer len 01758 * 01759 */ 01760 int32_t lsm6dsox_ln_pg_write(lsm6dsox_ctx_t *ctx, uint16_t address, 01761 uint8_t *buf, uint8_t len) 01762 { 01763 lsm6dsox_page_rw_t page_rw; 01764 lsm6dsox_page_sel_t page_sel; 01765 lsm6dsox_page_address_t page_address; 01766 int32_t ret; 01767 uint8_t msb, lsb; 01768 uint8_t i ; 01769 01770 msb = ((uint8_t)(address >> 8) & 0x0FU); 01771 lsb = (uint8_t)address & 0xFFU; 01772 01773 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 01774 if (ret == 0) { 01775 01776 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01777 } 01778 if (ret == 0) { 01779 page_rw.page_rw = 0x02; /* page_write enable*/ 01780 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01781 } 01782 if (ret == 0) { 01783 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01784 } 01785 if (ret == 0) { 01786 page_sel.page_sel = msb; 01787 page_sel.not_used_01 = 1; 01788 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01789 } 01790 if (ret == 0) { 01791 page_address.page_addr = lsb; 01792 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, 01793 (uint8_t*)&page_address, 1); 01794 } 01795 01796 if (ret == 0) { 01797 for (i = 0; ( (i < len) && (ret == 0) ); i++) 01798 { 01799 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1); 01800 lsb++; 01801 /* Check if page wrap */ 01802 if ( (lsb == 0x00U) && (ret == 0) ) { 01803 msb++; 01804 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*)&page_sel, 1); 01805 if (ret == 0) { 01806 page_sel.page_sel = msb; 01807 page_sel.not_used_01 = 1; 01808 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, 01809 (uint8_t*)&page_sel, 1); 01810 } 01811 } 01812 } 01813 } 01814 page_sel.page_sel = 0; 01815 page_sel.not_used_01 = 1; 01816 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01817 01818 if (ret == 0) { 01819 01820 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01821 } 01822 if (ret == 0) { 01823 page_rw.page_rw = 0x00; /* page_write disable */ 01824 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01825 } 01826 01827 if (ret == 0) { 01828 01829 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 01830 } 01831 return ret; 01832 } 01833 01834 /** 01835 * @brief Read a line(byte) in a page.[get] 01836 * 01837 * @param ctx read / write interface definitions 01838 * @param uint8_t address: page line address 01839 * @param val read value 01840 * 01841 */ 01842 int32_t lsm6dsox_ln_pg_read_byte(lsm6dsox_ctx_t *ctx, uint16_t address, 01843 uint8_t *val) 01844 { 01845 lsm6dsox_page_rw_t page_rw; 01846 lsm6dsox_page_sel_t page_sel; 01847 lsm6dsox_page_address_t page_address; 01848 int32_t ret; 01849 01850 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 01851 if (ret == 0) { 01852 01853 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01854 } 01855 if (ret == 0) { 01856 page_rw.page_rw = 0x01; /* page_read enable*/ 01857 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01858 } 01859 if (ret == 0) { 01860 01861 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01862 } 01863 if (ret == 0) { 01864 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); 01865 page_sel.not_used_01 = 1; 01866 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); 01867 } 01868 if (ret == 0) { 01869 page_address.page_addr = (uint8_t)address & 0x00FFU; 01870 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, 01871 (uint8_t*)&page_address, 1); 01872 } 01873 if (ret == 0) { 01874 01875 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1); 01876 } 01877 if (ret == 0) { 01878 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01879 } 01880 if (ret == 0) { 01881 page_rw.page_rw = 0x00; /* page_read disable */ 01882 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 01883 } 01884 if (ret == 0) { 01885 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 01886 } 01887 01888 return ret; 01889 } 01890 01891 /** 01892 * @brief Data-ready pulsed / letched mode.[set] 01893 * 01894 * @param ctx read / write interface definitions 01895 * @param val change the values of 01896 * dataready_pulsed in 01897 * reg COUNTER_BDR_REG1 01898 * 01899 */ 01900 int32_t lsm6dsox_data_ready_mode_set(lsm6dsox_ctx_t *ctx, 01901 lsm6dsox_dataready_pulsed_t val) 01902 { 01903 lsm6dsox_counter_bdr_reg1_t reg; 01904 int32_t ret; 01905 01906 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 01907 if (ret == 0) { 01908 reg.dataready_pulsed = (uint8_t)val; 01909 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 01910 } 01911 return ret; 01912 } 01913 01914 /** 01915 * @brief Data-ready pulsed / letched mode.[get] 01916 * 01917 * @param ctx read / write interface definitions 01918 * @param val Get the values of 01919 * dataready_pulsed in 01920 * reg COUNTER_BDR_REG1 01921 * 01922 */ 01923 int32_t lsm6dsox_data_ready_mode_get(lsm6dsox_ctx_t *ctx, 01924 lsm6dsox_dataready_pulsed_t *val) 01925 { 01926 lsm6dsox_counter_bdr_reg1_t reg; 01927 int32_t ret; 01928 01929 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 01930 switch (reg.dataready_pulsed) { 01931 case LSM6DSOX_DRDY_LATCHED: 01932 *val = LSM6DSOX_DRDY_LATCHED; 01933 break; 01934 case LSM6DSOX_DRDY_PULSED: 01935 *val = LSM6DSOX_DRDY_PULSED; 01936 break; 01937 default: 01938 *val = LSM6DSOX_DRDY_LATCHED; 01939 break; 01940 } 01941 return ret; 01942 } 01943 01944 /** 01945 * @brief Device "Who am I".[get] 01946 * 01947 * @param ctx read / write interface definitions 01948 * @param buff buffer that stores data read 01949 * 01950 */ 01951 int32_t lsm6dsox_device_id_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 01952 { 01953 int32_t ret; 01954 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, buff, 1); 01955 return ret; 01956 } 01957 01958 /** 01959 * @brief Software reset. Restore the default values 01960 * in user registers[set] 01961 * 01962 * @param ctx read / write interface definitions 01963 * @param val change the values of sw_reset in reg CTRL3_C 01964 * 01965 */ 01966 int32_t lsm6dsox_reset_set(lsm6dsox_ctx_t *ctx, uint8_t val) 01967 { 01968 lsm6dsox_ctrl3_c_t reg; 01969 int32_t ret; 01970 01971 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 01972 if (ret == 0) { 01973 reg.sw_reset = val; 01974 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 01975 } 01976 01977 return ret; 01978 } 01979 01980 /** 01981 * @brief Software reset. Restore the default values in user registers.[get] 01982 * 01983 * @param ctx read / write interface definitions 01984 * @param val change the values of sw_reset in reg CTRL3_C 01985 * 01986 */ 01987 int32_t lsm6dsox_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 01988 { 01989 lsm6dsox_ctrl3_c_t reg; 01990 int32_t ret; 01991 01992 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 01993 *val = reg.sw_reset; 01994 01995 return ret; 01996 } 01997 01998 /** 01999 * @brief Register address automatically incremented during a multiple byte 02000 * access with a serial interface.[set] 02001 * 02002 * @param ctx read / write interface definitions 02003 * @param val change the values of if_inc in reg CTRL3_C 02004 * 02005 */ 02006 int32_t lsm6dsox_auto_increment_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02007 { 02008 lsm6dsox_ctrl3_c_t reg; 02009 int32_t ret; 02010 02011 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 02012 if (ret == 0) { 02013 reg.if_inc = val; 02014 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 02015 } 02016 return ret; 02017 } 02018 02019 /** 02020 * @brief Register address automatically incremented during a multiple byte 02021 * access with a serial interface.[get] 02022 * 02023 * @param ctx read / write interface definitions 02024 * @param val change the values of if_inc in reg CTRL3_C 02025 * 02026 */ 02027 int32_t lsm6dsox_auto_increment_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02028 { 02029 lsm6dsox_ctrl3_c_t reg; 02030 int32_t ret; 02031 02032 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 02033 *val = reg.if_inc; 02034 02035 return ret; 02036 } 02037 02038 /** 02039 * @brief Reboot memory content. Reload the calibration parameters.[set] 02040 * 02041 * @param ctx read / write interface definitions 02042 * @param val change the values of boot in reg CTRL3_C 02043 * 02044 */ 02045 int32_t lsm6dsox_boot_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02046 { 02047 lsm6dsox_ctrl3_c_t reg; 02048 int32_t ret; 02049 02050 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 02051 if (ret == 0) { 02052 reg.boot = val; 02053 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 02054 } 02055 return ret; 02056 } 02057 02058 /** 02059 * @brief Reboot memory content. Reload the calibration parameters.[get] 02060 * 02061 * @param ctx read / write interface definitions 02062 * @param val change the values of boot in reg CTRL3_C 02063 * 02064 */ 02065 int32_t lsm6dsox_boot_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02066 { 02067 lsm6dsox_ctrl3_c_t reg; 02068 int32_t ret; 02069 02070 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 02071 *val = reg.boot; 02072 02073 return ret; 02074 } 02075 02076 /** 02077 * @brief Linear acceleration sensor self-test enable.[set] 02078 * 02079 * @param ctx read / write interface definitions 02080 * @param val change the values of st_xl in reg CTRL5_C 02081 * 02082 */ 02083 int32_t lsm6dsox_xl_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t val) 02084 { 02085 lsm6dsox_ctrl5_c_t reg; 02086 int32_t ret; 02087 02088 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 02089 if (ret == 0) { 02090 reg.st_xl = (uint8_t)val; 02091 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 02092 } 02093 return ret; 02094 } 02095 02096 /** 02097 * @brief Linear acceleration sensor self-test enable.[get] 02098 * 02099 * @param ctx read / write interface definitions 02100 * @param val Get the values of st_xl in reg CTRL5_C 02101 * 02102 */ 02103 int32_t lsm6dsox_xl_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t *val) 02104 { 02105 lsm6dsox_ctrl5_c_t reg; 02106 int32_t ret; 02107 02108 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 02109 switch (reg.st_xl) { 02110 case LSM6DSOX_XL_ST_DISABLE: 02111 *val = LSM6DSOX_XL_ST_DISABLE; 02112 break; 02113 case LSM6DSOX_XL_ST_POSITIVE: 02114 *val = LSM6DSOX_XL_ST_POSITIVE; 02115 break; 02116 case LSM6DSOX_XL_ST_NEGATIVE: 02117 *val = LSM6DSOX_XL_ST_NEGATIVE; 02118 break; 02119 default: 02120 *val = LSM6DSOX_XL_ST_DISABLE; 02121 break; 02122 } 02123 return ret; 02124 } 02125 02126 /** 02127 * @brief Angular rate sensor self-test enable.[set] 02128 * 02129 * @param ctx read / write interface definitions 02130 * @param val change the values of st_g in reg CTRL5_C 02131 * 02132 */ 02133 int32_t lsm6dsox_gy_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t val) 02134 { 02135 lsm6dsox_ctrl5_c_t reg; 02136 int32_t ret; 02137 02138 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 02139 if (ret == 0) { 02140 reg.st_g = (uint8_t)val; 02141 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 02142 } 02143 return ret; 02144 } 02145 02146 /** 02147 * @brief Angular rate sensor self-test enable.[get] 02148 * 02149 * @param ctx read / write interface definitions 02150 * @param val Get the values of st_g in reg CTRL5_C 02151 * 02152 */ 02153 int32_t lsm6dsox_gy_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t *val) 02154 { 02155 lsm6dsox_ctrl5_c_t reg; 02156 int32_t ret; 02157 02158 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); 02159 switch (reg.st_g) { 02160 case LSM6DSOX_GY_ST_DISABLE: 02161 *val = LSM6DSOX_GY_ST_DISABLE; 02162 break; 02163 case LSM6DSOX_GY_ST_POSITIVE: 02164 *val = LSM6DSOX_GY_ST_POSITIVE; 02165 break; 02166 case LSM6DSOX_GY_ST_NEGATIVE: 02167 *val = LSM6DSOX_GY_ST_NEGATIVE; 02168 break; 02169 default: 02170 *val = LSM6DSOX_GY_ST_DISABLE; 02171 break; 02172 } 02173 return ret; 02174 } 02175 02176 /** 02177 * @} 02178 * 02179 */ 02180 02181 /** 02182 * @defgroup LSM6DSOX_filters 02183 * @brief This section group all the functions concerning the 02184 * filters configuration 02185 * @{ 02186 * 02187 */ 02188 02189 /** 02190 * @brief Accelerometer output from LPF2 filtering stage selection.[set] 02191 * 02192 * @param ctx read / write interface definitions 02193 * @param val change the values of lpf2_xl_en in reg CTRL1_XL 02194 * 02195 */ 02196 int32_t lsm6dsox_xl_filter_lp2_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02197 { 02198 lsm6dsox_ctrl1_xl_t reg; 02199 int32_t ret; 02200 02201 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 02202 if (ret == 0) { 02203 reg.lpf2_xl_en = val; 02204 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 02205 } 02206 return ret; 02207 } 02208 02209 /** 02210 * @brief Accelerometer output from LPF2 filtering stage selection.[get] 02211 * 02212 * @param ctx read / write interface definitions 02213 * @param val change the values of lpf2_xl_en in reg CTRL1_XL 02214 * 02215 */ 02216 int32_t lsm6dsox_xl_filter_lp2_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02217 { 02218 lsm6dsox_ctrl1_xl_t reg; 02219 int32_t ret; 02220 02221 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); 02222 *val = reg.lpf2_xl_en; 02223 02224 return ret; 02225 } 02226 02227 /** 02228 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; 02229 * the bandwidth can be selected through FTYPE [2:0] 02230 * in CTRL6_C (15h).[set] 02231 * 02232 * @param ctx read / write interface definitions 02233 * @param val change the values of lpf1_sel_g in reg CTRL4_C 02234 * 02235 */ 02236 int32_t lsm6dsox_gy_filter_lp1_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02237 { 02238 lsm6dsox_ctrl4_c_t reg; 02239 int32_t ret; 02240 02241 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 02242 if (ret == 0) { 02243 reg.lpf1_sel_g = val; 02244 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 02245 } 02246 return ret; 02247 } 02248 02249 /** 02250 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; 02251 * the bandwidth can be selected through FTYPE [2:0] 02252 * in CTRL6_C (15h).[get] 02253 * 02254 * @param ctx read / write interface definitions 02255 * @param val change the values of lpf1_sel_g in reg CTRL4_C 02256 * 02257 */ 02258 int32_t lsm6dsox_gy_filter_lp1_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02259 { 02260 lsm6dsox_ctrl4_c_t reg; 02261 int32_t ret; 02262 02263 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 02264 *val = reg.lpf1_sel_g; 02265 02266 return ret; 02267 } 02268 02269 /** 02270 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends 02271 * (XL and Gyro independently masked).[set] 02272 * 02273 * @param ctx read / write interface definitions 02274 * @param val change the values of drdy_mask in reg CTRL4_C 02275 * 02276 */ 02277 int32_t lsm6dsox_filter_settling_mask_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02278 { 02279 lsm6dsox_ctrl4_c_t reg; 02280 int32_t ret; 02281 02282 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 02283 if (ret == 0) { 02284 reg.drdy_mask = val; 02285 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 02286 } 02287 return ret; 02288 } 02289 02290 /** 02291 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends 02292 * (XL and Gyro independently masked).[get] 02293 * 02294 * @param ctx read / write interface definitions 02295 * @param val change the values of drdy_mask in reg CTRL4_C 02296 * 02297 */ 02298 int32_t lsm6dsox_filter_settling_mask_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02299 { 02300 lsm6dsox_ctrl4_c_t reg; 02301 int32_t ret; 02302 02303 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 02304 *val = reg.drdy_mask; 02305 02306 return ret; 02307 } 02308 02309 /** 02310 * @brief Gyroscope lp1 bandwidth.[set] 02311 * 02312 * @param ctx read / write interface definitions 02313 * @param val change the values of ftype in reg CTRL6_C 02314 * 02315 */ 02316 int32_t lsm6dsox_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t val) 02317 { 02318 lsm6dsox_ctrl6_c_t reg; 02319 int32_t ret; 02320 02321 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 02322 if (ret == 0) { 02323 reg.ftype = (uint8_t)val; 02324 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 02325 } 02326 return ret; 02327 } 02328 02329 /** 02330 * @brief Gyroscope lp1 bandwidth.[get] 02331 * 02332 * @param ctx read / write interface definitions 02333 * @param val Get the values of ftype in reg CTRL6_C 02334 * 02335 */ 02336 int32_t lsm6dsox_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t *val) 02337 { 02338 lsm6dsox_ctrl6_c_t reg; 02339 int32_t ret; 02340 02341 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 02342 switch (reg.ftype) { 02343 case LSM6DSOX_ULTRA_LIGHT: 02344 *val = LSM6DSOX_ULTRA_LIGHT; 02345 break; 02346 case LSM6DSOX_VERY_LIGHT: 02347 *val = LSM6DSOX_VERY_LIGHT; 02348 break; 02349 case LSM6DSOX_LIGHT: 02350 *val = LSM6DSOX_LIGHT; 02351 break; 02352 case LSM6DSOX_MEDIUM: 02353 *val = LSM6DSOX_MEDIUM; 02354 break; 02355 case LSM6DSOX_STRONG: 02356 *val = LSM6DSOX_STRONG; 02357 break; 02358 case LSM6DSOX_VERY_STRONG: 02359 *val = LSM6DSOX_VERY_STRONG; 02360 break; 02361 case LSM6DSOX_AGGRESSIVE: 02362 *val = LSM6DSOX_AGGRESSIVE; 02363 break; 02364 case LSM6DSOX_XTREME: 02365 *val = LSM6DSOX_XTREME; 02366 break; 02367 default: 02368 *val = LSM6DSOX_ULTRA_LIGHT; 02369 break; 02370 } 02371 return ret; 02372 } 02373 02374 /** 02375 * @brief Low pass filter 2 on 6D function selection.[set] 02376 * 02377 * @param ctx read / write interface definitions 02378 * @param val change the values of low_pass_on_6d in reg CTRL8_XL 02379 * 02380 */ 02381 int32_t lsm6dsox_xl_lp2_on_6d_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02382 { 02383 lsm6dsox_ctrl8_xl_t reg; 02384 int32_t ret; 02385 02386 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02387 if (ret == 0) { 02388 reg.low_pass_on_6d = val; 02389 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02390 } 02391 return ret; 02392 } 02393 02394 /** 02395 * @brief Low pass filter 2 on 6D function selection.[get] 02396 * 02397 * @param ctx read / write interface definitions 02398 * @param val change the values of low_pass_on_6d in reg CTRL8_XL 02399 * 02400 */ 02401 int32_t lsm6dsox_xl_lp2_on_6d_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02402 { 02403 lsm6dsox_ctrl8_xl_t reg; 02404 int32_t ret; 02405 02406 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02407 *val = reg.low_pass_on_6d; 02408 02409 return ret; 02410 } 02411 02412 /** 02413 * @brief Accelerometer slope filter / high-pass filter selection 02414 * on output.[set] 02415 * 02416 * @param ctx read / write interface definitions 02417 * @param val change the values of hp_slope_xl_en 02418 * in reg CTRL8_XL 02419 * 02420 */ 02421 int32_t lsm6dsox_xl_hp_path_on_out_set(lsm6dsox_ctx_t *ctx, 02422 lsm6dsox_hp_slope_xl_en_t val) 02423 { 02424 lsm6dsox_ctrl8_xl_t reg; 02425 int32_t ret; 02426 02427 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02428 if (ret == 0) { 02429 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4; 02430 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5; 02431 reg.hpcf_xl = (uint8_t)val & 0x07U; 02432 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02433 } 02434 return ret; 02435 } 02436 02437 /** 02438 * @brief Accelerometer slope filter / high-pass filter selection 02439 * on output.[get] 02440 * 02441 * @param ctx read / write interface definitions 02442 * @param val Get the values of hp_slope_xl_en 02443 * in reg CTRL8_XL 02444 * 02445 */ 02446 int32_t lsm6dsox_xl_hp_path_on_out_get(lsm6dsox_ctx_t *ctx, 02447 lsm6dsox_hp_slope_xl_en_t *val) 02448 { 02449 lsm6dsox_ctrl8_xl_t reg; 02450 int32_t ret; 02451 02452 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02453 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | 02454 reg.hpcf_xl) { 02455 case LSM6DSOX_HP_PATH_DISABLE_ON_OUT: 02456 *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT; 02457 break; 02458 case LSM6DSOX_SLOPE_ODR_DIV_4: 02459 *val = LSM6DSOX_SLOPE_ODR_DIV_4; 02460 break; 02461 case LSM6DSOX_HP_ODR_DIV_10: 02462 *val = LSM6DSOX_HP_ODR_DIV_10; 02463 break; 02464 case LSM6DSOX_HP_ODR_DIV_20: 02465 *val = LSM6DSOX_HP_ODR_DIV_20; 02466 break; 02467 case LSM6DSOX_HP_ODR_DIV_45: 02468 *val = LSM6DSOX_HP_ODR_DIV_45; 02469 break; 02470 case LSM6DSOX_HP_ODR_DIV_100: 02471 *val = LSM6DSOX_HP_ODR_DIV_100; 02472 break; 02473 case LSM6DSOX_HP_ODR_DIV_200: 02474 *val = LSM6DSOX_HP_ODR_DIV_200; 02475 break; 02476 case LSM6DSOX_HP_ODR_DIV_400: 02477 *val = LSM6DSOX_HP_ODR_DIV_400; 02478 break; 02479 case LSM6DSOX_HP_ODR_DIV_800: 02480 *val = LSM6DSOX_HP_ODR_DIV_800; 02481 break; 02482 case LSM6DSOX_HP_REF_MD_ODR_DIV_10: 02483 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_10; 02484 break; 02485 case LSM6DSOX_HP_REF_MD_ODR_DIV_20: 02486 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_20; 02487 break; 02488 case LSM6DSOX_HP_REF_MD_ODR_DIV_45: 02489 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_45; 02490 break; 02491 case LSM6DSOX_HP_REF_MD_ODR_DIV_100: 02492 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_100; 02493 break; 02494 case LSM6DSOX_HP_REF_MD_ODR_DIV_200: 02495 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_200; 02496 break; 02497 case LSM6DSOX_HP_REF_MD_ODR_DIV_400: 02498 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_400; 02499 break; 02500 case LSM6DSOX_HP_REF_MD_ODR_DIV_800: 02501 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_800; 02502 break; 02503 case LSM6DSOX_LP_ODR_DIV_10: 02504 *val = LSM6DSOX_LP_ODR_DIV_10; 02505 break; 02506 case LSM6DSOX_LP_ODR_DIV_20: 02507 *val = LSM6DSOX_LP_ODR_DIV_20; 02508 break; 02509 case LSM6DSOX_LP_ODR_DIV_45: 02510 *val = LSM6DSOX_LP_ODR_DIV_45; 02511 break; 02512 case LSM6DSOX_LP_ODR_DIV_100: 02513 *val = LSM6DSOX_LP_ODR_DIV_100; 02514 break; 02515 case LSM6DSOX_LP_ODR_DIV_200: 02516 *val = LSM6DSOX_LP_ODR_DIV_200; 02517 break; 02518 case LSM6DSOX_LP_ODR_DIV_400: 02519 *val = LSM6DSOX_LP_ODR_DIV_400; 02520 break; 02521 case LSM6DSOX_LP_ODR_DIV_800: 02522 *val = LSM6DSOX_LP_ODR_DIV_800; 02523 break; 02524 default: 02525 *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT; 02526 break; 02527 } 02528 02529 return ret; 02530 } 02531 02532 /** 02533 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. 02534 * The filter sets the second samples after writing this bit. 02535 * Active only during device exit from power-down mode.[set] 02536 * 02537 * @param ctx read / write interface definitions 02538 * @param val change the values of fastsettl_mode_xl in 02539 * reg CTRL8_XL 02540 * 02541 */ 02542 int32_t lsm6dsox_xl_fast_settling_set(lsm6dsox_ctx_t *ctx, uint8_t val) 02543 { 02544 lsm6dsox_ctrl8_xl_t reg; 02545 int32_t ret; 02546 02547 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02548 if (ret == 0) { 02549 reg.fastsettl_mode_xl = val; 02550 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02551 } 02552 return ret; 02553 } 02554 02555 /** 02556 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. 02557 * The filter sets the second samples after writing this bit. 02558 * Active only during device exit from power-down mode.[get] 02559 * 02560 * @param ctx read / write interface definitions 02561 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL 02562 * 02563 */ 02564 int32_t lsm6dsox_xl_fast_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02565 { 02566 lsm6dsox_ctrl8_xl_t reg; 02567 int32_t ret; 02568 02569 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02570 *val = reg.fastsettl_mode_xl; 02571 02572 return ret; 02573 } 02574 02575 /** 02576 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity 02577 * functions.[set] 02578 * 02579 * @param ctx read / write interface definitions 02580 * @param val change the values of slope_fds in reg TAP_CFG0 02581 * 02582 */ 02583 int32_t lsm6dsox_xl_hp_path_internal_set(lsm6dsox_ctx_t *ctx, 02584 lsm6dsox_slope_fds_t val) 02585 { 02586 lsm6dsox_tap_cfg0_t reg; 02587 int32_t ret; 02588 02589 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 02590 if (ret == 0) { 02591 reg.slope_fds = (uint8_t)val; 02592 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 02593 } 02594 return ret; 02595 } 02596 02597 /** 02598 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity 02599 * functions.[get] 02600 * 02601 * @param ctx read / write interface definitions 02602 * @param val Change the values of slope_fds in reg TAP_CFG0 02603 * 02604 */ 02605 int32_t lsm6dsox_xl_hp_path_internal_get(lsm6dsox_ctx_t *ctx, 02606 lsm6dsox_slope_fds_t *val) 02607 { 02608 lsm6dsox_tap_cfg0_t reg; 02609 int32_t ret; 02610 02611 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 02612 switch (reg.slope_fds) { 02613 case LSM6DSOX_USE_SLOPE: 02614 *val = LSM6DSOX_USE_SLOPE; 02615 break; 02616 case LSM6DSOX_USE_HPF: 02617 *val = LSM6DSOX_USE_HPF; 02618 break; 02619 default: 02620 *val = LSM6DSOX_USE_SLOPE; 02621 break; 02622 } 02623 return ret; 02624 } 02625 02626 /** 02627 * @brief Enables gyroscope digital high-pass filter. The filter is 02628 * enabled only if the gyro is in HP mode.[set] 02629 * 02630 * @param ctx read / write interface definitions 02631 * @param val Get the values of hp_en_g and hp_en_g 02632 * in reg CTRL7_G 02633 * 02634 */ 02635 int32_t lsm6dsox_gy_hp_path_internal_set(lsm6dsox_ctx_t *ctx, 02636 lsm6dsox_hpm_g_t val) 02637 { 02638 lsm6dsox_ctrl7_g_t reg; 02639 int32_t ret; 02640 02641 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 02642 if (ret == 0) { 02643 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7; 02644 reg.hpm_g = (uint8_t)val & 0x03U; 02645 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 02646 } 02647 return ret; 02648 } 02649 02650 /** 02651 * @brief Enables gyroscope digital high-pass filter. The filter is 02652 * enabled only if the gyro is in HP mode.[get] 02653 * 02654 * @param ctx read / write interface definitions 02655 * @param val Get the values of hp_en_g and hp_en_g 02656 * in reg CTRL7_G 02657 * 02658 */ 02659 int32_t lsm6dsox_gy_hp_path_internal_get(lsm6dsox_ctx_t *ctx, 02660 lsm6dsox_hpm_g_t *val) 02661 { 02662 lsm6dsox_ctrl7_g_t reg; 02663 int32_t ret; 02664 02665 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 02666 switch ((reg.hp_en_g << 7) + reg.hpm_g) { 02667 case LSM6DSOX_HP_FILTER_NONE: 02668 *val = LSM6DSOX_HP_FILTER_NONE; 02669 break; 02670 case LSM6DSOX_HP_FILTER_16mHz: 02671 *val = LSM6DSOX_HP_FILTER_16mHz; 02672 break; 02673 case LSM6DSOX_HP_FILTER_65mHz: 02674 *val = LSM6DSOX_HP_FILTER_65mHz; 02675 break; 02676 case LSM6DSOX_HP_FILTER_260mHz: 02677 *val = LSM6DSOX_HP_FILTER_260mHz; 02678 break; 02679 case LSM6DSOX_HP_FILTER_1Hz04: 02680 *val = LSM6DSOX_HP_FILTER_1Hz04; 02681 break; 02682 default: 02683 *val = LSM6DSOX_HP_FILTER_NONE; 02684 break; 02685 } 02686 return ret; 02687 } 02688 02689 /** 02690 * @} 02691 * 02692 */ 02693 02694 /** 02695 * @defgroup LSM6DSOX_ Auxiliary_interface 02696 * @brief This section groups all the functions concerning 02697 * auxiliary interface. 02698 * @{ 02699 * 02700 */ 02701 02702 /** 02703 * @brief OIS data reading from Auxiliary / Main SPI.[set] 02704 * 02705 * @param ctx read / write interface definitions 02706 * @param val change the values of spi2_read_en in reg UI_INT_OIS 02707 * 02708 */ 02709 int32_t lsm6dsox_ois_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_spi2_read_en_t val) 02710 { 02711 lsm6dsox_func_cfg_access_t func_cfg_access; 02712 lsm6dsox_ui_int_ois_t ui_int_ois; 02713 int32_t ret; 02714 02715 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1); 02716 if (ret == 0) { 02717 ui_int_ois.spi2_read_en = ((uint8_t)val & 0x01U); 02718 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, 02719 (uint8_t*)&ui_int_ois, 1); 02720 } 02721 if (ret == 0) { 02722 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, 02723 (uint8_t*)&func_cfg_access, 1); 02724 } 02725 if (ret == 0) { 02726 func_cfg_access.ois_ctrl_from_ui = ( ((uint8_t)val & 0x02U) >> 1 ); 02727 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, 02728 (uint8_t*)&func_cfg_access, 1); 02729 } 02730 return ret; 02731 } 02732 02733 /** 02734 * @brief aux_ois_data: [get] OIS data reading from Auxiliary / Main SPI 02735 * 02736 * @param ctx read / write interface definitions 02737 * @param val Get the values of spi2_read_en 02738 * in reg UI_INT_OIS 02739 * 02740 */ 02741 int32_t lsm6dsox_ois_mode_get(lsm6dsox_ctx_t *ctx, 02742 lsm6dsox_spi2_read_en_t *val) 02743 { 02744 lsm6dsox_func_cfg_access_t func_cfg_access; 02745 lsm6dsox_ui_int_ois_t ui_int_ois; 02746 int32_t ret; 02747 02748 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1); 02749 if (ret == 0) { 02750 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, 02751 (uint8_t*)&func_cfg_access, 1); 02752 } 02753 switch ((func_cfg_access.ois_ctrl_from_ui << 1) + ui_int_ois.spi2_read_en) { 02754 case LSM6DSOX_OIS_CTRL_AUX_DATA_UI: 02755 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI; 02756 break; 02757 case LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX: 02758 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX; 02759 break; 02760 case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI: 02761 *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI; 02762 break; 02763 case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX: 02764 *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX; 02765 break; 02766 default: 02767 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI; 02768 break; 02769 } 02770 return ret; 02771 } 02772 02773 /** 02774 * @brief aOn auxiliary interface connect/disconnect SDO and OCS 02775 * internal pull-up.[set] 02776 * 02777 * @param ctx read / write interface definitions 02778 * @param val change the values of ois_pu_dis in 02779 * reg PIN_CTRL 02780 * 02781 */ 02782 int32_t lsm6dsox_aux_sdo_ocs_mode_set(lsm6dsox_ctx_t *ctx, 02783 lsm6dsox_ois_pu_dis_t val) 02784 { 02785 lsm6dsox_pin_ctrl_t reg; 02786 int32_t ret; 02787 02788 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); 02789 if (ret == 0) { 02790 reg.ois_pu_dis = (uint8_t)val; 02791 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); 02792 } 02793 return ret; 02794 } 02795 02796 /** 02797 * @brief On auxiliary interface connect/disconnect SDO and OCS 02798 * internal pull-up.[get] 02799 * 02800 * @param ctx read / write interface definitions 02801 * @param val Get the values of ois_pu_dis in reg PIN_CTRL 02802 * 02803 */ 02804 int32_t lsm6dsox_aux_sdo_ocs_mode_get(lsm6dsox_ctx_t *ctx, 02805 lsm6dsox_ois_pu_dis_t *val) 02806 { 02807 lsm6dsox_pin_ctrl_t reg; 02808 int32_t ret; 02809 02810 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); 02811 switch (reg.ois_pu_dis) { 02812 case LSM6DSOX_AUX_PULL_UP_DISC: 02813 *val = LSM6DSOX_AUX_PULL_UP_DISC; 02814 break; 02815 case LSM6DSOX_AUX_PULL_UP_CONNECT: 02816 *val = LSM6DSOX_AUX_PULL_UP_CONNECT; 02817 break; 02818 default: 02819 *val = LSM6DSOX_AUX_PULL_UP_DISC; 02820 break; 02821 } 02822 return ret; 02823 } 02824 02825 /** 02826 * @brief OIS chain on aux interface power on mode.[set] 02827 * 02828 * @param ctx read / write interface definitions 02829 * @param val change the values of ois_on in reg CTRL7_G 02830 * 02831 */ 02832 int32_t lsm6dsox_aux_pw_on_ctrl_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t val) 02833 { 02834 lsm6dsox_ctrl7_g_t reg; 02835 int32_t ret; 02836 02837 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 02838 if (ret == 0) { 02839 reg.ois_on_en = (uint8_t)val & 0x01U; 02840 reg.ois_on = (uint8_t)val & 0x01U; 02841 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 02842 } 02843 return ret; 02844 } 02845 02846 /** 02847 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode 02848 * 02849 * @param ctx read / write interface definitions 02850 * @param val Get the values of ois_on in reg CTRL7_G 02851 * 02852 */ 02853 int32_t lsm6dsox_aux_pw_on_ctrl_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t *val) 02854 { 02855 lsm6dsox_ctrl7_g_t reg; 02856 int32_t ret; 02857 02858 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); 02859 switch (reg.ois_on) { 02860 case LSM6DSOX_AUX_ON: 02861 *val = LSM6DSOX_AUX_ON; 02862 break; 02863 case LSM6DSOX_AUX_ON_BY_AUX_INTERFACE: 02864 *val = LSM6DSOX_AUX_ON_BY_AUX_INTERFACE; 02865 break; 02866 default: 02867 *val = LSM6DSOX_AUX_ON; 02868 break; 02869 } 02870 02871 return ret; 02872 } 02873 02874 /** 02875 * @brief Accelerometer full-scale management between UI chain and 02876 * OIS chain. When XL UI is on, the full scale is the same 02877 * between UI/OIS and is chosen by the UI CTRL registers; 02878 * when XL UI is in PD, the OIS can choose the FS. 02879 * Full scales are independent between the UI/OIS chain 02880 * but both bound to 8 g.[set] 02881 * 02882 * @param ctx read / write interface definitions 02883 * @param val change the values of xl_fs_mode in 02884 * reg CTRL8_XL 02885 * 02886 */ 02887 int32_t lsm6dsox_aux_xl_fs_mode_set(lsm6dsox_ctx_t *ctx, 02888 lsm6dsox_xl_fs_mode_t val) 02889 { 02890 lsm6dsox_ctrl8_xl_t reg; 02891 int32_t ret; 02892 02893 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02894 if (ret == 0) { 02895 reg.xl_fs_mode = (uint8_t)val; 02896 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02897 } 02898 return ret; 02899 } 02900 02901 /** 02902 * @brief Accelerometer full-scale management between UI chain and 02903 * OIS chain. When XL UI is on, the full scale is the same 02904 * between UI/OIS and is chosen by the UI CTRL registers; 02905 * when XL UI is in PD, the OIS can choose the FS. 02906 * Full scales are independent between the UI/OIS chain 02907 * but both bound to 8 g.[get] 02908 * 02909 * @param ctx read / write interface definitions 02910 * @param val Get the values of xl_fs_mode in reg CTRL8_XL 02911 * 02912 */ 02913 int32_t lsm6dsox_aux_xl_fs_mode_get(lsm6dsox_ctx_t *ctx, 02914 lsm6dsox_xl_fs_mode_t *val) 02915 { 02916 lsm6dsox_ctrl8_xl_t reg; 02917 int32_t ret; 02918 02919 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); 02920 switch (reg.xl_fs_mode) { 02921 case LSM6DSOX_USE_SAME_XL_FS: 02922 *val = LSM6DSOX_USE_SAME_XL_FS; 02923 break; 02924 case LSM6DSOX_USE_DIFFERENT_XL_FS: 02925 *val = LSM6DSOX_USE_DIFFERENT_XL_FS; 02926 break; 02927 default: 02928 *val = LSM6DSOX_USE_SAME_XL_FS; 02929 break; 02930 } 02931 02932 return ret; 02933 } 02934 02935 /** 02936 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get] 02937 * 02938 * @param ctx read / write interface definitions 02939 * @param val Get registers STATUS_SPIAUX 02940 * 02941 */ 02942 int32_t lsm6dsox_aux_status_reg_get(lsm6dsox_ctx_t *ctx, 02943 lsm6dsox_spi2_status_reg_ois_t *val) 02944 { 02945 int32_t ret; 02946 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*) val, 1); 02947 return ret; 02948 } 02949 02950 /** 02951 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available 02952 * 02953 * @param ctx read / write interface definitions 02954 * @param val change the values of xlda in reg STATUS_SPIAUX 02955 * 02956 */ 02957 int32_t lsm6dsox_aux_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02958 { 02959 lsm6dsox_spi2_status_reg_ois_t reg; 02960 int32_t ret; 02961 02962 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1); 02963 *val = reg.xlda; 02964 02965 return ret; 02966 } 02967 02968 /** 02969 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available. 02970 * 02971 * @param ctx read / write interface definitions 02972 * @param val change the values of gda in reg STATUS_SPIAUX 02973 * 02974 */ 02975 int32_t lsm6dsox_aux_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02976 { 02977 lsm6dsox_spi2_status_reg_ois_t reg; 02978 int32_t ret; 02979 02980 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1); 02981 *val = reg.gda; 02982 02983 return ret; 02984 } 02985 02986 /** 02987 * @brief High when the gyroscope output is in the settling phase.[get] 02988 * 02989 * @param ctx read / write interface definitions 02990 * @param val change the values of gyro_settling in reg STATUS_SPIAUX 02991 * 02992 */ 02993 int32_t lsm6dsox_aux_gy_flag_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 02994 { 02995 lsm6dsox_spi2_status_reg_ois_t reg; 02996 int32_t ret; 02997 02998 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1); 02999 *val = reg.gyro_settling; 03000 03001 return ret; 03002 } 03003 03004 /** 03005 * @brief Indicates polarity of DEN signal on OIS chain.[set] 03006 * 03007 * @param ctx read / write interface definitions 03008 * @param val change the values of den_lh_ois in 03009 * reg INT_OIS 03010 * 03011 */ 03012 int32_t lsm6dsox_aux_den_polarity_set(lsm6dsox_ctx_t *ctx, 03013 lsm6dsox_den_lh_ois_t val) 03014 { 03015 lsm6dsox_ui_int_ois_t reg; 03016 int32_t ret; 03017 03018 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); 03019 if (ret == 0) { 03020 reg.den_lh_ois = (uint8_t)val; 03021 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); 03022 } 03023 return ret; 03024 } 03025 03026 /** 03027 * @brief Indicates polarity of DEN signal on OIS chain.[get] 03028 * 03029 * @param ctx read / write interface definitions 03030 * @param val Get the values of den_lh_ois in reg INT_OIS 03031 * 03032 */ 03033 int32_t lsm6dsox_aux_den_polarity_get(lsm6dsox_ctx_t *ctx, 03034 lsm6dsox_den_lh_ois_t *val) 03035 { 03036 lsm6dsox_ui_int_ois_t reg; 03037 int32_t ret; 03038 03039 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); 03040 switch (reg.den_lh_ois) { 03041 case LSM6DSOX_AUX_DEN_ACTIVE_LOW: 03042 *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW; 03043 break; 03044 case LSM6DSOX_AUX_DEN_ACTIVE_HIGH: 03045 *val = LSM6DSOX_AUX_DEN_ACTIVE_HIGH; 03046 break; 03047 default: 03048 *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW; 03049 break; 03050 } 03051 return ret; 03052 } 03053 03054 /** 03055 * @brief Configure DEN mode on the OIS chain.[set] 03056 * 03057 * @param ctx read / write interface definitions 03058 * @param val change the values of lvl2_ois in reg INT_OIS 03059 * 03060 */ 03061 int32_t lsm6dsox_aux_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t val) 03062 { 03063 lsm6dsox_ui_ctrl1_ois_t ctrl1_ois; 03064 lsm6dsox_ui_int_ois_t int_ois; 03065 int32_t ret; 03066 03067 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1); 03068 if (ret == 0) { 03069 int_ois.lvl2_ois = (uint8_t)val & 0x01U; 03070 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1); 03071 } 03072 if (ret == 0) { 03073 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); 03074 } 03075 if (ret == 0) { 03076 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1; 03077 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); 03078 } 03079 return ret; 03080 } 03081 03082 /** 03083 * @brief Configure DEN mode on the OIS chain.[get] 03084 * 03085 * @param ctx read / write interface definitions 03086 * @param val Get the values of lvl2_ois in reg INT_OIS 03087 * 03088 */ 03089 int32_t lsm6dsox_aux_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val) 03090 { 03091 lsm6dsox_ui_ctrl1_ois_t ctrl1_ois; 03092 lsm6dsox_ui_int_ois_t int_ois; 03093 int32_t ret; 03094 03095 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1); 03096 if (ret == 0) { 03097 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); 03098 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) { 03099 case LSM6DSOX_AUX_DEN_DISABLE: 03100 *val = LSM6DSOX_AUX_DEN_DISABLE; 03101 break; 03102 case LSM6DSOX_AUX_DEN_LEVEL_LATCH: 03103 *val = LSM6DSOX_AUX_DEN_LEVEL_LATCH; 03104 break; 03105 case LSM6DSOX_AUX_DEN_LEVEL_TRIG: 03106 *val = LSM6DSOX_AUX_DEN_LEVEL_TRIG; 03107 break; 03108 default: 03109 *val = LSM6DSOX_AUX_DEN_DISABLE; 03110 break; 03111 } 03112 } 03113 return ret; 03114 } 03115 03116 /** 03117 * @brief Enables/Disable OIS chain DRDY on INT2 pin. 03118 * This setting has priority over all other INT2 settings.[set] 03119 * 03120 * @param ctx read / write interface definitions 03121 * @param val change the values of int2_drdy_ois in reg INT_OIS 03122 * 03123 */ 03124 int32_t lsm6dsox_aux_drdy_on_int2_set(lsm6dsox_ctx_t *ctx, uint8_t val) 03125 { 03126 lsm6dsox_ui_int_ois_t reg; 03127 int32_t ret; 03128 03129 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); 03130 if (ret == 0) { 03131 reg.int2_drdy_ois = val; 03132 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); 03133 } 03134 return ret; 03135 } 03136 03137 /** 03138 * @brief Enables/Disable OIS chain DRDY on INT2 pin. 03139 * This setting has priority over all other INT2 settings.[get] 03140 * 03141 * @param ctx read / write interface definitions 03142 * @param val change the values of int2_drdy_ois in reg INT_OIS 03143 * 03144 */ 03145 int32_t lsm6dsox_aux_drdy_on_int2_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 03146 { 03147 lsm6dsox_ui_int_ois_t reg; 03148 int32_t ret; 03149 03150 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); 03151 *val = reg.int2_drdy_ois; 03152 03153 return ret; 03154 } 03155 03156 /** 03157 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 03158 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). 03159 * When the OIS chain is enabled, the OIS outputs are available 03160 * through the SPI2 in registers OUTX_L_G (22h) through 03161 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and 03162 * LPF1 is dedicated to this chain.[set] 03163 * 03164 * @param ctx read / write interface definitions 03165 * @param val change the values of ois_en_spi2 in 03166 * reg CTRL1_OIS 03167 * 03168 */ 03169 int32_t lsm6dsox_aux_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val) 03170 { 03171 lsm6dsox_ui_ctrl1_ois_t reg; 03172 int32_t ret; 03173 03174 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03175 if (ret == 0) { 03176 reg.ois_en_spi2 = (uint8_t)val & 0x01U; 03177 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1; 03178 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03179 } 03180 return ret; 03181 } 03182 03183 /** 03184 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 03185 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). 03186 * When the OIS chain is enabled, the OIS outputs are available 03187 * through the SPI2 in registers OUTX_L_G (22h) through 03188 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and 03189 * LPF1 is dedicated to this chain.[get] 03190 * 03191 * @param ctx read / write interface definitions 03192 * @param val Get the values of ois_en_spi2 in 03193 * reg CTRL1_OIS 03194 * 03195 */ 03196 int32_t lsm6dsox_aux_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val) 03197 { 03198 lsm6dsox_ui_ctrl1_ois_t reg; 03199 int32_t ret; 03200 03201 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03202 switch ((reg.mode4_en << 1) | reg.ois_en_spi2) { 03203 case LSM6DSOX_AUX_DISABLE: 03204 *val = LSM6DSOX_AUX_DISABLE; 03205 break; 03206 case LSM6DSOX_MODE_3_GY: 03207 *val = LSM6DSOX_MODE_3_GY; 03208 break; 03209 case LSM6DSOX_MODE_4_GY_XL: 03210 *val = LSM6DSOX_MODE_4_GY_XL; 03211 break; 03212 default: 03213 *val = LSM6DSOX_AUX_DISABLE; 03214 break; 03215 } 03216 return ret; 03217 } 03218 03219 /** 03220 * @brief Selects gyroscope OIS chain full-scale.[set] 03221 * 03222 * @param ctx read / write interface definitions 03223 * @param val change the values of fs_g_ois in reg CTRL1_OIS 03224 * 03225 */ 03226 int32_t lsm6dsox_aux_gy_full_scale_set(lsm6dsox_ctx_t *ctx, 03227 lsm6dsox_fs_g_ois_t val) 03228 { 03229 lsm6dsox_ui_ctrl1_ois_t reg; 03230 int32_t ret; 03231 03232 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03233 if (ret == 0) { 03234 reg.fs_g_ois = (uint8_t)val; 03235 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03236 } 03237 return ret; 03238 } 03239 03240 /** 03241 * @brief Selects gyroscope OIS chain full-scale.[get] 03242 * 03243 * @param ctx read / write interface definitions 03244 * @param val Get the values of fs_g_ois in reg CTRL1_OIS 03245 * 03246 */ 03247 int32_t lsm6dsox_aux_gy_full_scale_get(lsm6dsox_ctx_t *ctx, 03248 lsm6dsox_fs_g_ois_t *val) 03249 { 03250 lsm6dsox_ui_ctrl1_ois_t reg; 03251 int32_t ret; 03252 03253 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03254 switch (reg.fs_g_ois) { 03255 case LSM6DSOX_250dps_AUX: 03256 *val = LSM6DSOX_250dps_AUX; 03257 break; 03258 case LSM6DSOX_125dps_AUX: 03259 *val = LSM6DSOX_125dps_AUX; 03260 break; 03261 case LSM6DSOX_500dps_AUX: 03262 *val = LSM6DSOX_500dps_AUX; 03263 break; 03264 case LSM6DSOX_1000dps_AUX: 03265 *val = LSM6DSOX_1000dps_AUX; 03266 break; 03267 case LSM6DSOX_2000dps_AUX: 03268 *val = LSM6DSOX_2000dps_AUX; 03269 break; 03270 default: 03271 *val = LSM6DSOX_250dps_AUX; 03272 break; 03273 } 03274 return ret; 03275 } 03276 03277 /** 03278 * @brief SPI2 3- or 4-wire interface.[set] 03279 * 03280 * @param ctx read / write interface definitions 03281 * @param val change the values of sim_ois in reg CTRL1_OIS 03282 * 03283 */ 03284 int32_t lsm6dsox_aux_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t val) 03285 { 03286 lsm6dsox_ui_ctrl1_ois_t reg; 03287 int32_t ret; 03288 03289 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03290 if (ret == 0) { 03291 reg.sim_ois = (uint8_t)val; 03292 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03293 } 03294 return ret; 03295 } 03296 03297 /** 03298 * @brief SPI2 3- or 4-wire interface.[get] 03299 * 03300 * @param ctx read / write interface definitions 03301 * @param val Get the values of sim_ois in reg CTRL1_OIS 03302 * 03303 */ 03304 int32_t lsm6dsox_aux_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t *val) 03305 { 03306 lsm6dsox_ui_ctrl1_ois_t reg; 03307 int32_t ret; 03308 03309 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); 03310 switch (reg.sim_ois) { 03311 case LSM6DSOX_AUX_SPI_4_WIRE: 03312 *val = LSM6DSOX_AUX_SPI_4_WIRE; 03313 break; 03314 case LSM6DSOX_AUX_SPI_3_WIRE: 03315 *val = LSM6DSOX_AUX_SPI_3_WIRE; 03316 break; 03317 default: 03318 *val = LSM6DSOX_AUX_SPI_4_WIRE; 03319 break; 03320 } 03321 return ret; 03322 } 03323 03324 /** 03325 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set] 03326 * 03327 * @param ctx read / write interface definitions 03328 * @param val change the values of ftype_ois in 03329 * reg CTRL2_OIS 03330 * 03331 */ 03332 int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, 03333 lsm6dsox_ftype_ois_t val) 03334 { 03335 lsm6dsox_ui_ctrl2_ois_t reg; 03336 int32_t ret; 03337 03338 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); 03339 if (ret == 0) { 03340 reg.ftype_ois = (uint8_t)val; 03341 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); 03342 } 03343 return ret; 03344 } 03345 03346 /** 03347 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get] 03348 * 03349 * @param ctx read / write interface definitions 03350 * @param val Get the values of ftype_ois in reg CTRL2_OIS 03351 * 03352 */ 03353 int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, 03354 lsm6dsox_ftype_ois_t *val) 03355 { 03356 lsm6dsox_ui_ctrl2_ois_t reg; 03357 int32_t ret; 03358 03359 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); 03360 switch (reg.ftype_ois) { 03361 case LSM6DSOX_351Hz39: 03362 *val = LSM6DSOX_351Hz39; 03363 break; 03364 case LSM6DSOX_236Hz63: 03365 *val = LSM6DSOX_236Hz63; 03366 break; 03367 case LSM6DSOX_172Hz70: 03368 *val = LSM6DSOX_172Hz70; 03369 break; 03370 case LSM6DSOX_937Hz91: 03371 *val = LSM6DSOX_937Hz91; 03372 break; 03373 default: 03374 *val = LSM6DSOX_351Hz39; 03375 break; 03376 } 03377 return ret; 03378 } 03379 03380 /** 03381 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set] 03382 * 03383 * @param ctx read / write interface definitions 03384 * @param val change the values of hpm_ois in reg CTRL2_OIS 03385 * 03386 */ 03387 int32_t lsm6dsox_aux_gy_hp_bandwidth_set(lsm6dsox_ctx_t *ctx, 03388 lsm6dsox_hpm_ois_t val) 03389 { 03390 lsm6dsox_ui_ctrl2_ois_t reg; 03391 int32_t ret; 03392 03393 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); 03394 if (ret == 0) { 03395 reg.hpm_ois = (uint8_t)val & 0x03U; 03396 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4; 03397 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); 03398 } 03399 return ret; 03400 } 03401 03402 /** 03403 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get] 03404 * 03405 * @param ctx read / write interface definitions 03406 * @param val Get the values of hpm_ois in reg CTRL2_OIS 03407 * 03408 */ 03409 int32_t lsm6dsox_aux_gy_hp_bandwidth_get(lsm6dsox_ctx_t *ctx, 03410 lsm6dsox_hpm_ois_t *val) 03411 { 03412 lsm6dsox_ui_ctrl2_ois_t reg; 03413 int32_t ret; 03414 03415 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); 03416 switch ((reg.hp_en_ois << 4) | reg.hpm_ois) { 03417 case LSM6DSOX_AUX_HP_DISABLE: 03418 *val = LSM6DSOX_AUX_HP_DISABLE; 03419 break; 03420 case LSM6DSOX_AUX_HP_Hz016: 03421 *val = LSM6DSOX_AUX_HP_Hz016; 03422 break; 03423 case LSM6DSOX_AUX_HP_Hz065: 03424 *val = LSM6DSOX_AUX_HP_Hz065; 03425 break; 03426 case LSM6DSOX_AUX_HP_Hz260: 03427 *val = LSM6DSOX_AUX_HP_Hz260; 03428 break; 03429 case LSM6DSOX_AUX_HP_1Hz040: 03430 *val = LSM6DSOX_AUX_HP_1Hz040; 03431 break; 03432 default: 03433 *val = LSM6DSOX_AUX_HP_DISABLE; 03434 break; 03435 } 03436 return ret; 03437 } 03438 03439 /** 03440 * @brief Enable / Disables OIS chain clamp. 03441 * Enable: All OIS chain outputs = 8000h 03442 * during self-test; Disable: OIS chain self-test 03443 * outputs dependent from the aux gyro full 03444 * scale selected.[set] 03445 * 03446 * @param ctx read / write interface definitions 03447 * @param val change the values of st_ois_clampdis in 03448 * reg CTRL3_OIS 03449 * 03450 */ 03451 int32_t lsm6dsox_aux_gy_clamp_set(lsm6dsox_ctx_t *ctx, 03452 lsm6dsox_st_ois_clampdis_t val) 03453 { 03454 lsm6dsox_ui_ctrl3_ois_t reg; 03455 int32_t ret; 03456 03457 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03458 if (ret == 0) { 03459 reg.st_ois_clampdis = (uint8_t)val; 03460 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03461 } 03462 return ret; 03463 } 03464 03465 /** 03466 * @brief Enable / Disables OIS chain clamp. 03467 * Enable: All OIS chain outputs = 8000h 03468 * during self-test; Disable: OIS chain self-test 03469 * outputs dependent from the aux gyro full 03470 * scale selected.[set] 03471 * 03472 * @param ctx read / write interface definitions 03473 * @param val Get the values of st_ois_clampdis in 03474 * reg CTRL3_OIS 03475 * 03476 */ 03477 int32_t lsm6dsox_aux_gy_clamp_get(lsm6dsox_ctx_t *ctx, 03478 lsm6dsox_st_ois_clampdis_t *val) 03479 { 03480 lsm6dsox_ui_ctrl3_ois_t reg; 03481 int32_t ret; 03482 03483 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03484 switch (reg.st_ois_clampdis) { 03485 case LSM6DSOX_ENABLE_CLAMP: 03486 *val = LSM6DSOX_ENABLE_CLAMP; 03487 break; 03488 case LSM6DSOX_DISABLE_CLAMP: 03489 *val = LSM6DSOX_DISABLE_CLAMP; 03490 break; 03491 default: 03492 *val = LSM6DSOX_ENABLE_CLAMP; 03493 break; 03494 } 03495 return ret; 03496 } 03497 03498 /** 03499 * @brief Selects accelerometer OIS channel bandwidth.[set] 03500 * 03501 * @param ctx read / write interface definitions 03502 * @param val change the values of 03503 * filter_xl_conf_ois in reg CTRL3_OIS 03504 * 03505 */ 03506 int32_t lsm6dsox_aux_xl_bandwidth_set(lsm6dsox_ctx_t *ctx, 03507 lsm6dsox_filter_xl_conf_ois_t val) 03508 { 03509 lsm6dsox_ui_ctrl3_ois_t reg; 03510 int32_t ret; 03511 03512 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03513 if (ret == 0) { 03514 reg.filter_xl_conf_ois = (uint8_t)val; 03515 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03516 } 03517 return ret; 03518 } 03519 03520 /** 03521 * @brief Selects accelerometer OIS channel bandwidth.[get] 03522 * 03523 * @param ctx read / write interface definitions 03524 * @param val Get the values of 03525 * filter_xl_conf_ois in reg CTRL3_OIS 03526 * 03527 */ 03528 int32_t lsm6dsox_aux_xl_bandwidth_get(lsm6dsox_ctx_t *ctx, 03529 lsm6dsox_filter_xl_conf_ois_t *val) 03530 { 03531 lsm6dsox_ui_ctrl3_ois_t reg; 03532 int32_t ret; 03533 03534 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03535 03536 switch (reg.filter_xl_conf_ois) { 03537 case LSM6DSOX_289Hz: 03538 *val = LSM6DSOX_289Hz; 03539 break; 03540 case LSM6DSOX_258Hz: 03541 *val = LSM6DSOX_258Hz; 03542 break; 03543 case LSM6DSOX_120Hz: 03544 *val = LSM6DSOX_120Hz; 03545 break; 03546 case LSM6DSOX_65Hz2: 03547 *val = LSM6DSOX_65Hz2; 03548 break; 03549 case LSM6DSOX_33Hz2: 03550 *val = LSM6DSOX_33Hz2; 03551 break; 03552 case LSM6DSOX_16Hz6: 03553 *val = LSM6DSOX_16Hz6; 03554 break; 03555 case LSM6DSOX_8Hz30: 03556 *val = LSM6DSOX_8Hz30; 03557 break; 03558 case LSM6DSOX_4Hz15: 03559 *val = LSM6DSOX_4Hz15; 03560 break; 03561 default: 03562 *val = LSM6DSOX_289Hz; 03563 break; 03564 } 03565 return ret; 03566 } 03567 03568 /** 03569 * @brief Selects accelerometer OIS channel full-scale.[set] 03570 * 03571 * @param ctx read / write interface definitions 03572 * @param val change the values of fs_xl_ois in 03573 * reg CTRL3_OIS 03574 * 03575 */ 03576 int32_t lsm6dsox_aux_xl_full_scale_set(lsm6dsox_ctx_t *ctx, 03577 lsm6dsox_fs_xl_ois_t val) 03578 { 03579 lsm6dsox_ui_ctrl3_ois_t reg; 03580 int32_t ret; 03581 03582 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03583 if (ret == 0) { 03584 reg.fs_xl_ois = (uint8_t)val; 03585 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03586 } 03587 return ret; 03588 } 03589 03590 /** 03591 * @brief Selects accelerometer OIS channel full-scale.[get] 03592 * 03593 * @param ctx read / write interface definitions 03594 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS 03595 * 03596 */ 03597 int32_t lsm6dsox_aux_xl_full_scale_get(lsm6dsox_ctx_t *ctx, 03598 lsm6dsox_fs_xl_ois_t *val) 03599 { 03600 lsm6dsox_ui_ctrl3_ois_t reg; 03601 int32_t ret; 03602 03603 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); 03604 switch (reg.fs_xl_ois) { 03605 case LSM6DSOX_AUX_2g: 03606 *val = LSM6DSOX_AUX_2g; 03607 break; 03608 case LSM6DSOX_AUX_16g: 03609 *val = LSM6DSOX_AUX_16g; 03610 break; 03611 case LSM6DSOX_AUX_4g: 03612 *val = LSM6DSOX_AUX_4g; 03613 break; 03614 case LSM6DSOX_AUX_8g: 03615 *val = LSM6DSOX_AUX_8g; 03616 break; 03617 default: 03618 *val = LSM6DSOX_AUX_2g; 03619 break; 03620 } 03621 return ret; 03622 } 03623 03624 /** 03625 * @} 03626 * 03627 */ 03628 03629 /** 03630 * @defgroup LSM6DSOX_ main_serial_interface 03631 * @brief This section groups all the functions concerning main 03632 * serial interface management (not auxiliary) 03633 * @{ 03634 * 03635 */ 03636 03637 /** 03638 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] 03639 * 03640 * @param ctx read / write interface definitions 03641 * @param val change the values of sdo_pu_en in 03642 * reg PIN_CTRL 03643 * 03644 */ 03645 int32_t lsm6dsox_sdo_sa0_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val) 03646 { 03647 lsm6dsox_pin_ctrl_t reg; 03648 int32_t ret; 03649 03650 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); 03651 if (ret == 0) { 03652 reg.sdo_pu_en = (uint8_t)val; 03653 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); 03654 } 03655 return ret; 03656 } 03657 03658 /** 03659 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] 03660 * 03661 * @param ctx read / write interface definitions 03662 * @param val Get the values of sdo_pu_en in reg PIN_CTRL 03663 * 03664 */ 03665 int32_t lsm6dsox_sdo_sa0_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val) 03666 { 03667 lsm6dsox_pin_ctrl_t reg; 03668 int32_t ret; 03669 03670 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); 03671 switch (reg.sdo_pu_en) { 03672 case LSM6DSOX_PULL_UP_DISC: 03673 *val = LSM6DSOX_PULL_UP_DISC; 03674 break; 03675 case LSM6DSOX_PULL_UP_CONNECT: 03676 *val = LSM6DSOX_PULL_UP_CONNECT; 03677 break; 03678 default: 03679 *val = LSM6DSOX_PULL_UP_DISC; 03680 break; 03681 } 03682 return ret; 03683 } 03684 03685 /** 03686 * @brief SPI Serial Interface Mode selection.[set] 03687 * 03688 * @param ctx read / write interface definitions 03689 * @param val change the values of sim in reg CTRL3_C 03690 * 03691 */ 03692 int32_t lsm6dsox_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t val) 03693 { 03694 lsm6dsox_ctrl3_c_t reg; 03695 int32_t ret; 03696 03697 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 03698 if (ret == 0) { 03699 reg.sim = (uint8_t)val; 03700 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 03701 } 03702 return ret; 03703 } 03704 03705 /** 03706 * @brief SPI Serial Interface Mode selection.[get] 03707 * 03708 * @param ctx read / write interface definitions 03709 * @param val Get the values of sim in reg CTRL3_C 03710 * 03711 */ 03712 int32_t lsm6dsox_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t *val) 03713 { 03714 lsm6dsox_ctrl3_c_t reg; 03715 int32_t ret; 03716 03717 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 03718 switch (reg.sim) { 03719 case LSM6DSOX_SPI_4_WIRE: 03720 *val = LSM6DSOX_SPI_4_WIRE; 03721 break; 03722 case LSM6DSOX_SPI_3_WIRE: 03723 *val = LSM6DSOX_SPI_3_WIRE; 03724 break; 03725 default: 03726 *val = LSM6DSOX_SPI_4_WIRE; 03727 break; 03728 } 03729 return ret; 03730 } 03731 03732 /** 03733 * @brief Disable / Enable I2C interface.[set] 03734 * 03735 * @param ctx read / write interface definitions 03736 * @param val change the values of i2c_disable in 03737 * reg CTRL4_C 03738 * 03739 */ 03740 int32_t lsm6dsox_i2c_interface_set(lsm6dsox_ctx_t *ctx, 03741 lsm6dsox_i2c_disable_t val) 03742 { 03743 lsm6dsox_ctrl4_c_t reg; 03744 int32_t ret; 03745 03746 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 03747 if (ret == 0) { 03748 reg.i2c_disable = (uint8_t)val; 03749 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 03750 } 03751 return ret; 03752 } 03753 03754 /** 03755 * @brief Disable / Enable I2C interface.[get] 03756 * 03757 * @param ctx read / write interface definitions 03758 * @param val Get the values of i2c_disable in 03759 * reg CTRL4_C 03760 * 03761 */ 03762 int32_t lsm6dsox_i2c_interface_get(lsm6dsox_ctx_t *ctx, 03763 lsm6dsox_i2c_disable_t *val) 03764 { 03765 lsm6dsox_ctrl4_c_t reg; 03766 int32_t ret; 03767 03768 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 03769 switch (reg.i2c_disable) { 03770 case LSM6DSOX_I2C_ENABLE: 03771 *val = LSM6DSOX_I2C_ENABLE; 03772 break; 03773 case LSM6DSOX_I2C_DISABLE: 03774 *val = LSM6DSOX_I2C_DISABLE; 03775 break; 03776 default: 03777 *val = LSM6DSOX_I2C_ENABLE; 03778 break; 03779 } 03780 return ret; 03781 } 03782 03783 /** 03784 * @brief I3C Enable/Disable communication protocol[.set] 03785 * 03786 * @param ctx read / write interface definitions 03787 * @param val change the values of i3c_disable 03788 * in reg CTRL9_XL 03789 * 03790 */ 03791 int32_t lsm6dsox_i3c_disable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t val) 03792 { 03793 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 03794 lsm6dsox_ctrl9_xl_t ctrl9_xl; 03795 int32_t ret; 03796 03797 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); 03798 if (ret == 0) { 03799 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; 03800 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); 03801 } 03802 if (ret == 0) { 03803 03804 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 03805 (uint8_t*)&i3c_bus_avb, 1); 03806 } 03807 if (ret == 0) { 03808 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; 03809 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 03810 (uint8_t*)&i3c_bus_avb, 1); 03811 } 03812 03813 return ret; 03814 } 03815 03816 /** 03817 * @brief I3C Enable/Disable communication protocol.[get] 03818 * 03819 * @param ctx read / write interface definitions 03820 * @param val change the values of i3c_disable in 03821 * reg CTRL9_XL 03822 * 03823 */ 03824 int32_t lsm6dsox_i3c_disable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t *val) 03825 { 03826 lsm6dsox_ctrl9_xl_t ctrl9_xl; 03827 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 03828 int32_t ret; 03829 03830 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); 03831 if (ret == 0) { 03832 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 03833 (uint8_t*)&i3c_bus_avb, 1); 03834 03835 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { 03836 case LSM6DSOX_I3C_DISABLE: 03837 *val = LSM6DSOX_I3C_DISABLE; 03838 break; 03839 case LSM6DSOX_I3C_ENABLE_T_50us: 03840 *val = LSM6DSOX_I3C_ENABLE_T_50us; 03841 break; 03842 case LSM6DSOX_I3C_ENABLE_T_2us: 03843 *val = LSM6DSOX_I3C_ENABLE_T_2us; 03844 break; 03845 case LSM6DSOX_I3C_ENABLE_T_1ms: 03846 *val = LSM6DSOX_I3C_ENABLE_T_1ms; 03847 break; 03848 case LSM6DSOX_I3C_ENABLE_T_25ms: 03849 *val = LSM6DSOX_I3C_ENABLE_T_25ms; 03850 break; 03851 default: 03852 *val = LSM6DSOX_I3C_DISABLE; 03853 break; 03854 } 03855 } 03856 return ret; 03857 } 03858 03859 /** 03860 * @} 03861 * 03862 */ 03863 03864 /** 03865 * @defgroup LSM6DSOX_interrupt_pins 03866 * @brief This section groups all the functions that manage interrup pins 03867 * @{ 03868 * 03869 */ 03870 03871 /** 03872 * @brief Push-pull/open drain selection on interrupt pads.[set] 03873 * 03874 * @param ctx read / write interface definitions 03875 * @param val change the values of pp_od in reg CTRL3_C 03876 * 03877 */ 03878 int32_t lsm6dsox_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t val) 03879 { 03880 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 03881 lsm6dsox_ctrl3_c_t ctrl3_c; 03882 int32_t ret; 03883 03884 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 03885 if (ret == 0) { 03886 ctrl3_c.pp_od = (uint8_t)val; 03887 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 03888 } 03889 if (ret == 0) { 03890 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 03891 (uint8_t*)&i3c_bus_avb, 1); 03892 } 03893 if (ret == 0) { 03894 i3c_bus_avb.pd_dis_int1 = ( (uint8_t) val & 0x02U ) >> 1; 03895 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 03896 (uint8_t*)&i3c_bus_avb, 1); 03897 } 03898 return ret; 03899 } 03900 03901 /** 03902 * @brief Push-pull/open drain selection on interrupt pads.[get] 03903 * 03904 * @param ctx read / write interface definitions 03905 * @param val Get the values of pp_od in reg CTRL3_C 03906 * 03907 */ 03908 int32_t lsm6dsox_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t *val) 03909 { 03910 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 03911 lsm6dsox_ctrl3_c_t ctrl3_c; 03912 int32_t ret; 03913 03914 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 03915 if (ret == 0) { 03916 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 03917 (uint8_t*)&i3c_bus_avb, 1); 03918 } 03919 03920 switch ( (i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) { 03921 case LSM6DSOX_PUSH_PULL: 03922 *val = LSM6DSOX_PUSH_PULL; 03923 break; 03924 case LSM6DSOX_OPEN_DRAIN: 03925 *val = LSM6DSOX_OPEN_DRAIN; 03926 break; 03927 case LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL: 03928 *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL; 03929 break; 03930 case LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN: 03931 *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN; 03932 break; 03933 default: 03934 *val = LSM6DSOX_PUSH_PULL; 03935 break; 03936 } 03937 return ret; 03938 } 03939 03940 /** 03941 * @brief Interrupt active-high/low.[set] 03942 * 03943 * @param ctx read / write interface definitions 03944 * @param val change the values of h_lactive in reg CTRL3_C 03945 * 03946 */ 03947 int32_t lsm6dsox_pin_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t val) 03948 { 03949 lsm6dsox_ctrl3_c_t reg; 03950 int32_t ret; 03951 03952 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 03953 if (ret == 0) { 03954 reg.h_lactive = (uint8_t)val; 03955 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 03956 } 03957 03958 return ret; 03959 } 03960 03961 /** 03962 * @brief Interrupt active-high/low.[get] 03963 * 03964 * @param ctx read / write interface definitions 03965 * @param val Get the values of h_lactive in reg CTRL3_C 03966 * 03967 */ 03968 int32_t lsm6dsox_pin_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t *val) 03969 { 03970 lsm6dsox_ctrl3_c_t reg; 03971 int32_t ret; 03972 03973 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); 03974 03975 switch (reg.h_lactive) { 03976 case LSM6DSOX_ACTIVE_HIGH: 03977 *val = LSM6DSOX_ACTIVE_HIGH; 03978 break; 03979 case LSM6DSOX_ACTIVE_LOW: 03980 *val = LSM6DSOX_ACTIVE_LOW; 03981 break; 03982 default: 03983 *val = LSM6DSOX_ACTIVE_HIGH; 03984 break; 03985 } 03986 return ret; 03987 } 03988 03989 /** 03990 * @brief All interrupt signals become available on INT1 pin.[set] 03991 * 03992 * @param ctx read / write interface definitions 03993 * @param val change the values of int2_on_int1 in reg CTRL4_C 03994 * 03995 */ 03996 int32_t lsm6dsox_all_on_int1_set(lsm6dsox_ctx_t *ctx, uint8_t val) 03997 { 03998 lsm6dsox_ctrl4_c_t reg; 03999 int32_t ret; 04000 04001 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 04002 if (ret == 0) { 04003 reg.int2_on_int1 = val; 04004 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 04005 } 04006 04007 return ret; 04008 } 04009 04010 /** 04011 * @brief All interrupt signals become available on INT1 pin.[get] 04012 * 04013 * @param ctx read / write interface definitions 04014 * @param val change the values of int2_on_int1 in reg CTRL4_C 04015 * 04016 */ 04017 int32_t lsm6dsox_all_on_int1_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04018 { 04019 lsm6dsox_ctrl4_c_t reg; 04020 int32_t ret; 04021 04022 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 04023 *val = reg.int2_on_int1; 04024 04025 return ret; 04026 } 04027 04028 /** 04029 * @brief Interrupt notification mode.[set] 04030 * 04031 * @param ctx read / write interface definitions 04032 * @param val change the values of lir in reg TAP_CFG0 04033 * 04034 */ 04035 int32_t lsm6dsox_int_notification_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t val) 04036 { 04037 lsm6dsox_tap_cfg0_t tap_cfg0; 04038 lsm6dsox_page_rw_t page_rw; 04039 int32_t ret; 04040 04041 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 04042 if (ret == 0) { 04043 tap_cfg0.lir = (uint8_t)val & 0x01U; 04044 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; 04045 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 04046 } 04047 if (ret == 0) { 04048 04049 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 04050 } 04051 if (ret == 0) { 04052 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 04053 } 04054 if (ret == 0) { 04055 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; 04056 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 04057 } 04058 if (ret == 0) { 04059 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 04060 } 04061 04062 return ret; 04063 } 04064 04065 /** 04066 * @brief Interrupt notification mode.[get] 04067 * 04068 * @param ctx read / write interface definitions 04069 * @param val Get the values of lir in reg TAP_CFG0 04070 * 04071 */ 04072 int32_t lsm6dsox_int_notification_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t *val) 04073 { 04074 lsm6dsox_tap_cfg0_t tap_cfg0; 04075 lsm6dsox_page_rw_t page_rw; 04076 int32_t ret; 04077 04078 04079 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 04080 if (ret == 0) { 04081 04082 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 04083 } 04084 if (ret == 0) { 04085 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 04086 } 04087 if (ret == 0) { 04088 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 04089 } 04090 if (ret == 0) { 04091 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) { 04092 case LSM6DSOX_ALL_INT_PULSED: 04093 *val = LSM6DSOX_ALL_INT_PULSED; 04094 break; 04095 case LSM6DSOX_BASE_LATCHED_EMB_PULSED: 04096 *val = LSM6DSOX_BASE_LATCHED_EMB_PULSED; 04097 break; 04098 case LSM6DSOX_BASE_PULSED_EMB_LATCHED: 04099 *val = LSM6DSOX_BASE_PULSED_EMB_LATCHED; 04100 break; 04101 case LSM6DSOX_ALL_INT_LATCHED: 04102 *val = LSM6DSOX_ALL_INT_LATCHED; 04103 break; 04104 default: 04105 *val = LSM6DSOX_ALL_INT_PULSED; 04106 break; 04107 } 04108 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 04109 } 04110 if (ret == 0) { 04111 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 04112 } 04113 if (ret == 0) { 04114 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 04115 } 04116 04117 return ret; 04118 } 04119 04120 /** 04121 * @} 04122 * 04123 */ 04124 04125 /** 04126 * @defgroup LSM6DSOX_Wake_Up_event 04127 * @brief This section groups all the functions that manage the Wake Up 04128 * event generation. 04129 * @{ 04130 * 04131 */ 04132 04133 /** 04134 * @brief Weight of 1 LSB of wakeup threshold.[set] 04135 * 0: 1 LSB =FS_XL / 64 04136 * 1: 1 LSB = FS_XL / 256 04137 * 04138 * @param ctx read / write interface definitions 04139 * @param val change the values of wake_ths_w in 04140 * reg WAKE_UP_DUR 04141 * 04142 */ 04143 int32_t lsm6dsox_wkup_ths_weight_set(lsm6dsox_ctx_t *ctx, 04144 lsm6dsox_wake_ths_w_t val) 04145 { 04146 lsm6dsox_wake_up_dur_t reg; 04147 int32_t ret; 04148 04149 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04150 if (ret == 0) { 04151 reg.wake_ths_w = (uint8_t)val; 04152 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04153 } 04154 return ret; 04155 } 04156 04157 /** 04158 * @brief Weight of 1 LSB of wakeup threshold.[get] 04159 * 0: 1 LSB =FS_XL / 64 04160 * 1: 1 LSB = FS_XL / 256 04161 * 04162 * @param ctx read / write interface definitions 04163 * @param val Get the values of wake_ths_w in 04164 * reg WAKE_UP_DUR 04165 * 04166 */ 04167 int32_t lsm6dsox_wkup_ths_weight_get(lsm6dsox_ctx_t *ctx, 04168 lsm6dsox_wake_ths_w_t *val) 04169 { 04170 lsm6dsox_wake_up_dur_t reg; 04171 int32_t ret; 04172 04173 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04174 04175 switch (reg.wake_ths_w) { 04176 case LSM6DSOX_LSb_FS_DIV_64: 04177 *val = LSM6DSOX_LSb_FS_DIV_64; 04178 break; 04179 case LSM6DSOX_LSb_FS_DIV_256: 04180 *val = LSM6DSOX_LSb_FS_DIV_256; 04181 break; 04182 default: 04183 *val = LSM6DSOX_LSb_FS_DIV_64; 04184 break; 04185 } 04186 return ret; 04187 } 04188 04189 /** 04190 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in 04191 * WAKE_UP_DUR.[set] 04192 * 04193 * @param ctx read / write interface definitions 04194 * @param val change the values of wk_ths in reg WAKE_UP_THS 04195 * 04196 */ 04197 int32_t lsm6dsox_wkup_threshold_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04198 { 04199 lsm6dsox_wake_up_ths_t reg; 04200 int32_t ret; 04201 04202 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04203 if (ret == 0) { 04204 reg.wk_ths = val; 04205 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04206 } 04207 return ret; 04208 } 04209 04210 /** 04211 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in 04212 * WAKE_UP_DUR.[get] 04213 * 04214 * @param ctx read / write interface definitions 04215 * @param val change the values of wk_ths in reg WAKE_UP_THS 04216 * 04217 */ 04218 int32_t lsm6dsox_wkup_threshold_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04219 { 04220 lsm6dsox_wake_up_ths_t reg; 04221 int32_t ret; 04222 04223 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04224 *val = reg.wk_ths; 04225 04226 return ret; 04227 } 04228 04229 /** 04230 * @brief Wake up duration event.[set] 04231 * 1LSb = 1 / ODR 04232 * 04233 * @param ctx read / write interface definitions 04234 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS 04235 * 04236 */ 04237 int32_t lsm6dsox_xl_usr_offset_on_wkup_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04238 { 04239 lsm6dsox_wake_up_ths_t reg; 04240 int32_t ret; 04241 04242 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04243 if (ret == 0) { 04244 reg.usr_off_on_wu = val; 04245 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04246 } 04247 return ret; 04248 } 04249 04250 /** 04251 * @brief Wake up duration event.[get] 04252 * 1LSb = 1 / ODR 04253 * 04254 * @param ctx read / write interface definitions 04255 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS 04256 * 04257 */ 04258 int32_t lsm6dsox_xl_usr_offset_on_wkup_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04259 { 04260 lsm6dsox_wake_up_ths_t reg; 04261 int32_t ret; 04262 04263 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04264 *val = reg.usr_off_on_wu; 04265 04266 return ret; 04267 } 04268 04269 /** 04270 * @brief Wake up duration event.[set] 04271 * 1LSb = 1 / ODR 04272 * 04273 * @param ctx read / write interface definitions 04274 * @param val change the values of wake_dur in reg WAKE_UP_DUR 04275 * 04276 */ 04277 int32_t lsm6dsox_wkup_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04278 { 04279 lsm6dsox_wake_up_dur_t reg; 04280 int32_t ret; 04281 04282 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04283 if (ret == 0) { 04284 reg.wake_dur = val; 04285 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04286 } 04287 return ret; 04288 } 04289 04290 /** 04291 * @brief Wake up duration event.[get] 04292 * 1LSb = 1 / ODR 04293 * 04294 * @param ctx read / write interface definitions 04295 * @param val change the values of wake_dur in reg WAKE_UP_DUR 04296 * 04297 */ 04298 int32_t lsm6dsox_wkup_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04299 { 04300 lsm6dsox_wake_up_dur_t reg; 04301 int32_t ret; 04302 04303 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04304 *val = reg.wake_dur; 04305 04306 return ret; 04307 } 04308 04309 /** 04310 * @} 04311 * 04312 */ 04313 04314 /** 04315 * @defgroup LSM6DSOX_ Activity/Inactivity_detection 04316 * @brief This section groups all the functions concerning 04317 * activity/inactivity detection. 04318 * @{ 04319 * 04320 */ 04321 04322 /** 04323 * @brief Enables gyroscope Sleep mode.[set] 04324 * 04325 * @param ctx read / write interface definitions 04326 * @param val change the values of sleep_g in reg CTRL4_C 04327 * 04328 */ 04329 int32_t lsm6dsox_gy_sleep_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04330 { 04331 lsm6dsox_ctrl4_c_t reg; 04332 int32_t ret; 04333 04334 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 04335 if (ret == 0) { 04336 reg.sleep_g = val; 04337 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 04338 } 04339 return ret; 04340 } 04341 04342 /** 04343 * @brief Enables gyroscope Sleep mode.[get] 04344 * 04345 * @param ctx read / write interface definitions 04346 * @param val change the values of sleep_g in reg CTRL4_C 04347 * 04348 */ 04349 int32_t lsm6dsox_gy_sleep_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04350 { 04351 lsm6dsox_ctrl4_c_t reg; 04352 int32_t ret; 04353 04354 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); 04355 *val = reg.sleep_g; 04356 04357 return ret; 04358 } 04359 04360 /** 04361 * @brief Drives the sleep status instead of 04362 * sleep change on INT pins 04363 * (only if INT1_SLEEP_CHANGE or 04364 * INT2_SLEEP_CHANGE bits are enabled).[set] 04365 * 04366 * @param ctx read / write interface definitions 04367 * @param val change the values of sleep_status_on_int in reg TAP_CFG0 04368 * 04369 */ 04370 int32_t lsm6dsox_act_pin_notification_set(lsm6dsox_ctx_t *ctx, 04371 lsm6dsox_sleep_status_on_int_t val) 04372 { 04373 lsm6dsox_tap_cfg0_t reg; 04374 int32_t ret; 04375 04376 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04377 if (ret == 0) { 04378 reg.sleep_status_on_int = (uint8_t)val; 04379 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04380 } 04381 return ret; 04382 } 04383 04384 /** 04385 * @brief Drives the sleep status instead of 04386 * sleep change on INT pins (only if 04387 * INT1_SLEEP_CHANGE or 04388 * INT2_SLEEP_CHANGE bits are enabled).[get] 04389 * 04390 * @param ctx read / write interface definitions 04391 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0 04392 * 04393 */ 04394 int32_t lsm6dsox_act_pin_notification_get(lsm6dsox_ctx_t *ctx, 04395 lsm6dsox_sleep_status_on_int_t *val) 04396 { 04397 lsm6dsox_tap_cfg0_t reg; 04398 int32_t ret; 04399 04400 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04401 switch (reg.sleep_status_on_int) { 04402 case LSM6DSOX_DRIVE_SLEEP_CHG_EVENT: 04403 *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT; 04404 break; 04405 case LSM6DSOX_DRIVE_SLEEP_STATUS: 04406 *val = LSM6DSOX_DRIVE_SLEEP_STATUS; 04407 break; 04408 default: 04409 *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT; 04410 break; 04411 } 04412 return ret; 04413 } 04414 04415 /** 04416 * @brief Enable inactivity function.[set] 04417 * 04418 * @param ctx read / write interface definitions 04419 * @param val change the values of inact_en in reg TAP_CFG2 04420 * 04421 */ 04422 int32_t lsm6dsox_act_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t val) 04423 { 04424 lsm6dsox_tap_cfg2_t reg; 04425 int32_t ret; 04426 04427 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); 04428 if (ret == 0) { 04429 reg.inact_en = (uint8_t)val; 04430 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); 04431 } 04432 return ret; 04433 } 04434 04435 /** 04436 * @brief Enable inactivity function.[get] 04437 * 04438 * @param ctx read / write interface definitions 04439 * @param val Get the values of inact_en in reg TAP_CFG2 04440 * 04441 */ 04442 int32_t lsm6dsox_act_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t *val) 04443 { 04444 lsm6dsox_tap_cfg2_t reg; 04445 int32_t ret; 04446 04447 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); 04448 switch (reg.inact_en) { 04449 case LSM6DSOX_XL_AND_GY_NOT_AFFECTED: 04450 *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED; 04451 break; 04452 case LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED: 04453 *val = LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED; 04454 break; 04455 case LSM6DSOX_XL_12Hz5_GY_SLEEP: 04456 *val = LSM6DSOX_XL_12Hz5_GY_SLEEP; 04457 break; 04458 case LSM6DSOX_XL_12Hz5_GY_PD: 04459 *val = LSM6DSOX_XL_12Hz5_GY_PD; 04460 break; 04461 default: 04462 *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED; 04463 break; 04464 } 04465 return ret; 04466 } 04467 04468 /** 04469 * @brief Duration to go in sleep mode.[set] 04470 * 1 LSb = 512 / ODR 04471 * 04472 * @param ctx read / write interface definitions 04473 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 04474 * 04475 */ 04476 int32_t lsm6dsox_act_sleep_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04477 { 04478 lsm6dsox_wake_up_dur_t reg; 04479 int32_t ret; 04480 04481 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04482 if (ret == 0) { 04483 reg.sleep_dur = val; 04484 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04485 } 04486 return ret; 04487 } 04488 04489 /** 04490 * @brief Duration to go in sleep mode.[get] 04491 * 1 LSb = 512 / ODR 04492 * 04493 * @param ctx read / write interface definitions 04494 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 04495 * 04496 */ 04497 int32_t lsm6dsox_act_sleep_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04498 { 04499 lsm6dsox_wake_up_dur_t reg; 04500 int32_t ret; 04501 04502 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); 04503 *val = reg.sleep_dur; 04504 04505 return ret; 04506 } 04507 04508 /** 04509 * @} 04510 * 04511 */ 04512 04513 /** 04514 * @defgroup LSM6DSOX_tap_generator 04515 * @brief This section groups all the functions that manage the 04516 * tap and double tap event generation. 04517 * @{ 04518 * 04519 */ 04520 04521 /** 04522 * @brief Enable Z direction in tap recognition.[set] 04523 * 04524 * @param ctx read / write interface definitions 04525 * @param val change the values of tap_z_en in reg TAP_CFG0 04526 * 04527 */ 04528 int32_t lsm6dsox_tap_detection_on_z_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04529 { 04530 lsm6dsox_tap_cfg0_t reg; 04531 int32_t ret; 04532 04533 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04534 if (ret == 0) { 04535 reg.tap_z_en = val; 04536 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04537 } 04538 return ret; 04539 } 04540 04541 /** 04542 * @brief Enable Z direction in tap recognition.[get] 04543 * 04544 * @param ctx read / write interface definitions 04545 * @param val change the values of tap_z_en in reg TAP_CFG0 04546 * 04547 */ 04548 int32_t lsm6dsox_tap_detection_on_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04549 { 04550 lsm6dsox_tap_cfg0_t reg; 04551 int32_t ret; 04552 04553 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04554 *val = reg.tap_z_en; 04555 04556 return ret; 04557 } 04558 04559 /** 04560 * @brief Enable Y direction in tap recognition.[set] 04561 * 04562 * @param ctx read / write interface definitions 04563 * @param val change the values of tap_y_en in reg TAP_CFG0 04564 * 04565 */ 04566 int32_t lsm6dsox_tap_detection_on_y_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04567 { 04568 lsm6dsox_tap_cfg0_t reg; 04569 int32_t ret; 04570 04571 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04572 if (ret == 0) { 04573 reg.tap_y_en = val; 04574 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04575 } 04576 return ret; 04577 } 04578 04579 /** 04580 * @brief Enable Y direction in tap recognition.[get] 04581 * 04582 * @param ctx read / write interface definitions 04583 * @param val change the values of tap_y_en in reg TAP_CFG0 04584 * 04585 */ 04586 int32_t lsm6dsox_tap_detection_on_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04587 { 04588 lsm6dsox_tap_cfg0_t reg; 04589 int32_t ret; 04590 04591 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04592 *val = reg.tap_y_en; 04593 04594 return ret; 04595 } 04596 04597 /** 04598 * @brief Enable X direction in tap recognition.[set] 04599 * 04600 * @param ctx read / write interface definitions 04601 * @param val change the values of tap_x_en in reg TAP_CFG0 04602 * 04603 */ 04604 int32_t lsm6dsox_tap_detection_on_x_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04605 { 04606 lsm6dsox_tap_cfg0_t reg; 04607 int32_t ret; 04608 04609 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04610 if (ret == 0) { 04611 reg.tap_x_en = val; 04612 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04613 } 04614 return ret; 04615 } 04616 04617 /** 04618 * @brief Enable X direction in tap recognition.[get] 04619 * 04620 * @param ctx read / write interface definitions 04621 * @param val change the values of tap_x_en in reg TAP_CFG0 04622 * 04623 */ 04624 int32_t lsm6dsox_tap_detection_on_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04625 { 04626 lsm6dsox_tap_cfg0_t reg; 04627 int32_t ret; 04628 04629 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); 04630 *val = reg.tap_x_en; 04631 04632 return ret; 04633 } 04634 04635 /** 04636 * @brief X-axis tap recognition threshold.[set] 04637 * 04638 * @param ctx read / write interface definitions 04639 * @param val change the values of tap_ths_x in reg TAP_CFG1 04640 * 04641 */ 04642 int32_t lsm6dsox_tap_threshold_x_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04643 { 04644 lsm6dsox_tap_cfg1_t reg; 04645 int32_t ret; 04646 04647 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); 04648 if (ret == 0) { 04649 reg.tap_ths_x = val; 04650 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); 04651 } 04652 return ret; 04653 } 04654 04655 /** 04656 * @brief X-axis tap recognition threshold.[get] 04657 * 04658 * @param ctx read / write interface definitions 04659 * @param val change the values of tap_ths_x in reg TAP_CFG1 04660 * 04661 */ 04662 int32_t lsm6dsox_tap_threshold_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04663 { 04664 lsm6dsox_tap_cfg1_t reg; 04665 int32_t ret; 04666 04667 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); 04668 *val = reg.tap_ths_x; 04669 04670 return ret; 04671 } 04672 04673 /** 04674 * @brief Selection of axis priority for TAP detection.[set] 04675 * 04676 * @param ctx read / write interface definitions 04677 * @param val change the values of tap_priority in 04678 * reg TAP_CFG1 04679 * 04680 */ 04681 int32_t lsm6dsox_tap_axis_priority_set(lsm6dsox_ctx_t *ctx, 04682 lsm6dsox_tap_priority_t val) 04683 { 04684 lsm6dsox_tap_cfg1_t reg; 04685 int32_t ret; 04686 04687 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); 04688 if (ret == 0) { 04689 reg.tap_priority = (uint8_t)val; 04690 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); 04691 } 04692 return ret; 04693 } 04694 04695 /** 04696 * @brief Selection of axis priority for TAP detection.[get] 04697 * 04698 * @param ctx read / write interface definitions 04699 * @param val Get the values of tap_priority in 04700 * reg TAP_CFG1 04701 * 04702 */ 04703 int32_t lsm6dsox_tap_axis_priority_get(lsm6dsox_ctx_t *ctx, 04704 lsm6dsox_tap_priority_t *val) 04705 { 04706 lsm6dsox_tap_cfg1_t reg; 04707 int32_t ret; 04708 04709 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); 04710 switch (reg.tap_priority) { 04711 case LSM6DSOX_XYZ: 04712 *val = LSM6DSOX_XYZ; 04713 break; 04714 case LSM6DSOX_YXZ: 04715 *val = LSM6DSOX_YXZ; 04716 break; 04717 case LSM6DSOX_XZY: 04718 *val = LSM6DSOX_XZY; 04719 break; 04720 case LSM6DSOX_ZYX: 04721 *val = LSM6DSOX_ZYX; 04722 break; 04723 case LSM6DSOX_YZX: 04724 *val = LSM6DSOX_YZX; 04725 break; 04726 case LSM6DSOX_ZXY: 04727 *val = LSM6DSOX_ZXY; 04728 break; 04729 default: 04730 *val = LSM6DSOX_XYZ; 04731 break; 04732 } 04733 return ret; 04734 } 04735 04736 /** 04737 * @brief Y-axis tap recognition threshold.[set] 04738 * 04739 * @param ctx read / write interface definitions 04740 * @param val change the values of tap_ths_y in reg TAP_CFG2 04741 * 04742 */ 04743 int32_t lsm6dsox_tap_threshold_y_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04744 { 04745 lsm6dsox_tap_cfg2_t reg; 04746 int32_t ret; 04747 04748 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); 04749 if (ret == 0) { 04750 reg.tap_ths_y = val; 04751 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); 04752 } 04753 return ret; 04754 } 04755 04756 /** 04757 * @brief Y-axis tap recognition threshold.[get] 04758 * 04759 * @param ctx read / write interface definitions 04760 * @param val change the values of tap_ths_y in reg TAP_CFG2 04761 * 04762 */ 04763 int32_t lsm6dsox_tap_threshold_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04764 { 04765 lsm6dsox_tap_cfg2_t reg; 04766 int32_t ret; 04767 04768 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); 04769 *val = reg.tap_ths_y; 04770 04771 return ret; 04772 } 04773 04774 /** 04775 * @brief Z-axis recognition threshold.[set] 04776 * 04777 * @param ctx read / write interface definitions 04778 * @param val change the values of tap_ths_z in reg TAP_THS_6D 04779 * 04780 */ 04781 int32_t lsm6dsox_tap_threshold_z_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04782 { 04783 lsm6dsox_tap_ths_6d_t reg; 04784 int32_t ret; 04785 04786 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 04787 if (ret == 0) { 04788 reg.tap_ths_z = val; 04789 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 04790 } 04791 return ret; 04792 } 04793 04794 /** 04795 * @brief Z-axis recognition threshold.[get] 04796 * 04797 * @param ctx read / write interface definitions 04798 * @param val change the values of tap_ths_z in reg TAP_THS_6D 04799 * 04800 */ 04801 int32_t lsm6dsox_tap_threshold_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04802 { 04803 lsm6dsox_tap_ths_6d_t reg; 04804 int32_t ret; 04805 04806 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 04807 *val = reg.tap_ths_z; 04808 04809 return ret; 04810 } 04811 04812 /** 04813 * @brief Maximum duration is the maximum time of an 04814 * over threshold signal detection to be recognized 04815 * as a tap event. The default value of these bits 04816 * is 00b which corresponds to 4*ODR_XL time. 04817 * If the SHOCK[1:0] bits are set to a different 04818 * value, 1LSB corresponds to 8*ODR_XL time.[set] 04819 * 04820 * @param ctx read / write interface definitions 04821 * @param val change the values of shock in reg INT_DUR2 04822 * 04823 */ 04824 int32_t lsm6dsox_tap_shock_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04825 { 04826 lsm6dsox_int_dur2_t reg; 04827 int32_t ret; 04828 04829 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04830 if (ret == 0) { 04831 reg.shock = val; 04832 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04833 } 04834 return ret; 04835 } 04836 04837 /** 04838 * @brief Maximum duration is the maximum time of an 04839 * over threshold signal detection to be recognized 04840 * as a tap event. The default value of these bits 04841 * is 00b which corresponds to 4*ODR_XL time. 04842 * If the SHOCK[1:0] bits are set to a different 04843 * value, 1LSB corresponds to 8*ODR_XL time.[get] 04844 * 04845 * @param ctx read / write interface definitions 04846 * @param val change the values of shock in reg INT_DUR2 04847 * 04848 */ 04849 int32_t lsm6dsox_tap_shock_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04850 { 04851 lsm6dsox_int_dur2_t reg; 04852 int32_t ret; 04853 04854 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04855 *val = reg.shock; 04856 04857 return ret; 04858 } 04859 04860 /** 04861 * @brief Quiet time is the time after the first detected 04862 * tap in which there must not be any over threshold 04863 * event. 04864 * The default value of these bits is 00b which 04865 * corresponds to 2*ODR_XL time. If the QUIET[1:0] 04866 * bits are set to a different value, 04867 * 1LSB corresponds to 4*ODR_XL time.[set] 04868 * 04869 * @param ctx read / write interface definitions 04870 * @param val change the values of quiet in reg INT_DUR2 04871 * 04872 */ 04873 int32_t lsm6dsox_tap_quiet_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04874 { 04875 lsm6dsox_int_dur2_t reg; 04876 int32_t ret; 04877 04878 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04879 if (ret == 0) { 04880 reg.quiet = val; 04881 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04882 } 04883 return ret; 04884 } 04885 04886 /** 04887 * @brief Quiet time is the time after the first detected 04888 * tap in which there must not be any over threshold 04889 * event. 04890 * The default value of these bits is 00b which 04891 * corresponds to 2*ODR_XL time. 04892 * If the QUIET[1:0] bits are set to a different 04893 * value, 1LSB corresponds to 4*ODR_XL time.[get] 04894 * 04895 * @param ctx read / write interface definitions 04896 * @param val change the values of quiet in reg INT_DUR2 04897 * 04898 */ 04899 int32_t lsm6dsox_tap_quiet_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04900 { 04901 lsm6dsox_int_dur2_t reg; 04902 int32_t ret; 04903 04904 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04905 *val = reg.quiet; 04906 04907 return ret; 04908 } 04909 04910 /** 04911 * @brief When double tap recognition is enabled, 04912 * this register expresses the maximum time 04913 * between two consecutive detected taps to 04914 * determine a double tap event. 04915 * The default value of these bits is 0000b which 04916 * corresponds to 16*ODR_XL time. 04917 * If the DUR[3:0] bits are set to a different value, 04918 * 1LSB corresponds to 32*ODR_XL time.[set] 04919 * 04920 * @param ctx read / write interface definitions 04921 * @param val change the values of dur in reg INT_DUR2 04922 * 04923 */ 04924 int32_t lsm6dsox_tap_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) 04925 { 04926 lsm6dsox_int_dur2_t reg; 04927 int32_t ret; 04928 04929 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04930 if (ret == 0) { 04931 reg.dur = val; 04932 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04933 } 04934 return ret; 04935 } 04936 04937 /** 04938 * @brief When double tap recognition is enabled, 04939 * this register expresses the maximum time 04940 * between two consecutive detected taps to 04941 * determine a double tap event. 04942 * The default value of these bits is 0000b which 04943 * corresponds to 16*ODR_XL time. If the DUR[3:0] 04944 * bits are set to a different value, 04945 * 1LSB corresponds to 32*ODR_XL time.[get] 04946 * 04947 * @param ctx read / write interface definitions 04948 * @param val change the values of dur in reg INT_DUR2 04949 * 04950 */ 04951 int32_t lsm6dsox_tap_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 04952 { 04953 lsm6dsox_int_dur2_t reg; 04954 int32_t ret; 04955 04956 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); 04957 *val = reg.dur; 04958 04959 return ret; 04960 } 04961 04962 /** 04963 * @brief Single/double-tap event enable.[set] 04964 * 04965 * @param ctx read / write interface definitions 04966 * @param val change the values of single_double_tap in reg WAKE_UP_THS 04967 * 04968 */ 04969 int32_t lsm6dsox_tap_mode_set(lsm6dsox_ctx_t *ctx, 04970 lsm6dsox_single_double_tap_t val) 04971 { 04972 lsm6dsox_wake_up_ths_t reg; 04973 int32_t ret; 04974 04975 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04976 if (ret == 0) { 04977 reg.single_double_tap = (uint8_t)val; 04978 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04979 } 04980 return ret; 04981 } 04982 04983 /** 04984 * @brief Single/double-tap event enable.[get] 04985 * 04986 * @param ctx read / write interface definitions 04987 * @param val Get the values of single_double_tap in reg WAKE_UP_THS 04988 * 04989 */ 04990 int32_t lsm6dsox_tap_mode_get(lsm6dsox_ctx_t *ctx, 04991 lsm6dsox_single_double_tap_t *val) 04992 { 04993 lsm6dsox_wake_up_ths_t reg; 04994 int32_t ret; 04995 04996 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); 04997 04998 switch (reg.single_double_tap) { 04999 case LSM6DSOX_ONLY_SINGLE: 05000 *val = LSM6DSOX_ONLY_SINGLE; 05001 break; 05002 case LSM6DSOX_BOTH_SINGLE_DOUBLE: 05003 *val = LSM6DSOX_BOTH_SINGLE_DOUBLE; 05004 break; 05005 default: 05006 *val = LSM6DSOX_ONLY_SINGLE; 05007 break; 05008 } 05009 05010 return ret; 05011 } 05012 05013 /** 05014 * @} 05015 * 05016 */ 05017 05018 /** 05019 * @defgroup LSM6DSOX_ Six_position_detection(6D/4D) 05020 * @brief This section groups all the functions concerning six position 05021 * detection (6D). 05022 * @{ 05023 * 05024 */ 05025 05026 /** 05027 * @brief Threshold for 4D/6D function.[set] 05028 * 05029 * @param ctx read / write interface definitions 05030 * @param val change the values of sixd_ths in reg TAP_THS_6D 05031 * 05032 */ 05033 int32_t lsm6dsox_6d_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t val) 05034 { 05035 lsm6dsox_tap_ths_6d_t reg; 05036 int32_t ret; 05037 05038 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 05039 if (ret == 0) { 05040 reg.sixd_ths = (uint8_t)val; 05041 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 05042 } 05043 return ret; 05044 } 05045 05046 /** 05047 * @brief Threshold for 4D/6D function.[get] 05048 * 05049 * @param ctx read / write interface definitions 05050 * @param val Get the values of sixd_ths in reg TAP_THS_6D 05051 * 05052 */ 05053 int32_t lsm6dsox_6d_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t *val) 05054 { 05055 lsm6dsox_tap_ths_6d_t reg; 05056 int32_t ret; 05057 05058 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 05059 switch (reg.sixd_ths) { 05060 case LSM6DSOX_DEG_80: 05061 *val = LSM6DSOX_DEG_80; 05062 break; 05063 case LSM6DSOX_DEG_70: 05064 *val = LSM6DSOX_DEG_70; 05065 break; 05066 case LSM6DSOX_DEG_60: 05067 *val = LSM6DSOX_DEG_60; 05068 break; 05069 case LSM6DSOX_DEG_50: 05070 *val = LSM6DSOX_DEG_50; 05071 break; 05072 default: 05073 *val = LSM6DSOX_DEG_80; 05074 break; 05075 } 05076 return ret; 05077 } 05078 05079 /** 05080 * @brief 4D orientation detection enable.[set] 05081 * 05082 * @param ctx read / write interface definitions 05083 * @param val change the values of d4d_en in reg TAP_THS_6D 05084 * 05085 */ 05086 int32_t lsm6dsox_4d_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val) 05087 { 05088 lsm6dsox_tap_ths_6d_t reg; 05089 int32_t ret; 05090 05091 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 05092 if (ret == 0) { 05093 reg.d4d_en = val; 05094 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 05095 } 05096 return ret; 05097 } 05098 05099 /** 05100 * @brief 4D orientation detection enable.[get] 05101 * 05102 * @param ctx read / write interface definitions 05103 * @param val change the values of d4d_en in reg TAP_THS_6D 05104 * 05105 */ 05106 int32_t lsm6dsox_4d_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 05107 { 05108 lsm6dsox_tap_ths_6d_t reg; 05109 int32_t ret; 05110 05111 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); 05112 *val = reg.d4d_en; 05113 05114 return ret; 05115 } 05116 05117 /** 05118 * @} 05119 * 05120 */ 05121 05122 /** 05123 * @defgroup LSM6DSOX_free_fall 05124 * @brief This section group all the functions concerning the free 05125 * fall detection. 05126 * @{ 05127 * 05128 */ 05129 /** 05130 * @brief Free fall threshold setting.[set] 05131 * 05132 * @param ctx read / write interface definitions 05133 * @param val change the values of ff_ths in reg FREE_FALL 05134 * 05135 */ 05136 int32_t lsm6dsox_ff_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t val) 05137 { 05138 lsm6dsox_free_fall_t reg; 05139 int32_t ret; 05140 05141 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1); 05142 if (ret == 0) { 05143 reg.ff_ths = (uint8_t)val; 05144 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1); 05145 } 05146 return ret; 05147 } 05148 05149 /** 05150 * @brief Free fall threshold setting.[get] 05151 * 05152 * @param ctx read / write interface definitions 05153 * @param val Get the values of ff_ths in reg FREE_FALL 05154 * 05155 */ 05156 int32_t lsm6dsox_ff_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t *val) 05157 { 05158 lsm6dsox_free_fall_t reg; 05159 int32_t ret; 05160 05161 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1); 05162 switch (reg.ff_ths) { 05163 case LSM6DSOX_FF_TSH_156mg: 05164 *val = LSM6DSOX_FF_TSH_156mg; 05165 break; 05166 case LSM6DSOX_FF_TSH_219mg: 05167 *val = LSM6DSOX_FF_TSH_219mg; 05168 break; 05169 case LSM6DSOX_FF_TSH_250mg: 05170 *val = LSM6DSOX_FF_TSH_250mg; 05171 break; 05172 case LSM6DSOX_FF_TSH_312mg: 05173 *val = LSM6DSOX_FF_TSH_312mg; 05174 break; 05175 case LSM6DSOX_FF_TSH_344mg: 05176 *val = LSM6DSOX_FF_TSH_344mg; 05177 break; 05178 case LSM6DSOX_FF_TSH_406mg: 05179 *val = LSM6DSOX_FF_TSH_406mg; 05180 break; 05181 case LSM6DSOX_FF_TSH_469mg: 05182 *val = LSM6DSOX_FF_TSH_469mg; 05183 break; 05184 case LSM6DSOX_FF_TSH_500mg: 05185 *val = LSM6DSOX_FF_TSH_500mg; 05186 break; 05187 default: 05188 *val = LSM6DSOX_FF_TSH_156mg; 05189 break; 05190 } 05191 return ret; 05192 } 05193 05194 /** 05195 * @brief Free-fall duration event.[set] 05196 * 1LSb = 1 / ODR 05197 * 05198 * @param ctx read / write interface definitions 05199 * @param val change the values of ff_dur in reg FREE_FALL 05200 * 05201 */ 05202 int32_t lsm6dsox_ff_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) 05203 { 05204 lsm6dsox_wake_up_dur_t wake_up_dur; 05205 lsm6dsox_free_fall_t free_fall; 05206 int32_t ret; 05207 05208 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); 05209 if (ret == 0) { 05210 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1); 05211 } 05212 if (ret == 0) { 05213 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; 05214 free_fall.ff_dur = (uint8_t)val & 0x1FU; 05215 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, 05216 (uint8_t*)&wake_up_dur, 1); 05217 } 05218 if (ret == 0) { 05219 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1); 05220 } 05221 return ret; 05222 } 05223 05224 /** 05225 * @brief Free-fall duration event.[get] 05226 * 1LSb = 1 / ODR 05227 * 05228 * @param ctx read / write interface definitions 05229 * @param val change the values of ff_dur in reg FREE_FALL 05230 * 05231 */ 05232 int32_t lsm6dsox_ff_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 05233 { 05234 lsm6dsox_wake_up_dur_t wake_up_dur; 05235 lsm6dsox_free_fall_t free_fall; 05236 int32_t ret; 05237 05238 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); 05239 if (ret == 0) { 05240 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1); 05241 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; 05242 } 05243 return ret; 05244 } 05245 05246 /** 05247 * @} 05248 * 05249 */ 05250 05251 /** 05252 * @defgroup LSM6DSOX_fifo 05253 * @brief This section group all the functions concerning the fifo usage 05254 * @{ 05255 * 05256 */ 05257 05258 /** 05259 * @brief FIFO watermark level selection.[set] 05260 * 05261 * @param ctx read / write interface definitions 05262 * @param val change the values of wtm in reg FIFO_CTRL1 05263 * 05264 */ 05265 int32_t lsm6dsox_fifo_watermark_set(lsm6dsox_ctx_t *ctx, uint16_t val) 05266 { 05267 lsm6dsox_fifo_ctrl1_t fifo_ctrl1; 05268 lsm6dsox_fifo_ctrl2_t fifo_ctrl2; 05269 int32_t ret; 05270 05271 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); 05272 if (ret == 0) { 05273 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val; 05274 fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8); 05275 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); 05276 } 05277 if (ret == 0) { 05278 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); 05279 } 05280 return ret; 05281 } 05282 05283 /** 05284 * @brief FIFO watermark level selection.[get] 05285 * 05286 * @param ctx read / write interface definitions 05287 * @param val change the values of wtm in reg FIFO_CTRL1 05288 * 05289 */ 05290 int32_t lsm6dsox_fifo_watermark_get(lsm6dsox_ctx_t *ctx, uint16_t *val) 05291 { 05292 lsm6dsox_fifo_ctrl1_t fifo_ctrl1; 05293 lsm6dsox_fifo_ctrl2_t fifo_ctrl2; 05294 int32_t ret; 05295 05296 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); 05297 if (ret == 0) { 05298 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); 05299 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; 05300 } 05301 return ret; 05302 } 05303 05304 /** 05305 * @brief FIFO compression feature initialization request [set]. 05306 * 05307 * @param ctx read / write interface definitions 05308 * @param val change the values of FIFO_COMPR_INIT in 05309 * reg EMB_FUNC_INIT_B 05310 * 05311 */ 05312 int32_t lsm6dsox_compression_algo_init_set(lsm6dsox_ctx_t *ctx, uint8_t val) 05313 { 05314 lsm6dsox_emb_func_init_b_t reg; 05315 int32_t ret; 05316 05317 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 05318 if (ret == 0) { 05319 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 05320 } 05321 if (ret == 0) { 05322 reg.fifo_compr_init = val; 05323 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 05324 } 05325 if (ret == 0) { 05326 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 05327 } 05328 05329 return ret; 05330 } 05331 05332 /** 05333 * @brief FIFO compression feature initialization request [get]. 05334 * 05335 * @param ctx read / write interface definitions 05336 * @param val change the values of FIFO_COMPR_INIT in 05337 * reg EMB_FUNC_INIT_B 05338 * 05339 */ 05340 int32_t lsm6dsox_compression_algo_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 05341 { 05342 lsm6dsox_emb_func_init_b_t reg; 05343 int32_t ret; 05344 05345 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 05346 if (ret == 0) { 05347 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 05348 } 05349 if (ret == 0) { 05350 *val = reg.fifo_compr_init; 05351 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 05352 } 05353 05354 return ret; 05355 } 05356 05357 /** 05358 * @brief Enable and configure compression algo.[set] 05359 * 05360 * @param ctx read / write interface definitions 05361 * @param val change the values of uncoptr_rate in 05362 * reg FIFO_CTRL2 05363 * 05364 */ 05365 int32_t lsm6dsox_compression_algo_set(lsm6dsox_ctx_t *ctx, 05366 lsm6dsox_uncoptr_rate_t val) 05367 { 05368 lsm6dsox_fifo_ctrl2_t fifo_ctrl2; 05369 int32_t ret; 05370 05371 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, 05372 (uint8_t*)&fifo_ctrl2, 1); 05373 if (ret == 0) { 05374 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2; 05375 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U; 05376 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, 05377 (uint8_t*)&fifo_ctrl2, 1); 05378 } 05379 return ret; 05380 } 05381 05382 /** 05383 * @brief Enable and configure compression algo.[get] 05384 * 05385 * @param ctx read / write interface definitions 05386 * @param val Get the values of uncoptr_rate in 05387 * reg FIFO_CTRL2 05388 * 05389 */ 05390 int32_t lsm6dsox_compression_algo_get(lsm6dsox_ctx_t *ctx, 05391 lsm6dsox_uncoptr_rate_t *val) 05392 { 05393 lsm6dsox_fifo_ctrl2_t reg; 05394 int32_t ret; 05395 05396 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05397 05398 switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) { 05399 case LSM6DSOX_CMP_DISABLE: 05400 *val = LSM6DSOX_CMP_DISABLE; 05401 break; 05402 case LSM6DSOX_CMP_ALWAYS: 05403 *val = LSM6DSOX_CMP_ALWAYS; 05404 break; 05405 case LSM6DSOX_CMP_8_TO_1: 05406 *val = LSM6DSOX_CMP_8_TO_1; 05407 break; 05408 case LSM6DSOX_CMP_16_TO_1: 05409 *val = LSM6DSOX_CMP_16_TO_1; 05410 break; 05411 case LSM6DSOX_CMP_32_TO_1: 05412 *val = LSM6DSOX_CMP_32_TO_1; 05413 break; 05414 default: 05415 *val = LSM6DSOX_CMP_DISABLE; 05416 break; 05417 } 05418 return ret; 05419 } 05420 05421 /** 05422 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] 05423 * 05424 * @param ctx read / write interface definitions 05425 * @param val change the values of odrchg_en in reg FIFO_CTRL2 05426 * 05427 */ 05428 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(lsm6dsox_ctx_t *ctx, 05429 uint8_t val) 05430 { 05431 lsm6dsox_fifo_ctrl2_t reg; 05432 int32_t ret; 05433 05434 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05435 if (ret == 0) { 05436 reg.odrchg_en = val; 05437 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05438 } 05439 return ret; 05440 } 05441 05442 /** 05443 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] 05444 * 05445 * @param ctx read / write interface definitions 05446 * @param val change the values of odrchg_en in reg FIFO_CTRL2 05447 * 05448 */ 05449 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(lsm6dsox_ctx_t *ctx, 05450 uint8_t *val) 05451 { 05452 lsm6dsox_fifo_ctrl2_t reg; 05453 int32_t ret; 05454 05455 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05456 *val = reg.odrchg_en; 05457 05458 return ret; 05459 } 05460 05461 /** 05462 * @brief Enables/Disables compression algorithm runtime.[set] 05463 * 05464 * @param ctx read / write interface definitions 05465 * @param val change the values of fifo_compr_rt_en in 05466 * reg FIFO_CTRL2 05467 * 05468 */ 05469 int32_t lsm6dsox_compression_algo_real_time_set(lsm6dsox_ctx_t *ctx, 05470 uint8_t val) 05471 { 05472 lsm6dsox_fifo_ctrl2_t reg; 05473 int32_t ret; 05474 05475 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05476 if (ret == 0) { 05477 reg.fifo_compr_rt_en = val; 05478 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05479 } 05480 return ret; 05481 } 05482 05483 /** 05484 * @brief Enables/Disables compression algorithm runtime. [get] 05485 * 05486 * @param ctx read / write interface definitions 05487 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2 05488 * 05489 */ 05490 int32_t lsm6dsox_compression_algo_real_time_get(lsm6dsox_ctx_t *ctx, 05491 uint8_t *val) 05492 { 05493 lsm6dsox_fifo_ctrl2_t reg; 05494 int32_t ret; 05495 05496 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05497 *val = reg.fifo_compr_rt_en; 05498 05499 return ret; 05500 } 05501 05502 /** 05503 * @brief Sensing chain FIFO stop values memorization at 05504 * threshold level.[set] 05505 * 05506 * @param ctx read / write interface definitions 05507 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 05508 * 05509 */ 05510 int32_t lsm6dsox_fifo_stop_on_wtm_set(lsm6dsox_ctx_t *ctx, uint8_t val) 05511 { 05512 lsm6dsox_fifo_ctrl2_t reg; 05513 int32_t ret; 05514 05515 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05516 if (ret == 0) { 05517 reg.stop_on_wtm = val; 05518 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05519 } 05520 return ret; 05521 } 05522 05523 /** 05524 * @brief Sensing chain FIFO stop values memorization at 05525 * threshold level.[get] 05526 * 05527 * @param ctx read / write interface definitions 05528 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 05529 * 05530 */ 05531 int32_t lsm6dsox_fifo_stop_on_wtm_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 05532 { 05533 lsm6dsox_fifo_ctrl2_t reg; 05534 int32_t ret; 05535 05536 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); 05537 *val = reg.stop_on_wtm; 05538 05539 return ret; 05540 } 05541 05542 /** 05543 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05544 * for accelerometer data.[set] 05545 * 05546 * @param ctx read / write interface definitions 05547 * @param val change the values of bdr_xl in reg FIFO_CTRL3 05548 * 05549 */ 05550 int32_t lsm6dsox_fifo_xl_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t val) 05551 { 05552 lsm6dsox_fifo_ctrl3_t reg; 05553 int32_t ret; 05554 05555 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); 05556 if (ret == 0) { 05557 reg.bdr_xl = (uint8_t)val; 05558 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); 05559 } 05560 return ret; 05561 } 05562 05563 /** 05564 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05565 * for accelerometer data.[get] 05566 * 05567 * @param ctx read / write interface definitions 05568 * @param val Get the values of bdr_xl in reg FIFO_CTRL3 05569 * 05570 */ 05571 int32_t lsm6dsox_fifo_xl_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t *val) 05572 { 05573 lsm6dsox_fifo_ctrl3_t reg; 05574 int32_t ret; 05575 05576 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); 05577 switch (reg.bdr_xl) { 05578 case LSM6DSOX_XL_NOT_BATCHED: 05579 *val = LSM6DSOX_XL_NOT_BATCHED; 05580 break; 05581 case LSM6DSOX_XL_BATCHED_AT_12Hz5: 05582 *val = LSM6DSOX_XL_BATCHED_AT_12Hz5; 05583 break; 05584 case LSM6DSOX_XL_BATCHED_AT_26Hz: 05585 *val = LSM6DSOX_XL_BATCHED_AT_26Hz; 05586 break; 05587 case LSM6DSOX_XL_BATCHED_AT_52Hz: 05588 *val = LSM6DSOX_XL_BATCHED_AT_52Hz; 05589 break; 05590 case LSM6DSOX_XL_BATCHED_AT_104Hz: 05591 *val = LSM6DSOX_XL_BATCHED_AT_104Hz; 05592 break; 05593 case LSM6DSOX_XL_BATCHED_AT_208Hz: 05594 *val = LSM6DSOX_XL_BATCHED_AT_208Hz; 05595 break; 05596 case LSM6DSOX_XL_BATCHED_AT_417Hz: 05597 *val = LSM6DSOX_XL_BATCHED_AT_417Hz; 05598 break; 05599 case LSM6DSOX_XL_BATCHED_AT_833Hz: 05600 *val = LSM6DSOX_XL_BATCHED_AT_833Hz; 05601 break; 05602 case LSM6DSOX_XL_BATCHED_AT_1667Hz: 05603 *val = LSM6DSOX_XL_BATCHED_AT_1667Hz; 05604 break; 05605 case LSM6DSOX_XL_BATCHED_AT_3333Hz: 05606 *val = LSM6DSOX_XL_BATCHED_AT_3333Hz; 05607 break; 05608 case LSM6DSOX_XL_BATCHED_AT_6667Hz: 05609 *val = LSM6DSOX_XL_BATCHED_AT_6667Hz; 05610 break; 05611 case LSM6DSOX_XL_BATCHED_AT_6Hz5: 05612 *val = LSM6DSOX_XL_BATCHED_AT_6Hz5; 05613 break; 05614 default: 05615 *val = LSM6DSOX_XL_NOT_BATCHED; 05616 break; 05617 } 05618 05619 return ret; 05620 } 05621 05622 /** 05623 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05624 * for gyroscope data.[set] 05625 * 05626 * @param ctx read / write interface definitions 05627 * @param val change the values of bdr_gy in reg FIFO_CTRL3 05628 * 05629 */ 05630 int32_t lsm6dsox_fifo_gy_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t val) 05631 { 05632 lsm6dsox_fifo_ctrl3_t reg; 05633 int32_t ret; 05634 05635 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); 05636 if (ret == 0) { 05637 reg.bdr_gy = (uint8_t)val; 05638 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); 05639 } 05640 return ret; 05641 } 05642 05643 /** 05644 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05645 * for gyroscope data.[get] 05646 * 05647 * @param ctx read / write interface definitions 05648 * @param val Get the values of bdr_gy in reg FIFO_CTRL3 05649 * 05650 */ 05651 int32_t lsm6dsox_fifo_gy_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t *val) 05652 { 05653 lsm6dsox_fifo_ctrl3_t reg; 05654 int32_t ret; 05655 05656 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); 05657 switch (reg.bdr_gy) { 05658 case LSM6DSOX_GY_NOT_BATCHED: 05659 *val = LSM6DSOX_GY_NOT_BATCHED; 05660 break; 05661 case LSM6DSOX_GY_BATCHED_AT_12Hz5: 05662 *val = LSM6DSOX_GY_BATCHED_AT_12Hz5; 05663 break; 05664 case LSM6DSOX_GY_BATCHED_AT_26Hz: 05665 *val = LSM6DSOX_GY_BATCHED_AT_26Hz; 05666 break; 05667 case LSM6DSOX_GY_BATCHED_AT_52Hz: 05668 *val = LSM6DSOX_GY_BATCHED_AT_52Hz; 05669 break; 05670 case LSM6DSOX_GY_BATCHED_AT_104Hz: 05671 *val = LSM6DSOX_GY_BATCHED_AT_104Hz; 05672 break; 05673 case LSM6DSOX_GY_BATCHED_AT_208Hz: 05674 *val = LSM6DSOX_GY_BATCHED_AT_208Hz; 05675 break; 05676 case LSM6DSOX_GY_BATCHED_AT_417Hz: 05677 *val = LSM6DSOX_GY_BATCHED_AT_417Hz; 05678 break; 05679 case LSM6DSOX_GY_BATCHED_AT_833Hz: 05680 *val = LSM6DSOX_GY_BATCHED_AT_833Hz; 05681 break; 05682 case LSM6DSOX_GY_BATCHED_AT_1667Hz: 05683 *val = LSM6DSOX_GY_BATCHED_AT_1667Hz; 05684 break; 05685 case LSM6DSOX_GY_BATCHED_AT_3333Hz: 05686 *val = LSM6DSOX_GY_BATCHED_AT_3333Hz; 05687 break; 05688 case LSM6DSOX_GY_BATCHED_AT_6667Hz: 05689 *val = LSM6DSOX_GY_BATCHED_AT_6667Hz; 05690 break; 05691 case LSM6DSOX_GY_BATCHED_AT_6Hz5: 05692 *val = LSM6DSOX_GY_BATCHED_AT_6Hz5; 05693 break; 05694 default: 05695 *val = LSM6DSOX_GY_NOT_BATCHED; 05696 break; 05697 } 05698 return ret; 05699 } 05700 05701 /** 05702 * @brief FIFO mode selection.[set] 05703 * 05704 * @param ctx read / write interface definitions 05705 * @param val change the values of fifo_mode in reg FIFO_CTRL4 05706 * 05707 */ 05708 int32_t lsm6dsox_fifo_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t val) 05709 { 05710 lsm6dsox_fifo_ctrl4_t reg; 05711 int32_t ret; 05712 05713 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05714 if (ret == 0) { 05715 reg.fifo_mode = (uint8_t)val; 05716 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05717 } 05718 return ret; 05719 } 05720 05721 /** 05722 * @brief FIFO mode selection.[get] 05723 * 05724 * @param ctx read / write interface definitions 05725 * @param val Get the values of fifo_mode in reg FIFO_CTRL4 05726 * 05727 */ 05728 int32_t lsm6dsox_fifo_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t *val) 05729 { 05730 lsm6dsox_fifo_ctrl4_t reg; 05731 int32_t ret; 05732 05733 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05734 05735 switch (reg.fifo_mode) { 05736 case LSM6DSOX_BYPASS_MODE: 05737 *val = LSM6DSOX_BYPASS_MODE; 05738 break; 05739 case LSM6DSOX_FIFO_MODE: 05740 *val = LSM6DSOX_FIFO_MODE; 05741 break; 05742 case LSM6DSOX_STREAM_TO_FIFO_MODE: 05743 *val = LSM6DSOX_STREAM_TO_FIFO_MODE; 05744 break; 05745 case LSM6DSOX_BYPASS_TO_STREAM_MODE: 05746 *val = LSM6DSOX_BYPASS_TO_STREAM_MODE; 05747 break; 05748 case LSM6DSOX_STREAM_MODE: 05749 *val = LSM6DSOX_STREAM_MODE; 05750 break; 05751 case LSM6DSOX_BYPASS_TO_FIFO_MODE: 05752 *val = LSM6DSOX_BYPASS_TO_FIFO_MODE; 05753 break; 05754 default: 05755 *val = LSM6DSOX_BYPASS_MODE; 05756 break; 05757 } 05758 return ret; 05759 } 05760 05761 /** 05762 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05763 * for temperature data.[set] 05764 * 05765 * @param ctx read / write interface definitions 05766 * @param val change the values of odr_t_batch in reg FIFO_CTRL4 05767 * 05768 */ 05769 int32_t lsm6dsox_fifo_temp_batch_set(lsm6dsox_ctx_t *ctx, 05770 lsm6dsox_odr_t_batch_t val) 05771 { 05772 lsm6dsox_fifo_ctrl4_t reg; 05773 int32_t ret; 05774 05775 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05776 if (ret == 0) { 05777 reg.odr_t_batch = (uint8_t)val; 05778 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05779 } 05780 return ret; 05781 } 05782 05783 /** 05784 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05785 * for temperature data.[get] 05786 * 05787 * @param ctx read / write interface definitions 05788 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 05789 * 05790 */ 05791 int32_t lsm6dsox_fifo_temp_batch_get(lsm6dsox_ctx_t *ctx, 05792 lsm6dsox_odr_t_batch_t *val) 05793 { 05794 lsm6dsox_fifo_ctrl4_t reg; 05795 int32_t ret; 05796 05797 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05798 05799 switch (reg.odr_t_batch) { 05800 case LSM6DSOX_TEMP_NOT_BATCHED: 05801 *val = LSM6DSOX_TEMP_NOT_BATCHED; 05802 break; 05803 case LSM6DSOX_TEMP_BATCHED_AT_1Hz6: 05804 *val = LSM6DSOX_TEMP_BATCHED_AT_1Hz6; 05805 break; 05806 case LSM6DSOX_TEMP_BATCHED_AT_12Hz5: 05807 *val = LSM6DSOX_TEMP_BATCHED_AT_12Hz5; 05808 break; 05809 case LSM6DSOX_TEMP_BATCHED_AT_52Hz: 05810 *val = LSM6DSOX_TEMP_BATCHED_AT_52Hz; 05811 break; 05812 default: 05813 *val = LSM6DSOX_TEMP_NOT_BATCHED; 05814 break; 05815 } 05816 return ret; 05817 } 05818 05819 /** 05820 * @brief Selects decimation for timestamp batching in FIFO. 05821 * Writing rate will be the maximum rate between XL and 05822 * GYRO BDR divided by decimation decoder.[set] 05823 * 05824 * @param ctx read / write interface definitions 05825 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4 05826 * 05827 */ 05828 int32_t lsm6dsox_fifo_timestamp_decimation_set(lsm6dsox_ctx_t *ctx, 05829 lsm6dsox_odr_ts_batch_t val) 05830 { 05831 lsm6dsox_fifo_ctrl4_t reg; 05832 int32_t ret; 05833 05834 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05835 if (ret == 0) { 05836 reg.odr_ts_batch = (uint8_t)val; 05837 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05838 } 05839 return ret; 05840 } 05841 05842 /** 05843 * @brief Selects decimation for timestamp batching in FIFO. 05844 * Writing rate will be the maximum rate between XL and 05845 * GYRO BDR divided by decimation decoder.[get] 05846 * 05847 * @param ctx read / write interface definitions 05848 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4 05849 * 05850 */ 05851 int32_t lsm6dsox_fifo_timestamp_decimation_get(lsm6dsox_ctx_t *ctx, 05852 lsm6dsox_odr_ts_batch_t *val) 05853 { 05854 lsm6dsox_fifo_ctrl4_t reg; 05855 int32_t ret; 05856 05857 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); 05858 switch (reg.odr_ts_batch) { 05859 case LSM6DSOX_NO_DECIMATION: 05860 *val = LSM6DSOX_NO_DECIMATION; 05861 break; 05862 case LSM6DSOX_DEC_1: 05863 *val = LSM6DSOX_DEC_1; 05864 break; 05865 case LSM6DSOX_DEC_8: 05866 *val = LSM6DSOX_DEC_8; 05867 break; 05868 case LSM6DSOX_DEC_32: 05869 *val = LSM6DSOX_DEC_32; 05870 break; 05871 default: 05872 *val = LSM6DSOX_NO_DECIMATION; 05873 break; 05874 } 05875 return ret; 05876 } 05877 05878 /** 05879 * @brief Selects the trigger for the internal counter of batching events 05880 * between XL and gyro.[set] 05881 * 05882 * @param ctx read / write interface definitions 05883 * @param val change the values of trig_counter_bdr 05884 * in reg COUNTER_BDR_REG1 05885 * 05886 */ 05887 int32_t lsm6dsox_fifo_cnt_event_batch_set(lsm6dsox_ctx_t *ctx, 05888 lsm6dsox_trig_counter_bdr_t val) 05889 { 05890 lsm6dsox_counter_bdr_reg1_t reg; 05891 int32_t ret; 05892 05893 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05894 if (ret == 0) { 05895 reg.trig_counter_bdr = (uint8_t)val; 05896 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05897 } 05898 return ret; 05899 } 05900 05901 /** 05902 * @brief Selects the trigger for the internal counter of batching events 05903 * between XL and gyro.[get] 05904 * 05905 * @param ctx read / write interface definitions 05906 * @param val Get the values of trig_counter_bdr 05907 * in reg COUNTER_BDR_REG1 05908 * 05909 */ 05910 int32_t lsm6dsox_fifo_cnt_event_batch_get(lsm6dsox_ctx_t *ctx, 05911 lsm6dsox_trig_counter_bdr_t *val) 05912 { 05913 lsm6dsox_counter_bdr_reg1_t reg; 05914 int32_t ret; 05915 05916 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05917 switch (reg.trig_counter_bdr) { 05918 case LSM6DSOX_XL_BATCH_EVENT: 05919 *val = LSM6DSOX_XL_BATCH_EVENT; 05920 break; 05921 case LSM6DSOX_GYRO_BATCH_EVENT: 05922 *val = LSM6DSOX_GYRO_BATCH_EVENT; 05923 break; 05924 default: 05925 *val = LSM6DSOX_XL_BATCH_EVENT; 05926 break; 05927 } 05928 return ret; 05929 } 05930 05931 /** 05932 * @brief Resets the internal counter of batching vents for a single sensor. 05933 * This bit is automatically reset to zero if it was set to ‘1’.[set] 05934 * 05935 * @param ctx read / write interface definitions 05936 * @param val change the values of rst_counter_bdr in 05937 * reg COUNTER_BDR_REG1 05938 * 05939 */ 05940 int32_t lsm6dsox_rst_batch_counter_set(lsm6dsox_ctx_t *ctx, uint8_t val) 05941 { 05942 lsm6dsox_counter_bdr_reg1_t reg; 05943 int32_t ret; 05944 05945 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05946 if (ret == 0) { 05947 reg.rst_counter_bdr = val; 05948 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05949 } 05950 return ret; 05951 } 05952 05953 /** 05954 * @brief Resets the internal counter of batching events for a single sensor. 05955 * This bit is automatically reset to zero if it was set to ‘1’.[get] 05956 * 05957 * @param ctx read / write interface definitions 05958 * @param val change the values of rst_counter_bdr in 05959 * reg COUNTER_BDR_REG1 05960 * 05961 */ 05962 int32_t lsm6dsox_rst_batch_counter_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 05963 { 05964 lsm6dsox_counter_bdr_reg1_t reg; 05965 int32_t ret; 05966 05967 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05968 *val = reg.rst_counter_bdr; 05969 05970 return ret; 05971 } 05972 05973 /** 05974 * @brief Batch data rate counter.[set] 05975 * 05976 * @param ctx read / write interface definitions 05977 * @param val change the values of cnt_bdr_th in 05978 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. 05979 * 05980 */ 05981 int32_t lsm6dsox_batch_counter_threshold_set(lsm6dsox_ctx_t *ctx, uint16_t val) 05982 { 05983 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; 05984 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; 05985 int32_t ret; 05986 05987 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, 05988 (uint8_t*)&counter_bdr_reg1, 1); 05989 if (ret == 0) { 05990 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val; 05991 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8; 05992 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, 05993 (uint8_t*)&counter_bdr_reg1, 1); 05994 } 05995 if (ret == 0) { 05996 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2, 05997 (uint8_t*)&counter_bdr_reg2, 1); 05998 } 05999 return ret; 06000 } 06001 06002 /** 06003 * @brief Batch data rate counter.[get] 06004 * 06005 * @param ctx read / write interface definitions 06006 * @param val change the values of cnt_bdr_th in 06007 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. 06008 * 06009 */ 06010 int32_t lsm6dsox_batch_counter_threshold_get(lsm6dsox_ctx_t *ctx, uint16_t *val) 06011 { 06012 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; 06013 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; 06014 int32_t ret; 06015 06016 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, 06017 (uint8_t*)&counter_bdr_reg1, 1); 06018 if (ret == 0) { 06019 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2, 06020 (uint8_t*)&counter_bdr_reg2, 1); 06021 06022 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) 06023 + (uint16_t)counter_bdr_reg2.cnt_bdr_th; 06024 } 06025 06026 return ret; 06027 } 06028 06029 /** 06030 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get] 06031 * 06032 * @param ctx read / write interface definitions 06033 * @param val change the values of diff_fifo in reg FIFO_STATUS1 06034 * 06035 */ 06036 int32_t lsm6dsox_fifo_data_level_get(lsm6dsox_ctx_t *ctx, uint16_t *val) 06037 { 06038 lsm6dsox_fifo_status1_t fifo_status1; 06039 lsm6dsox_fifo_status2_t fifo_status2; 06040 int32_t ret; 06041 06042 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, 06043 (uint8_t*)&fifo_status1, 1); 06044 if (ret == 0) { 06045 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, 06046 (uint8_t*)&fifo_status2, 1); 06047 *val = ((uint16_t)fifo_status2.diff_fifo << 8) + 06048 (uint16_t)fifo_status1.diff_fifo; 06049 } 06050 return ret; 06051 } 06052 06053 /** 06054 * @brief FIFO status.[get] 06055 * 06056 * @param ctx read / write interface definitions 06057 * @param val registers FIFO_STATUS2 06058 * 06059 */ 06060 int32_t lsm6dsox_fifo_status_get(lsm6dsox_ctx_t *ctx, 06061 lsm6dsox_fifo_status2_t *val) 06062 { 06063 int32_t ret; 06064 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*) val, 1); 06065 return ret; 06066 } 06067 06068 /** 06069 * @brief Smart FIFO full status.[get] 06070 * 06071 * @param ctx read / write interface definitions 06072 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2 06073 * 06074 */ 06075 int32_t lsm6dsox_fifo_full_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06076 { 06077 lsm6dsox_fifo_status2_t reg; 06078 int32_t ret; 06079 06080 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1); 06081 *val = reg.fifo_full_ia; 06082 06083 return ret; 06084 } 06085 06086 /** 06087 * @brief FIFO overrun status.[get] 06088 * 06089 * @param ctx read / write interface definitions 06090 * @param val change the values of fifo_over_run_latched in 06091 * reg FIFO_STATUS2 06092 * 06093 */ 06094 int32_t lsm6dsox_fifo_ovr_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06095 { 06096 lsm6dsox_fifo_status2_t reg; 06097 int32_t ret; 06098 06099 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1); 06100 *val = reg.fifo_ovr_ia; 06101 06102 return ret; 06103 } 06104 06105 /** 06106 * @brief FIFO watermark status.[get] 06107 * 06108 * @param ctx read / write interface definitions 06109 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2 06110 * 06111 */ 06112 int32_t lsm6dsox_fifo_wtm_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06113 { 06114 lsm6dsox_fifo_status2_t reg; 06115 int32_t ret; 06116 06117 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1); 06118 *val = reg.fifo_wtm_ia; 06119 06120 return ret; 06121 } 06122 06123 /** 06124 * @brief Identifies the sensor in FIFO_DATA_OUT.[get] 06125 * 06126 * @param ctx read / write interface definitions 06127 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG 06128 * 06129 */ 06130 int32_t lsm6dsox_fifo_sensor_tag_get(lsm6dsox_ctx_t *ctx, 06131 lsm6dsox_fifo_tag_t *val) 06132 { 06133 lsm6dsox_fifo_data_out_tag_t reg; 06134 int32_t ret; 06135 06136 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG, (uint8_t*)®, 1); 06137 switch (reg.tag_sensor) { 06138 case LSM6DSOX_GYRO_NC_TAG: 06139 *val = LSM6DSOX_GYRO_NC_TAG; 06140 break; 06141 case LSM6DSOX_XL_NC_TAG: 06142 *val = LSM6DSOX_XL_NC_TAG; 06143 break; 06144 case LSM6DSOX_TEMPERATURE_TAG: 06145 *val = LSM6DSOX_TEMPERATURE_TAG; 06146 break; 06147 case LSM6DSOX_TIMESTAMP_TAG: 06148 *val = LSM6DSOX_TIMESTAMP_TAG; 06149 break; 06150 case LSM6DSOX_CFG_CHANGE_TAG: 06151 *val = LSM6DSOX_CFG_CHANGE_TAG; 06152 break; 06153 case LSM6DSOX_XL_NC_T_2_TAG: 06154 *val = LSM6DSOX_XL_NC_T_2_TAG; 06155 break; 06156 case LSM6DSOX_XL_NC_T_1_TAG: 06157 *val = LSM6DSOX_XL_NC_T_1_TAG; 06158 break; 06159 case LSM6DSOX_XL_2XC_TAG: 06160 *val = LSM6DSOX_XL_2XC_TAG; 06161 break; 06162 case LSM6DSOX_XL_3XC_TAG: 06163 *val = LSM6DSOX_XL_3XC_TAG; 06164 break; 06165 case LSM6DSOX_GYRO_NC_T_2_TAG: 06166 *val = LSM6DSOX_GYRO_NC_T_2_TAG; 06167 break; 06168 case LSM6DSOX_GYRO_NC_T_1_TAG: 06169 *val = LSM6DSOX_GYRO_NC_T_1_TAG; 06170 break; 06171 case LSM6DSOX_GYRO_2XC_TAG: 06172 *val = LSM6DSOX_GYRO_2XC_TAG; 06173 break; 06174 case LSM6DSOX_GYRO_3XC_TAG: 06175 *val = LSM6DSOX_GYRO_3XC_TAG; 06176 break; 06177 case LSM6DSOX_SENSORHUB_SLAVE0_TAG: 06178 *val = LSM6DSOX_SENSORHUB_SLAVE0_TAG; 06179 break; 06180 case LSM6DSOX_SENSORHUB_SLAVE1_TAG: 06181 *val = LSM6DSOX_SENSORHUB_SLAVE1_TAG; 06182 break; 06183 case LSM6DSOX_SENSORHUB_SLAVE2_TAG: 06184 *val = LSM6DSOX_SENSORHUB_SLAVE2_TAG; 06185 break; 06186 case LSM6DSOX_SENSORHUB_SLAVE3_TAG: 06187 *val = LSM6DSOX_SENSORHUB_SLAVE3_TAG; 06188 break; 06189 case LSM6DSOX_STEP_CPUNTER_TAG: 06190 *val = LSM6DSOX_STEP_CPUNTER_TAG; 06191 break; 06192 case LSM6DSOX_GAME_ROTATION_TAG: 06193 *val = LSM6DSOX_GAME_ROTATION_TAG; 06194 break; 06195 case LSM6DSOX_GEOMAG_ROTATION_TAG: 06196 *val = LSM6DSOX_GEOMAG_ROTATION_TAG; 06197 break; 06198 case LSM6DSOX_ROTATION_TAG: 06199 *val = LSM6DSOX_ROTATION_TAG; 06200 break; 06201 case LSM6DSOX_SENSORHUB_NACK_TAG: 06202 *val = LSM6DSOX_SENSORHUB_NACK_TAG; 06203 break; 06204 default: 06205 *val = LSM6DSOX_GYRO_NC_TAG; 06206 break; 06207 } 06208 return ret; 06209 } 06210 06211 /** 06212 * @brief : Enable FIFO batching of pedometer embedded 06213 * function values.[set] 06214 * 06215 * @param ctx read / write interface definitions 06216 * @param val change the values of gbias_fifo_en in 06217 * reg LSM6DSOX_EMB_FUNC_FIFO_CFG 06218 * 06219 */ 06220 int32_t lsm6dsox_fifo_pedo_batch_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06221 { 06222 lsm6dsox_emb_func_fifo_cfg_t reg; 06223 int32_t ret; 06224 06225 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 06226 if (ret == 0) { 06227 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1); 06228 } 06229 if (ret == 0) { 06230 reg.pedo_fifo_en = val; 06231 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, 06232 (uint8_t*)®, 1); 06233 } 06234 if (ret == 0) { 06235 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06236 } 06237 return ret; 06238 } 06239 06240 /** 06241 * @brief Enable FIFO batching of pedometer embedded function values.[get] 06242 * 06243 * @param ctx read / write interface definitions 06244 * @param val change the values of pedo_fifo_en in 06245 * reg LSM6DSOX_EMB_FUNC_FIFO_CFG 06246 * 06247 */ 06248 int32_t lsm6dsox_fifo_pedo_batch_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06249 { 06250 lsm6dsox_emb_func_fifo_cfg_t reg; 06251 int32_t ret; 06252 06253 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 06254 if (ret == 0) { 06255 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1); 06256 } 06257 if (ret == 0) { 06258 *val = reg.pedo_fifo_en; 06259 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06260 } 06261 return ret; 06262 } 06263 06264 /** 06265 * @brief Enable FIFO batching data of first slave.[set] 06266 * 06267 * @param ctx read / write interface definitions 06268 * @param val change the values of batch_ext_sens_0_en in 06269 * reg SLV0_CONFIG 06270 * 06271 */ 06272 int32_t lsm6dsox_sh_batch_slave_0_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06273 { 06274 lsm6dsox_slv0_config_t reg; 06275 int32_t ret; 06276 06277 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06278 if (ret == 0) { 06279 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); 06280 } 06281 if (ret == 0) { 06282 reg.batch_ext_sens_0_en = val; 06283 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); 06284 } 06285 if (ret == 0) { 06286 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06287 } 06288 return ret; 06289 } 06290 06291 /** 06292 * @brief Enable FIFO batching data of first slave.[get] 06293 * 06294 * @param ctx read / write interface definitions 06295 * @param val change the values of batch_ext_sens_0_en in 06296 * reg SLV0_CONFIG 06297 * 06298 */ 06299 int32_t lsm6dsox_sh_batch_slave_0_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06300 { 06301 lsm6dsox_slv0_config_t reg; 06302 int32_t ret; 06303 06304 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06305 if (ret == 0) { 06306 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); 06307 } 06308 if (ret == 0) { 06309 *val = reg.batch_ext_sens_0_en; 06310 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06311 } 06312 return ret; 06313 } 06314 06315 /** 06316 * @brief Enable FIFO batching data of second slave.[set] 06317 * 06318 * @param ctx read / write interface definitions 06319 * @param val change the values of batch_ext_sens_1_en in 06320 * reg SLV1_CONFIG 06321 * 06322 */ 06323 int32_t lsm6dsox_sh_batch_slave_1_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06324 { 06325 lsm6dsox_slv1_config_t reg; 06326 int32_t ret; 06327 06328 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06329 if (ret == 0) { 06330 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); 06331 } 06332 if (ret == 0) { 06333 reg.batch_ext_sens_1_en = val; 06334 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); 06335 } 06336 if (ret == 0) { 06337 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06338 } 06339 06340 return ret; 06341 } 06342 06343 /** 06344 * @brief Enable FIFO batching data of second slave.[get] 06345 * 06346 * @param ctx read / write interface definitions 06347 * @param val change the values of batch_ext_sens_1_en in 06348 * reg SLV1_CONFIG 06349 * 06350 */ 06351 int32_t lsm6dsox_sh_batch_slave_1_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06352 { 06353 lsm6dsox_slv1_config_t reg; 06354 int32_t ret; 06355 06356 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06357 if (ret == 0) { 06358 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); 06359 *val = reg.batch_ext_sens_1_en; 06360 } 06361 if (ret == 0) { 06362 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06363 } 06364 return ret; 06365 } 06366 06367 /** 06368 * @brief Enable FIFO batching data of third slave.[set] 06369 * 06370 * @param ctx read / write interface definitions 06371 * @param val change the values of batch_ext_sens_2_en in 06372 * reg SLV2_CONFIG 06373 * 06374 */ 06375 int32_t lsm6dsox_sh_batch_slave_2_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06376 { 06377 lsm6dsox_slv2_config_t reg; 06378 int32_t ret; 06379 06380 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06381 06382 if (ret == 0) { 06383 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1); 06384 } 06385 if (ret == 0) { 06386 reg.batch_ext_sens_2_en = val; 06387 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1); 06388 } 06389 if (ret == 0) { 06390 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06391 } 06392 return ret; 06393 } 06394 06395 /** 06396 * @brief Enable FIFO batching data of third slave.[get] 06397 * 06398 * @param ctx read / write interface definitions 06399 * @param val change the values of batch_ext_sens_2_en in 06400 * reg SLV2_CONFIG 06401 * 06402 */ 06403 int32_t lsm6dsox_sh_batch_slave_2_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06404 { 06405 lsm6dsox_slv2_config_t reg; 06406 int32_t ret; 06407 06408 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06409 if (ret == 0) { 06410 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1); 06411 } 06412 if (ret == 0) { 06413 *val = reg.batch_ext_sens_2_en; 06414 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06415 } 06416 06417 return ret; 06418 } 06419 06420 /** 06421 * @brief Enable FIFO batching data of fourth slave.[set] 06422 * 06423 * @param ctx read / write interface definitions 06424 * @param val change the values of batch_ext_sens_3_en 06425 * in reg SLV3_CONFIG 06426 * 06427 */ 06428 int32_t lsm6dsox_sh_batch_slave_3_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06429 { 06430 lsm6dsox_slv3_config_t reg; 06431 int32_t ret; 06432 06433 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06434 if (ret == 0) { 06435 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1); 06436 } 06437 if (ret == 0) { 06438 reg.batch_ext_sens_3_en = val; 06439 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1); 06440 } 06441 if (ret == 0) { 06442 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06443 } 06444 06445 return ret; 06446 } 06447 06448 /** 06449 * @brief Enable FIFO batching data of fourth slave.[get] 06450 * 06451 * @param ctx read / write interface definitions 06452 * @param val change the values of batch_ext_sens_3_en in 06453 * reg SLV3_CONFIG 06454 * 06455 */ 06456 int32_t lsm6dsox_sh_batch_slave_3_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06457 { 06458 lsm6dsox_slv3_config_t reg; 06459 int32_t ret; 06460 06461 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 06462 if (ret == 0) { 06463 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1); 06464 } 06465 if (ret == 0) { 06466 *val = reg.batch_ext_sens_3_en; 06467 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06468 } 06469 06470 return ret; 06471 } 06472 06473 /** 06474 * @} 06475 * 06476 */ 06477 06478 /** 06479 * @defgroup LSM6DSOX_DEN_functionality 06480 * @brief This section groups all the functions concerning 06481 * DEN functionality. 06482 * @{ 06483 * 06484 */ 06485 06486 /** 06487 * @brief DEN functionality marking mode.[set] 06488 * 06489 * @param ctx read / write interface definitions 06490 * @param val change the values of den_mode in reg CTRL6_C 06491 * 06492 */ 06493 int32_t lsm6dsox_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t val) 06494 { 06495 lsm6dsox_ctrl6_c_t reg; 06496 int32_t ret; 06497 06498 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 06499 if (ret == 0) { 06500 reg.den_mode = (uint8_t)val; 06501 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 06502 } 06503 06504 return ret; 06505 } 06506 06507 /** 06508 * @brief DEN functionality marking mode.[get] 06509 * 06510 * @param ctx read / write interface definitions 06511 * @param val Get the values of den_mode in reg CTRL6_C 06512 * 06513 */ 06514 int32_t lsm6dsox_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t *val) 06515 { 06516 lsm6dsox_ctrl6_c_t reg; 06517 int32_t ret; 06518 06519 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); 06520 06521 switch (reg.den_mode) { 06522 case LSM6DSOX_DEN_DISABLE: 06523 *val = LSM6DSOX_DEN_DISABLE; 06524 break; 06525 case LSM6DSOX_LEVEL_FIFO: 06526 *val = LSM6DSOX_LEVEL_FIFO; 06527 break; 06528 case LSM6DSOX_LEVEL_LETCHED: 06529 *val = LSM6DSOX_LEVEL_LETCHED; 06530 break; 06531 case LSM6DSOX_LEVEL_TRIGGER: 06532 *val = LSM6DSOX_LEVEL_TRIGGER; 06533 break; 06534 case LSM6DSOX_EDGE_TRIGGER: 06535 *val = LSM6DSOX_EDGE_TRIGGER; 06536 break; 06537 default: 06538 *val = LSM6DSOX_DEN_DISABLE; 06539 break; 06540 } 06541 return ret; 06542 } 06543 06544 /** 06545 * @brief DEN active level configuration.[set] 06546 * 06547 * @param ctx read / write interface definitions 06548 * @param val change the values of den_lh in reg CTRL9_XL 06549 * 06550 */ 06551 int32_t lsm6dsox_den_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t val) 06552 { 06553 lsm6dsox_ctrl9_xl_t reg; 06554 int32_t ret; 06555 06556 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06557 if (ret == 0) { 06558 reg.den_lh = (uint8_t)val; 06559 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06560 } 06561 06562 return ret; 06563 } 06564 06565 /** 06566 * @brief DEN active level configuration.[get] 06567 * 06568 * @param ctx read / write interface definitions 06569 * @param val Get the values of den_lh in reg CTRL9_XL 06570 * 06571 */ 06572 int32_t lsm6dsox_den_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t *val) 06573 { 06574 lsm6dsox_ctrl9_xl_t reg; 06575 int32_t ret; 06576 06577 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06578 06579 switch (reg.den_lh) { 06580 case LSM6DSOX_DEN_ACT_LOW: 06581 *val = LSM6DSOX_DEN_ACT_LOW; 06582 break; 06583 case LSM6DSOX_DEN_ACT_HIGH: 06584 *val = LSM6DSOX_DEN_ACT_HIGH; 06585 break; 06586 default: 06587 *val = LSM6DSOX_DEN_ACT_LOW; 06588 break; 06589 } 06590 return ret; 06591 } 06592 06593 /** 06594 * @brief DEN enable.[set] 06595 * 06596 * @param ctx read / write interface definitions 06597 * @param val change the values of den_xl_g in reg CTRL9_XL 06598 * 06599 */ 06600 int32_t lsm6dsox_den_enable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t val) 06601 { 06602 lsm6dsox_ctrl9_xl_t reg; 06603 int32_t ret; 06604 06605 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06606 if (ret == 0) { 06607 reg.den_xl_g = (uint8_t)val; 06608 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06609 } 06610 06611 return ret; 06612 } 06613 06614 /** 06615 * @brief DEN enable.[get] 06616 * 06617 * @param ctx read / write interface definitions 06618 * @param val Get the values of den_xl_g in reg CTRL9_XL 06619 * 06620 */ 06621 int32_t lsm6dsox_den_enable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t *val) 06622 { 06623 lsm6dsox_ctrl9_xl_t reg; 06624 int32_t ret; 06625 06626 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06627 06628 switch (reg.den_xl_g) { 06629 case LSM6DSOX_STAMP_IN_GY_DATA: 06630 *val = LSM6DSOX_STAMP_IN_GY_DATA; 06631 break; 06632 case LSM6DSOX_STAMP_IN_XL_DATA: 06633 *val = LSM6DSOX_STAMP_IN_XL_DATA; 06634 break; 06635 case LSM6DSOX_STAMP_IN_GY_XL_DATA: 06636 *val = LSM6DSOX_STAMP_IN_GY_XL_DATA; 06637 break; 06638 default: 06639 *val = LSM6DSOX_STAMP_IN_GY_DATA; 06640 break; 06641 } 06642 return ret; 06643 } 06644 06645 /** 06646 * @brief DEN value stored in LSB of X-axis.[set] 06647 * 06648 * @param ctx read / write interface definitions 06649 * @param val change the values of den_z in reg CTRL9_XL 06650 * 06651 */ 06652 int32_t lsm6dsox_den_mark_axis_x_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06653 { 06654 lsm6dsox_ctrl9_xl_t reg; 06655 int32_t ret; 06656 06657 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06658 if (ret == 0) { 06659 reg.den_z = val; 06660 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06661 } 06662 06663 return ret; 06664 } 06665 06666 /** 06667 * @brief DEN value stored in LSB of X-axis.[get] 06668 * 06669 * @param ctx read / write interface definitions 06670 * @param val change the values of den_z in reg CTRL9_XL 06671 * 06672 */ 06673 int32_t lsm6dsox_den_mark_axis_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06674 { 06675 lsm6dsox_ctrl9_xl_t reg; 06676 int32_t ret; 06677 06678 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06679 *val = reg.den_z; 06680 06681 return ret; 06682 } 06683 06684 /** 06685 * @brief DEN value stored in LSB of Y-axis.[set] 06686 * 06687 * @param ctx read / write interface definitions 06688 * @param val change the values of den_y in reg CTRL9_XL 06689 * 06690 */ 06691 int32_t lsm6dsox_den_mark_axis_y_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06692 { 06693 lsm6dsox_ctrl9_xl_t reg; 06694 int32_t ret; 06695 06696 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06697 if (ret == 0) { 06698 reg.den_y = val; 06699 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06700 } 06701 06702 return ret; 06703 } 06704 06705 /** 06706 * @brief DEN value stored in LSB of Y-axis.[get] 06707 * 06708 * @param ctx read / write interface definitions 06709 * @param val change the values of den_y in reg CTRL9_XL 06710 * 06711 */ 06712 int32_t lsm6dsox_den_mark_axis_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06713 { 06714 lsm6dsox_ctrl9_xl_t reg; 06715 int32_t ret; 06716 06717 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06718 *val = reg.den_y; 06719 06720 return ret; 06721 } 06722 06723 /** 06724 * @brief DEN value stored in LSB of Z-axis.[set] 06725 * 06726 * @param ctx read / write interface definitions 06727 * @param val change the values of den_x in reg CTRL9_XL 06728 * 06729 */ 06730 int32_t lsm6dsox_den_mark_axis_z_set(lsm6dsox_ctx_t *ctx, uint8_t val) 06731 { 06732 lsm6dsox_ctrl9_xl_t reg; 06733 int32_t ret; 06734 06735 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06736 if (ret == 0) { 06737 reg.den_x = val; 06738 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06739 } 06740 06741 return ret; 06742 } 06743 06744 /** 06745 * @brief DEN value stored in LSB of Z-axis.[get] 06746 * 06747 * @param ctx read / write interface definitions 06748 * @param val change the values of den_x in reg CTRL9_XL 06749 * 06750 */ 06751 int32_t lsm6dsox_den_mark_axis_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06752 { 06753 lsm6dsox_ctrl9_xl_t reg; 06754 int32_t ret; 06755 06756 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); 06757 *val = reg.den_x; 06758 06759 return ret; 06760 } 06761 06762 /** 06763 * @} 06764 * 06765 */ 06766 06767 /** 06768 * @defgroup LSM6DSOX_Pedometer 06769 * @brief This section groups all the functions that manage pedometer. 06770 * @{ 06771 * 06772 */ 06773 06774 /** 06775 * @brief Enable pedometer algorithm.[set] 06776 * 06777 * @param ctx read / write interface definitions 06778 * @param val turn on and configure pedometer 06779 * 06780 */ 06781 int32_t lsm6dsox_pedo_sens_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t val) 06782 { 06783 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; 06784 int32_t ret; 06785 06786 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, 06787 (uint8_t*)&pedo_cmd_reg); 06788 06789 if (ret == 0) { 06790 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4; 06791 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5; 06792 06793 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG, 06794 (uint8_t*)&pedo_cmd_reg); 06795 } 06796 return ret; 06797 } 06798 06799 /** 06800 * @brief Enable pedometer algorithm.[get] 06801 * 06802 * @param ctx read / write interface definitions 06803 * @param val turn on and configure pedometer 06804 * 06805 */ 06806 int32_t lsm6dsox_pedo_sens_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t *val) 06807 { 06808 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; 06809 int32_t ret; 06810 06811 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, 06812 (uint8_t*)&pedo_cmd_reg); 06813 switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) ){ 06814 case LSM6DSOX_PEDO_BASE_MODE: 06815 *val = LSM6DSOX_PEDO_BASE_MODE; 06816 break; 06817 case LSM6DSOX_FALSE_STEP_REJ: 06818 *val = LSM6DSOX_FALSE_STEP_REJ; 06819 break; 06820 case LSM6DSOX_FALSE_STEP_REJ_ADV_MODE: 06821 *val = LSM6DSOX_FALSE_STEP_REJ_ADV_MODE; 06822 break; 06823 default: 06824 *val = LSM6DSOX_PEDO_BASE_MODE; 06825 break; 06826 } 06827 return ret; 06828 } 06829 06830 /** 06831 * @brief Interrupt status bit for step detection.[get] 06832 * 06833 * @param ctx read / write interface definitions 06834 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS 06835 * 06836 */ 06837 int32_t lsm6dsox_pedo_step_detect_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06838 { 06839 lsm6dsox_emb_func_status_t reg; 06840 int32_t ret; 06841 06842 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 06843 if (ret == 0) { 06844 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); 06845 } 06846 if (ret == 0) { 06847 *val = reg.is_step_det; 06848 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 06849 } 06850 06851 return ret; 06852 } 06853 06854 /** 06855 * @brief Pedometer debounce configuration register (r/w).[set] 06856 * 06857 * @param ctx read / write interface definitions 06858 * @param buff buffer that contains data to write 06859 * 06860 */ 06861 int32_t lsm6dsox_pedo_debounce_steps_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 06862 { 06863 int32_t ret; 06864 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff); 06865 return ret; 06866 } 06867 06868 /** 06869 * @brief Pedometer debounce configuration register (r/w).[get] 06870 * 06871 * @param ctx read / write interface definitions 06872 * @param buff buffer that stores data read 06873 * 06874 */ 06875 int32_t lsm6dsox_pedo_debounce_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 06876 { 06877 int32_t ret; 06878 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff); 06879 return ret; 06880 } 06881 06882 /** 06883 * @brief Time period register for step detection on delta time (r/w).[set] 06884 * 06885 * @param ctx read / write interface definitions 06886 * @param buff buffer that contains data to write 06887 * 06888 */ 06889 int32_t lsm6dsox_pedo_steps_period_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 06890 { 06891 int32_t ret; 06892 uint8_t index; 06893 06894 index = 0x00U; 06895 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]); 06896 if (ret == 0) { 06897 index++; 06898 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H, 06899 &buff[index]); 06900 } 06901 return ret; 06902 } 06903 06904 /** 06905 * @brief Time period register for step detection on delta time (r/w).[get] 06906 * 06907 * @param ctx read / write interface definitions 06908 * @param buff buffer that stores data read 06909 * 06910 */ 06911 int32_t lsm6dsox_pedo_steps_period_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 06912 { 06913 int32_t ret; 06914 uint8_t index; 06915 06916 index = 0x00U; 06917 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]); 06918 if (ret == 0) { 06919 index++; 06920 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H, 06921 &buff[index]); 06922 } 06923 return ret; 06924 } 06925 06926 /** 06927 * @brief Set when user wants to generate interrupt on count overflow 06928 * event/every step.[set] 06929 * 06930 * @param ctx read / write interface definitions 06931 * @param val change the values of carry_count_en in reg PEDO_CMD_REG 06932 * 06933 */ 06934 int32_t lsm6dsox_pedo_int_mode_set(lsm6dsox_ctx_t *ctx, 06935 lsm6dsox_carry_count_en_t val) 06936 { 06937 lsm6dsox_pedo_cmd_reg_t reg; 06938 int32_t ret; 06939 06940 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)®); 06941 if (ret == 0) { 06942 reg.carry_count_en = (uint8_t)val; 06943 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG, 06944 (uint8_t*)®); 06945 } 06946 return ret; 06947 } 06948 06949 /** 06950 * @brief Set when user wants to generate interrupt on count overflow 06951 * event/every step.[get] 06952 * 06953 * @param ctx read / write interface definitions 06954 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG 06955 * 06956 */ 06957 int32_t lsm6dsox_pedo_int_mode_get(lsm6dsox_ctx_t *ctx, 06958 lsm6dsox_carry_count_en_t *val) 06959 { 06960 lsm6dsox_pedo_cmd_reg_t reg; 06961 int32_t ret; 06962 06963 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)®); 06964 switch (reg.carry_count_en) { 06965 case LSM6DSOX_EVERY_STEP: 06966 *val = LSM6DSOX_EVERY_STEP; 06967 break; 06968 case LSM6DSOX_COUNT_OVERFLOW: 06969 *val = LSM6DSOX_COUNT_OVERFLOW; 06970 break; 06971 default: 06972 *val = LSM6DSOX_EVERY_STEP; 06973 break; 06974 } 06975 return ret; 06976 } 06977 06978 /** 06979 * @} 06980 * 06981 */ 06982 06983 /** 06984 * @defgroup LSM6DSOX_significant_motion 06985 * @brief This section groups all the functions that manage the 06986 * significant motion detection. 06987 * @{ 06988 * 06989 */ 06990 06991 /** 06992 * @brief Interrupt status bit for significant motion detection.[get] 06993 * 06994 * @param ctx read / write interface definitions 06995 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS 06996 * 06997 */ 06998 int32_t lsm6dsox_motion_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 06999 { 07000 lsm6dsox_emb_func_status_t reg; 07001 int32_t ret; 07002 07003 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07004 if (ret == 0) { 07005 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); 07006 } 07007 if (ret == 0) { 07008 *val = reg.is_sigmot; 07009 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07010 } 07011 07012 return ret; 07013 } 07014 07015 /** 07016 * @} 07017 * 07018 */ 07019 07020 /** 07021 * @defgroup LSM6DSOX_tilt_detection 07022 * @brief This section groups all the functions that manage the tilt 07023 * event detection. 07024 * @{ 07025 * 07026 */ 07027 07028 /** 07029 * @brief Interrupt status bit for tilt detection.[get] 07030 * 07031 * @param ctx read / write interface definitions 07032 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS 07033 * 07034 */ 07035 int32_t lsm6dsox_tilt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 07036 { 07037 lsm6dsox_emb_func_status_t reg; 07038 int32_t ret; 07039 07040 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07041 if (ret == 0) { 07042 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); 07043 } 07044 if (ret == 0) { 07045 *val = reg.is_tilt; 07046 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07047 } 07048 07049 return ret; 07050 } 07051 07052 /** 07053 * @} 07054 * 07055 */ 07056 07057 /** 07058 * @defgroup LSM6DSOX_ magnetometer_sensor 07059 * @brief This section groups all the functions that manage additional 07060 * magnetometer sensor. 07061 * @{ 07062 * 07063 */ 07064 07065 /** 07066 * @brief External magnetometer sensitivity value register for 07067 * Sensor hub.[set] 07068 * 07069 * @param ctx read / write interface definitions 07070 * @param buff buffer that contains data to write 07071 * 07072 */ 07073 int32_t lsm6dsox_sh_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07074 { 07075 int32_t ret; 07076 uint8_t index; 07077 07078 index = 0x00U; 07079 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L, 07080 &buff[index]); 07081 if (ret == 0) { 07082 index++; 07083 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H, 07084 &buff[index]); 07085 } 07086 07087 return ret; 07088 } 07089 07090 /** 07091 * @brief External magnetometer sensitivity value register for 07092 * Sensor hub.[get] 07093 * 07094 * @param ctx read / write interface definitions 07095 * @param buff buffer that stores data read 07096 * 07097 */ 07098 int32_t lsm6dsox_sh_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07099 { 07100 int32_t ret; 07101 uint8_t index; 07102 07103 index = 0x00U; 07104 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L, 07105 &buff[index]); 07106 if (ret == 0) { 07107 index++; 07108 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H, 07109 &buff[index]); 07110 } 07111 07112 return ret; 07113 } 07114 07115 /** 07116 * @brief External magnetometer sensitivity value register for 07117 * Machine Learning Core.[set] 07118 * 07119 * @param ctx read / write interface definitions 07120 * @param buff buffer that contains data to write 07121 * 07122 */ 07123 int32_t lsm6dsox_mlc_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07124 { 07125 int32_t ret; 07126 uint8_t index; 07127 07128 index = 0x00U; 07129 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L, 07130 &buff[index]); 07131 if (ret == 0) { 07132 index++; 07133 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H, 07134 &buff[index]); 07135 } 07136 return ret; 07137 } 07138 07139 /** 07140 * @brief External magnetometer sensitivity value register for 07141 * Machine Learning Core.[get] 07142 * 07143 * @param ctx read / write interface definitions 07144 * @param buff buffer that stores data read 07145 * 07146 */ 07147 int32_t lsm6dsox_mlc_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07148 { 07149 int32_t ret; 07150 uint8_t index; 07151 07152 index = 0x00U; 07153 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L, 07154 &buff[index]); 07155 if (ret == 0) { 07156 index++; 07157 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H, 07158 &buff[index]); 07159 } 07160 return ret; 07161 } 07162 07163 07164 /** 07165 * @brief Offset for hard-iron compensation register (r/w).[set] 07166 * 07167 * @param ctx read / write interface definitions 07168 * @param buff buffer that contains data to write 07169 * 07170 */ 07171 int32_t lsm6dsox_mag_offset_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07172 { 07173 int32_t ret; 07174 uint8_t index; 07175 07176 index = 0x00U; 07177 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]); 07178 if (ret == 0) { 07179 index++; 07180 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]); 07181 } 07182 if (ret == 0) { 07183 index++; 07184 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]); 07185 } 07186 if (ret == 0) { 07187 index++; 07188 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]); 07189 } 07190 if (ret == 0) { 07191 index++; 07192 07193 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]); 07194 } 07195 if (ret == 0) { 07196 index++; 07197 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]); 07198 } 07199 07200 return ret; 07201 } 07202 07203 /** 07204 * @brief Offset for hard-iron compensation register (r/w).[get] 07205 * 07206 * @param ctx read / write interface definitions 07207 * @param buff buffer that stores data read 07208 * 07209 */ 07210 int32_t lsm6dsox_mag_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07211 { 07212 int32_t ret; 07213 uint8_t index; 07214 07215 index = 0x00U; 07216 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]); 07217 if (ret == 0) { 07218 index++; 07219 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]); 07220 } 07221 if (ret == 0) { 07222 index++; 07223 07224 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]); 07225 } 07226 if (ret == 0) { 07227 index++; 07228 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]); 07229 } 07230 if (ret == 0) { 07231 index++; 07232 07233 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]); 07234 } 07235 if (ret == 0) { 07236 index++; 07237 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]); 07238 } 07239 return ret; 07240 } 07241 07242 /** 07243 * @brief Soft-iron (3x3 symmetric) matrix correction 07244 * register (r/w). The value is expressed as 07245 * half-precision floating-point format: 07246 * SEEEEEFFFFFFFFFF 07247 * S: 1 sign bit; 07248 * E: 5 exponent bits; 07249 * F: 10 fraction bits).[set] 07250 * 07251 * @param ctx read / write interface definitions 07252 * @param buff buffer that contains data to write 07253 * 07254 */ 07255 int32_t lsm6dsox_mag_soft_iron_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07256 { 07257 int32_t ret; 07258 uint8_t index; 07259 07260 index = 0x00U; 07261 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]); 07262 if (ret == 0) { 07263 index++; 07264 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]); 07265 } 07266 if (ret == 0) { 07267 index++; 07268 07269 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]); 07270 } 07271 if (ret == 0) { 07272 index++; 07273 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]); 07274 } 07275 if (ret == 0) { 07276 index++; 07277 07278 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]); 07279 } 07280 if (ret == 0) { 07281 index++; 07282 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]); 07283 } 07284 if (ret == 0) { 07285 index++; 07286 07287 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]); 07288 } 07289 if (ret == 0) { 07290 index++; 07291 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]); 07292 } 07293 if (ret == 0) { 07294 index++; 07295 07296 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]); 07297 } 07298 if (ret == 0) { 07299 index++; 07300 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]); 07301 } 07302 if (ret == 0) { 07303 index++; 07304 07305 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]); 07306 } 07307 if (ret == 0) { 07308 index++; 07309 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]); 07310 } 07311 07312 return ret; 07313 } 07314 07315 /** 07316 * @brief Soft-iron (3x3 symmetric) matrix 07317 * correction register (r/w). 07318 * The value is expressed as half-precision 07319 * floating-point format: 07320 * SEEEEEFFFFFFFFFF 07321 * S: 1 sign bit; 07322 * E: 5 exponent bits; 07323 * F: 10 fraction bits.[get] 07324 * 07325 * @param ctx read / write interface definitions 07326 * @param buff buffer that stores data read 07327 * 07328 */ 07329 int32_t lsm6dsox_mag_soft_iron_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07330 { 07331 int32_t ret; 07332 uint8_t index; 07333 07334 index = 0x00U; 07335 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]); 07336 if (ret == 0) { 07337 index++; 07338 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]); 07339 } 07340 if (ret == 0) { 07341 index++; 07342 07343 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]); 07344 } 07345 if (ret == 0) { 07346 index++; 07347 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]); 07348 } 07349 if (ret == 0) { 07350 index++; 07351 07352 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]); 07353 } 07354 if (ret == 0) { 07355 index++; 07356 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]); 07357 } 07358 if (ret == 0) { 07359 index++; 07360 07361 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]); 07362 } 07363 if (ret == 0) { 07364 index++; 07365 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]); 07366 } 07367 if (ret == 0) { 07368 index++; 07369 07370 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]); 07371 } 07372 if (ret == 0) { 07373 index++; 07374 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]); 07375 } 07376 if (ret == 0) { 07377 index++; 07378 07379 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]); 07380 } 07381 if (ret == 0) { 07382 index++; 07383 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]); 07384 } 07385 07386 return ret; 07387 } 07388 07389 /** 07390 * @brief Magnetometer Z-axis coordinates 07391 * rotation (to be aligned to 07392 * accelerometer/gyroscope axes 07393 * orientation).[set] 07394 * 07395 * @param ctx read / write interface definitions 07396 * @param val change the values of mag_z_axis in reg MAG_CFG_A 07397 * 07398 */ 07399 int32_t lsm6dsox_mag_z_orient_set(lsm6dsox_ctx_t *ctx, lsm6dsox_mag_z_axis_t val) 07400 { 07401 lsm6dsox_mag_cfg_a_t reg; 07402 int32_t ret; 07403 07404 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); 07405 if (ret == 0) { 07406 reg.mag_z_axis = (uint8_t) val; 07407 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); 07408 } 07409 07410 return ret; 07411 } 07412 07413 /** 07414 * @brief Magnetometer Z-axis coordinates 07415 * rotation (to be aligned to 07416 * accelerometer/gyroscope axes 07417 * orientation).[get] 07418 * 07419 * @param ctx read / write interface definitions 07420 * @param val Get the values of mag_z_axis in reg MAG_CFG_A 07421 * 07422 */ 07423 int32_t lsm6dsox_mag_z_orient_get(lsm6dsox_ctx_t *ctx, 07424 lsm6dsox_mag_z_axis_t *val) 07425 { 07426 lsm6dsox_mag_cfg_a_t reg; 07427 int32_t ret; 07428 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); 07429 switch (reg.mag_z_axis) { 07430 case LSM6DSOX_Z_EQ_Y: 07431 *val = LSM6DSOX_Z_EQ_Y; 07432 break; 07433 case LSM6DSOX_Z_EQ_MIN_Y: 07434 *val = LSM6DSOX_Z_EQ_MIN_Y; 07435 break; 07436 case LSM6DSOX_Z_EQ_X: 07437 *val = LSM6DSOX_Z_EQ_X; 07438 break; 07439 case LSM6DSOX_Z_EQ_MIN_X: 07440 *val = LSM6DSOX_Z_EQ_MIN_X; 07441 break; 07442 case LSM6DSOX_Z_EQ_MIN_Z: 07443 *val = LSM6DSOX_Z_EQ_MIN_Z; 07444 break; 07445 case LSM6DSOX_Z_EQ_Z: 07446 *val = LSM6DSOX_Z_EQ_Z; 07447 break; 07448 default: 07449 *val = LSM6DSOX_Z_EQ_Y; 07450 break; 07451 } 07452 return ret; 07453 } 07454 07455 /** 07456 * @brief Magnetometer Y-axis coordinates 07457 * rotation (to be aligned to 07458 * accelerometer/gyroscope axes 07459 * orientation).[set] 07460 * 07461 * @param ctx read / write interface definitions 07462 * @param val change the values of mag_y_axis in reg MAG_CFG_A 07463 * 07464 */ 07465 int32_t lsm6dsox_mag_y_orient_set(lsm6dsox_ctx_t *ctx, 07466 lsm6dsox_mag_y_axis_t val) 07467 { 07468 lsm6dsox_mag_cfg_a_t reg; 07469 int32_t ret; 07470 07471 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); 07472 if (ret == 0) { 07473 reg.mag_y_axis = (uint8_t)val; 07474 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,(uint8_t*) ®); 07475 } 07476 return ret; 07477 } 07478 07479 /** 07480 * @brief Magnetometer Y-axis coordinates 07481 * rotation (to be aligned to 07482 * accelerometer/gyroscope axes 07483 * orientation).[get] 07484 * 07485 * @param ctx read / write interface definitions 07486 * @param val Get the values of mag_y_axis in reg MAG_CFG_A 07487 * 07488 */ 07489 int32_t lsm6dsox_mag_y_orient_get(lsm6dsox_ctx_t *ctx, 07490 lsm6dsox_mag_y_axis_t *val) 07491 { 07492 lsm6dsox_mag_cfg_a_t reg; 07493 int32_t ret; 07494 07495 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); 07496 switch (reg.mag_y_axis) { 07497 case LSM6DSOX_Y_EQ_Y: 07498 *val = LSM6DSOX_Y_EQ_Y; 07499 break; 07500 case LSM6DSOX_Y_EQ_MIN_Y: 07501 *val = LSM6DSOX_Y_EQ_MIN_Y; 07502 break; 07503 case LSM6DSOX_Y_EQ_X: 07504 *val = LSM6DSOX_Y_EQ_X; 07505 break; 07506 case LSM6DSOX_Y_EQ_MIN_X: 07507 *val = LSM6DSOX_Y_EQ_MIN_X; 07508 break; 07509 case LSM6DSOX_Y_EQ_MIN_Z: 07510 *val = LSM6DSOX_Y_EQ_MIN_Z; 07511 break; 07512 case LSM6DSOX_Y_EQ_Z: 07513 *val = LSM6DSOX_Y_EQ_Z; 07514 break; 07515 default: 07516 *val = LSM6DSOX_Y_EQ_Y; 07517 break; 07518 } 07519 return ret; 07520 } 07521 07522 /** 07523 * @brief Magnetometer X-axis coordinates 07524 * rotation (to be aligned to 07525 * accelerometer/gyroscope axes 07526 * orientation).[set] 07527 * 07528 * @param ctx read / write interface definitions 07529 * @param val change the values of mag_x_axis in reg MAG_CFG_B 07530 * 07531 */ 07532 int32_t lsm6dsox_mag_x_orient_set(lsm6dsox_ctx_t *ctx, 07533 lsm6dsox_mag_x_axis_t val) 07534 { 07535 lsm6dsox_mag_cfg_b_t reg; 07536 int32_t ret; 07537 07538 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®); 07539 if (ret == 0) { 07540 reg.mag_x_axis = (uint8_t)val; 07541 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®); 07542 } 07543 return ret; 07544 } 07545 07546 /** 07547 * @brief Magnetometer X-axis coordinates 07548 * rotation (to be aligned to 07549 * accelerometer/gyroscope axes 07550 * orientation).[get] 07551 * 07552 * @param ctx read / write interface definitions 07553 * @param val Get the values of mag_x_axis in reg MAG_CFG_B 07554 * 07555 */ 07556 int32_t lsm6dsox_mag_x_orient_get(lsm6dsox_ctx_t *ctx, 07557 lsm6dsox_mag_x_axis_t *val) 07558 { 07559 lsm6dsox_mag_cfg_b_t reg; 07560 int32_t ret; 07561 07562 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®); 07563 switch (reg.mag_x_axis) { 07564 case LSM6DSOX_X_EQ_Y: 07565 *val = LSM6DSOX_X_EQ_Y; 07566 break; 07567 case LSM6DSOX_X_EQ_MIN_Y: 07568 *val = LSM6DSOX_X_EQ_MIN_Y; 07569 break; 07570 case LSM6DSOX_X_EQ_X: 07571 *val = LSM6DSOX_X_EQ_X; 07572 break; 07573 case LSM6DSOX_X_EQ_MIN_X: 07574 *val = LSM6DSOX_X_EQ_MIN_X; 07575 break; 07576 case LSM6DSOX_X_EQ_MIN_Z: 07577 *val = LSM6DSOX_X_EQ_MIN_Z; 07578 break; 07579 case LSM6DSOX_X_EQ_Z: 07580 *val = LSM6DSOX_X_EQ_Z; 07581 break; 07582 default: 07583 *val = LSM6DSOX_X_EQ_Y; 07584 break; 07585 } 07586 return ret; 07587 } 07588 07589 /** 07590 * @} 07591 * 07592 */ 07593 07594 /** 07595 * @defgroup LSM6DSOX_finite_state_machine 07596 * @brief This section groups all the functions that manage the 07597 * state_machine. 07598 * @{ 07599 * 07600 */ 07601 07602 /** 07603 * @brief Interrupt status bit for FSM long counter 07604 * timeout interrupt event.[get] 07605 * 07606 * @param ctx read / write interface definitions 07607 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS 07608 * 07609 */ 07610 int32_t lsm6dsox_long_cnt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 07611 { 07612 lsm6dsox_emb_func_status_t reg; 07613 int32_t ret; 07614 07615 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07616 if (ret == 0) { 07617 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); 07618 } 07619 if (ret == 0) { 07620 *val = reg.is_fsm_lc; 07621 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07622 } 07623 return ret; 07624 } 07625 07626 /** 07627 * @brief Finite State Machine enable.[set] 07628 * 07629 * @param ctx read / write interface definitions 07630 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B 07631 * 07632 */ 07633 int32_t lsm6dsox_fsm_enable_set(lsm6dsox_ctx_t *ctx, 07634 lsm6dsox_emb_fsm_enable_t *val) 07635 { 07636 int32_t ret; 07637 07638 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07639 if (ret == 0) { 07640 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_A, 07641 (uint8_t*)&val->fsm_enable_a, 1); 07642 } 07643 if (ret == 0) { 07644 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_B, 07645 (uint8_t*)&val->fsm_enable_b, 1); 07646 } 07647 if (ret == 0) { 07648 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07649 } 07650 07651 return ret; 07652 } 07653 07654 /** 07655 * @brief Finite State Machine enable.[get] 07656 * 07657 * @param ctx read / write interface definitions 07658 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B 07659 * 07660 */ 07661 int32_t lsm6dsox_fsm_enable_get(lsm6dsox_ctx_t *ctx, 07662 lsm6dsox_emb_fsm_enable_t *val) 07663 { 07664 int32_t ret; 07665 07666 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07667 if (ret == 0) { 07668 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t*) val, 2); 07669 } 07670 if (ret == 0) { 07671 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07672 } 07673 return ret; 07674 } 07675 07676 /** 07677 * @brief FSM long counter status register. Long counter value is an 07678 * unsigned integer value (16-bit format).[set] 07679 * 07680 * @param ctx read / write interface definitions 07681 * @param buff buffer that contains data to write 07682 * 07683 */ 07684 int32_t lsm6dsox_long_cnt_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07685 { 07686 int32_t ret; 07687 07688 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07689 if (ret == 0) { 07690 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2); 07691 } 07692 if (ret == 0) { 07693 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07694 } 07695 07696 return ret; 07697 } 07698 07699 /** 07700 * @brief FSM long counter status register. Long counter value is an 07701 * unsigned integer value (16-bit format).[get] 07702 * 07703 * @param ctx read / write interface definitions 07704 * @param buff buffer that stores data read 07705 * 07706 */ 07707 int32_t lsm6dsox_long_cnt_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) 07708 { 07709 int32_t ret; 07710 07711 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07712 if (ret == 0) { 07713 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2); 07714 } 07715 if (ret == 0) { 07716 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07717 } 07718 07719 return ret; 07720 } 07721 07722 /** 07723 * @brief Clear FSM long counter value.[set] 07724 * 07725 * @param ctx read / write interface definitions 07726 * @param val change the values of fsm_lc_clr in 07727 * reg FSM_LONG_COUNTER_CLEAR 07728 * 07729 */ 07730 int32_t lsm6dsox_long_clr_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val) 07731 { 07732 lsm6dsox_fsm_long_counter_clear_t reg; 07733 int32_t ret; 07734 07735 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07736 if (ret == 0) { 07737 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR, 07738 (uint8_t*)®, 1); 07739 } 07740 if (ret == 0) { 07741 reg. fsm_lc_clr = (uint8_t)val; 07742 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR, 07743 (uint8_t*)®, 1); 07744 } 07745 if (ret == 0) { 07746 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07747 } 07748 return ret; 07749 } 07750 07751 /** 07752 * @brief Clear FSM long counter value.[get] 07753 * 07754 * @param ctx read / write interface definitions 07755 * @param val Get the values of fsm_lc_clr in 07756 * reg FSM_LONG_COUNTER_CLEAR 07757 * 07758 */ 07759 int32_t lsm6dsox_long_clr_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val) 07760 { 07761 lsm6dsox_fsm_long_counter_clear_t reg; 07762 int32_t ret; 07763 07764 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07765 if (ret == 0) { 07766 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR, 07767 (uint8_t*)®, 1); 07768 } 07769 if (ret == 0) { 07770 switch (reg.fsm_lc_clr) { 07771 case LSM6DSOX_LC_NORMAL: 07772 *val = LSM6DSOX_LC_NORMAL; 07773 break; 07774 case LSM6DSOX_LC_CLEAR: 07775 *val = LSM6DSOX_LC_CLEAR; 07776 break; 07777 case LSM6DSOX_LC_CLEAR_DONE: 07778 *val = LSM6DSOX_LC_CLEAR_DONE; 07779 break; 07780 default: 07781 *val = LSM6DSOX_LC_NORMAL; 07782 break; 07783 } 07784 } 07785 07786 if (ret == 0) { 07787 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07788 } 07789 07790 return ret; 07791 } 07792 07793 /** 07794 * @brief FSM output registers[get] 07795 * 07796 * @param ctx read / write interface definitions 07797 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16 07798 * 07799 */ 07800 int32_t lsm6dsox_fsm_out_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_out_t *val) 07801 { 07802 int32_t ret; 07803 07804 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07805 if (ret == 0) { 07806 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t*)val, 16); 07807 } 07808 if (ret == 0) { 07809 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07810 } 07811 07812 return ret; 07813 } 07814 07815 /** 07816 * @brief Finite State Machine ODR configuration.[set] 07817 * 07818 * @param ctx read / write interface definitions 07819 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B 07820 * 07821 */ 07822 int32_t lsm6dsox_fsm_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t val) 07823 { 07824 lsm6dsox_emb_func_odr_cfg_b_t reg; 07825 int32_t ret; 07826 07827 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07828 if (ret == 0) { 07829 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, 07830 (uint8_t*)®, 1); 07831 } 07832 if (ret == 0) { 07833 reg.not_used_01 = 3; /* set default values */ 07834 reg.not_used_02 = 2; /* set default values */ 07835 reg.fsm_odr = (uint8_t)val; 07836 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, 07837 (uint8_t*)®, 1); 07838 } 07839 if (ret == 0) { 07840 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07841 } 07842 return ret; 07843 } 07844 07845 /** 07846 * @brief Finite State Machine ODR configuration.[get] 07847 * 07848 * @param ctx read / write interface definitions 07849 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B 07850 * 07851 */ 07852 int32_t lsm6dsox_fsm_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t *val) 07853 { 07854 lsm6dsox_emb_func_odr_cfg_b_t reg; 07855 int32_t ret; 07856 07857 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07858 if (ret == 0) { 07859 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, 07860 (uint8_t*)®, 1); 07861 } 07862 if (ret == 0) { 07863 switch (reg.fsm_odr) { 07864 case LSM6DSOX_ODR_FSM_12Hz5: 07865 *val = LSM6DSOX_ODR_FSM_12Hz5; 07866 break; 07867 case LSM6DSOX_ODR_FSM_26Hz: 07868 *val = LSM6DSOX_ODR_FSM_26Hz; 07869 break; 07870 case LSM6DSOX_ODR_FSM_52Hz: 07871 *val = LSM6DSOX_ODR_FSM_52Hz; 07872 break; 07873 case LSM6DSOX_ODR_FSM_104Hz: 07874 *val = LSM6DSOX_ODR_FSM_104Hz; 07875 break; 07876 default: 07877 *val = LSM6DSOX_ODR_FSM_12Hz5; 07878 break; 07879 } 07880 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07881 } 07882 07883 return ret; 07884 } 07885 07886 /** 07887 * @brief FSM initialization request.[set] 07888 * 07889 * @param ctx read / write interface definitions 07890 * @param val change the values of fsm_init in reg FSM_INIT 07891 * 07892 */ 07893 int32_t lsm6dsox_fsm_init_set(lsm6dsox_ctx_t *ctx, uint8_t val) 07894 { 07895 lsm6dsox_emb_func_init_b_t reg; 07896 int32_t ret; 07897 07898 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07899 if (ret == 0) { 07900 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 07901 } 07902 if (ret == 0) { 07903 reg.fsm_init = val; 07904 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 07905 } 07906 if (ret == 0) { 07907 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07908 } 07909 07910 return ret; 07911 } 07912 07913 /** 07914 * @brief FSM initialization request.[get] 07915 * 07916 * @param ctx read / write interface definitions 07917 * @param val change the values of fsm_init in reg FSM_INIT 07918 * 07919 */ 07920 int32_t lsm6dsox_fsm_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 07921 { 07922 lsm6dsox_emb_func_init_b_t reg; 07923 int32_t ret; 07924 07925 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 07926 if (ret == 0) { 07927 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 07928 } 07929 if (ret == 0) { 07930 *val = reg.fsm_init; 07931 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 07932 } 07933 return ret; 07934 } 07935 07936 /** 07937 * @brief FSM long counter timeout register (r/w). The long counter 07938 * timeout value is an unsigned integer value (16-bit format). 07939 * When the long counter value reached this value, 07940 * the FSM generates an interrupt.[set] 07941 * 07942 * @param ctx read / write interface definitions 07943 * @param val the value of long counter 07944 * 07945 */ 07946 int32_t lsm6dsox_long_cnt_int_value_set(lsm6dsox_ctx_t *ctx, uint16_t val) 07947 { 07948 int32_t ret; 07949 uint8_t add_l; 07950 uint8_t add_h; 07951 07952 add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 ); 07953 add_l = (uint8_t)( val & 0x00FFU ); 07954 07955 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l); 07956 if (ret == 0) { 07957 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h); 07958 } 07959 07960 return ret; 07961 } 07962 07963 /** 07964 * @brief FSM long counter timeout register (r/w). The long counter 07965 * timeout value is an unsigned integer value (16-bit format). 07966 * When the long counter value reached this value, 07967 * the FSM generates an interrupt.[get] 07968 * 07969 * @param ctx read / write interface definitions 07970 * @param val buffer that stores the value of long counter 07971 * 07972 */ 07973 int32_t lsm6dsox_long_cnt_int_value_get(lsm6dsox_ctx_t *ctx, uint16_t *val) 07974 { 07975 int32_t ret; 07976 uint8_t add_l; 07977 uint8_t add_h; 07978 07979 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l); 07980 if (ret == 0) { 07981 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h); 07982 *val = add_h; 07983 *val = *val << 8; 07984 *val += add_l; 07985 } 07986 07987 return ret; 07988 } 07989 07990 /** 07991 * @brief FSM number of programs register.[set] 07992 * 07993 * @param ctx read / write interface definitions 07994 * @param val value to write 07995 * 07996 */ 07997 int32_t lsm6dsox_fsm_number_of_programs_set(lsm6dsox_ctx_t *ctx, uint8_t val) 07998 { 07999 int32_t ret; 08000 08001 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_PROGRAMS, &val); 08002 08003 return ret; 08004 } 08005 08006 /** 08007 * @brief FSM number of programs register.[get] 08008 * 08009 * @param ctx read / write interface definitions 08010 * @param val buffer that stores data read. 08011 * 08012 */ 08013 int32_t lsm6dsox_fsm_number_of_programs_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 08014 { 08015 int32_t ret; 08016 08017 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_PROGRAMS, val); 08018 08019 return ret; 08020 } 08021 08022 /** 08023 * @brief FSM start address register (r/w). 08024 * First available address is 0x033C.[set] 08025 * 08026 * @param ctx read / write interface definitions 08027 * @param val the value of start address 08028 * 08029 */ 08030 int32_t lsm6dsox_fsm_start_address_set(lsm6dsox_ctx_t *ctx, uint16_t val) 08031 { 08032 int32_t ret; 08033 uint8_t add_l; 08034 uint8_t add_h; 08035 08036 add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 ); 08037 add_l = (uint8_t)( val & 0x00FFU ); 08038 08039 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l); 08040 if (ret == 0) { 08041 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h); 08042 } 08043 return ret; 08044 } 08045 08046 /** 08047 * @brief FSM start address register (r/w). 08048 * First available address is 0x033C.[get] 08049 * 08050 * @param ctx read / write interface definitions 08051 * @param val buffer the value of start address. 08052 * 08053 */ 08054 int32_t lsm6dsox_fsm_start_address_get(lsm6dsox_ctx_t *ctx, uint16_t *val) 08055 { 08056 int32_t ret; 08057 uint8_t add_l; 08058 uint8_t add_h; 08059 08060 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l); 08061 if (ret == 0) { 08062 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h); 08063 *val = add_h; 08064 *val = *val << 8; 08065 *val += add_l; 08066 } 08067 return ret; 08068 } 08069 08070 /** 08071 * @} 08072 * 08073 */ 08074 08075 /** 08076 * @addtogroup Machine Learning Core 08077 * @brief This section group all the functions concerning the 08078 * usage of Machine Learning Core 08079 * @{ 08080 * 08081 */ 08082 08083 /** 08084 * @brief Machine Learning Core status register[get] 08085 * 08086 * @param ctx read / write interface definitions 08087 * @param val register MLC_STATUS_MAINPAGE 08088 * 08089 */ 08090 int32_t lsm6dsox_mlc_status_get(lsm6dsox_ctx_t *ctx, 08091 lsm6dsox_mlc_status_mainpage_t *val) 08092 { 08093 return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE, 08094 (uint8_t*) val, 1); 08095 } 08096 08097 /** 08098 * @brief Machine Learning Core data rate selection.[set] 08099 * 08100 * @param ctx read / write interface definitions 08101 * @param val get the values of mlc_odr in 08102 * reg EMB_FUNC_ODR_CFG_C 08103 * 08104 */ 08105 int32_t lsm6dsox_mlc_data_rate_set(lsm6dsox_ctx_t *ctx, 08106 lsm6dsox_mlc_odr_t val) 08107 { 08108 lsm6dsox_emb_func_odr_cfg_c_t reg; 08109 int32_t ret; 08110 08111 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 08112 if (ret == 0) { 08113 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, 08114 (uint8_t*)®, 1); 08115 } 08116 if (ret == 0) { 08117 reg.mlc_odr = (uint8_t)val; 08118 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, (uint8_t*)®, 1); 08119 } 08120 if (ret == 0) { 08121 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08122 } 08123 08124 return ret; 08125 } 08126 08127 /** 08128 * @brief Machine Learning Core data rate selection.[get] 08129 * 08130 * @param ctx read / write interface definitions 08131 * @param val change the values of mlc_odr in 08132 * reg EMB_FUNC_ODR_CFG_C 08133 * 08134 */ 08135 int32_t lsm6dsox_mlc_data_rate_get(lsm6dsox_ctx_t *ctx, 08136 lsm6dsox_mlc_odr_t *val) 08137 { 08138 lsm6dsox_emb_func_odr_cfg_c_t reg; 08139 int32_t ret; 08140 08141 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 08142 if (ret == 0) { 08143 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, 08144 (uint8_t*)®, 1); 08145 } 08146 if (ret == 0) { 08147 switch (reg.mlc_odr) { 08148 case LSM6DSOX_ODR_PRGS_12Hz5: 08149 *val = LSM6DSOX_ODR_PRGS_12Hz5; 08150 break; 08151 case LSM6DSOX_ODR_PRGS_26Hz: 08152 *val = LSM6DSOX_ODR_PRGS_26Hz; 08153 break; 08154 case LSM6DSOX_ODR_PRGS_52Hz: 08155 *val = LSM6DSOX_ODR_PRGS_52Hz; 08156 break; 08157 case LSM6DSOX_ODR_PRGS_104Hz: 08158 *val = LSM6DSOX_ODR_PRGS_104Hz; 08159 break; 08160 default: 08161 *val = LSM6DSOX_ODR_PRGS_12Hz5; 08162 break; 08163 } 08164 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08165 } 08166 return ret; 08167 } 08168 08169 /** 08170 * @} 08171 * 08172 */ 08173 08174 /** 08175 * @defgroup LSM6DSOX_Sensor_hub 08176 * @brief This section groups all the functions that manage the 08177 * sensor hub. 08178 * @{ 08179 * 08180 */ 08181 08182 /** 08183 * @brief Sensor hub output registers.[get] 08184 * 08185 * @param ctx read / write interface definitions 08186 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18 08187 * 08188 */ 08189 int32_t lsm6dsox_sh_read_data_raw_get(lsm6dsox_ctx_t *ctx, 08190 lsm6dsox_emb_sh_read_t *val, 08191 uint8_t len) 08192 { 08193 int32_t ret; 08194 08195 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08196 if (ret == 0) { 08197 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t*) val, len); 08198 } 08199 if (ret == 0) { 08200 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08201 } 08202 08203 return ret; 08204 } 08205 08206 /** 08207 * @brief Number of external sensors to be read by the sensor hub.[set] 08208 * 08209 * @param ctx read / write interface definitions 08210 * @param val change the values of aux_sens_on in reg MASTER_CONFIG 08211 * 08212 */ 08213 int32_t lsm6dsox_sh_slave_connected_set(lsm6dsox_ctx_t *ctx, 08214 lsm6dsox_aux_sens_on_t val) 08215 { 08216 lsm6dsox_master_config_t reg; 08217 int32_t ret; 08218 08219 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08220 if (ret == 0) { 08221 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08222 } 08223 if (ret == 0) { 08224 reg.aux_sens_on = (uint8_t)val; 08225 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08226 } 08227 if (ret == 0) { 08228 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08229 } 08230 return ret; 08231 } 08232 08233 /** 08234 * @brief Number of external sensors to be read by the sensor hub.[get] 08235 * 08236 * @param ctx read / write interface definitions 08237 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG 08238 * 08239 */ 08240 int32_t lsm6dsox_sh_slave_connected_get(lsm6dsox_ctx_t *ctx, 08241 lsm6dsox_aux_sens_on_t *val) 08242 { 08243 lsm6dsox_master_config_t reg; 08244 int32_t ret; 08245 08246 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08247 if (ret == 0) { 08248 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08249 } 08250 if (ret == 0) { 08251 switch (reg.aux_sens_on) { 08252 case LSM6DSOX_SLV_0: 08253 *val = LSM6DSOX_SLV_0; 08254 break; 08255 case LSM6DSOX_SLV_0_1: 08256 *val = LSM6DSOX_SLV_0_1; 08257 break; 08258 case LSM6DSOX_SLV_0_1_2: 08259 *val = LSM6DSOX_SLV_0_1_2; 08260 break; 08261 case LSM6DSOX_SLV_0_1_2_3: 08262 *val = LSM6DSOX_SLV_0_1_2_3; 08263 break; 08264 default: 08265 *val = LSM6DSOX_SLV_0; 08266 break; 08267 } 08268 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08269 } 08270 08271 return ret; 08272 } 08273 08274 /** 08275 * @brief Sensor hub I2C master enable.[set] 08276 * 08277 * @param ctx read / write interface definitions 08278 * @param val change the values of master_on in reg MASTER_CONFIG 08279 * 08280 */ 08281 int32_t lsm6dsox_sh_master_set(lsm6dsox_ctx_t *ctx, uint8_t val) 08282 { 08283 lsm6dsox_master_config_t reg; 08284 int32_t ret; 08285 08286 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08287 if (ret == 0) { 08288 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08289 } 08290 if (ret == 0) { 08291 reg.master_on = val; 08292 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08293 } 08294 if (ret == 0) { 08295 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08296 } 08297 return ret; 08298 } 08299 08300 /** 08301 * @brief Sensor hub I2C master enable.[get] 08302 * 08303 * @param ctx read / write interface definitions 08304 * @param val change the values of master_on in reg MASTER_CONFIG 08305 * 08306 */ 08307 int32_t lsm6dsox_sh_master_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 08308 { 08309 lsm6dsox_master_config_t reg; 08310 int32_t ret; 08311 08312 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08313 if (ret == 0) { 08314 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08315 } 08316 if (ret == 0) { 08317 *val = reg.master_on; 08318 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08319 } 08320 08321 return ret; 08322 } 08323 08324 /** 08325 * @brief Master I2C pull-up enable.[set] 08326 * 08327 * @param ctx read / write interface definitions 08328 * @param val change the values of shub_pu_en in reg MASTER_CONFIG 08329 * 08330 */ 08331 int32_t lsm6dsox_sh_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t val) 08332 { 08333 lsm6dsox_master_config_t reg; 08334 int32_t ret; 08335 08336 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08337 if (ret == 0) { 08338 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08339 } 08340 if (ret == 0) { 08341 reg.shub_pu_en = (uint8_t)val; 08342 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08343 } 08344 if (ret == 0) { 08345 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08346 } 08347 08348 return ret; 08349 } 08350 08351 /** 08352 * @brief Master I2C pull-up enable.[get] 08353 * 08354 * @param ctx read / write interface definitions 08355 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG 08356 * 08357 */ 08358 int32_t lsm6dsox_sh_pin_mode_get(lsm6dsox_ctx_t *ctx, 08359 lsm6dsox_shub_pu_en_t *val) 08360 { 08361 lsm6dsox_master_config_t reg; 08362 int32_t ret; 08363 08364 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08365 if (ret == 0) { 08366 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08367 } 08368 if (ret == 0) { 08369 switch (reg.shub_pu_en) { 08370 case LSM6DSOX_EXT_PULL_UP: 08371 *val = LSM6DSOX_EXT_PULL_UP; 08372 break; 08373 case LSM6DSOX_INTERNAL_PULL_UP: 08374 *val = LSM6DSOX_INTERNAL_PULL_UP; 08375 break; 08376 default: 08377 *val = LSM6DSOX_EXT_PULL_UP; 08378 break; 08379 } 08380 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08381 } 08382 08383 return ret; 08384 } 08385 08386 /** 08387 * @brief I2C interface pass-through.[set] 08388 * 08389 * @param ctx read / write interface definitions 08390 * @param val change the values of pass_through_mode in 08391 * reg MASTER_CONFIG 08392 * 08393 */ 08394 int32_t lsm6dsox_sh_pass_through_set(lsm6dsox_ctx_t *ctx, uint8_t val) 08395 { 08396 lsm6dsox_master_config_t reg; 08397 int32_t ret; 08398 08399 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08400 if (ret == 0) { 08401 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08402 } 08403 if (ret == 0) { 08404 reg.pass_through_mode = val; 08405 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08406 } 08407 if (ret == 0) { 08408 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08409 } 08410 08411 return ret; 08412 } 08413 08414 /** 08415 * @brief I2C interface pass-through.[get] 08416 * 08417 * @param ctx read / write interface definitions 08418 * @param val change the values of pass_through_mode in 08419 * reg MASTER_CONFIG 08420 * 08421 */ 08422 int32_t lsm6dsox_sh_pass_through_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 08423 { 08424 lsm6dsox_master_config_t reg; 08425 int32_t ret; 08426 08427 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08428 if (ret == 0) { 08429 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08430 } 08431 if (ret == 0) { 08432 *val = reg.pass_through_mode; 08433 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08434 } 08435 08436 return ret; 08437 } 08438 08439 /** 08440 * @brief Sensor hub trigger signal selection.[set] 08441 * 08442 * @param ctx read / write interface definitions 08443 * @param val change the values of start_config in reg MASTER_CONFIG 08444 * 08445 */ 08446 int32_t lsm6dsox_sh_syncro_mode_set(lsm6dsox_ctx_t *ctx, 08447 lsm6dsox_start_config_t val) 08448 { 08449 lsm6dsox_master_config_t reg; 08450 int32_t ret; 08451 08452 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08453 if (ret == 0) { 08454 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08455 } 08456 if (ret == 0) { 08457 reg.start_config = (uint8_t)val; 08458 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08459 } 08460 if (ret == 0) { 08461 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08462 } 08463 08464 return ret; 08465 } 08466 08467 /** 08468 * @brief Sensor hub trigger signal selection.[get] 08469 * 08470 * @param ctx read / write interface definitions 08471 * @param val Get the values of start_config in reg MASTER_CONFIG 08472 * 08473 */ 08474 int32_t lsm6dsox_sh_syncro_mode_get(lsm6dsox_ctx_t *ctx, 08475 lsm6dsox_start_config_t *val) 08476 { 08477 lsm6dsox_master_config_t reg; 08478 int32_t ret; 08479 08480 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08481 if (ret == 0) { 08482 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08483 } 08484 if (ret == 0) { 08485 switch (reg.start_config) { 08486 case LSM6DSOX_EXT_ON_INT2_PIN: 08487 *val = LSM6DSOX_EXT_ON_INT2_PIN; 08488 break; 08489 case LSM6DSOX_XL_GY_DRDY: 08490 *val = LSM6DSOX_XL_GY_DRDY; 08491 break; 08492 default: 08493 *val = LSM6DSOX_EXT_ON_INT2_PIN; 08494 break; 08495 } 08496 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08497 } 08498 return ret; 08499 } 08500 08501 /** 08502 * @brief Slave 0 write operation is performed only at the first 08503 * sensor hub cycle.[set] 08504 * 08505 * @param ctx read / write interface definitions 08506 * @param val change the values of write_once in reg MASTER_CONFIG 08507 * 08508 */ 08509 int32_t lsm6dsox_sh_write_mode_set(lsm6dsox_ctx_t *ctx, 08510 lsm6dsox_write_once_t val) 08511 { 08512 lsm6dsox_master_config_t reg; 08513 int32_t ret; 08514 08515 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08516 if (ret == 0) { 08517 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08518 } 08519 if (ret == 0) { 08520 reg.write_once = (uint8_t)val; 08521 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08522 } 08523 if (ret == 0) { 08524 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08525 } 08526 08527 return ret; 08528 } 08529 08530 /** 08531 * @brief Slave 0 write operation is performed only at the first sensor 08532 * hub cycle.[get] 08533 * 08534 * @param ctx read / write interface definitions 08535 * @param val Get the values of write_once in reg MASTER_CONFIG 08536 * 08537 */ 08538 int32_t lsm6dsox_sh_write_mode_get(lsm6dsox_ctx_t *ctx, 08539 lsm6dsox_write_once_t *val) 08540 { 08541 lsm6dsox_master_config_t reg; 08542 int32_t ret; 08543 08544 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08545 if (ret == 0) { 08546 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08547 } 08548 if (ret == 0) { 08549 switch (reg.write_once) { 08550 case LSM6DSOX_EACH_SH_CYCLE: 08551 *val = LSM6DSOX_EACH_SH_CYCLE; 08552 break; 08553 case LSM6DSOX_ONLY_FIRST_CYCLE: 08554 *val = LSM6DSOX_ONLY_FIRST_CYCLE; 08555 break; 08556 default: 08557 *val = LSM6DSOX_EACH_SH_CYCLE; 08558 break; 08559 } 08560 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08561 } 08562 08563 return ret; 08564 } 08565 08566 /** 08567 * @brief Reset Master logic and output registers.[set] 08568 * 08569 * @param ctx read / write interface definitions 08570 * 08571 */ 08572 int32_t lsm6dsox_sh_reset_set(lsm6dsox_ctx_t *ctx) 08573 { 08574 lsm6dsox_master_config_t reg; 08575 int32_t ret; 08576 08577 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08578 if (ret == 0) { 08579 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08580 } 08581 if (ret == 0) { 08582 reg.rst_master_regs = PROPERTY_ENABLE; 08583 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08584 } 08585 if (ret == 0) { 08586 reg.rst_master_regs = PROPERTY_DISABLE; 08587 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08588 } 08589 if (ret == 0) { 08590 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08591 } 08592 08593 return ret; 08594 } 08595 08596 /** 08597 * @brief Reset Master logic and output registers.[get] 08598 * 08599 * @param ctx read / write interface definitions 08600 * @param val change the values of rst_master_regs in reg MASTER_CONFIG 08601 * 08602 */ 08603 int32_t lsm6dsox_sh_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 08604 { 08605 lsm6dsox_master_config_t reg; 08606 int32_t ret; 08607 08608 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08609 if (ret == 0) { 08610 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); 08611 } 08612 if (ret == 0) { 08613 *val = reg.rst_master_regs; 08614 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08615 } 08616 return ret; 08617 } 08618 08619 /** 08620 * @brief Rate at which the master communicates.[set] 08621 * 08622 * @param ctx read / write interface definitions 08623 * @param val change the values of shub_odr in reg slv1_CONFIG 08624 * 08625 */ 08626 int32_t lsm6dsox_sh_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t val) 08627 { 08628 lsm6dsox_slv0_config_t reg; 08629 int32_t ret; 08630 08631 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08632 if (ret == 0) { 08633 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); 08634 } 08635 if (ret == 0) { 08636 reg.shub_odr = (uint8_t)val; 08637 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); 08638 } 08639 if (ret == 0) { 08640 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08641 } 08642 08643 return ret; 08644 } 08645 08646 /** 08647 * @brief Rate at which the master communicates.[get] 08648 * 08649 * @param ctx read / write interface definitions 08650 * @param val Get the values of shub_odr in reg slv1_CONFIG 08651 * 08652 */ 08653 int32_t lsm6dsox_sh_data_rate_get(lsm6dsox_ctx_t *ctx, 08654 lsm6dsox_shub_odr_t *val) 08655 { 08656 lsm6dsox_slv0_config_t reg; 08657 int32_t ret; 08658 08659 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08660 if (ret == 0) { 08661 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); 08662 } 08663 if (ret == 0) { 08664 switch (reg.shub_odr) { 08665 case LSM6DSOX_SH_ODR_104Hz: 08666 *val = LSM6DSOX_SH_ODR_104Hz; 08667 break; 08668 case LSM6DSOX_SH_ODR_52Hz: 08669 *val = LSM6DSOX_SH_ODR_52Hz; 08670 break; 08671 case LSM6DSOX_SH_ODR_26Hz: 08672 *val = LSM6DSOX_SH_ODR_26Hz; 08673 break; 08674 case LSM6DSOX_SH_ODR_13Hz: 08675 *val = LSM6DSOX_SH_ODR_13Hz; 08676 break; 08677 default: 08678 *val = LSM6DSOX_SH_ODR_104Hz; 08679 break; 08680 } 08681 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08682 } 08683 08684 return ret; 08685 } 08686 08687 /** 08688 * @brief Configure slave 0 for perform a write.[set] 08689 * 08690 * @param ctx read / write interface definitions 08691 * @param val a structure that contain 08692 * - uint8_t slv1_add; 8 bit i2c device address 08693 * - uint8_t slv1_subadd; 8 bit register device address 08694 * - uint8_t slv1_data; 8 bit data to write 08695 * 08696 */ 08697 int32_t lsm6dsox_sh_cfg_write(lsm6dsox_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val) 08698 { 08699 lsm6dsox_slv0_add_t reg; 08700 int32_t ret; 08701 08702 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08703 if (ret == 0) { 08704 reg.slave0 = val->slv0_add; 08705 reg.rw_0 = 0; 08706 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)®, 1); 08707 } 08708 if (ret == 0) { 08709 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD, 08710 &(val->slv0_subadd), 1); 08711 } 08712 if (ret == 0) { 08713 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_DATAWRITE_SLV0, 08714 &(val->slv0_data), 1); 08715 } 08716 if (ret == 0) { 08717 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08718 } 08719 return ret; 08720 } 08721 08722 /** 08723 * @brief Configure slave 0 for perform a read.[set] 08724 * 08725 * @param ctx read / write interface definitions 08726 * @param val Structure that contain 08727 * - uint8_t slv1_add; 8 bit i2c device address 08728 * - uint8_t slv1_subadd; 8 bit register device address 08729 * - uint8_t slv1_len; num of bit to read 08730 * 08731 */ 08732 int32_t lsm6dsox_sh_slv0_cfg_read(lsm6dsox_ctx_t *ctx, 08733 lsm6dsox_sh_cfg_read_t *val) 08734 { 08735 lsm6dsox_slv0_add_t slv0_add; 08736 lsm6dsox_slv0_config_t slv0_config; 08737 int32_t ret; 08738 08739 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08740 if (ret == 0) { 08741 slv0_add.slave0 = val->slv_add; 08742 slv0_add.rw_0 = 1; 08743 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&slv0_add, 1); 08744 } 08745 if (ret == 0) { 08746 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD, 08747 &(val->slv_subadd), 1); 08748 } 08749 if (ret == 0) { 08750 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, 08751 (uint8_t*)&slv0_config, 1); 08752 } 08753 if (ret == 0) { 08754 slv0_config.slave0_numop = val->slv_len; 08755 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, 08756 (uint8_t*)&slv0_config, 1); 08757 } 08758 if (ret == 0) { 08759 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08760 } 08761 08762 return ret; 08763 } 08764 08765 /** 08766 * @brief Configure slave 0 for perform a write/read.[set] 08767 * 08768 * @param ctx read / write interface definitions 08769 * @param val Structure that contain 08770 * - uint8_t slv1_add; 8 bit i2c device address 08771 * - uint8_t slv1_subadd; 8 bit register device address 08772 * - uint8_t slv1_len; num of bit to read 08773 * 08774 */ 08775 int32_t lsm6dsox_sh_slv1_cfg_read(lsm6dsox_ctx_t *ctx, 08776 lsm6dsox_sh_cfg_read_t *val) 08777 { 08778 lsm6dsox_slv1_add_t slv1_add; 08779 lsm6dsox_slv1_config_t slv1_config; 08780 int32_t ret; 08781 08782 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08783 if (ret == 0) { 08784 slv1_add.slave1_add = val->slv_add; 08785 slv1_add.r_1 = 1; 08786 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t*)&slv1_add, 1); 08787 } 08788 if (ret == 0) { 08789 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_SUBADD, 08790 &(val->slv_subadd), 1); 08791 } 08792 if (ret == 0) { 08793 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, 08794 (uint8_t*)&slv1_config, 1); 08795 } 08796 if (ret == 0) { 08797 slv1_config.slave1_numop = val->slv_len; 08798 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, 08799 (uint8_t*)&slv1_config, 1); 08800 } 08801 if (ret == 0) { 08802 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08803 } 08804 08805 return ret; 08806 } 08807 08808 /** 08809 * @brief Configure slave 0 for perform a write/read.[set] 08810 * 08811 * @param ctx read / write interface definitions 08812 * @param val Structure that contain 08813 * - uint8_t slv2_add; 8 bit i2c device address 08814 * - uint8_t slv2_subadd; 8 bit register device address 08815 * - uint8_t slv2_len; num of bit to read 08816 * 08817 */ 08818 int32_t lsm6dsox_sh_slv2_cfg_read(lsm6dsox_ctx_t *ctx, 08819 lsm6dsox_sh_cfg_read_t *val) 08820 { 08821 lsm6dsox_slv2_add_t slv2_add; 08822 lsm6dsox_slv2_config_t slv2_config; 08823 int32_t ret; 08824 08825 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08826 if (ret == 0) { 08827 slv2_add.slave2_add = val->slv_add; 08828 slv2_add.r_2 = 1; 08829 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t*)&slv2_add, 1); 08830 } 08831 if (ret == 0) { 08832 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_SUBADD, 08833 &(val->slv_subadd), 1); 08834 } 08835 if (ret == 0) { 08836 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, 08837 (uint8_t*)&slv2_config, 1); 08838 } 08839 if (ret == 0) { 08840 slv2_config.slave2_numop = val->slv_len; 08841 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, 08842 (uint8_t*)&slv2_config, 1); 08843 } 08844 if (ret == 0) { 08845 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08846 } 08847 return ret; 08848 } 08849 08850 /** 08851 * @brief Configure slave 0 for perform a write/read.[set] 08852 * 08853 * @param ctx read / write interface definitions 08854 * @param val Structure that contain 08855 * - uint8_t slv3_add; 8 bit i2c device address 08856 * - uint8_t slv3_subadd; 8 bit register device address 08857 * - uint8_t slv3_len; num of bit to read 08858 * 08859 */ 08860 int32_t lsm6dsox_sh_slv3_cfg_read(lsm6dsox_ctx_t *ctx, 08861 lsm6dsox_sh_cfg_read_t *val) 08862 { 08863 lsm6dsox_slv3_add_t slv3_add; 08864 lsm6dsox_slv3_config_t slv3_config; 08865 int32_t ret; 08866 08867 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08868 if (ret == 0) { 08869 slv3_add.slave3_add = val->slv_add; 08870 slv3_add.r_3 = 1; 08871 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t*)&slv3_add, 1); 08872 } 08873 if (ret == 0) { 08874 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_SUBADD, 08875 &(val->slv_subadd), 1); 08876 } 08877 if (ret == 0) { 08878 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, 08879 (uint8_t*)&slv3_config, 1); 08880 } 08881 if (ret == 0) { 08882 slv3_config.slave3_numop = val->slv_len; 08883 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, 08884 (uint8_t*)&slv3_config, 1); 08885 } 08886 if (ret == 0) { 08887 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08888 } 08889 return ret; 08890 } 08891 08892 /** 08893 * @brief Sensor hub source register.[get] 08894 * 08895 * @param ctx read / write interface definitions 08896 * @param val union of registers from STATUS_MASTER to 08897 * 08898 */ 08899 int32_t lsm6dsox_sh_status_get(lsm6dsox_ctx_t *ctx, 08900 lsm6dsox_status_master_t *val) 08901 { 08902 int32_t ret; 08903 08904 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); 08905 if (ret == 0) { 08906 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t*) val, 1); 08907 } 08908 if (ret == 0) { 08909 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 08910 } 08911 08912 return ret; 08913 } 08914 08915 /** 08916 * @} 08917 * 08918 */ 08919 08920 /** 08921 * @addtogroup Sensors for Smart Mobile Devices 08922 * @brief This section groups all the functions that manage the 08923 * Sensors for Smart Mobile Devices. 08924 * @{ 08925 * 08926 */ 08927 08928 /** 08929 * @brief s4s_tph_res: [set] Sensor synchronization time frame resolution 08930 * 08931 * @param *ctx read / write interface definitions 08932 * @param val change the values of tph_h_sel in LSM6DSOX_S4S_TPH_L 08933 * 08934 */ 08935 int32_t lsm6dsox_s4s_tph_res_set(lsm6dsox_ctx_t *ctx, 08936 lsm6dsox_s4s_tph_res_t val) 08937 { 08938 lsm6dsox_s4s_tph_l_t reg; 08939 int32_t ret; 08940 08941 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1); 08942 if (ret == 0) { 08943 reg.tph_h_sel = (uint8_t)val; 08944 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1); 08945 } 08946 return ret; 08947 } 08948 08949 /** 08950 * @brief s4s_tph_res: [get] Sensor synchronization time frame resolution 08951 * 08952 * @param *ctx read / write interface definitions 08953 * @param val get the values of tph_h_sel in LSM6DSOX_S4S_TPH_L 08954 * 08955 */ 08956 int32_t lsm6dsox_s4s_tph_res_get(lsm6dsox_ctx_t *ctx, 08957 lsm6dsox_s4s_tph_res_t *val) 08958 { 08959 lsm6dsox_s4s_tph_l_t reg; 08960 int32_t ret; 08961 08962 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1); 08963 switch (reg.tph_h_sel) { 08964 case LSM6DSOX_S4S_TPH_7bit: 08965 *val = LSM6DSOX_S4S_TPH_7bit; 08966 break; 08967 case LSM6DSOX_S4S_TPH_15bit: 08968 *val = LSM6DSOX_S4S_TPH_15bit; 08969 break; 08970 default: 08971 *val = LSM6DSOX_S4S_TPH_7bit; 08972 break; 08973 } 08974 08975 return ret; 08976 } 08977 08978 /** 08979 * @brief s4s_tph_val: [set] Sensor synchronization time frame 08980 * 08981 * @param *ctx read / write interface definitions 08982 * @param val change the values of tph_l in S4S_TPH_L and 08983 * tph_h in S4S_TPH_H 08984 * 08985 */ 08986 int32_t lsm6dsox_s4s_tph_val_set(lsm6dsox_ctx_t *ctx, uint16_t val) 08987 { 08988 lsm6dsox_s4s_tph_l_t s4s_tph_l; 08989 lsm6dsox_s4s_tph_h_t s4s_tph_h; 08990 int32_t ret; 08991 08992 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1); 08993 if (ret == 0) { 08994 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU); 08995 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1); 08996 } 08997 if (ret == 0) { 08998 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1); 08999 s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7; 09000 } 09001 if (ret == 0) { 09002 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1); 09003 } 09004 return ret; 09005 } 09006 09007 /** 09008 * @brief s4s_tph_val: [get] Sensor synchronization time frame. 09009 * 09010 * @param *ctx read / write interface definitions 09011 * @param val get the values of tph_l in S4S_TPH_L and 09012 * tph_h in S4S_TPH_H 09013 * 09014 */ 09015 int32_t lsm6dsox_s4s_tph_val_get(lsm6dsox_ctx_t *ctx, uint16_t *val) 09016 { 09017 lsm6dsox_s4s_tph_l_t s4s_tph_l; 09018 lsm6dsox_s4s_tph_h_t s4s_tph_h; 09019 int32_t ret; 09020 09021 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1); 09022 if (ret == 0) { 09023 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1); 09024 *val = s4s_tph_h.tph_h; 09025 *val = *val << 7; 09026 *val += s4s_tph_l.tph_l; 09027 } 09028 return ret; 09029 } 09030 09031 /** 09032 * @brief s4s_res_ratio: [set]Sensor synchronization resolution 09033 * ratio register. 09034 * 09035 * @param *ctx read / write interface definitions. 09036 * @param val change the values of rr in S4S_RR. 09037 * 09038 */ 09039 int32_t lsm6dsox_s4s_res_ratio_set(lsm6dsox_ctx_t *ctx, 09040 lsm6dsox_s4s_res_ratio_t val) 09041 { 09042 lsm6dsox_s4s_rr_t reg; 09043 int32_t ret; 09044 09045 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1); 09046 if (ret == 0) { 09047 reg.rr = (uint8_t)val; 09048 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1); 09049 } 09050 return ret; 09051 } 09052 09053 /** 09054 * @brief s4s_res_ratio: [get]Sensor synchronization resolution 09055 * ratio register. 09056 * 09057 * @param *ctx read / write interface definitions 09058 * @param val get the values of rr in S4S_RR 09059 * 09060 */ 09061 int32_t lsm6dsox_s4s_res_ratio_get(lsm6dsox_ctx_t *ctx, 09062 lsm6dsox_s4s_res_ratio_t *val) 09063 { 09064 lsm6dsox_s4s_rr_t reg; 09065 int32_t ret; 09066 09067 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1); 09068 switch (reg.rr) { 09069 case LSM6DSOX_S4S_DT_RES_11: 09070 *val = LSM6DSOX_S4S_DT_RES_11; 09071 break; 09072 case LSM6DSOX_S4S_DT_RES_12: 09073 *val = LSM6DSOX_S4S_DT_RES_12; 09074 break; 09075 case LSM6DSOX_S4S_DT_RES_13: 09076 *val = LSM6DSOX_S4S_DT_RES_13; 09077 break; 09078 case LSM6DSOX_S4S_DT_RES_14: 09079 *val = LSM6DSOX_S4S_DT_RES_14; 09080 break; 09081 default: 09082 *val = LSM6DSOX_S4S_DT_RES_11; 09083 break; 09084 } 09085 return ret; 09086 } 09087 09088 /** 09089 * @brief s4s_command: [set] s4s master command. 09090 * 09091 * @param *ctx read / write interface definitions. 09092 * @param val change the values of S4S_ST_CMD_CODE. 09093 * 09094 */ 09095 int32_t lsm6dsox_s4s_command_set(lsm6dsox_ctx_t *ctx, uint8_t val) 09096 { 09097 lsm6dsox_s4s_st_cmd_code_t reg; 09098 int32_t ret; 09099 09100 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1); 09101 09102 if (ret == 0) { 09103 reg.s4s_st_cmd_code = val; 09104 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1); 09105 } 09106 return ret; 09107 } 09108 09109 /** 09110 * @brief s4s_command: [get] s4s master command. 09111 * 09112 * @param *ctx read / write interface definitions. 09113 * @param val get the values of S4S_ST_CMD_CODE. 09114 * 09115 */ 09116 int32_t lsm6dsox_s4s_command_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 09117 { 09118 lsm6dsox_s4s_st_cmd_code_t reg; 09119 int32_t ret; 09120 09121 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1); 09122 *val = reg.s4s_st_cmd_code; 09123 09124 return ret; 09125 } 09126 09127 /** 09128 * @brief s4s_dt: [set] S4S DT register. 09129 * 09130 * @param *ctx read / write interface definitions. 09131 * @param val change the values of S4S_DT_REG. 09132 * 09133 */ 09134 int32_t lsm6dsox_s4s_dt_set(lsm6dsox_ctx_t *ctx, uint8_t val) 09135 { 09136 lsm6dsox_s4s_dt_reg_t reg; 09137 int32_t ret; 09138 09139 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1); 09140 if (ret == 0) { 09141 reg.dt = val; 09142 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1); 09143 } 09144 return ret; 09145 } 09146 09147 /** 09148 * @brief s4s_dt: [get] S4S DT register. 09149 * 09150 * @param *ctx read / write interface definitions. 09151 * @param val get the values of S4S_DT_REG. 09152 * 09153 */ 09154 int32_t lsm6dsox_s4s_dt_get(lsm6dsox_ctx_t *ctx, uint8_t *val) 09155 { 09156 lsm6dsox_s4s_dt_reg_t reg; 09157 int32_t ret; 09158 09159 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1); 09160 *val = reg.dt; 09161 09162 return ret; 09163 } 09164 09165 /** 09166 * @} 09167 * 09168 */ 09169 09170 /** 09171 * @defgroup Basic configuration 09172 * @brief This section groups all the functions concerning 09173 * device basic configuration. 09174 * @{ 09175 * 09176 */ 09177 09178 /** 09179 * @brief Device "Who am I".[get] 09180 * 09181 * @param ctx communication interface handler. Use NULL to ingnore 09182 * this interface.(ptr) 09183 * @param aux_ctx auxiliary communication interface handler. Use NULL 09184 * to ingnore this interface.(ptr) 09185 * @param val ID values read from the two interfaces. ID values 09186 * will be the same.(ptr) 09187 * 09188 */ 09189 int32_t lsm6dsox_id_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 09190 lsm6dsox_id_t *val) 09191 { 09192 int32_t ret = 0; 09193 09194 if (ctx != NULL){ 09195 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, 09196 (uint8_t*)&(val->ui), 1); 09197 } 09198 if (aux_ctx != NULL){ 09199 if (ret == 0) { 09200 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_WHO_AM_I, 09201 (uint8_t*)&(val->aux), 1); 09202 } 09203 } 09204 return ret; 09205 } 09206 09207 /** 09208 * @brief Re-initialize the device.[set] 09209 * 09210 * @param ctx communication interface handler.(ptr) 09211 * @param val re-initialization mode. Refer to datasheet 09212 * and application note for more information 09213 * about differencies beetween boot and sw_reset 09214 * procedure. 09215 * 09216 */ 09217 int32_t lsm6dsox_init_set(lsm6dsox_ctx_t *ctx, lsm6dsox_init_t val) 09218 { 09219 lsm6dsox_emb_func_init_a_t emb_func_init_a; 09220 lsm6dsox_emb_func_init_b_t emb_func_init_b; 09221 lsm6dsox_ctrl3_c_t ctrl3_c; 09222 int32_t ret; 09223 09224 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 09225 if (ret == 0) { 09226 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, 09227 (uint8_t*)&emb_func_init_b, 1); 09228 } 09229 if (ret == 0) { 09230 emb_func_init_b.fifo_compr_init = (uint8_t)val 09231 & ( (uint8_t)LSM6DSOX_FIFO_COMP >> 2 ); 09232 emb_func_init_b.fsm_init = (uint8_t)val 09233 & ( (uint8_t)LSM6DSOX_FSM >> 3 ); 09234 emb_func_init_b.mlc_init = (uint8_t)val 09235 & ( (uint8_t)LSM6DSOX_MLC >> 4 ); 09236 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, 09237 (uint8_t*)&emb_func_init_b, 1); 09238 } 09239 if (ret == 0) { 09240 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A, 09241 (uint8_t*)&emb_func_init_a, 1); 09242 } 09243 if (ret == 0) { 09244 emb_func_init_a.step_det_init = ( (uint8_t)val 09245 & (uint8_t)LSM6DSOX_PEDO ) >> 5; 09246 emb_func_init_a.tilt_init = ( (uint8_t)val 09247 & (uint8_t)LSM6DSOX_TILT ) >> 6; 09248 emb_func_init_a.sig_mot_init = ( (uint8_t)val 09249 & (uint8_t)LSM6DSOX_SMOTION ) >> 7; 09250 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A, 09251 (uint8_t*)&emb_func_init_a, 1); 09252 } 09253 if (ret == 0) { 09254 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 09255 } 09256 09257 if (ret == 0) { 09258 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09259 } 09260 if ( ( (val == LSM6DSOX_BOOT) || (val == LSM6DSOX_RESET) ) && (ret == 0) ) { 09261 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSOX_BOOT; 09262 ctrl3_c.sw_reset = ( (uint8_t)val & (uint8_t)LSM6DSOX_RESET) >> 1; 09263 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09264 } 09265 if ( ( val == LSM6DSOX_DRV_RDY ) 09266 && ( (ctrl3_c.bdu == PROPERTY_DISABLE) 09267 || (ctrl3_c.if_inc == PROPERTY_DISABLE) ) && (ret == 0) ) { 09268 ctrl3_c.bdu = PROPERTY_ENABLE; 09269 ctrl3_c.if_inc = PROPERTY_ENABLE; 09270 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09271 } 09272 09273 return ret; 09274 } 09275 09276 /** 09277 * @brief Configures the bus operating mode.[set] 09278 * 09279 * @param ctx communication interface handler. Use NULL to ingnore 09280 * this interface.(ptr) 09281 * @param aux_ctx auxiliary communication interface handler. Use NULL 09282 * to ingnore this interface.(ptr) 09283 * @param val configures the bus operating mode for both the 09284 * main and the auxiliary interface. 09285 * 09286 */ 09287 int32_t lsm6dsox_bus_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 09288 lsm6dsox_bus_mode_t val) 09289 { 09290 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; 09291 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 09292 lsm6dsox_ctrl9_xl_t ctrl9_xl; 09293 lsm6dsox_ctrl3_c_t ctrl3_c; 09294 lsm6dsox_ctrl4_c_t ctrl4_c; 09295 uint8_t bit_val; 09296 int32_t ret; 09297 09298 ret = 0; 09299 09300 if (aux_ctx != NULL) { 09301 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, 09302 (uint8_t*)&spi2_ctrl1_ois, 1); 09303 09304 bit_val = ( (uint8_t)val.aux_bus_md & 0x04U ) >> 2; 09305 if ( ( ret == 0 ) && ( spi2_ctrl1_ois.sim_ois != bit_val ) ) { 09306 spi2_ctrl1_ois.sim_ois = bit_val; 09307 ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, 09308 (uint8_t*)&spi2_ctrl1_ois, 1); 09309 } 09310 } 09311 09312 if (ctx != NULL) { 09313 if (ret == 0) { 09314 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, 09315 (uint8_t*)&ctrl9_xl, 1); 09316 } 09317 09318 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2; 09319 if ( ( ret == 0 ) && ( ctrl9_xl.i3c_disable != bit_val ) ) { 09320 ctrl9_xl.i3c_disable = bit_val; 09321 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, 09322 (uint8_t*)&ctrl9_xl, 1); 09323 } 09324 09325 if (ret == 0) { 09326 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 09327 (uint8_t*)&i3c_bus_avb, 1); 09328 } 09329 09330 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4; 09331 if ( ( ret == 0 ) && ( i3c_bus_avb.i3c_bus_avb_sel != bit_val ) ) { 09332 i3c_bus_avb.i3c_bus_avb_sel = bit_val; 09333 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 09334 (uint8_t*)&i3c_bus_avb, 1); 09335 } 09336 if (ret == 0) { 09337 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, 09338 (uint8_t*)&ctrl4_c, 1); 09339 } 09340 bit_val = ( (uint8_t)val.ui_bus_md & 0x02U ) >> 1; 09341 if ( ( ret == 0 ) && ( ctrl4_c.i2c_disable != bit_val ) ) { 09342 ctrl4_c.i2c_disable = bit_val; 09343 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, 09344 (uint8_t*)&ctrl4_c, 1); 09345 } 09346 if (ret == 0) { 09347 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, 09348 (uint8_t*)&ctrl3_c, 1); 09349 } 09350 bit_val = (uint8_t)val.ui_bus_md & 0x01U; 09351 if ( ( ret == 0 ) && ( ctrl3_c.sim != bit_val ) ) { 09352 ctrl3_c.sim = bit_val; 09353 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, 09354 (uint8_t*)&ctrl3_c, 1); 09355 } 09356 } 09357 09358 return ret; 09359 09360 } 09361 09362 /** 09363 * @brief Get the bus operating mode.[get] 09364 * 09365 * @param ctx communication interface handler. Use NULL to ingnore 09366 * this interface.(ptr) 09367 * @param aux_ctx auxiliary communication interface handler. Use NULL 09368 * to ingnore this interface.(ptr) 09369 * @param val retrieves the bus operating mode for both the main 09370 * and the auxiliary interface.(ptr) 09371 * 09372 */ 09373 int32_t lsm6dsox_bus_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 09374 lsm6dsox_bus_mode_t *val) 09375 { 09376 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; 09377 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 09378 lsm6dsox_ctrl9_xl_t ctrl9_xl; 09379 lsm6dsox_ctrl3_c_t ctrl3_c; 09380 lsm6dsox_ctrl4_c_t ctrl4_c; 09381 09382 int32_t ret = 0; 09383 09384 if (aux_ctx != NULL) { 09385 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, 09386 (uint8_t*)&spi2_ctrl1_ois, 1); 09387 switch ( spi2_ctrl1_ois.sim_ois ) { 09388 case LSM6DSOX_SPI_4W_AUX: 09389 val->aux_bus_md = LSM6DSOX_SPI_4W_AUX; 09390 break; 09391 case LSM6DSOX_SPI_3W_AUX: 09392 val->aux_bus_md = LSM6DSOX_SPI_3W_AUX; 09393 break; 09394 default: 09395 val->aux_bus_md = LSM6DSOX_SPI_4W_AUX; 09396 break; 09397 } 09398 } 09399 09400 if (ctx != NULL) { 09401 if (ret == 0) { 09402 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, 09403 (uint8_t*)&ctrl9_xl, 1); 09404 } 09405 if (ret == 0) { 09406 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 09407 (uint8_t*)&i3c_bus_avb, 1); 09408 } 09409 if (ret == 0) { 09410 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, 09411 (uint8_t*)&ctrl4_c, 1); 09412 } 09413 if (ret == 0) { 09414 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, 09415 (uint8_t*)&ctrl3_c, 1); 09416 09417 switch ( ( i3c_bus_avb.i3c_bus_avb_sel << 4 ) & 09418 ( ctrl9_xl.i3c_disable << 2 ) & 09419 ( ctrl4_c.i2c_disable << 1) & ctrl3_c.sim ) { 09420 case LSM6DSOX_SEL_BY_HW: 09421 val->ui_bus_md = LSM6DSOX_SEL_BY_HW; 09422 break; 09423 case LSM6DSOX_SPI_4W: 09424 val->ui_bus_md = LSM6DSOX_SPI_4W; 09425 break; 09426 case LSM6DSOX_SPI_3W: 09427 val->ui_bus_md = LSM6DSOX_SPI_3W; 09428 break; 09429 case LSM6DSOX_I2C: 09430 val->ui_bus_md = LSM6DSOX_I2C; 09431 break; 09432 case LSM6DSOX_I3C_T_50us: 09433 val->ui_bus_md = LSM6DSOX_I3C_T_50us; 09434 break; 09435 case LSM6DSOX_I3C_T_2us: 09436 val->ui_bus_md = LSM6DSOX_I3C_T_2us; 09437 break; 09438 case LSM6DSOX_I3C_T_1ms: 09439 val->ui_bus_md = LSM6DSOX_I3C_T_1ms; 09440 break; 09441 case LSM6DSOX_I3C_T_25ms: 09442 val->ui_bus_md = LSM6DSOX_I3C_T_25ms; 09443 break; 09444 default: 09445 val->ui_bus_md = LSM6DSOX_SEL_BY_HW; 09446 break; 09447 } 09448 } 09449 } 09450 return ret; 09451 } 09452 09453 /** 09454 * @brief Get the status of the device.[get] 09455 * 09456 * @param ctx communication interface handler. Use NULL to ingnore 09457 * this interface.(ptr) 09458 * @param aux_ctx auxiliary communication interface handler. Use NULL 09459 * to ingnore this interface.(ptr) 09460 * @param val the status of the device.(ptr) 09461 * 09462 */ 09463 int32_t lsm6dsox_status_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 09464 lsm6dsox_status_t *val) 09465 { 09466 lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois; 09467 lsm6dsox_ui_status_reg_ois_t ui_status_reg_ois; 09468 lsm6dsox_status_reg_t status_reg; 09469 lsm6dsox_ctrl3_c_t ctrl3_c; 09470 int32_t ret; 09471 09472 ret = 0; 09473 09474 if (aux_ctx != NULL){ 09475 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, 09476 (uint8_t*)&spi2_status_reg_ois, 1); 09477 val->ois_drdy_xl = spi2_status_reg_ois.xlda; 09478 val->ois_drdy_g = spi2_status_reg_ois.gda; 09479 val->ois_gyro_settling = spi2_status_reg_ois.gyro_settling; 09480 } 09481 09482 if (ctx != NULL){ 09483 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09484 val->sw_reset = ctrl3_c.sw_reset; 09485 val->boot = ctrl3_c.boot; 09486 09487 if ( (ret == 0) && ( ctrl3_c.sw_reset == PROPERTY_DISABLE ) && 09488 ( ctrl3_c.boot == PROPERTY_DISABLE ) ) { 09489 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, 09490 (uint8_t*)&status_reg, 1); 09491 val->drdy_xl = status_reg.xlda; 09492 val->drdy_g = status_reg.gda; 09493 val->drdy_temp = status_reg.tda; 09494 } 09495 if (aux_ctx == NULL){ 09496 if (ret == 0) { 09497 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_STATUS_REG_OIS, 09498 (uint8_t*)&ui_status_reg_ois, 1); 09499 val->ois_drdy_xl = ui_status_reg_ois.xlda; 09500 val->ois_drdy_g = ui_status_reg_ois.gda; 09501 val->ois_gyro_settling = ui_status_reg_ois.gyro_settling; 09502 } 09503 } 09504 } 09505 return ret; 09506 } 09507 09508 /** 09509 * @brief Electrical pin configuration.[set] 09510 * 09511 * @param ctx communication interface handler.(ptr) 09512 * @param val the electrical settings for the configurable 09513 * pins. 09514 * 09515 */ 09516 int32_t lsm6dsox_pin_conf_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pin_conf_t val) 09517 { 09518 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 09519 lsm6dsox_pin_ctrl_t pin_ctrl; 09520 lsm6dsox_ctrl3_c_t ctrl3_c; 09521 int32_t ret; 09522 09523 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1); 09524 if (ret == 0) { 09525 pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up; 09526 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up; 09527 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1); 09528 } 09529 if (ret == 0) { 09530 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09531 } 09532 if (ret == 0) { 09533 ctrl3_c.pp_od = ~val.int1_int2_push_pull; 09534 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09535 } 09536 if (ret == 0) { 09537 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 09538 (uint8_t*)&i3c_bus_avb, 1); 09539 } 09540 if (ret == 0) { 09541 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down; 09542 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 09543 (uint8_t*)&i3c_bus_avb, 1); 09544 } 09545 return ret; 09546 } 09547 09548 /** 09549 * @brief Electrical pin configuration.[get] 09550 * 09551 * @param ctx communication interface handler.(ptr) 09552 * @param val the electrical settings for the configurable 09553 * pins.(ptr) 09554 * 09555 */ 09556 int32_t lsm6dsox_pin_conf_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pin_conf_t *val) 09557 { 09558 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 09559 lsm6dsox_pin_ctrl_t pin_ctrl; 09560 lsm6dsox_ctrl3_c_t ctrl3_c; 09561 int32_t ret; 09562 09563 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)&pin_ctrl, 1); 09564 if (ret == 0) { 09565 val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis; 09566 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en; 09567 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09568 } 09569 if (ret == 0) { 09570 val->int1_int2_push_pull = ~ctrl3_c.pp_od; 09571 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, 09572 (uint8_t*)&i3c_bus_avb, 1); 09573 } 09574 if (ret == 0) { 09575 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1; 09576 } 09577 return ret; 09578 } 09579 09580 /** 09581 * @brief Interrupt pins hardware signal configuration.[set] 09582 * 09583 * @param ctx communication interface handler.(ptr) 09584 * @param val the pins hardware signal settings. 09585 * 09586 */ 09587 int32_t lsm6dsox_interrupt_mode_set(lsm6dsox_ctx_t *ctx, 09588 lsm6dsox_int_mode_t val) 09589 { 09590 lsm6dsox_tap_cfg0_t tap_cfg0; 09591 lsm6dsox_page_rw_t page_rw; 09592 lsm6dsox_ctrl3_c_t ctrl3_c; 09593 int32_t ret; 09594 09595 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09596 if (ret == 0) { 09597 ctrl3_c.h_lactive = val.active_low; 09598 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09599 } 09600 if (ret == 0) { 09601 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 09602 } 09603 if (ret == 0) { 09604 tap_cfg0.lir = val.base_latched; 09605 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched; 09606 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 09607 } 09608 if (ret == 0) { 09609 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 09610 } 09611 if (ret == 0) { 09612 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 09613 } 09614 if (ret == 0) { 09615 page_rw.emb_func_lir = val.emb_latched; 09616 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 09617 } 09618 if (ret == 0) { 09619 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 09620 } 09621 return ret; 09622 } 09623 09624 /** 09625 * @brief Interrupt pins hardware signal configuration.[get] 09626 * 09627 * @param ctx communication interface handler.(ptr) 09628 * @param val the pins hardware signal settings.(ptr) 09629 * 09630 */ 09631 int32_t lsm6dsox_interrupt_mode_get(lsm6dsox_ctx_t *ctx, 09632 lsm6dsox_int_mode_t *val) 09633 { 09634 lsm6dsox_tap_cfg0_t tap_cfg0; 09635 lsm6dsox_page_rw_t page_rw; 09636 lsm6dsox_ctrl3_c_t ctrl3_c; 09637 int32_t ret; 09638 09639 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 09640 if (ret == 0) { 09641 ctrl3_c.h_lactive = val->active_low; 09642 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 09643 } 09644 if (ret == 0) { 09645 tap_cfg0.lir = val->base_latched; 09646 tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched; 09647 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 09648 } 09649 if (ret == 0) { 09650 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 09651 } 09652 if (ret == 0) { 09653 page_rw.emb_func_lir = val->emb_latched; 09654 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); 09655 } 09656 if (ret == 0) { 09657 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 09658 } 09659 return ret; 09660 } 09661 09662 /** 09663 * @brief Route interrupt signals on int1 pin.[set] 09664 * 09665 * @param ctx communication interface handler.(ptr) 09666 * @param val the signals to route on int1 pin. 09667 * 09668 */ 09669 int32_t lsm6dsox_pin_int1_route_set(lsm6dsox_ctx_t *ctx, 09670 lsm6dsox_pin_int1_route_t val) 09671 { 09672 lsm6dsox_pin_int2_route_t pin_int2_route; 09673 lsm6dsox_emb_func_int1_t emb_func_int1; 09674 lsm6dsox_fsm_int1_a_t fsm_int1_a; 09675 lsm6dsox_fsm_int1_b_t fsm_int1_b; 09676 lsm6dsox_int1_ctrl_t int1_ctrl; 09677 lsm6dsox_int2_ctrl_t int2_ctrl; 09678 lsm6dsox_mlc_int1_t mlc_int1; 09679 lsm6dsox_tap_cfg2_t tap_cfg2; 09680 lsm6dsox_md2_cfg_t md2_cfg; 09681 lsm6dsox_md1_cfg_t md1_cfg; 09682 lsm6dsox_ctrl4_c_t ctrl4_c; 09683 int32_t ret; 09684 09685 int1_ctrl.int1_drdy_xl = val.drdy_xl; 09686 int1_ctrl.int1_drdy_g = val.drdy_g; 09687 int1_ctrl.int1_boot = val.boot; 09688 int1_ctrl.int1_fifo_th = val.fifo_th; 09689 int1_ctrl.int1_fifo_ovr = val.fifo_ovr; 09690 int1_ctrl.int1_fifo_full = val.fifo_full; 09691 int1_ctrl.int1_cnt_bdr = val.fifo_bdr; 09692 int1_ctrl.den_drdy_flag = val.den_flag; 09693 09694 md1_cfg.int1_shub = val.sh_endop; 09695 md1_cfg.int1_6d = val.six_d; 09696 md1_cfg.int1_double_tap = val.double_tap; 09697 md1_cfg.int1_ff = val.free_fall; 09698 md1_cfg.int1_wu = val.wake_up; 09699 md1_cfg.int1_single_tap = val.single_tap; 09700 md1_cfg.int1_sleep_change = val.sleep_change; 09701 09702 emb_func_int1.not_used_01 = 0; 09703 emb_func_int1.int1_step_detector = val.step_detector; 09704 emb_func_int1.int1_tilt = val.tilt; 09705 emb_func_int1.int1_sig_mot = val.sig_mot; 09706 emb_func_int1.not_used_02 = 0; 09707 emb_func_int1.int1_fsm_lc = val.fsm_lc; 09708 09709 fsm_int1_a.int1_fsm1 = val.fsm1; 09710 fsm_int1_a.int1_fsm2 = val.fsm2; 09711 fsm_int1_a.int1_fsm3 = val.fsm3; 09712 fsm_int1_a.int1_fsm4 = val.fsm4; 09713 fsm_int1_a.int1_fsm5 = val.fsm5; 09714 fsm_int1_a.int1_fsm6 = val.fsm6; 09715 fsm_int1_a.int1_fsm7 = val.fsm7; 09716 fsm_int1_a.int1_fsm8 = val.fsm8; 09717 09718 fsm_int1_b.int1_fsm9 = val.fsm9 ; 09719 fsm_int1_b.int1_fsm10 = val.fsm10; 09720 fsm_int1_b.int1_fsm11 = val.fsm11; 09721 fsm_int1_b.int1_fsm12 = val.fsm12; 09722 fsm_int1_b.int1_fsm13 = val.fsm13; 09723 fsm_int1_b.int1_fsm14 = val.fsm14; 09724 fsm_int1_b.int1_fsm15 = val.fsm15; 09725 fsm_int1_b.int1_fsm16 = val.fsm16; 09726 09727 mlc_int1.int1_mlc1 = val.mlc1; 09728 mlc_int1.int1_mlc2 = val.mlc2; 09729 mlc_int1.int1_mlc3 = val.mlc3; 09730 mlc_int1.int1_mlc4 = val.mlc4; 09731 mlc_int1.int1_mlc5 = val.mlc5; 09732 mlc_int1.int1_mlc6 = val.mlc6; 09733 mlc_int1.int1_mlc7 = val.mlc7; 09734 mlc_int1.int1_mlc8 = val.mlc8; 09735 09736 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09737 if (ret == 0) { 09738 if( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE) { 09739 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE; 09740 } 09741 else{ 09742 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE; 09743 } 09744 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09745 } 09746 09747 if (ret == 0) { 09748 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 09749 } 09750 if (ret == 0) { 09751 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1, 09752 (uint8_t*)&mlc_int1, 1); 09753 } 09754 if (ret == 0) { 09755 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1, 09756 (uint8_t*)&emb_func_int1, 1); 09757 } 09758 if (ret == 0) { 09759 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A, 09760 (uint8_t*)&fsm_int1_a, 1); 09761 } 09762 if (ret == 0) { 09763 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B, 09764 (uint8_t*)&fsm_int1_b, 1); 09765 } 09766 if (ret == 0) { 09767 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 09768 } 09769 09770 if (ret == 0) { 09771 if ( ( emb_func_int1.int1_fsm_lc 09772 | emb_func_int1.int1_sig_mot 09773 | emb_func_int1.int1_step_detector 09774 | emb_func_int1.int1_tilt 09775 | fsm_int1_a.int1_fsm1 09776 | fsm_int1_a.int1_fsm2 09777 | fsm_int1_a.int1_fsm3 09778 | fsm_int1_a.int1_fsm4 09779 | fsm_int1_a.int1_fsm5 09780 | fsm_int1_a.int1_fsm6 09781 | fsm_int1_a.int1_fsm7 09782 | fsm_int1_a.int1_fsm8 09783 | fsm_int1_b.int1_fsm9 09784 | fsm_int1_b.int1_fsm10 09785 | fsm_int1_b.int1_fsm11 09786 | fsm_int1_b.int1_fsm12 09787 | fsm_int1_b.int1_fsm13 09788 | fsm_int1_b.int1_fsm14 09789 | fsm_int1_b.int1_fsm15 09790 | fsm_int1_b.int1_fsm16 09791 | mlc_int1.int1_mlc1 09792 | mlc_int1.int1_mlc2 09793 | mlc_int1.int1_mlc3 09794 | mlc_int1.int1_mlc4 09795 | mlc_int1.int1_mlc5 09796 | mlc_int1.int1_mlc6 09797 | mlc_int1.int1_mlc7 09798 | mlc_int1.int1_mlc8) != PROPERTY_DISABLE){ 09799 md1_cfg.int1_emb_func = PROPERTY_ENABLE; 09800 } 09801 else{ 09802 md1_cfg.int1_emb_func = PROPERTY_DISABLE; 09803 } 09804 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT1_CTRL, 09805 (uint8_t*)&int1_ctrl, 1); 09806 } 09807 if (ret == 0) { 09808 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&md1_cfg, 1); 09809 } 09810 09811 if (ret == 0) { 09812 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); 09813 } 09814 if (ret == 0) { 09815 int2_ctrl.int2_drdy_temp = val.drdy_temp; 09816 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); 09817 } 09818 if (ret == 0) { 09819 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09820 } 09821 if (ret == 0) { 09822 md2_cfg.int2_timestamp = val.timestamp; 09823 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09824 } 09825 09826 if (ret == 0) { 09827 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 09828 } 09829 if (ret == 0) { 09830 ret = lsm6dsox_pin_int2_route_get(ctx, NULL, &pin_int2_route); 09831 } 09832 if (ret == 0) { 09833 if ( ( pin_int2_route.fifo_bdr 09834 | pin_int2_route.drdy_g 09835 | pin_int2_route.drdy_temp 09836 | pin_int2_route.drdy_xl 09837 | pin_int2_route.fifo_full 09838 | pin_int2_route.fifo_ovr 09839 | pin_int2_route.fifo_th 09840 | pin_int2_route.six_d 09841 | pin_int2_route.double_tap 09842 | pin_int2_route.free_fall 09843 | pin_int2_route.wake_up 09844 | pin_int2_route.single_tap 09845 | pin_int2_route.sleep_change 09846 | int1_ctrl.den_drdy_flag 09847 | int1_ctrl.int1_boot 09848 | int1_ctrl.int1_cnt_bdr 09849 | int1_ctrl.int1_drdy_g 09850 | int1_ctrl.int1_drdy_xl 09851 | int1_ctrl.int1_fifo_full 09852 | int1_ctrl.int1_fifo_ovr 09853 | int1_ctrl.int1_fifo_th 09854 | md1_cfg.int1_shub 09855 | md1_cfg.int1_6d 09856 | md1_cfg.int1_double_tap 09857 | md1_cfg.int1_ff 09858 | md1_cfg.int1_wu 09859 | md1_cfg.int1_single_tap 09860 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) { 09861 tap_cfg2.interrupts_enable = PROPERTY_ENABLE; 09862 } 09863 else{ 09864 tap_cfg2.interrupts_enable = PROPERTY_DISABLE; 09865 } 09866 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 09867 } 09868 return ret; 09869 } 09870 09871 /** 09872 * @brief Route interrupt signals on int1 pin.[get] 09873 * 09874 * @param ctx communication interface handler.(ptr) 09875 * @param val the signals that are routed on int1 pin.(ptr) 09876 * 09877 */ 09878 int32_t lsm6dsox_pin_int1_route_get(lsm6dsox_ctx_t *ctx, 09879 lsm6dsox_pin_int1_route_t *val) 09880 { 09881 lsm6dsox_emb_func_int1_t emb_func_int1; 09882 lsm6dsox_fsm_int1_a_t fsm_int1_a; 09883 lsm6dsox_fsm_int1_b_t fsm_int1_b; 09884 lsm6dsox_int1_ctrl_t int1_ctrl; 09885 lsm6dsox_int2_ctrl_t int2_ctrl; 09886 lsm6dsox_mlc_int1_t mlc_int1; 09887 lsm6dsox_md2_cfg_t md2_cfg; 09888 lsm6dsox_md1_cfg_t md1_cfg; 09889 lsm6dsox_ctrl4_c_t ctrl4_c; 09890 int32_t ret; 09891 09892 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 09893 if (ret == 0) { 09894 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT1, 09895 (uint8_t*)&mlc_int1, 1); 09896 } 09897 if (ret == 0) { 09898 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT1, 09899 (uint8_t*)&emb_func_int1, 1); 09900 } 09901 if (ret == 0) { 09902 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_A, 09903 (uint8_t*)&fsm_int1_a, 1); 09904 } 09905 if (ret == 0) { 09906 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_B, 09907 (uint8_t*)&fsm_int1_b, 1); 09908 } 09909 if (ret == 0) { 09910 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 09911 } 09912 if (ret == 0) { 09913 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT1_CTRL, 09914 (uint8_t*)&int1_ctrl, 1); 09915 } 09916 if (ret == 0) { 09917 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&md1_cfg, 1); 09918 } 09919 if (ret == 0) { 09920 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09921 } 09922 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE){ 09923 if (ret == 0) { 09924 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); 09925 val->drdy_temp = int2_ctrl.int2_drdy_temp; 09926 } 09927 if (ret == 0) { 09928 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09929 val->timestamp = md2_cfg.int2_timestamp; 09930 } 09931 } 09932 else { 09933 val->drdy_temp = PROPERTY_DISABLE; 09934 val->timestamp = PROPERTY_DISABLE; 09935 } 09936 09937 val->drdy_xl = int1_ctrl.int1_drdy_xl; 09938 val->drdy_g = int1_ctrl.int1_drdy_g; 09939 val->boot = int1_ctrl.int1_boot; 09940 val->fifo_th = int1_ctrl.int1_fifo_th; 09941 val->fifo_ovr = int1_ctrl.int1_fifo_ovr; 09942 val->fifo_full = int1_ctrl.int1_fifo_full; 09943 val->fifo_bdr = int1_ctrl.int1_cnt_bdr; 09944 val->den_flag = int1_ctrl.den_drdy_flag; 09945 09946 val->sh_endop = md1_cfg.int1_shub; 09947 val->six_d = md1_cfg.int1_6d; 09948 val->double_tap = md1_cfg.int1_double_tap; 09949 val->free_fall = md1_cfg.int1_ff; 09950 val->wake_up = md1_cfg.int1_wu; 09951 val->single_tap = md1_cfg.int1_single_tap; 09952 val->sleep_change = md1_cfg.int1_sleep_change; 09953 09954 val->step_detector = emb_func_int1.int1_step_detector; 09955 val->tilt = emb_func_int1.int1_tilt; 09956 val->sig_mot = emb_func_int1.int1_sig_mot; 09957 val->fsm_lc = emb_func_int1.int1_fsm_lc; 09958 09959 val->fsm1 = fsm_int1_a.int1_fsm1; 09960 val->fsm2 = fsm_int1_a.int1_fsm2; 09961 val->fsm3 = fsm_int1_a.int1_fsm3; 09962 val->fsm4 = fsm_int1_a.int1_fsm4; 09963 val->fsm5 = fsm_int1_a.int1_fsm5; 09964 val->fsm6 = fsm_int1_a.int1_fsm6; 09965 val->fsm7 = fsm_int1_a.int1_fsm7; 09966 val->fsm8 = fsm_int1_a.int1_fsm8; 09967 09968 val->fsm9 = fsm_int1_b.int1_fsm9; 09969 val->fsm10 = fsm_int1_b.int1_fsm10; 09970 val->fsm11 = fsm_int1_b.int1_fsm11; 09971 val->fsm12 = fsm_int1_b.int1_fsm12; 09972 val->fsm13 = fsm_int1_b.int1_fsm13; 09973 val->fsm14 = fsm_int1_b.int1_fsm14; 09974 val->fsm15 = fsm_int1_b.int1_fsm15; 09975 val->fsm16 = fsm_int1_b.int1_fsm16; 09976 09977 val->mlc1 = mlc_int1.int1_mlc1; 09978 val->mlc2 = mlc_int1.int1_mlc2; 09979 val->mlc3 = mlc_int1.int1_mlc3; 09980 val->mlc4 = mlc_int1.int1_mlc4; 09981 val->mlc5 = mlc_int1.int1_mlc5; 09982 val->mlc6 = mlc_int1.int1_mlc6; 09983 val->mlc7 = mlc_int1.int1_mlc7; 09984 val->mlc8 = mlc_int1.int1_mlc8; 09985 09986 return ret; 09987 } 09988 09989 /** 09990 * @brief Route interrupt signals on int2 pin.[set] 09991 * 09992 * @param ctx communication interface handler. Use NULL to ingnore 09993 * this interface.(ptr) 09994 * @param aux_ctx auxiliary communication interface handler. Use NULL 09995 * to ingnore this interface.(ptr) 09996 * @param val the signals to route on int2 pin. 09997 * 09998 */ 09999 int32_t lsm6dsox_pin_int2_route_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 10000 lsm6dsox_pin_int2_route_t val) 10001 { 10002 lsm6dsox_pin_int1_route_t pin_int1_route; 10003 lsm6dsox_emb_func_int2_t emb_func_int2; 10004 lsm6dsox_spi2_int_ois_t spi2_int_ois; 10005 lsm6dsox_fsm_int2_a_t fsm_int2_a; 10006 lsm6dsox_fsm_int2_b_t fsm_int2_b; 10007 lsm6dsox_int2_ctrl_t int2_ctrl; 10008 lsm6dsox_mlc_int2_t mlc_int2; 10009 lsm6dsox_tap_cfg2_t tap_cfg2; 10010 lsm6dsox_md2_cfg_t md2_cfg; 10011 lsm6dsox_ctrl4_c_t ctrl4_c; 10012 int32_t ret; 10013 10014 ret = 0; 10015 10016 if( aux_ctx != NULL ) { 10017 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS, 10018 (uint8_t*)&spi2_int_ois, 1); 10019 if (ret == 0) { 10020 spi2_int_ois.int2_drdy_ois = val.drdy_ois; 10021 ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS, 10022 (uint8_t*)&spi2_int_ois, 1); 10023 } 10024 } 10025 10026 if( ctx != NULL ) { 10027 int2_ctrl.int2_drdy_xl = val.drdy_xl; 10028 int2_ctrl.int2_drdy_g = val.drdy_g; 10029 int2_ctrl.int2_drdy_temp = val.drdy_temp; 10030 int2_ctrl.int2_fifo_th = val.fifo_th; 10031 int2_ctrl.int2_fifo_ovr = val.fifo_ovr; 10032 int2_ctrl.int2_fifo_full = val.fifo_full; 10033 int2_ctrl.int2_cnt_bdr = val.fifo_bdr; 10034 int2_ctrl.not_used_01 = 0; 10035 10036 md2_cfg.int2_timestamp = val.timestamp; 10037 md2_cfg.int2_6d = val.six_d; 10038 md2_cfg.int2_double_tap = val.double_tap; 10039 md2_cfg.int2_ff = val.free_fall; 10040 md2_cfg.int2_wu = val.wake_up; 10041 md2_cfg.int2_single_tap = val.single_tap; 10042 md2_cfg.int2_sleep_change = val.sleep_change; 10043 10044 emb_func_int2.not_used_01 = 0; 10045 emb_func_int2. int2_step_detector = val.step_detector; 10046 emb_func_int2.int2_tilt = val.tilt; 10047 emb_func_int2.int2_sig_mot = val.sig_mot; 10048 emb_func_int2.not_used_02 = 0; 10049 emb_func_int2.int2_fsm_lc = val.fsm_lc; 10050 10051 fsm_int2_a.int2_fsm1 = val.fsm1; 10052 fsm_int2_a.int2_fsm2 = val.fsm2; 10053 fsm_int2_a.int2_fsm3 = val.fsm3; 10054 fsm_int2_a.int2_fsm4 = val.fsm4; 10055 fsm_int2_a.int2_fsm5 = val.fsm5; 10056 fsm_int2_a.int2_fsm6 = val.fsm6; 10057 fsm_int2_a.int2_fsm7 = val.fsm7; 10058 fsm_int2_a.int2_fsm8 = val.fsm8; 10059 10060 fsm_int2_b.int2_fsm9 = val.fsm9 ; 10061 fsm_int2_b.int2_fsm10 = val.fsm10; 10062 fsm_int2_b.int2_fsm11 = val.fsm11; 10063 fsm_int2_b.int2_fsm12 = val.fsm12; 10064 fsm_int2_b.int2_fsm13 = val.fsm13; 10065 fsm_int2_b.int2_fsm14 = val.fsm14; 10066 fsm_int2_b.int2_fsm15 = val.fsm15; 10067 fsm_int2_b.int2_fsm16 = val.fsm16; 10068 10069 mlc_int2.int2_mlc1 = val.mlc1; 10070 mlc_int2.int2_mlc2 = val.mlc2; 10071 mlc_int2.int2_mlc3 = val.mlc3; 10072 mlc_int2.int2_mlc4 = val.mlc4; 10073 mlc_int2.int2_mlc5 = val.mlc5; 10074 mlc_int2.int2_mlc6 = val.mlc6; 10075 mlc_int2.int2_mlc7 = val.mlc7; 10076 mlc_int2.int2_mlc8 = val.mlc8; 10077 10078 if (ret == 0) { 10079 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 10080 if (ret == 0) { 10081 if ( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE ) { 10082 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE; 10083 } 10084 10085 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 10086 } 10087 } 10088 10089 if (ret == 0) { 10090 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 10091 } 10092 if (ret == 0) { 10093 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT2, 10094 (uint8_t*)&mlc_int2, 1); 10095 } 10096 if (ret == 0) { 10097 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, 10098 (uint8_t*)&emb_func_int2, 1); 10099 } 10100 if (ret == 0) { 10101 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A, 10102 (uint8_t*)&fsm_int2_a, 1); 10103 } 10104 if (ret == 0) { 10105 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B, 10106 (uint8_t*)&fsm_int2_b, 1); 10107 } 10108 if (ret == 0) { 10109 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 10110 } 10111 10112 if (ret == 0) { 10113 if (( emb_func_int2.int2_fsm_lc 10114 | emb_func_int2.int2_sig_mot 10115 | emb_func_int2.int2_step_detector 10116 | emb_func_int2.int2_tilt 10117 | fsm_int2_a.int2_fsm1 10118 | fsm_int2_a.int2_fsm2 10119 | fsm_int2_a.int2_fsm3 10120 | fsm_int2_a.int2_fsm4 10121 | fsm_int2_a.int2_fsm5 10122 | fsm_int2_a.int2_fsm6 10123 | fsm_int2_a.int2_fsm7 10124 | fsm_int2_a.int2_fsm8 10125 | fsm_int2_b.int2_fsm9 10126 | fsm_int2_b.int2_fsm10 10127 | fsm_int2_b.int2_fsm11 10128 | fsm_int2_b.int2_fsm12 10129 | fsm_int2_b.int2_fsm13 10130 | fsm_int2_b.int2_fsm14 10131 | fsm_int2_b.int2_fsm15 10132 | fsm_int2_b.int2_fsm16 10133 | mlc_int2.int2_mlc1 10134 | mlc_int2.int2_mlc2 10135 | mlc_int2.int2_mlc3 10136 | mlc_int2.int2_mlc4 10137 | mlc_int2.int2_mlc5 10138 | mlc_int2.int2_mlc6 10139 | mlc_int2.int2_mlc7 10140 | mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){ 10141 md2_cfg.int2_emb_func = PROPERTY_ENABLE; 10142 } 10143 else{ 10144 md2_cfg.int2_emb_func = PROPERTY_DISABLE; 10145 } 10146 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL, 10147 (uint8_t*)&int2_ctrl, 1); 10148 } 10149 if (ret == 0) { 10150 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1); 10151 } 10152 if (ret == 0) { 10153 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 10154 } 10155 10156 if (ret == 0) { 10157 ret = lsm6dsox_pin_int1_route_get(ctx, &pin_int1_route); 10158 } 10159 10160 if (ret == 0) { 10161 if ( ( val.fifo_bdr 10162 | val.drdy_g 10163 | val.drdy_temp 10164 | val.drdy_xl 10165 | val.fifo_full 10166 | val.fifo_ovr 10167 | val.fifo_th 10168 | val.six_d 10169 | val.double_tap 10170 | val.free_fall 10171 | val.wake_up 10172 | val.single_tap 10173 | val.sleep_change 10174 | pin_int1_route.den_flag 10175 | pin_int1_route.boot 10176 | pin_int1_route.fifo_bdr 10177 | pin_int1_route.drdy_g 10178 | pin_int1_route.drdy_xl 10179 | pin_int1_route.fifo_full 10180 | pin_int1_route.fifo_ovr 10181 | pin_int1_route.fifo_th 10182 | pin_int1_route.six_d 10183 | pin_int1_route.double_tap 10184 | pin_int1_route.free_fall 10185 | pin_int1_route.wake_up 10186 | pin_int1_route.single_tap 10187 | pin_int1_route.sleep_change ) != PROPERTY_DISABLE) { 10188 tap_cfg2.interrupts_enable = PROPERTY_ENABLE; 10189 } 10190 else{ 10191 tap_cfg2.interrupts_enable = PROPERTY_DISABLE; 10192 } 10193 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 10194 } 10195 } 10196 return ret; 10197 } 10198 10199 /** 10200 * @brief Route interrupt signals on int2 pin.[get] 10201 * 10202 * @param ctx communication interface handler. Use NULL to ingnore 10203 * this interface.(ptr) 10204 * @param aux_ctx auxiliary communication interface handler. Use NULL 10205 * to ingnore this interface.(ptr) 10206 * @param val the signals that are routed on int2 pin.(ptr) 10207 * 10208 */ 10209 int32_t lsm6dsox_pin_int2_route_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 10210 lsm6dsox_pin_int2_route_t *val) 10211 { 10212 lsm6dsox_emb_func_int2_t emb_func_int2; 10213 lsm6dsox_spi2_int_ois_t spi2_int_ois; 10214 lsm6dsox_fsm_int2_a_t fsm_int2_a; 10215 lsm6dsox_fsm_int2_b_t fsm_int2_b; 10216 lsm6dsox_int2_ctrl_t int2_ctrl; 10217 lsm6dsox_mlc_int2_t mlc_int2; 10218 lsm6dsox_md2_cfg_t md2_cfg; 10219 lsm6dsox_ctrl4_c_t ctrl4_c; 10220 int32_t ret; 10221 10222 ret = 0; 10223 10224 if( aux_ctx != NULL ) { 10225 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS, 10226 (uint8_t*)&spi2_int_ois, 1); 10227 val->drdy_ois = spi2_int_ois.int2_drdy_ois; 10228 } 10229 10230 if( ctx != NULL ) { 10231 if (ret == 0) { 10232 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 10233 } 10234 if (ret == 0) { 10235 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2, 10236 (uint8_t*)&mlc_int2, 1); 10237 } 10238 if (ret == 0) { 10239 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, 10240 (uint8_t*)&emb_func_int2, 1); 10241 } 10242 if (ret == 0) { 10243 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A, 10244 (uint8_t*)&fsm_int2_a, 1); 10245 } 10246 if (ret == 0) { 10247 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B, 10248 (uint8_t*)&fsm_int2_b, 1); 10249 } 10250 if (ret == 0) { 10251 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 10252 } 10253 if (ret == 0) { 10254 10255 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, 10256 (uint8_t*)&int2_ctrl, 1); 10257 } 10258 if (ret == 0) { 10259 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, 10260 (uint8_t*)&md2_cfg, 1); 10261 } 10262 10263 if (ret == 0) { 10264 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 10265 } 10266 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE){ 10267 if (ret == 0) { 10268 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, 10269 (uint8_t*)&int2_ctrl, 1); 10270 val->drdy_temp = int2_ctrl.int2_drdy_temp; 10271 } 10272 if (ret == 0) { 10273 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&md2_cfg, 1); 10274 val->timestamp = md2_cfg.int2_timestamp; 10275 } 10276 } 10277 else { 10278 val->drdy_temp = PROPERTY_DISABLE; 10279 val->timestamp = PROPERTY_DISABLE; 10280 } 10281 10282 val->drdy_xl = int2_ctrl.int2_drdy_xl; 10283 val->drdy_g = int2_ctrl.int2_drdy_g; 10284 val->drdy_temp = int2_ctrl.int2_drdy_temp; 10285 val->fifo_th = int2_ctrl.int2_fifo_th; 10286 val->fifo_ovr = int2_ctrl.int2_fifo_ovr; 10287 val->fifo_full = int2_ctrl.int2_fifo_full; 10288 val->fifo_bdr = int2_ctrl.int2_cnt_bdr; 10289 10290 val->timestamp = md2_cfg.int2_timestamp; 10291 val->six_d = md2_cfg.int2_6d; 10292 val->double_tap = md2_cfg.int2_double_tap; 10293 val->free_fall = md2_cfg.int2_ff; 10294 val->wake_up = md2_cfg.int2_wu; 10295 val->single_tap = md2_cfg.int2_single_tap; 10296 val->sleep_change = md2_cfg.int2_sleep_change; 10297 10298 val->step_detector = emb_func_int2. int2_step_detector; 10299 val->tilt = emb_func_int2.int2_tilt; 10300 val->fsm_lc = emb_func_int2.int2_fsm_lc; 10301 10302 val->fsm1 = fsm_int2_a.int2_fsm1; 10303 val->fsm2 = fsm_int2_a.int2_fsm2; 10304 val->fsm3 = fsm_int2_a.int2_fsm3; 10305 val->fsm4 = fsm_int2_a.int2_fsm4; 10306 val->fsm5 = fsm_int2_a.int2_fsm5; 10307 val->fsm6 = fsm_int2_a.int2_fsm6; 10308 val->fsm7 = fsm_int2_a.int2_fsm7; 10309 val->fsm8 = fsm_int2_a.int2_fsm8; 10310 10311 val->fsm9 = fsm_int2_b.int2_fsm9; 10312 val->fsm10 = fsm_int2_b.int2_fsm10; 10313 val->fsm11 = fsm_int2_b.int2_fsm11; 10314 val->fsm12 = fsm_int2_b.int2_fsm12; 10315 val->fsm13 = fsm_int2_b.int2_fsm13; 10316 val->fsm14 = fsm_int2_b.int2_fsm14; 10317 val->fsm15 = fsm_int2_b.int2_fsm15; 10318 val->fsm16 = fsm_int2_b.int2_fsm16; 10319 10320 val->mlc1 = mlc_int2.int2_mlc1; 10321 val->mlc2 = mlc_int2.int2_mlc2; 10322 val->mlc3 = mlc_int2.int2_mlc3; 10323 val->mlc4 = mlc_int2.int2_mlc4; 10324 val->mlc5 = mlc_int2.int2_mlc5; 10325 val->mlc6 = mlc_int2.int2_mlc6; 10326 val->mlc7 = mlc_int2.int2_mlc7; 10327 val->mlc8 = mlc_int2.int2_mlc8; 10328 } 10329 10330 return ret; 10331 } 10332 10333 /** 10334 * @brief Get the status of all the interrupt sources.[get] 10335 * 10336 * @param ctx communication interface handler.(ptr) 10337 * @param val the status of all the interrupt sources.(ptr) 10338 * 10339 */ 10340 int32_t lsm6dsox_all_sources_get(lsm6dsox_ctx_t *ctx, 10341 lsm6dsox_all_sources_t *val) 10342 { 10343 lsm6dsox_emb_func_status_mainpage_t emb_func_status_mainpage; 10344 lsm6dsox_status_master_mainpage_t status_master_mainpage; 10345 lsm6dsox_fsm_status_a_mainpage_t fsm_status_a_mainpage; 10346 lsm6dsox_fsm_status_b_mainpage_t fsm_status_b_mainpage; 10347 lsm6dsox_mlc_status_mainpage_t mlc_status_mainpage; 10348 lsm6dsox_fifo_status1_t fifo_status1; 10349 lsm6dsox_fifo_status2_t fifo_status2; 10350 lsm6dsox_all_int_src_t all_int_src; 10351 lsm6dsox_wake_up_src_t wake_up_src; 10352 lsm6dsox_status_reg_t status_reg; 10353 lsm6dsox_tap_src_t tap_src; 10354 lsm6dsox_d6d_src_t d6d_src; 10355 lsm6dsox_ctrl5_c_t ctrl5_c; 10356 uint8_t reg[12]; 10357 int32_t ret; 10358 10359 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1); 10360 if (ret == 0) { 10361 ctrl5_c.rounding_status = PROPERTY_ENABLE; 10362 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1); 10363 } 10364 if (ret == 0) { 10365 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_ALL_INT_SRC, reg, 12); 10366 } 10367 10368 if (ret == 0) { 10369 bytecpy(( uint8_t*)&all_int_src, ®[0]); 10370 bytecpy(( uint8_t*)&wake_up_src, ®[1]); 10371 bytecpy(( uint8_t*)&tap_src, ®[2]); 10372 bytecpy(( uint8_t*)&d6d_src, ®[3]); 10373 bytecpy(( uint8_t*)&status_reg, ®[4]); 10374 bytecpy(( uint8_t*)&emb_func_status_mainpage, ®[5]); 10375 bytecpy(( uint8_t*)&fsm_status_a_mainpage, ®[6]); 10376 bytecpy(( uint8_t*)&fsm_status_b_mainpage, ®[7]); 10377 bytecpy(( uint8_t*)&mlc_status_mainpage, ®[8]); 10378 bytecpy(( uint8_t*)&status_master_mainpage, ®[9]); 10379 bytecpy(( uint8_t*)&fifo_status1, ®[10]); 10380 bytecpy(( uint8_t*)&fifo_status2, ®[11]); 10381 10382 val->timestamp = all_int_src.timestamp_endcount; 10383 10384 val->wake_up_z = wake_up_src.z_wu; 10385 val->wake_up_y = wake_up_src.y_wu; 10386 val->wake_up_x = wake_up_src.x_wu; 10387 val->wake_up = wake_up_src.wu_ia; 10388 val->sleep_state = wake_up_src.sleep_state; 10389 val->free_fall = wake_up_src.ff_ia; 10390 val->sleep_change = wake_up_src.sleep_change_ia; 10391 10392 val->tap_x = tap_src.x_tap; 10393 val->tap_y = tap_src.y_tap; 10394 val->tap_z = tap_src.z_tap; 10395 val->tap_sign = tap_src.tap_sign; 10396 val->double_tap = tap_src.double_tap; 10397 val->single_tap = tap_src.single_tap; 10398 10399 val->six_d_xl = d6d_src.xl; 10400 val->six_d_xh = d6d_src.xh; 10401 val->six_d_yl = d6d_src.yl; 10402 val->six_d_yh = d6d_src.yh; 10403 val->six_d_zl = d6d_src.zl; 10404 val->six_d_zh = d6d_src.zh; 10405 val->six_d = d6d_src.d6d_ia; 10406 val->den_flag = d6d_src.den_drdy; 10407 10408 val->drdy_xl = status_reg.xlda; 10409 val->drdy_g = status_reg.gda; 10410 val->drdy_temp = status_reg.tda; 10411 10412 val->step_detector = emb_func_status_mainpage.is_step_det; 10413 val->tilt = emb_func_status_mainpage.is_tilt; 10414 val->sig_mot = emb_func_status_mainpage.is_sigmot; 10415 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; 10416 10417 val->fsm1 = fsm_status_a_mainpage.is_fsm1; 10418 val->fsm2 = fsm_status_a_mainpage.is_fsm2; 10419 val->fsm3 = fsm_status_a_mainpage.is_fsm3; 10420 val->fsm4 = fsm_status_a_mainpage.is_fsm4; 10421 val->fsm5 = fsm_status_a_mainpage.is_fsm5; 10422 val->fsm6 = fsm_status_a_mainpage.is_fsm6; 10423 val->fsm7 = fsm_status_a_mainpage.is_fsm7; 10424 val->fsm8 = fsm_status_a_mainpage.is_fsm8; 10425 10426 val->fsm9 = fsm_status_b_mainpage.is_fsm9; 10427 val->fsm10 = fsm_status_b_mainpage.is_fsm10; 10428 val->fsm11 = fsm_status_b_mainpage.is_fsm11; 10429 val->fsm12 = fsm_status_b_mainpage.is_fsm12; 10430 val->fsm13 = fsm_status_b_mainpage.is_fsm13; 10431 val->fsm14 = fsm_status_b_mainpage.is_fsm14; 10432 val->fsm15 = fsm_status_b_mainpage.is_fsm15; 10433 val->fsm16 = fsm_status_b_mainpage.is_fsm16; 10434 10435 val->mlc1 = mlc_status_mainpage.is_mlc1; 10436 val->mlc2 = mlc_status_mainpage.is_mlc2; 10437 val->mlc3 = mlc_status_mainpage.is_mlc3; 10438 val->mlc4 = mlc_status_mainpage.is_mlc4; 10439 val->mlc5 = mlc_status_mainpage.is_mlc5; 10440 val->mlc6 = mlc_status_mainpage.is_mlc6; 10441 val->mlc7 = mlc_status_mainpage.is_mlc7; 10442 val->mlc8 = mlc_status_mainpage.is_mlc8; 10443 10444 val->sh_endop = status_master_mainpage.sens_hub_endop; 10445 val->sh_slave0_nack = status_master_mainpage.slave0_nack; 10446 val->sh_slave1_nack = status_master_mainpage.slave1_nack; 10447 val->sh_slave2_nack = status_master_mainpage.slave2_nack; 10448 val->sh_slave3_nack = status_master_mainpage.slave3_nack; 10449 val->sh_wr_once = status_master_mainpage.wr_once_done; 10450 10451 val->fifo_diff = (256U * fifo_status2.diff_fifo) + fifo_status1.diff_fifo; 10452 10453 val->fifo_ovr_latched = fifo_status2.over_run_latched; 10454 val->fifo_bdr = fifo_status2.counter_bdr_ia; 10455 val->fifo_full = fifo_status2.fifo_full_ia; 10456 val->fifo_ovr = fifo_status2.fifo_ovr_ia; 10457 val->fifo_th = fifo_status2.fifo_wtm_ia; 10458 10459 ctrl5_c.rounding_status = PROPERTY_DISABLE; 10460 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)&ctrl5_c, 1); 10461 10462 } 10463 10464 return ret; 10465 } 10466 10467 /** 10468 * @brief Sensor conversion parameters selection.[set] 10469 * 10470 * @param ctx communication interface handler. Use NULL to ingnore 10471 * this interface.(ptr) 10472 * @param aux_ctx auxiliary communication interface handler. Use NULL 10473 * to ingnore this interface.(ptr) 10474 * @param val set the sensor conversion parameters by checking 10475 * the constraints of the device.(ptr) 10476 * 10477 */ 10478 int32_t lsm6dsox_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 10479 lsm6dsox_md_t *val) 10480 { 10481 lsm6dsox_func_cfg_access_t func_cfg_access; 10482 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; 10483 lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois; 10484 lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois; 10485 lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois; 10486 lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois; 10487 lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois; 10488 lsm6dsox_ctrl1_xl_t ctrl1_xl; 10489 lsm6dsox_ctrl8_xl_t ctrl8_xl; 10490 lsm6dsox_ctrl2_g_t ctrl2_g; 10491 lsm6dsox_ctrl3_c_t ctrl3_c; 10492 lsm6dsox_ctrl4_c_t ctrl4_c; 10493 lsm6dsox_ctrl5_c_t ctrl5_c; 10494 lsm6dsox_ctrl6_c_t ctrl6_c; 10495 lsm6dsox_ctrl7_g_t ctrl7_g; 10496 uint8_t xl_hm_mode; 10497 uint8_t g_hm_mode; 10498 uint8_t xl_ulp_en; 10499 uint8_t odr_gy; 10500 uint8_t odr_xl; 10501 uint8_t reg[8]; 10502 int32_t ret; 10503 10504 ret = 0; 10505 10506 /* reading input configuration */ 10507 xl_hm_mode = ( (uint8_t)val->ui.xl.odr & 0x10U ) >> 4; 10508 xl_ulp_en = ( (uint8_t)val->ui.xl.odr & 0x20U ) >> 5; 10509 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU; 10510 10511 /* if enable xl ultra low power mode disable gy and OIS chain */ 10512 if (xl_ulp_en == PROPERTY_ENABLE) { 10513 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 10514 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 10515 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF; 10516 } 10517 /* if OIS xl is enabled also gyro OIS is enabled */ 10518 if (val->ois.xl.odr == LSM6DSOX_XL_OIS_6667Hz_HP){ 10519 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP; 10520 } 10521 g_hm_mode = ( (uint8_t)val->ui.gy.odr & 0x10U ) >> 4; 10522 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU; 10523 10524 /* reading registers to be configured */ 10525 if( ctx != NULL ) { 10526 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 8); 10527 bytecpy(( uint8_t*)&ctrl1_xl, ®[0]); 10528 bytecpy(( uint8_t*)&ctrl2_g, ®[1]); 10529 bytecpy(( uint8_t*)&ctrl3_c, ®[2]); 10530 bytecpy(( uint8_t*)&ctrl4_c, ®[3]); 10531 bytecpy(( uint8_t*)&ctrl5_c, ®[4]); 10532 bytecpy(( uint8_t*)&ctrl6_c, ®[5]); 10533 bytecpy(( uint8_t*)&ctrl7_g, ®[6]); 10534 bytecpy(( uint8_t*)&ctrl8_xl, ®[7]); 10535 if ( ret == 0 ) { 10536 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, 10537 (uint8_t*)&func_cfg_access, 1); 10538 } 10539 /* if toggle xl ultra low power mode, turn off xl before reconfigure */ 10540 if (ctrl5_c.xl_ulp_en != xl_ulp_en) { 10541 ctrl1_xl.odr_xl = (uint8_t) 0x00U; 10542 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, 10543 (uint8_t*)&ctrl1_xl, 1); 10544 } 10545 } 10546 10547 /* reading OIS registers to be configured */ 10548 if( aux_ctx != NULL ) { 10549 if (ret == 0) { 10550 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3); 10551 } 10552 bytecpy(( uint8_t*)&spi2_ctrl1_ois, ®[0]); 10553 bytecpy(( uint8_t*)&spi2_ctrl2_ois, ®[1]); 10554 bytecpy(( uint8_t*)&spi2_ctrl3_ois, ®[2]); 10555 } 10556 else { 10557 if( ctx != NULL ) { 10558 if (ret == 0) { 10559 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3); 10560 } 10561 bytecpy(( uint8_t*)&ui_ctrl1_ois, ®[0]); 10562 bytecpy(( uint8_t*)&ui_ctrl2_ois, ®[1]); 10563 bytecpy(( uint8_t*)&ui_ctrl3_ois, ®[2]); 10564 } 10565 } 10566 10567 /* Check the Finite State Machine data rate constraints */ 10568 if (val->fsm.sens != LSM6DSOX_FSM_DISABLE) { 10569 switch (val->fsm.odr) { 10570 case LSM6DSOX_FSM_12Hz5: 10571 if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl == 0x00U) ) { 10572 odr_xl = 0x01U; 10573 } 10574 if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy == 0x00U) ) { 10575 xl_ulp_en = PROPERTY_DISABLE; 10576 odr_gy = 0x01U; 10577 } 10578 break; 10579 case LSM6DSOX_FSM_26Hz: 10580 if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x02U) ) { 10581 odr_xl = 0x02U; 10582 } 10583 if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x02U) ) { 10584 xl_ulp_en = PROPERTY_DISABLE; 10585 odr_gy = 0x02U; 10586 } 10587 break; 10588 case LSM6DSOX_FSM_52Hz: 10589 if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x03U) ) { 10590 odr_xl = 0x03U; 10591 } 10592 if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x03U) ) { 10593 xl_ulp_en = PROPERTY_DISABLE; 10594 odr_gy = 0x03U; 10595 } 10596 break; 10597 case LSM6DSOX_FSM_104Hz: 10598 if ( (val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x04U) ) { 10599 odr_xl = 0x04U; 10600 } 10601 if ( (val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x04U) ) { 10602 xl_ulp_en = PROPERTY_DISABLE; 10603 odr_gy = 0x04U; 10604 } 10605 break; 10606 default: 10607 odr_xl = 0x00U; 10608 odr_gy = 0x00U; 10609 break; 10610 } 10611 } 10612 10613 /* Check the Machine Learning Core data rate constraints */ 10614 if (val->mlc.sens != LSM6DSOX_MLC_DISABLE) { 10615 switch (val->mlc.odr) { 10616 case LSM6DSOX_MLC_12Hz5: 10617 if (odr_xl == 0x00U) { 10618 odr_xl = 0x01U; 10619 } 10620 if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy == 0x00U) ) { 10621 xl_ulp_en = PROPERTY_DISABLE; 10622 odr_gy = 0x01U; 10623 } 10624 break; 10625 case LSM6DSOX_MLC_26Hz: 10626 if (odr_xl < 0x02U) { 10627 odr_xl = 0x02U; 10628 } 10629 if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x02U) ) { 10630 xl_ulp_en = PROPERTY_DISABLE; 10631 odr_gy = 0x02U; 10632 } 10633 break; 10634 case LSM6DSOX_MLC_52Hz: 10635 if (odr_xl < 0x03U) { 10636 odr_xl = 0x03U; 10637 } 10638 if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x03U) ) { 10639 xl_ulp_en = PROPERTY_DISABLE; 10640 odr_gy = 0x03U; 10641 } 10642 break; 10643 case LSM6DSOX_MLC_104Hz: 10644 if (odr_xl < 0x04U) { 10645 odr_xl = 0x04U; 10646 } 10647 if ( (val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x04U) ) { 10648 xl_ulp_en = PROPERTY_DISABLE; 10649 odr_gy = 0x04U; 10650 } 10651 break; 10652 default: 10653 odr_xl = 0x00U; 10654 odr_gy = 0x00U; 10655 break; 10656 } 10657 } 10658 10659 /* Updating the accelerometer data rate configuration */ 10660 switch ( ( ctrl5_c.xl_ulp_en << 5 ) | ( ctrl6_c.xl_hm_mode << 4 ) | 10661 ctrl1_xl.odr_xl ) { 10662 case LSM6DSOX_XL_UI_OFF: 10663 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF; 10664 break; 10665 case LSM6DSOX_XL_UI_12Hz5_HP: 10666 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP; 10667 break; 10668 case LSM6DSOX_XL_UI_26Hz_HP: 10669 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP; 10670 break; 10671 case LSM6DSOX_XL_UI_52Hz_HP: 10672 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP; 10673 break; 10674 case LSM6DSOX_XL_UI_104Hz_HP: 10675 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP; 10676 break; 10677 case LSM6DSOX_XL_UI_208Hz_HP: 10678 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP; 10679 break; 10680 case LSM6DSOX_XL_UI_416Hz_HP: 10681 val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP; 10682 break; 10683 case LSM6DSOX_XL_UI_833Hz_HP: 10684 val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP; 10685 break; 10686 case LSM6DSOX_XL_UI_1667Hz_HP: 10687 val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP; 10688 break; 10689 case LSM6DSOX_XL_UI_3333Hz_HP: 10690 val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP; 10691 break; 10692 case LSM6DSOX_XL_UI_6667Hz_HP: 10693 val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP; 10694 break; 10695 case LSM6DSOX_XL_UI_1Hz6_LP: 10696 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP; 10697 break; 10698 case LSM6DSOX_XL_UI_12Hz5_LP: 10699 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP; 10700 break; 10701 case LSM6DSOX_XL_UI_26Hz_LP: 10702 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP; 10703 break; 10704 case LSM6DSOX_XL_UI_52Hz_LP: 10705 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP; 10706 break; 10707 case LSM6DSOX_XL_UI_104Hz_NM: 10708 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM; 10709 break; 10710 case LSM6DSOX_XL_UI_208Hz_NM: 10711 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM; 10712 break; 10713 case LSM6DSOX_XL_UI_1Hz6_ULP: 10714 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP; 10715 break; 10716 case LSM6DSOX_XL_UI_12Hz5_ULP: 10717 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP; 10718 break; 10719 case LSM6DSOX_XL_UI_26Hz_ULP: 10720 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP; 10721 break; 10722 case LSM6DSOX_XL_UI_52Hz_ULP: 10723 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP; 10724 break; 10725 case LSM6DSOX_XL_UI_104Hz_ULP: 10726 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP; 10727 break; 10728 case LSM6DSOX_XL_UI_208Hz_ULP: 10729 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP; 10730 break; 10731 default: 10732 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF; 10733 break; 10734 } 10735 10736 /* Updating the accelerometer data rate configuration */ 10737 switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) { 10738 case LSM6DSOX_GY_UI_OFF: 10739 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF; 10740 break; 10741 case LSM6DSOX_GY_UI_12Hz5_LP: 10742 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP; 10743 break; 10744 case LSM6DSOX_GY_UI_12Hz5_HP: 10745 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP; 10746 break; 10747 case LSM6DSOX_GY_UI_26Hz_LP: 10748 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP; 10749 break; 10750 case LSM6DSOX_GY_UI_26Hz_HP: 10751 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP; 10752 break; 10753 case LSM6DSOX_GY_UI_52Hz_LP: 10754 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP; 10755 break; 10756 case LSM6DSOX_GY_UI_52Hz_HP: 10757 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP; 10758 break; 10759 case LSM6DSOX_GY_UI_104Hz_NM: 10760 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM; 10761 break; 10762 case LSM6DSOX_GY_UI_104Hz_HP: 10763 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP; 10764 break; 10765 case LSM6DSOX_GY_UI_208Hz_NM: 10766 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM; 10767 break; 10768 case LSM6DSOX_GY_UI_208Hz_HP: 10769 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP; 10770 break; 10771 case LSM6DSOX_GY_UI_416Hz_HP: 10772 val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP; 10773 break; 10774 case LSM6DSOX_GY_UI_833Hz_HP: 10775 val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP; 10776 break; 10777 case LSM6DSOX_GY_UI_1667Hz_HP: 10778 val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP; 10779 break; 10780 case LSM6DSOX_GY_UI_3333Hz_HP: 10781 val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP; 10782 break; 10783 case LSM6DSOX_GY_UI_6667Hz_HP: 10784 val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP; 10785 break; 10786 default: 10787 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF; 10788 break; 10789 } 10790 10791 /* Check accelerometer full scale constraints */ 10792 /* Full scale of 16g must be the same for UI and OIS */ 10793 if ( (val->ui.xl.fs == LSM6DSOX_XL_UI_16g) || 10794 (val->ois.xl.fs == LSM6DSOX_XL_OIS_16g) ){ 10795 val->ui.xl.fs = LSM6DSOX_XL_UI_16g; 10796 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g; 10797 } 10798 10799 /* prapare new configuration */ 10800 10801 /* Full scale of 16g must be the same for UI and OIS */ 10802 if (val->ui.xl.fs == LSM6DSOX_XL_UI_16g) { 10803 ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE; 10804 } 10805 else { 10806 ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE; 10807 } 10808 10809 /* OIS new configuration */ 10810 ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U; 10811 func_cfg_access.ois_ctrl_from_ui = (val->ois.ctrl_md & 0x02U) >> 1; 10812 10813 switch (val->ois.ctrl_md) { 10814 case LSM6DSOX_OIS_ONLY_AUX: 10815 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10816 spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10817 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10818 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10819 break; 10820 case LSM6DSOX_OIS_ONLY_UI: 10821 ui_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10822 ui_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10823 ui_ctrl1_ois.mode4_en = (uint8_t)val->ois.xl.odr; 10824 ui_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10825 break; 10826 case LSM6DSOX_OIS_MIXED: 10827 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10828 ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10829 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10830 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10831 break; 10832 default: 10833 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10834 spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10835 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10836 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10837 break; 10838 } 10839 10840 /* UI new configuration */ 10841 ctrl1_xl.odr_xl = odr_xl; 10842 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs; 10843 ctrl5_c.xl_ulp_en = xl_ulp_en; 10844 ctrl6_c.xl_hm_mode = xl_hm_mode; 10845 ctrl7_g.g_hm_mode = g_hm_mode; 10846 ctrl2_g.odr_g = odr_gy; 10847 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs; 10848 10849 /* writing checked configuration */ 10850 if( ctx != NULL ) { 10851 bytecpy(®[0], ( uint8_t*)&ctrl1_xl); 10852 bytecpy(®[1], ( uint8_t*)&ctrl2_g); 10853 bytecpy(®[2], ( uint8_t*)&ctrl3_c); 10854 bytecpy(®[3], ( uint8_t*)&ctrl4_c); 10855 bytecpy(®[4], ( uint8_t*)&ctrl5_c); 10856 bytecpy(®[5], ( uint8_t*)&ctrl6_c); 10857 bytecpy(®[6], ( uint8_t*)&ctrl7_g); 10858 bytecpy(®[7], ( uint8_t*)&ctrl8_xl); 10859 if ( ret == 0 ) { 10860 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 8); 10861 } 10862 if ( ret == 0 ) { 10863 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, 10864 (uint8_t*)&func_cfg_access, 1); 10865 } 10866 } 10867 10868 /* writing OIS checked configuration */ 10869 if( aux_ctx != NULL ) { 10870 bytecpy(®[0], ( uint8_t*)&spi2_ctrl1_ois); 10871 bytecpy(®[1], ( uint8_t*)&spi2_ctrl2_ois); 10872 bytecpy(®[2], ( uint8_t*)&spi2_ctrl3_ois); 10873 if (ret == 0) { 10874 ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3); 10875 } 10876 } 10877 else { 10878 if( ctx != NULL ) { 10879 bytecpy(®[0], ( uint8_t*)&ui_ctrl1_ois); 10880 bytecpy(®[1], ( uint8_t*)&ui_ctrl2_ois); 10881 bytecpy(®[2], ( uint8_t*)&ui_ctrl3_ois); 10882 if (ret == 0) { 10883 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3); 10884 } 10885 } 10886 } 10887 10888 return ret; 10889 } 10890 10891 /** 10892 * @brief Sensor conversion parameters selection.[get] 10893 * 10894 * @param ctx communication interface handler. Use NULL to ingnore 10895 * this interface.(ptr) 10896 * @param aux_ctx auxiliary communication interface handler. Use NULL 10897 * to ingnore this interface.(ptr) 10898 * @param val get the sensor conversion parameters.(ptr) 10899 * 10900 */ 10901 int32_t lsm6dsox_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 10902 lsm6dsox_md_t *val) 10903 { 10904 10905 lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 10906 lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 10907 lsm6dsox_func_cfg_access_t func_cfg_access; 10908 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; 10909 lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois; 10910 lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois; 10911 lsm6dsox_emb_func_en_b_t emb_func_en_b; 10912 lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois; 10913 lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois; 10914 lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois; 10915 lsm6dsox_fsm_enable_a_t fsm_enable_a; 10916 lsm6dsox_fsm_enable_b_t fsm_enable_b; 10917 lsm6dsox_ctrl1_xl_t ctrl1_xl; 10918 lsm6dsox_ctrl2_g_t ctrl2_g; 10919 lsm6dsox_ctrl3_c_t ctrl3_c; 10920 lsm6dsox_ctrl4_c_t ctrl4_c; 10921 lsm6dsox_ctrl5_c_t ctrl5_c; 10922 lsm6dsox_ctrl6_c_t ctrl6_c; 10923 lsm6dsox_ctrl7_g_t ctrl7_g; 10924 10925 uint8_t reg[8]; 10926 int32_t ret; 10927 10928 ret = 0; 10929 10930 /* reading the registers of the device */ 10931 if( ctx != NULL ) { 10932 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 7); 10933 bytecpy(( uint8_t*)&ctrl1_xl, ®[0]); 10934 bytecpy(( uint8_t*)&ctrl2_g, ®[1]); 10935 bytecpy(( uint8_t*)&ctrl3_c, ®[2]); 10936 bytecpy(( uint8_t*)&ctrl4_c, ®[3]); 10937 bytecpy(( uint8_t*)&ctrl5_c, ®[4]); 10938 bytecpy(( uint8_t*)&ctrl6_c, ®[5]); 10939 bytecpy(( uint8_t*)&ctrl7_g, ®[6]); 10940 if ( ret == 0 ) { 10941 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, 10942 (uint8_t*)&func_cfg_access, 1); 10943 } 10944 if (ret == 0) { 10945 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 10946 } 10947 if (ret == 0) { 10948 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, reg, 2); 10949 bytecpy(( uint8_t*)&emb_func_odr_cfg_b, ®[0]); 10950 bytecpy(( uint8_t*)&emb_func_odr_cfg_c, ®[1]); 10951 } 10952 if (ret == 0) { 10953 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, 10954 (uint8_t*)&emb_func_en_b, 1); 10955 } 10956 if (ret == 0) { 10957 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, reg, 2); 10958 bytecpy(( uint8_t*)&fsm_enable_a, ®[0]); 10959 bytecpy(( uint8_t*)&fsm_enable_b, ®[1]); 10960 } 10961 if (ret == 0) { 10962 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 10963 } 10964 } 10965 10966 if( aux_ctx != NULL ) { 10967 if (ret == 0) { 10968 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3); 10969 } 10970 bytecpy(( uint8_t*)&spi2_ctrl1_ois, ®[0]); 10971 bytecpy(( uint8_t*)&spi2_ctrl2_ois, ®[1]); 10972 bytecpy(( uint8_t*)&spi2_ctrl3_ois, ®[2]); 10973 } 10974 else { 10975 if( ctx != NULL ) { 10976 if (ret == 0) { 10977 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3); 10978 } 10979 bytecpy(( uint8_t*)&ui_ctrl1_ois, ®[0]); 10980 bytecpy(( uint8_t*)&ui_ctrl2_ois, ®[1]); 10981 bytecpy(( uint8_t*)&ui_ctrl3_ois, ®[2]); 10982 } 10983 } 10984 10985 /* fill the input structure */ 10986 10987 /* get accelerometer configuration */ 10988 switch ( (ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) | 10989 ctrl1_xl.odr_xl ) { 10990 case LSM6DSOX_XL_UI_OFF: 10991 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF; 10992 break; 10993 case LSM6DSOX_XL_UI_12Hz5_HP: 10994 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP; 10995 break; 10996 case LSM6DSOX_XL_UI_26Hz_HP: 10997 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP; 10998 break; 10999 case LSM6DSOX_XL_UI_52Hz_HP: 11000 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP; 11001 break; 11002 case LSM6DSOX_XL_UI_104Hz_HP: 11003 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP; 11004 break; 11005 case LSM6DSOX_XL_UI_208Hz_HP: 11006 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP; 11007 break; 11008 case LSM6DSOX_XL_UI_416Hz_HP: 11009 val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP; 11010 break; 11011 case LSM6DSOX_XL_UI_833Hz_HP: 11012 val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP; 11013 break; 11014 case LSM6DSOX_XL_UI_1667Hz_HP: 11015 val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP; 11016 break; 11017 case LSM6DSOX_XL_UI_3333Hz_HP: 11018 val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP; 11019 break; 11020 case LSM6DSOX_XL_UI_6667Hz_HP: 11021 val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP; 11022 break; 11023 case LSM6DSOX_XL_UI_1Hz6_LP: 11024 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP; 11025 break; 11026 case LSM6DSOX_XL_UI_12Hz5_LP: 11027 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP; 11028 break; 11029 case LSM6DSOX_XL_UI_26Hz_LP: 11030 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP; 11031 break; 11032 case LSM6DSOX_XL_UI_52Hz_LP: 11033 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP; 11034 break; 11035 case LSM6DSOX_XL_UI_104Hz_NM: 11036 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM; 11037 break; 11038 case LSM6DSOX_XL_UI_208Hz_NM: 11039 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM; 11040 break; 11041 case LSM6DSOX_XL_UI_1Hz6_ULP: 11042 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP; 11043 break; 11044 case LSM6DSOX_XL_UI_12Hz5_ULP: 11045 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP; 11046 break; 11047 case LSM6DSOX_XL_UI_26Hz_ULP: 11048 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP; 11049 break; 11050 case LSM6DSOX_XL_UI_52Hz_ULP: 11051 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP; 11052 break; 11053 case LSM6DSOX_XL_UI_104Hz_ULP: 11054 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP; 11055 break; 11056 case LSM6DSOX_XL_UI_208Hz_ULP: 11057 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP; 11058 break; 11059 default: 11060 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF; 11061 break; 11062 } 11063 11064 switch ( ctrl1_xl.fs_xl ) { 11065 case LSM6DSOX_XL_UI_2g: 11066 val->ui.xl.fs = LSM6DSOX_XL_UI_2g; 11067 break; 11068 case LSM6DSOX_XL_UI_4g: 11069 val->ui.xl.fs = LSM6DSOX_XL_UI_4g; 11070 break; 11071 case LSM6DSOX_XL_UI_8g: 11072 val->ui.xl.fs = LSM6DSOX_XL_UI_8g; 11073 break; 11074 case LSM6DSOX_XL_UI_16g: 11075 val->ui.xl.fs = LSM6DSOX_XL_UI_16g; 11076 break; 11077 default: 11078 val->ui.xl.fs = LSM6DSOX_XL_UI_2g; 11079 break; 11080 } 11081 11082 /* get gyroscope configuration */ 11083 switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) { 11084 case LSM6DSOX_GY_UI_OFF: 11085 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF; 11086 break; 11087 case LSM6DSOX_GY_UI_12Hz5_LP: 11088 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP; 11089 break; 11090 case LSM6DSOX_GY_UI_12Hz5_HP: 11091 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP; 11092 break; 11093 case LSM6DSOX_GY_UI_26Hz_LP: 11094 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP; 11095 break; 11096 case LSM6DSOX_GY_UI_26Hz_HP: 11097 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP; 11098 break; 11099 case LSM6DSOX_GY_UI_52Hz_LP: 11100 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP; 11101 break; 11102 case LSM6DSOX_GY_UI_52Hz_HP: 11103 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP; 11104 break; 11105 case LSM6DSOX_GY_UI_104Hz_NM: 11106 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM; 11107 break; 11108 case LSM6DSOX_GY_UI_104Hz_HP: 11109 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP; 11110 break; 11111 case LSM6DSOX_GY_UI_208Hz_NM: 11112 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM; 11113 break; 11114 case LSM6DSOX_GY_UI_208Hz_HP: 11115 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP; 11116 break; 11117 case LSM6DSOX_GY_UI_416Hz_HP: 11118 val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP; 11119 break; 11120 case LSM6DSOX_GY_UI_833Hz_HP: 11121 val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP; 11122 break; 11123 case LSM6DSOX_GY_UI_1667Hz_HP: 11124 val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP; 11125 break; 11126 case LSM6DSOX_GY_UI_3333Hz_HP: 11127 val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP; 11128 break; 11129 case LSM6DSOX_GY_UI_6667Hz_HP: 11130 val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP; 11131 break; 11132 default: 11133 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF; 11134 break; 11135 } 11136 11137 switch (ctrl2_g.fs_g) { 11138 case LSM6DSOX_GY_UI_125dps: 11139 val->ui.gy.fs = LSM6DSOX_GY_UI_125dps; 11140 break; 11141 case LSM6DSOX_GY_UI_250dps: 11142 val->ui.gy.fs = LSM6DSOX_GY_UI_250dps; 11143 break; 11144 case LSM6DSOX_GY_UI_500dps: 11145 val->ui.gy.fs = LSM6DSOX_GY_UI_500dps; 11146 break; 11147 case LSM6DSOX_GY_UI_1000dps: 11148 val->ui.gy.fs = LSM6DSOX_GY_UI_1000dps; 11149 break; 11150 case LSM6DSOX_GY_UI_2000dps: 11151 val->ui.gy.fs = LSM6DSOX_GY_UI_2000dps; 11152 break; 11153 default: 11154 val->ui.gy.fs = LSM6DSOX_GY_UI_125dps; 11155 break; 11156 } 11157 11158 /* get finite state machine configuration */ 11159 if ( (fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en | fsm_enable_a.fsm3_en | 11160 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en | 11161 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en | 11162 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en | 11163 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en | 11164 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en | 11165 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE ){ 11166 switch (emb_func_odr_cfg_b.fsm_odr) { 11167 case LSM6DSOX_FSM_12Hz5: 11168 val->fsm.odr = LSM6DSOX_FSM_12Hz5; 11169 break; 11170 case LSM6DSOX_FSM_26Hz: 11171 val->fsm.odr = LSM6DSOX_FSM_26Hz; 11172 break; 11173 case LSM6DSOX_FSM_52Hz: 11174 val->fsm.odr = LSM6DSOX_FSM_52Hz; 11175 break; 11176 case LSM6DSOX_FSM_104Hz: 11177 val->fsm.odr = LSM6DSOX_FSM_104Hz; 11178 break; 11179 default: 11180 val->fsm.odr = LSM6DSOX_FSM_12Hz5; 11181 break; 11182 } 11183 11184 val->fsm.sens = LSM6DSOX_FSM_XL_GY; 11185 if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF) { 11186 val->fsm.sens = LSM6DSOX_FSM_XL; 11187 } 11188 if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF) { 11189 val->fsm.sens = LSM6DSOX_FSM_GY; 11190 } 11191 } 11192 else { 11193 val->fsm.sens = LSM6DSOX_FSM_DISABLE; 11194 } 11195 11196 /* get machine learning core configuration */ 11197 if (emb_func_en_b.mlc_en == PROPERTY_ENABLE) { 11198 switch (emb_func_odr_cfg_c.mlc_odr) { 11199 case LSM6DSOX_MLC_12Hz5: 11200 val->mlc.odr = LSM6DSOX_MLC_12Hz5; 11201 break; 11202 case LSM6DSOX_MLC_26Hz: 11203 val->mlc.odr = LSM6DSOX_MLC_26Hz; 11204 break; 11205 case LSM6DSOX_MLC_52Hz: 11206 val->mlc.odr = LSM6DSOX_MLC_52Hz; 11207 break; 11208 case LSM6DSOX_MLC_104Hz: 11209 val->mlc.odr = LSM6DSOX_MLC_104Hz; 11210 break; 11211 default: 11212 val->mlc.odr = LSM6DSOX_MLC_12Hz5; 11213 break; 11214 } 11215 11216 val->mlc.sens = LSM6DSOX_MLC_XL_GY; 11217 if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF) { 11218 val->mlc.sens = LSM6DSOX_MLC_XL; 11219 } 11220 if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF) { 11221 val->mlc.sens = LSM6DSOX_MLC_DISABLE; 11222 } 11223 } 11224 else { 11225 val->mlc.sens = LSM6DSOX_MLC_DISABLE; 11226 } 11227 11228 /* get ois configuration */ 11229 11230 /* OIS configuration mode */ 11231 switch ( (func_cfg_access.ois_ctrl_from_ui << 1) + ctrl7_g.ois_on_en ) { 11232 case LSM6DSOX_OIS_ONLY_AUX: 11233 switch ( spi2_ctrl3_ois.fs_xl_ois ) { 11234 case LSM6DSOX_XL_OIS_2g: 11235 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g; 11236 break; 11237 case LSM6DSOX_XL_OIS_4g: 11238 val->ois.xl.fs = LSM6DSOX_XL_OIS_4g; 11239 break; 11240 case LSM6DSOX_XL_OIS_8g: 11241 val->ois.xl.fs = LSM6DSOX_XL_OIS_8g; 11242 break; 11243 case LSM6DSOX_XL_OIS_16g: 11244 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g; 11245 break; 11246 default: 11247 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g; 11248 break; 11249 } 11250 switch ( spi2_ctrl1_ois.mode4_en ) { 11251 case LSM6DSOX_XL_OIS_OFF: 11252 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 11253 break; 11254 case LSM6DSOX_XL_OIS_6667Hz_HP: 11255 val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP; 11256 break; 11257 default: 11258 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 11259 break; 11260 } 11261 switch ( spi2_ctrl1_ois.fs_g_ois ) { 11262 case LSM6DSOX_GY_OIS_250dps: 11263 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps; 11264 break; 11265 case LSM6DSOX_GY_OIS_500dps: 11266 val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps; 11267 break; 11268 case LSM6DSOX_GY_OIS_1000dps: 11269 val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps; 11270 break; 11271 case LSM6DSOX_GY_OIS_2000dps: 11272 val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps; 11273 break; 11274 default: 11275 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps; 11276 break; 11277 } 11278 switch ( spi2_ctrl1_ois.ois_en_spi2 ) { 11279 case LSM6DSOX_GY_OIS_OFF: 11280 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 11281 break; 11282 case LSM6DSOX_GY_OIS_6667Hz_HP: 11283 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP; 11284 break; 11285 default: 11286 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 11287 break; 11288 } 11289 val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX; 11290 break; 11291 case LSM6DSOX_OIS_ONLY_UI: 11292 switch ( ui_ctrl3_ois.fs_xl_ois ) { 11293 case LSM6DSOX_XL_OIS_2g: 11294 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g; 11295 break; 11296 case LSM6DSOX_XL_OIS_4g: 11297 val->ois.xl.fs = LSM6DSOX_XL_OIS_4g; 11298 break; 11299 case LSM6DSOX_XL_OIS_8g: 11300 val->ois.xl.fs = LSM6DSOX_XL_OIS_8g; 11301 break; 11302 case LSM6DSOX_XL_OIS_16g: 11303 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g; 11304 break; 11305 default: 11306 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g; 11307 break; 11308 } 11309 switch ( ui_ctrl1_ois.ois_en_spi2 ) { 11310 case LSM6DSOX_GY_OIS_OFF: 11311 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 11312 break; 11313 case LSM6DSOX_GY_OIS_6667Hz_HP: 11314 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP; 11315 break; 11316 default: 11317 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 11318 break; 11319 } 11320 switch ( ui_ctrl1_ois.fs_g_ois ) { 11321 case LSM6DSOX_GY_OIS_250dps: 11322 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps; 11323 break; 11324 case LSM6DSOX_GY_OIS_125dps: 11325 val->ois.gy.fs = LSM6DSOX_GY_OIS_125dps; 11326 break; 11327 case LSM6DSOX_GY_OIS_500dps: 11328 val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps; 11329 break; 11330 case LSM6DSOX_GY_OIS_1000dps: 11331 val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps; 11332 break; 11333 case LSM6DSOX_GY_OIS_2000dps: 11334 val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps; 11335 break; 11336 default: 11337 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps; 11338 break; 11339 } 11340 switch ( ui_ctrl1_ois.mode4_en ) { 11341 case LSM6DSOX_XL_OIS_OFF: 11342 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 11343 break; 11344 case LSM6DSOX_XL_OIS_6667Hz_HP: 11345 val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP; 11346 break; 11347 default: 11348 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 11349 break; 11350 } 11351 val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_UI; 11352 break; 11353 case LSM6DSOX_OIS_MIXED: 11354 switch ( spi2_ctrl3_ois.fs_xl_ois ) { 11355 case LSM6DSOX_XL_OIS_2g: 11356 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g; 11357 break; 11358 case LSM6DSOX_XL_OIS_4g: 11359 val->ois.xl.fs = LSM6DSOX_XL_OIS_4g; 11360 break; 11361 case LSM6DSOX_XL_OIS_8g: 11362 val->ois.xl.fs = LSM6DSOX_XL_OIS_8g; 11363 break; 11364 case LSM6DSOX_XL_OIS_16g: 11365 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g; 11366 break; 11367 default: 11368 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g; 11369 break; 11370 } 11371 switch ( spi2_ctrl1_ois.mode4_en ) { 11372 case LSM6DSOX_XL_OIS_OFF: 11373 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 11374 break; 11375 case LSM6DSOX_XL_OIS_6667Hz_HP: 11376 val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP; 11377 break; 11378 default: 11379 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF; 11380 break; 11381 } 11382 switch ( spi2_ctrl1_ois.fs_g_ois ) { 11383 case LSM6DSOX_GY_OIS_250dps: 11384 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps; 11385 break; 11386 case LSM6DSOX_GY_OIS_500dps: 11387 val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps; 11388 break; 11389 case LSM6DSOX_GY_OIS_1000dps: 11390 val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps; 11391 break; 11392 case LSM6DSOX_GY_OIS_2000dps: 11393 val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps; 11394 break; 11395 default: 11396 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps; 11397 break; 11398 } 11399 switch ( ui_ctrl1_ois.ois_en_spi2 ) { 11400 case LSM6DSOX_GY_OIS_OFF: 11401 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 11402 break; 11403 case LSM6DSOX_GY_OIS_6667Hz_HP: 11404 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP; 11405 break; 11406 default: 11407 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF; 11408 break; 11409 } 11410 val->ois.ctrl_md = LSM6DSOX_OIS_MIXED; 11411 break; 11412 default: 11413 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 11414 spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 11415 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 11416 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 11417 val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX; 11418 break; 11419 } 11420 11421 return ret; 11422 } 11423 11424 /** 11425 * @brief Read data in engineering unit.[get] 11426 * 11427 * @param ctx communication interface handler.(ptr) 11428 * @param md the sensor conversion parameters.(ptr) 11429 * 11430 */ 11431 int32_t lsm6dsox_data_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ctx_t *aux_ctx, 11432 lsm6dsox_md_t *md, lsm6dsox_data_t *data) 11433 { 11434 uint8_t buff[14]; 11435 int32_t ret; 11436 uint8_t i; 11437 uint8_t j; 11438 11439 ret = 0; 11440 11441 /* read data */ 11442 if( ctx != NULL ) { 11443 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 14); 11444 } 11445 j = 0; 11446 11447 /* temperature conversion */ 11448 data->ui.heat.raw = (int16_t)buff[j+1U]; 11449 data->ui.heat.raw = ( ((int16_t)data->ui.heat.raw * (int16_t)256) + 11450 (int16_t)buff[j] ); 11451 j+=2U; 11452 data->ui.heat.deg_c = lsm6dsox_from_lsb_to_celsius((int16_t)data->ui.heat.raw); 11453 11454 /* angular rate conversion */ 11455 for (i = 0U; i < 3U; i++) { 11456 data->ui.gy.raw[i] = (int16_t)buff[j+1U]; 11457 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j]; 11458 j+=2U; 11459 switch ( md->ui.gy.fs ) { 11460 case LSM6DSOX_GY_UI_250dps: 11461 data->ui.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ui.gy.raw[i]); 11462 break; 11463 case LSM6DSOX_GY_UI_125dps: 11464 data->ui.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ui.gy.raw[i]); 11465 break; 11466 case LSM6DSOX_GY_UI_500dps: 11467 data->ui.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ui.gy.raw[i]); 11468 break; 11469 case LSM6DSOX_GY_UI_1000dps: 11470 data->ui.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(data->ui.gy.raw[i]); 11471 break; 11472 case LSM6DSOX_GY_UI_2000dps: 11473 data->ui.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(data->ui.gy.raw[i]); 11474 break; 11475 default: 11476 data->ui.gy.mdps[i] = 0.0f; 11477 break; 11478 } 11479 } 11480 11481 /* acceleration conversion */ 11482 for (i = 0U; i < 3U; i++) { 11483 data->ui.xl.raw[i] = (int16_t)buff[j+1U]; 11484 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j]; 11485 j+=2U; 11486 switch ( md->ui.xl.fs ) { 11487 case LSM6DSOX_XL_UI_2g: 11488 data->ui.xl.mg[i] =lsm6dsox_from_fs2_to_mg(data->ui.xl.raw[i]); 11489 break; 11490 case LSM6DSOX_XL_UI_4g: 11491 data->ui.xl.mg[i] =lsm6dsox_from_fs4_to_mg(data->ui.xl.raw[i]); 11492 break; 11493 case LSM6DSOX_XL_UI_8g: 11494 data->ui.xl.mg[i] =lsm6dsox_from_fs8_to_mg(data->ui.xl.raw[i]); 11495 break; 11496 case LSM6DSOX_XL_UI_16g: 11497 data->ui.xl.mg[i] =lsm6dsox_from_fs16_to_mg(data->ui.xl.raw[i]); 11498 break; 11499 default: 11500 data->ui.xl.mg[i] = 0.0f; 11501 break; 11502 } 11503 11504 } 11505 11506 /* read data from ois chain */ 11507 if (aux_ctx != NULL) { 11508 if (ret == 0) { 11509 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 12); 11510 } 11511 } 11512 else { 11513 if ((ctx != NULL) && (md->ois.ctrl_md == LSM6DSOX_OIS_ONLY_UI)) { 11514 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 12); 11515 } 11516 } 11517 j = 0; 11518 11519 /* ois angular rate conversion */ 11520 for (i = 0U; i < 3U; i++) { 11521 data->ois.gy.raw[i] = (int16_t) buff[j+1U]; 11522 data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j]; 11523 j+=2U; 11524 switch ( md->ois.gy.fs ) { 11525 case LSM6DSOX_GY_UI_250dps: 11526 data->ois.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ois.gy.raw[i]); 11527 break; 11528 case LSM6DSOX_GY_UI_125dps: 11529 data->ois.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ois.gy.raw[i]); 11530 break; 11531 case LSM6DSOX_GY_UI_500dps: 11532 data->ois.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ois.gy.raw[i]); 11533 break; 11534 case LSM6DSOX_GY_UI_1000dps: 11535 data->ois.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(data->ois.gy.raw[i]); 11536 break; 11537 case LSM6DSOX_GY_UI_2000dps: 11538 data->ois.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(data->ois.gy.raw[i]); 11539 break; 11540 default: 11541 data->ois.gy.mdps[i] = 0.0f; 11542 break; 11543 } 11544 } 11545 11546 /* ois acceleration conversion */ 11547 for (i = 0U; i < 3U; i++) { 11548 data->ois.xl.raw[i] = (int16_t) buff[j+1U]; 11549 data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j]; 11550 j+=2U; 11551 switch ( md->ois.xl.fs ) { 11552 case LSM6DSOX_XL_UI_2g: 11553 data->ois.xl.mg[i] =lsm6dsox_from_fs2_to_mg(data->ois.xl.raw[i]); 11554 break; 11555 case LSM6DSOX_XL_UI_4g: 11556 data->ois.xl.mg[i] =lsm6dsox_from_fs4_to_mg(data->ois.xl.raw[i]); 11557 break; 11558 case LSM6DSOX_XL_UI_8g: 11559 data->ois.xl.mg[i] =lsm6dsox_from_fs8_to_mg(data->ois.xl.raw[i]); 11560 break; 11561 case LSM6DSOX_XL_UI_16g: 11562 data->ois.xl.mg[i] =lsm6dsox_from_fs16_to_mg(data->ois.xl.raw[i]); 11563 break; 11564 default: 11565 data->ois.xl.mg[i] = 0.0f; 11566 break; 11567 } 11568 } 11569 11570 return ret; 11571 } 11572 11573 /** 11574 * @brief Embedded functions.[set] 11575 * 11576 * @param ctx read / write interface definitions 11577 * @param val change the values of registers 11578 * EMB_FUNC_EN_A e EMB_FUNC_EN_B. 11579 * 11580 */ 11581 int32_t lsm6dsox_embedded_sens_set(lsm6dsox_ctx_t *ctx, 11582 lsm6dsox_emb_sens_t *val) 11583 { 11584 lsm6dsox_emb_func_en_a_t emb_func_en_a; 11585 lsm6dsox_emb_func_en_b_t emb_func_en_b; 11586 int32_t ret; 11587 11588 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 11589 if (ret == 0) { 11590 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, 11591 (uint8_t*)&emb_func_en_a, 1); 11592 } 11593 if (ret == 0) { 11594 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, 11595 (uint8_t*)&emb_func_en_b, 1); 11596 11597 emb_func_en_b.mlc_en = val->mlc; 11598 emb_func_en_b.fsm_en = val->fsm; 11599 emb_func_en_a.tilt_en = val->tilt; 11600 emb_func_en_a.pedo_en = val->step; 11601 emb_func_en_a.sign_motion_en = val->sig_mot; 11602 emb_func_en_b.fifo_compr_en = val->fifo_compr; 11603 11604 } 11605 if (ret == 0) { 11606 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, 11607 (uint8_t*)&emb_func_en_a, 1); 11608 } 11609 if (ret == 0) { 11610 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, 11611 (uint8_t*)&emb_func_en_b, 1); 11612 } 11613 if (ret == 0) { 11614 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 11615 } 11616 11617 return ret; 11618 } 11619 11620 /** 11621 * @brief Embedded functions.[get] 11622 * 11623 * @param ctx read / write interface definitions 11624 * @param val get the values of registers 11625 * EMB_FUNC_EN_A e EMB_FUNC_EN_B. 11626 * 11627 */ 11628 int32_t lsm6dsox_embedded_sens_get(lsm6dsox_ctx_t *ctx, 11629 lsm6dsox_emb_sens_t *emb_sens) 11630 { 11631 lsm6dsox_emb_func_en_a_t emb_func_en_a; 11632 lsm6dsox_emb_func_en_b_t emb_func_en_b; 11633 int32_t ret; 11634 11635 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 11636 if (ret == 0) { 11637 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, 11638 (uint8_t*)&emb_func_en_a, 1); 11639 } 11640 if (ret == 0) { 11641 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, 11642 (uint8_t*)&emb_func_en_b, 1); 11643 11644 emb_sens->mlc = emb_func_en_b.mlc_en; 11645 emb_sens->fsm = emb_func_en_b.fsm_en; 11646 emb_sens->tilt = emb_func_en_a.tilt_en; 11647 emb_sens->step = emb_func_en_a.pedo_en; 11648 emb_sens->sig_mot = emb_func_en_a.sign_motion_en; 11649 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en; 11650 11651 } 11652 if (ret == 0) { 11653 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 11654 } 11655 11656 return ret; 11657 } 11658 11659 /** 11660 * @brief turn off all embedded functions.[get] 11661 * 11662 * @param ctx read / write interface definitions 11663 * @param val get the values of registers 11664 * EMB_FUNC_EN_A e EMB_FUNC_EN_B. 11665 * 11666 */ 11667 int32_t lsm6dsox_embedded_sens_off(lsm6dsox_ctx_t *ctx) 11668 { 11669 lsm6dsox_emb_func_en_a_t emb_func_en_a; 11670 lsm6dsox_emb_func_en_b_t emb_func_en_b; 11671 int32_t ret; 11672 11673 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); 11674 if (ret == 0) { 11675 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, 11676 (uint8_t*)&emb_func_en_a, 1); 11677 } 11678 if (ret == 0) { 11679 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, 11680 (uint8_t*)&emb_func_en_b, 1); 11681 11682 emb_func_en_b.mlc_en = PROPERTY_DISABLE; 11683 emb_func_en_b.fsm_en = PROPERTY_DISABLE; 11684 emb_func_en_a.tilt_en = PROPERTY_DISABLE; 11685 emb_func_en_a.pedo_en = PROPERTY_DISABLE; 11686 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE; 11687 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE; 11688 11689 } 11690 if (ret == 0) { 11691 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, 11692 (uint8_t*)&emb_func_en_a, 1); 11693 } 11694 if (ret == 0) { 11695 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, 11696 (uint8_t*)&emb_func_en_b, 1); 11697 } 11698 if (ret == 0) { 11699 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); 11700 } 11701 11702 return ret; 11703 } 11704 11705 /** 11706 * @} 11707 * 11708 */ 11709 11710 /** 11711 * @} 11712 * 11713 */ 11714 11715 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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