ST / BSP_DISCO_L496AG

BSP driver for DISCO_L496AG

Dependents:   DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo

Drivers/BSP/STM32L496G-Discovery/stm32l496g_discovery_sram.c@0:d83f1c8ca282, 2018-03-26 (annotated)

Committer:
bcostm
Date:
Mon Mar 26 10:28:18 2018 +0200
Revision:
0:d83f1c8ca282
Child:
2:106c7b82e064
Add BSP files coming from CubeL4 V1.11.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:d83f1c8ca282 1 /**
bcostm 0:d83f1c8ca282 2 ******************************************************************************
bcostm 0:d83f1c8ca282 3 * @file stm32l496g_discovery_sram.c
bcostm 0:d83f1c8ca282 4 * @author MCD Application Team
bcostm 0:d83f1c8ca282 5 * @brief This file provides a set of functions needed to drive the
bcostm 0:d83f1c8ca282 6 * IS66WV51216EBLL SRAM memory mounted on STM32L496G-Discovery board.
bcostm 0:d83f1c8ca282 7 @verbatim
bcostm 0:d83f1c8ca282 8 ==============================================================================
bcostm 0:d83f1c8ca282 9 ##### How to use this driver #####
bcostm 0:d83f1c8ca282 10 ==============================================================================
bcostm 0:d83f1c8ca282 11 [..]
bcostm 0:d83f1c8ca282 12 (#) This driver is used to drive the IS66WV51216EBLL-70BLI SRAM external memory mounted
bcostm 0:d83f1c8ca282 13 on STM32L496G-Discovery evaluation board.
bcostm 0:d83f1c8ca282 14
bcostm 0:d83f1c8ca282 15 (#) This driver does not need a specific component driver for the SRAM device
bcostm 0:d83f1c8ca282 16 to be included with.
bcostm 0:d83f1c8ca282 17
bcostm 0:d83f1c8ca282 18 (#) Initialization steps:
bcostm 0:d83f1c8ca282 19 (++) Initialize the SRAM external memory using the BSP_SRAM_Init() function. This
bcostm 0:d83f1c8ca282 20 function includes the MSP layer hardware resources initialization and the
bcostm 0:d83f1c8ca282 21 FMC controller configuration to interface with the external SRAM memory.
bcostm 0:d83f1c8ca282 22
bcostm 0:d83f1c8ca282 23 (#) SRAM read/write operations
bcostm 0:d83f1c8ca282 24 (++) SRAM external memory can be accessed with read/write operations once it is
bcostm 0:d83f1c8ca282 25 initialized.
bcostm 0:d83f1c8ca282 26 Read/write operation can be performed with AHB access using the functions
bcostm 0:d83f1c8ca282 27 BSP_SRAM_ReadData()/BSP_SRAM_WriteData(), or by DMA transfer using the functions
bcostm 0:d83f1c8ca282 28 BSP_SRAM_ReadData_DMA()/BSP_SRAM_WriteData_DMA().
bcostm 0:d83f1c8ca282 29 (++) The AHB access is performed with 16-bit width transaction, the DMA transfer
bcostm 0:d83f1c8ca282 30 configuration is fixed at single (no burst) halfword transfer
bcostm 0:d83f1c8ca282 31 (see the SRAM_MspInit() static function).
bcostm 0:d83f1c8ca282 32 (++) User can implement his own functions for read/write access with his desired
bcostm 0:d83f1c8ca282 33 configurations.
bcostm 0:d83f1c8ca282 34 (++) If interrupt mode is used for DMA transfer, the function BSP_SRAM_DMA_IRQHandler()
bcostm 0:d83f1c8ca282 35 is called in IRQ handler file, to serve the generated interrupt once the DMA
bcostm 0:d83f1c8ca282 36 transfer is complete.
bcostm 0:d83f1c8ca282 37 @endverbatim
bcostm 0:d83f1c8ca282 38 ******************************************************************************
bcostm 0:d83f1c8ca282 39 * @attention
bcostm 0:d83f1c8ca282 40 *
bcostm 0:d83f1c8ca282 41 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bcostm 0:d83f1c8ca282 42 *
bcostm 0:d83f1c8ca282 43 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:d83f1c8ca282 44 * are permitted provided that the following conditions are met:
bcostm 0:d83f1c8ca282 45 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:d83f1c8ca282 46 * this list of conditions and the following disclaimer.
bcostm 0:d83f1c8ca282 47 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:d83f1c8ca282 48 * this list of conditions and the following disclaimer in the documentation
bcostm 0:d83f1c8ca282 49 * and/or other materials provided with the distribution.
bcostm 0:d83f1c8ca282 50 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:d83f1c8ca282 51 * may be used to endorse or promote products derived from this software
bcostm 0:d83f1c8ca282 52 * without specific prior written permission.
bcostm 0:d83f1c8ca282 53 *
bcostm 0:d83f1c8ca282 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:d83f1c8ca282 55 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:d83f1c8ca282 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:d83f1c8ca282 57 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:d83f1c8ca282 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:d83f1c8ca282 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:d83f1c8ca282 60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:d83f1c8ca282 61 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:d83f1c8ca282 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:d83f1c8ca282 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:d83f1c8ca282 64 *
bcostm 0:d83f1c8ca282 65 ******************************************************************************
bcostm 0:d83f1c8ca282 66 */
bcostm 0:d83f1c8ca282 67
bcostm 0:d83f1c8ca282 68 /* Includes ------------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 69 #include "stm32l496g_discovery_sram.h"
bcostm 0:d83f1c8ca282 70
bcostm 0:d83f1c8ca282 71 /** @addtogroup BSP
bcostm 0:d83f1c8ca282 72 * @{
bcostm 0:d83f1c8ca282 73 */
bcostm 0:d83f1c8ca282 74
bcostm 0:d83f1c8ca282 75 /** @addtogroup STM32L496G_DISCOVERY
bcostm 0:d83f1c8ca282 76 * @{
bcostm 0:d83f1c8ca282 77 */
bcostm 0:d83f1c8ca282 78
bcostm 0:d83f1c8ca282 79 /** @defgroup STM32L496G_DISCOVERY_SRAM STM32L496G-DISCOVERY SRAM
bcostm 0:d83f1c8ca282 80 * @{
bcostm 0:d83f1c8ca282 81 */
bcostm 0:d83f1c8ca282 82
bcostm 0:d83f1c8ca282 83
bcostm 0:d83f1c8ca282 84 /* Private variables ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 85
bcostm 0:d83f1c8ca282 86 /** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Variables Private Variables
bcostm 0:d83f1c8ca282 87 * @{
bcostm 0:d83f1c8ca282 88 */
bcostm 0:d83f1c8ca282 89 static SRAM_HandleTypeDef sramHandle;
bcostm 0:d83f1c8ca282 90 static FMC_NORSRAM_TimingTypeDef Timing;
bcostm 0:d83f1c8ca282 91
bcostm 0:d83f1c8ca282 92 /**
bcostm 0:d83f1c8ca282 93 * @}
bcostm 0:d83f1c8ca282 94 */
bcostm 0:d83f1c8ca282 95
bcostm 0:d83f1c8ca282 96 /* Private macros ------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 97 /* Private constants ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 98
bcostm 0:d83f1c8ca282 99 /** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Constants Private Constants
bcostm 0:d83f1c8ca282 100 * @{
bcostm 0:d83f1c8ca282 101 */
bcostm 0:d83f1c8ca282 102 /* Timings for SRAM IS66WV51216EBLL-70BLI */
bcostm 0:d83f1c8ca282 103 #define SRAM_ADDR_SETUP_TIME 5 /* 60ns with a clock at 80 MHz (period of 12.5 ns) */
bcostm 0:d83f1c8ca282 104 #define SRAM_DATA_SETUP_TIME 3 /* 30ns with a clock at 80 MHz (period of 12.5 ns) */
bcostm 0:d83f1c8ca282 105 #define SRAM_TURN_AROUND_TIME 1 /* 5ns with a clock at 80 MHz (perido of 12.5 ns) */
bcostm 0:d83f1c8ca282 106
bcostm 0:d83f1c8ca282 107 /**
bcostm 0:d83f1c8ca282 108 * @}
bcostm 0:d83f1c8ca282 109 */
bcostm 0:d83f1c8ca282 110
bcostm 0:d83f1c8ca282 111 /* Private function prototypes -----------------------------------------------*/
bcostm 0:d83f1c8ca282 112
bcostm 0:d83f1c8ca282 113 /** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Functions Private Functions
bcostm 0:d83f1c8ca282 114 * @{
bcostm 0:d83f1c8ca282 115 */
bcostm 0:d83f1c8ca282 116 static void SRAM_MspInit(void);
bcostm 0:d83f1c8ca282 117
bcostm 0:d83f1c8ca282 118 /**
bcostm 0:d83f1c8ca282 119 * @}
bcostm 0:d83f1c8ca282 120 */
bcostm 0:d83f1c8ca282 121
bcostm 0:d83f1c8ca282 122 /* Private functions ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 123
bcostm 0:d83f1c8ca282 124 /** @defgroup STM32L496G_DISCOVERY_SRAM_Exported_Functions Exported Functions
bcostm 0:d83f1c8ca282 125 * @{
bcostm 0:d83f1c8ca282 126 */
bcostm 0:d83f1c8ca282 127
bcostm 0:d83f1c8ca282 128 /**
bcostm 0:d83f1c8ca282 129 * @brief Initializes the SRAM device.
bcostm 0:d83f1c8ca282 130 * @retval SRAM status
bcostm 0:d83f1c8ca282 131 */
bcostm 0:d83f1c8ca282 132 uint8_t BSP_SRAM_Init(void)
bcostm 0:d83f1c8ca282 133 {
bcostm 0:d83f1c8ca282 134 sramHandle.Instance = FMC_NORSRAM_DEVICE;
bcostm 0:d83f1c8ca282 135 sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
bcostm 0:d83f1c8ca282 136
bcostm 0:d83f1c8ca282 137 /* SRAM device configuration */
bcostm 0:d83f1c8ca282 138 Timing.AddressSetupTime = SRAM_ADDR_SETUP_TIME;
bcostm 0:d83f1c8ca282 139 Timing.DataSetupTime = SRAM_DATA_SETUP_TIME;
bcostm 0:d83f1c8ca282 140 Timing.BusTurnAroundDuration = SRAM_TURN_AROUND_TIME;
bcostm 0:d83f1c8ca282 141 Timing.AccessMode = FMC_ACCESS_MODE_A;
bcostm 0:d83f1c8ca282 142
bcostm 0:d83f1c8ca282 143 sramHandle.Init.NSBank = FMC_NORSRAM_BANK2;
bcostm 0:d83f1c8ca282 144 sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
bcostm 0:d83f1c8ca282 145 sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
bcostm 0:d83f1c8ca282 146 sramHandle.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
bcostm 0:d83f1c8ca282 147 sramHandle.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
bcostm 0:d83f1c8ca282 148 sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
bcostm 0:d83f1c8ca282 149 sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
bcostm 0:d83f1c8ca282 150 sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
bcostm 0:d83f1c8ca282 151 sramHandle.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
bcostm 0:d83f1c8ca282 152 sramHandle.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
bcostm 0:d83f1c8ca282 153 sramHandle.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
bcostm 0:d83f1c8ca282 154 sramHandle.Init.PageSize = FMC_PAGE_SIZE_NONE;
bcostm 0:d83f1c8ca282 155
bcostm 0:d83f1c8ca282 156 /* SRAM controller initialization */
bcostm 0:d83f1c8ca282 157 SRAM_MspInit();
bcostm 0:d83f1c8ca282 158 if (HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
bcostm 0:d83f1c8ca282 159 {
bcostm 0:d83f1c8ca282 160 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 161 }
bcostm 0:d83f1c8ca282 162 else
bcostm 0:d83f1c8ca282 163 {
bcostm 0:d83f1c8ca282 164 return SRAM_OK;
bcostm 0:d83f1c8ca282 165 }
bcostm 0:d83f1c8ca282 166 }
bcostm 0:d83f1c8ca282 167
bcostm 0:d83f1c8ca282 168 /**
bcostm 0:d83f1c8ca282 169 * @brief Reads an amount of data from the SRAM device in polling mode.
bcostm 0:d83f1c8ca282 170 * @param uwStartAddress: Read start address
bcostm 0:d83f1c8ca282 171 * @param pData: Pointer to data to be read
bcostm 0:d83f1c8ca282 172 * @param uwDataSize: Size of read data from the memory
bcostm 0:d83f1c8ca282 173 * @retval SRAM status
bcostm 0:d83f1c8ca282 174 */
bcostm 0:d83f1c8ca282 175 uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 176 {
bcostm 0:d83f1c8ca282 177 if (HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 178 {
bcostm 0:d83f1c8ca282 179 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 180 }
bcostm 0:d83f1c8ca282 181 else
bcostm 0:d83f1c8ca282 182 {
bcostm 0:d83f1c8ca282 183 return SRAM_OK;
bcostm 0:d83f1c8ca282 184 }
bcostm 0:d83f1c8ca282 185 }
bcostm 0:d83f1c8ca282 186
bcostm 0:d83f1c8ca282 187 /**
bcostm 0:d83f1c8ca282 188 * @brief Reads an amount of data from the SRAM device in DMA mode.
bcostm 0:d83f1c8ca282 189 * @param uwStartAddress: Read start address
bcostm 0:d83f1c8ca282 190 * @param pData: Pointer to data to be read
bcostm 0:d83f1c8ca282 191 * @param uwDataSize: Size of read data from the memory
bcostm 0:d83f1c8ca282 192 * @retval SRAM status
bcostm 0:d83f1c8ca282 193 */
bcostm 0:d83f1c8ca282 194 uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 195 {
bcostm 0:d83f1c8ca282 196 if (HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 197 {
bcostm 0:d83f1c8ca282 198 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 199 }
bcostm 0:d83f1c8ca282 200 else
bcostm 0:d83f1c8ca282 201 {
bcostm 0:d83f1c8ca282 202 return SRAM_OK;
bcostm 0:d83f1c8ca282 203 }
bcostm 0:d83f1c8ca282 204 }
bcostm 0:d83f1c8ca282 205
bcostm 0:d83f1c8ca282 206 /**
bcostm 0:d83f1c8ca282 207 * @brief Writes an amount of data from the SRAM device in polling mode.
bcostm 0:d83f1c8ca282 208 * @param uwStartAddress: Write start address
bcostm 0:d83f1c8ca282 209 * @param pData: Pointer to data to be written
bcostm 0:d83f1c8ca282 210 * @param uwDataSize: Size of written data from the memory
bcostm 0:d83f1c8ca282 211 * @retval SRAM status
bcostm 0:d83f1c8ca282 212 */
bcostm 0:d83f1c8ca282 213 uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 214 {
bcostm 0:d83f1c8ca282 215 if (HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 216 {
bcostm 0:d83f1c8ca282 217 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 218 }
bcostm 0:d83f1c8ca282 219 else
bcostm 0:d83f1c8ca282 220 {
bcostm 0:d83f1c8ca282 221 return SRAM_OK;
bcostm 0:d83f1c8ca282 222 }
bcostm 0:d83f1c8ca282 223 }
bcostm 0:d83f1c8ca282 224
bcostm 0:d83f1c8ca282 225 /**
bcostm 0:d83f1c8ca282 226 * @brief Writes an amount of data from the SRAM device in DMA mode.
bcostm 0:d83f1c8ca282 227 * @param uwStartAddress: Write start address
bcostm 0:d83f1c8ca282 228 * @param pData: Pointer to data to be written
bcostm 0:d83f1c8ca282 229 * @param uwDataSize: Size of written data from the memory
bcostm 0:d83f1c8ca282 230 * @retval SRAM status
bcostm 0:d83f1c8ca282 231 */
bcostm 0:d83f1c8ca282 232 uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 233 {
bcostm 0:d83f1c8ca282 234 if (HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 235 {
bcostm 0:d83f1c8ca282 236 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 237 }
bcostm 0:d83f1c8ca282 238 else
bcostm 0:d83f1c8ca282 239 {
bcostm 0:d83f1c8ca282 240 return SRAM_OK;
bcostm 0:d83f1c8ca282 241 }
bcostm 0:d83f1c8ca282 242 }
bcostm 0:d83f1c8ca282 243
bcostm 0:d83f1c8ca282 244 /**
bcostm 0:d83f1c8ca282 245 * @brief Handles SRAM DMA transfer interrupt request.
bcostm 0:d83f1c8ca282 246 * @retval None
bcostm 0:d83f1c8ca282 247 */
bcostm 0:d83f1c8ca282 248 void BSP_SRAM_DMA_IRQHandler(void)
bcostm 0:d83f1c8ca282 249 {
bcostm 0:d83f1c8ca282 250 HAL_DMA_IRQHandler(sramHandle.hdma);
bcostm 0:d83f1c8ca282 251 }
bcostm 0:d83f1c8ca282 252
bcostm 0:d83f1c8ca282 253 /** @addtogroup STM32L476G_EVAL_SRAM_Private_Functions
bcostm 0:d83f1c8ca282 254 * @{
bcostm 0:d83f1c8ca282 255 */
bcostm 0:d83f1c8ca282 256
bcostm 0:d83f1c8ca282 257 /**
bcostm 0:d83f1c8ca282 258 * @brief Initializes SRAM MSP.
bcostm 0:d83f1c8ca282 259 * @retval None
bcostm 0:d83f1c8ca282 260 */
bcostm 0:d83f1c8ca282 261 static void SRAM_MspInit(void)
bcostm 0:d83f1c8ca282 262 {
bcostm 0:d83f1c8ca282 263 static DMA_HandleTypeDef dmaHandle;
bcostm 0:d83f1c8ca282 264 GPIO_InitTypeDef gpioinitstruct;
bcostm 0:d83f1c8ca282 265 SRAM_HandleTypeDef *hsram = &sramHandle;
bcostm 0:d83f1c8ca282 266
bcostm 0:d83f1c8ca282 267 /* Enable FMC clock */
bcostm 0:d83f1c8ca282 268 __HAL_RCC_FMC_CLK_ENABLE();
bcostm 0:d83f1c8ca282 269
bcostm 0:d83f1c8ca282 270 /* Enable chosen DMAx clock */
bcostm 0:d83f1c8ca282 271 SRAM_DMAx_CLK_ENABLE();
bcostm 0:d83f1c8ca282 272
bcostm 0:d83f1c8ca282 273 /* Enable GPIOs clock */
bcostm 0:d83f1c8ca282 274 __HAL_RCC_GPIOD_CLK_ENABLE();
bcostm 0:d83f1c8ca282 275 __HAL_RCC_GPIOE_CLK_ENABLE();
bcostm 0:d83f1c8ca282 276 __HAL_RCC_GPIOF_CLK_ENABLE();
bcostm 0:d83f1c8ca282 277 __HAL_RCC_GPIOG_CLK_ENABLE();
bcostm 0:d83f1c8ca282 278 __HAL_RCC_PWR_CLK_ENABLE();
bcostm 0:d83f1c8ca282 279 HAL_PWREx_EnableVddIO2();
bcostm 0:d83f1c8ca282 280
bcostm 0:d83f1c8ca282 281 /* Common GPIO configuration */
bcostm 0:d83f1c8ca282 282 gpioinitstruct.Mode = GPIO_MODE_AF_PP;
bcostm 0:d83f1c8ca282 283 gpioinitstruct.Pull = GPIO_NOPULL;
bcostm 0:d83f1c8ca282 284 gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
bcostm 0:d83f1c8ca282 285 gpioinitstruct.Alternate = GPIO_AF12_FMC;
bcostm 0:d83f1c8ca282 286
bcostm 0:d83f1c8ca282 287 /*## Data Bus #######*/
bcostm 0:d83f1c8ca282 288 /* GPIOD configuration */
bcostm 0:d83f1c8ca282 289 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
bcostm 0:d83f1c8ca282 290 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:d83f1c8ca282 291 HAL_GPIO_Init(GPIOD, &gpioinitstruct);
bcostm 0:d83f1c8ca282 292
bcostm 0:d83f1c8ca282 293 /* GPIOE configuration */
bcostm 0:d83f1c8ca282 294 gpioinitstruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |
bcostm 0:d83f1c8ca282 295 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
bcostm 0:d83f1c8ca282 296 GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:d83f1c8ca282 297 HAL_GPIO_Init(GPIOE, &gpioinitstruct);
bcostm 0:d83f1c8ca282 298
bcostm 0:d83f1c8ca282 299 /*## Address Bus #######*/
bcostm 0:d83f1c8ca282 300 /* GPIOD configuration */
bcostm 0:d83f1c8ca282 301 gpioinitstruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
bcostm 0:d83f1c8ca282 302 HAL_GPIO_Init(GPIOD, &gpioinitstruct);
bcostm 0:d83f1c8ca282 303
bcostm 0:d83f1c8ca282 304 /* GPIOF configuration */
bcostm 0:d83f1c8ca282 305 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
bcostm 0:d83f1c8ca282 306 GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 |
bcostm 0:d83f1c8ca282 307 GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:d83f1c8ca282 308 HAL_GPIO_Init(GPIOF, &gpioinitstruct);
bcostm 0:d83f1c8ca282 309
bcostm 0:d83f1c8ca282 310 /* GPIOG configuration */
bcostm 0:d83f1c8ca282 311 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
bcostm 0:d83f1c8ca282 312 GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
bcostm 0:d83f1c8ca282 313 HAL_GPIO_Init(GPIOG, &gpioinitstruct);
bcostm 0:d83f1c8ca282 314
bcostm 0:d83f1c8ca282 315 /*## NOE and NWE configuration #######*/
bcostm 0:d83f1c8ca282 316 gpioinitstruct.Pull = GPIO_PULLUP;
bcostm 0:d83f1c8ca282 317 gpioinitstruct.Pin = GPIO_PIN_4 | GPIO_PIN_5;
bcostm 0:d83f1c8ca282 318 HAL_GPIO_Init(GPIOD, &gpioinitstruct);
bcostm 0:d83f1c8ca282 319 HAL_Delay(1);
bcostm 0:d83f1c8ca282 320
bcostm 0:d83f1c8ca282 321 /*## NBL0, NBL1 configuration #######*/
bcostm 0:d83f1c8ca282 322 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
bcostm 0:d83f1c8ca282 323 HAL_GPIO_Init(GPIOE, &gpioinitstruct);
bcostm 0:d83f1c8ca282 324
bcostm 0:d83f1c8ca282 325 /*## NE configuration #######*/
bcostm 0:d83f1c8ca282 326 gpioinitstruct.Pin = GPIO_PIN_9;
bcostm 0:d83f1c8ca282 327 HAL_GPIO_Init(GPIOG, &gpioinitstruct);
bcostm 0:d83f1c8ca282 328
bcostm 0:d83f1c8ca282 329 /* Configure common DMA parameters */
bcostm 0:d83f1c8ca282 330 dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;
bcostm 0:d83f1c8ca282 331 dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;
bcostm 0:d83f1c8ca282 332 dmaHandle.Init.MemInc = DMA_MINC_ENABLE;
bcostm 0:d83f1c8ca282 333 dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
bcostm 0:d83f1c8ca282 334 dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
bcostm 0:d83f1c8ca282 335 dmaHandle.Init.Mode = DMA_NORMAL;
bcostm 0:d83f1c8ca282 336 dmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
bcostm 0:d83f1c8ca282 337
bcostm 0:d83f1c8ca282 338 dmaHandle.Instance = SRAM_DMAx_CHANNEL;
bcostm 0:d83f1c8ca282 339
bcostm 0:d83f1c8ca282 340 /* Associate the DMA handle */
bcostm 0:d83f1c8ca282 341 __HAL_LINKDMA(hsram, hdma, dmaHandle);
bcostm 0:d83f1c8ca282 342
bcostm 0:d83f1c8ca282 343 /* Deinitialize the Stream for new transfer */
bcostm 0:d83f1c8ca282 344 HAL_DMA_DeInit(&dmaHandle);
bcostm 0:d83f1c8ca282 345
bcostm 0:d83f1c8ca282 346 /* Configure the DMA Stream */
bcostm 0:d83f1c8ca282 347 HAL_DMA_Init(&dmaHandle);
bcostm 0:d83f1c8ca282 348
bcostm 0:d83f1c8ca282 349 /* NVIC configuration for DMA transfer complete interrupt */
bcostm 0:d83f1c8ca282 350 HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 5, 0);
bcostm 0:d83f1c8ca282 351 HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
bcostm 0:d83f1c8ca282 352 }
bcostm 0:d83f1c8ca282 353
bcostm 0:d83f1c8ca282 354 /**
bcostm 0:d83f1c8ca282 355 * @}
bcostm 0:d83f1c8ca282 356 */
bcostm 0:d83f1c8ca282 357
bcostm 0:d83f1c8ca282 358 /**
bcostm 0:d83f1c8ca282 359 * @}
bcostm 0:d83f1c8ca282 360 */
bcostm 0:d83f1c8ca282 361
bcostm 0:d83f1c8ca282 362 /**
bcostm 0:d83f1c8ca282 363 * @}
bcostm 0:d83f1c8ca282 364 */
bcostm 0:d83f1c8ca282 365
bcostm 0:d83f1c8ca282 366 /**
bcostm 0:d83f1c8ca282 367 * @}
bcostm 0:d83f1c8ca282 368 */
bcostm 0:d83f1c8ca282 369
bcostm 0:d83f1c8ca282 370 /**
bcostm 0:d83f1c8ca282 371 * @}
bcostm 0:d83f1c8ca282 372 */
bcostm 0:d83f1c8ca282 373
bcostm 0:d83f1c8ca282 374 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/