ST / BSP_DISCO_L496AG

BSP driver for DISCO_L496AG

Dependents:   DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo

Drivers/BSP/STM32L496G-Discovery/stm32l496g_discovery_sram.c@2:106c7b82e064, 2019-11-20 (annotated)

Committer:
Jerome Coutant
Date:
Wed Nov 20 16:48:24 2019 +0100
Revision:
2:106c7b82e064
Parent:
0:d83f1c8ca282 
Update BSP files with CubeL4 V1.14.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:d83f1c8ca282 1 /**
bcostm 0:d83f1c8ca282 2 ******************************************************************************
bcostm 0:d83f1c8ca282 3 * @file stm32l496g_discovery_sram.c
bcostm 0:d83f1c8ca282 4 * @author MCD Application Team
bcostm 0:d83f1c8ca282 5 * @brief This file provides a set of functions needed to drive the
bcostm 0:d83f1c8ca282 6 * IS66WV51216EBLL SRAM memory mounted on STM32L496G-Discovery board.
bcostm 0:d83f1c8ca282 7 @verbatim
bcostm 0:d83f1c8ca282 8 ==============================================================================
bcostm 0:d83f1c8ca282 9 ##### How to use this driver #####
bcostm 0:d83f1c8ca282 10 ==============================================================================
bcostm 0:d83f1c8ca282 11 [..]
bcostm 0:d83f1c8ca282 12 (#) This driver is used to drive the IS66WV51216EBLL-70BLI SRAM external memory mounted
bcostm 0:d83f1c8ca282 13 on STM32L496G-Discovery evaluation board.
bcostm 0:d83f1c8ca282 14
bcostm 0:d83f1c8ca282 15 (#) This driver does not need a specific component driver for the SRAM device
bcostm 0:d83f1c8ca282 16 to be included with.
bcostm 0:d83f1c8ca282 17
bcostm 0:d83f1c8ca282 18 (#) Initialization steps:
bcostm 0:d83f1c8ca282 19 (++) Initialize the SRAM external memory using the BSP_SRAM_Init() function. This
bcostm 0:d83f1c8ca282 20 function includes the MSP layer hardware resources initialization and the
bcostm 0:d83f1c8ca282 21 FMC controller configuration to interface with the external SRAM memory.
bcostm 0:d83f1c8ca282 22
bcostm 0:d83f1c8ca282 23 (#) SRAM read/write operations
bcostm 0:d83f1c8ca282 24 (++) SRAM external memory can be accessed with read/write operations once it is
bcostm 0:d83f1c8ca282 25 initialized.
bcostm 0:d83f1c8ca282 26 Read/write operation can be performed with AHB access using the functions
bcostm 0:d83f1c8ca282 27 BSP_SRAM_ReadData()/BSP_SRAM_WriteData(), or by DMA transfer using the functions
bcostm 0:d83f1c8ca282 28 BSP_SRAM_ReadData_DMA()/BSP_SRAM_WriteData_DMA().
bcostm 0:d83f1c8ca282 29 (++) The AHB access is performed with 16-bit width transaction, the DMA transfer
bcostm 0:d83f1c8ca282 30 configuration is fixed at single (no burst) halfword transfer
bcostm 0:d83f1c8ca282 31 (see the SRAM_MspInit() static function).
bcostm 0:d83f1c8ca282 32 (++) User can implement his own functions for read/write access with his desired
bcostm 0:d83f1c8ca282 33 configurations.
bcostm 0:d83f1c8ca282 34 (++) If interrupt mode is used for DMA transfer, the function BSP_SRAM_DMA_IRQHandler()
bcostm 0:d83f1c8ca282 35 is called in IRQ handler file, to serve the generated interrupt once the DMA
bcostm 0:d83f1c8ca282 36 transfer is complete.
bcostm 0:d83f1c8ca282 37 @endverbatim
bcostm 0:d83f1c8ca282 38 ******************************************************************************
bcostm 0:d83f1c8ca282 39 * @attention
bcostm 0:d83f1c8ca282 40 *
Jerome Coutant 2:106c7b82e064 41 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
Jerome Coutant 2:106c7b82e064 42 * All rights reserved.</center></h2>
bcostm 0:d83f1c8ca282 43 *
Jerome Coutant 2:106c7b82e064 44 * This software component is licensed by ST under BSD 3-Clause license,
Jerome Coutant 2:106c7b82e064 45 * the "License"; You may not use this file except in compliance with the
Jerome Coutant 2:106c7b82e064 46 * License. You may obtain a copy of the License at:
Jerome Coutant 2:106c7b82e064 47 * opensource.org/licenses/BSD-3-Clause
bcostm 0:d83f1c8ca282 48 *
bcostm 0:d83f1c8ca282 49 ******************************************************************************
bcostm 0:d83f1c8ca282 50 */
bcostm 0:d83f1c8ca282 51
bcostm 0:d83f1c8ca282 52 /* Includes ------------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 53 #include "stm32l496g_discovery_sram.h"
bcostm 0:d83f1c8ca282 54
bcostm 0:d83f1c8ca282 55 /** @addtogroup BSP
bcostm 0:d83f1c8ca282 56 * @{
bcostm 0:d83f1c8ca282 57 */
bcostm 0:d83f1c8ca282 58
bcostm 0:d83f1c8ca282 59 /** @addtogroup STM32L496G_DISCOVERY
bcostm 0:d83f1c8ca282 60 * @{
bcostm 0:d83f1c8ca282 61 */
bcostm 0:d83f1c8ca282 62
bcostm 0:d83f1c8ca282 63 /** @defgroup STM32L496G_DISCOVERY_SRAM STM32L496G-DISCOVERY SRAM
bcostm 0:d83f1c8ca282 64 * @{
bcostm 0:d83f1c8ca282 65 */
bcostm 0:d83f1c8ca282 66
bcostm 0:d83f1c8ca282 67
bcostm 0:d83f1c8ca282 68 /* Private variables ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 69
bcostm 0:d83f1c8ca282 70 /** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Variables Private Variables
bcostm 0:d83f1c8ca282 71 * @{
bcostm 0:d83f1c8ca282 72 */
bcostm 0:d83f1c8ca282 73 static SRAM_HandleTypeDef sramHandle;
bcostm 0:d83f1c8ca282 74 static FMC_NORSRAM_TimingTypeDef Timing;
bcostm 0:d83f1c8ca282 75
bcostm 0:d83f1c8ca282 76 /**
bcostm 0:d83f1c8ca282 77 * @}
bcostm 0:d83f1c8ca282 78 */
bcostm 0:d83f1c8ca282 79
bcostm 0:d83f1c8ca282 80 /* Private macros ------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 81 /* Private constants ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 82
bcostm 0:d83f1c8ca282 83 /** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Constants Private Constants
bcostm 0:d83f1c8ca282 84 * @{
bcostm 0:d83f1c8ca282 85 */
bcostm 0:d83f1c8ca282 86 /* Timings for SRAM IS66WV51216EBLL-70BLI */
bcostm 0:d83f1c8ca282 87 #define SRAM_ADDR_SETUP_TIME 5 /* 60ns with a clock at 80 MHz (period of 12.5 ns) */
bcostm 0:d83f1c8ca282 88 #define SRAM_DATA_SETUP_TIME 3 /* 30ns with a clock at 80 MHz (period of 12.5 ns) */
bcostm 0:d83f1c8ca282 89 #define SRAM_TURN_AROUND_TIME 1 /* 5ns with a clock at 80 MHz (perido of 12.5 ns) */
bcostm 0:d83f1c8ca282 90
bcostm 0:d83f1c8ca282 91 /**
bcostm 0:d83f1c8ca282 92 * @}
bcostm 0:d83f1c8ca282 93 */
bcostm 0:d83f1c8ca282 94
bcostm 0:d83f1c8ca282 95 /* Private function prototypes -----------------------------------------------*/
bcostm 0:d83f1c8ca282 96
bcostm 0:d83f1c8ca282 97 /** @defgroup STM32L496G_DISCOVERY_SRAM_Private_Functions Private Functions
bcostm 0:d83f1c8ca282 98 * @{
bcostm 0:d83f1c8ca282 99 */
bcostm 0:d83f1c8ca282 100 static void SRAM_MspInit(void);
bcostm 0:d83f1c8ca282 101
bcostm 0:d83f1c8ca282 102 /**
bcostm 0:d83f1c8ca282 103 * @}
bcostm 0:d83f1c8ca282 104 */
bcostm 0:d83f1c8ca282 105
bcostm 0:d83f1c8ca282 106 /* Private functions ---------------------------------------------------------*/
bcostm 0:d83f1c8ca282 107
bcostm 0:d83f1c8ca282 108 /** @defgroup STM32L496G_DISCOVERY_SRAM_Exported_Functions Exported Functions
bcostm 0:d83f1c8ca282 109 * @{
bcostm 0:d83f1c8ca282 110 */
bcostm 0:d83f1c8ca282 111
bcostm 0:d83f1c8ca282 112 /**
bcostm 0:d83f1c8ca282 113 * @brief Initializes the SRAM device.
bcostm 0:d83f1c8ca282 114 * @retval SRAM status
bcostm 0:d83f1c8ca282 115 */
bcostm 0:d83f1c8ca282 116 uint8_t BSP_SRAM_Init(void)
bcostm 0:d83f1c8ca282 117 {
bcostm 0:d83f1c8ca282 118 sramHandle.Instance = FMC_NORSRAM_DEVICE;
bcostm 0:d83f1c8ca282 119 sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
bcostm 0:d83f1c8ca282 120
bcostm 0:d83f1c8ca282 121 /* SRAM device configuration */
bcostm 0:d83f1c8ca282 122 Timing.AddressSetupTime = SRAM_ADDR_SETUP_TIME;
bcostm 0:d83f1c8ca282 123 Timing.DataSetupTime = SRAM_DATA_SETUP_TIME;
bcostm 0:d83f1c8ca282 124 Timing.BusTurnAroundDuration = SRAM_TURN_AROUND_TIME;
bcostm 0:d83f1c8ca282 125 Timing.AccessMode = FMC_ACCESS_MODE_A;
bcostm 0:d83f1c8ca282 126
bcostm 0:d83f1c8ca282 127 sramHandle.Init.NSBank = FMC_NORSRAM_BANK2;
bcostm 0:d83f1c8ca282 128 sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
bcostm 0:d83f1c8ca282 129 sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
bcostm 0:d83f1c8ca282 130 sramHandle.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
bcostm 0:d83f1c8ca282 131 sramHandle.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
bcostm 0:d83f1c8ca282 132 sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
bcostm 0:d83f1c8ca282 133 sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
bcostm 0:d83f1c8ca282 134 sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
bcostm 0:d83f1c8ca282 135 sramHandle.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
bcostm 0:d83f1c8ca282 136 sramHandle.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
bcostm 0:d83f1c8ca282 137 sramHandle.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
bcostm 0:d83f1c8ca282 138 sramHandle.Init.PageSize = FMC_PAGE_SIZE_NONE;
bcostm 0:d83f1c8ca282 139
bcostm 0:d83f1c8ca282 140 /* SRAM controller initialization */
bcostm 0:d83f1c8ca282 141 SRAM_MspInit();
bcostm 0:d83f1c8ca282 142 if (HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
bcostm 0:d83f1c8ca282 143 {
bcostm 0:d83f1c8ca282 144 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 145 }
bcostm 0:d83f1c8ca282 146 else
bcostm 0:d83f1c8ca282 147 {
bcostm 0:d83f1c8ca282 148 return SRAM_OK;
bcostm 0:d83f1c8ca282 149 }
bcostm 0:d83f1c8ca282 150 }
bcostm 0:d83f1c8ca282 151
bcostm 0:d83f1c8ca282 152 /**
bcostm 0:d83f1c8ca282 153 * @brief Reads an amount of data from the SRAM device in polling mode.
bcostm 0:d83f1c8ca282 154 * @param uwStartAddress: Read start address
bcostm 0:d83f1c8ca282 155 * @param pData: Pointer to data to be read
bcostm 0:d83f1c8ca282 156 * @param uwDataSize: Size of read data from the memory
bcostm 0:d83f1c8ca282 157 * @retval SRAM status
bcostm 0:d83f1c8ca282 158 */
bcostm 0:d83f1c8ca282 159 uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 160 {
bcostm 0:d83f1c8ca282 161 if (HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 162 {
bcostm 0:d83f1c8ca282 163 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 164 }
bcostm 0:d83f1c8ca282 165 else
bcostm 0:d83f1c8ca282 166 {
bcostm 0:d83f1c8ca282 167 return SRAM_OK;
bcostm 0:d83f1c8ca282 168 }
bcostm 0:d83f1c8ca282 169 }
bcostm 0:d83f1c8ca282 170
bcostm 0:d83f1c8ca282 171 /**
bcostm 0:d83f1c8ca282 172 * @brief Reads an amount of data from the SRAM device in DMA mode.
bcostm 0:d83f1c8ca282 173 * @param uwStartAddress: Read start address
bcostm 0:d83f1c8ca282 174 * @param pData: Pointer to data to be read
bcostm 0:d83f1c8ca282 175 * @param uwDataSize: Size of read data from the memory
bcostm 0:d83f1c8ca282 176 * @retval SRAM status
bcostm 0:d83f1c8ca282 177 */
bcostm 0:d83f1c8ca282 178 uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 179 {
bcostm 0:d83f1c8ca282 180 if (HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 181 {
bcostm 0:d83f1c8ca282 182 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 183 }
bcostm 0:d83f1c8ca282 184 else
bcostm 0:d83f1c8ca282 185 {
bcostm 0:d83f1c8ca282 186 return SRAM_OK;
bcostm 0:d83f1c8ca282 187 }
bcostm 0:d83f1c8ca282 188 }
bcostm 0:d83f1c8ca282 189
bcostm 0:d83f1c8ca282 190 /**
bcostm 0:d83f1c8ca282 191 * @brief Writes an amount of data from the SRAM device in polling mode.
bcostm 0:d83f1c8ca282 192 * @param uwStartAddress: Write start address
bcostm 0:d83f1c8ca282 193 * @param pData: Pointer to data to be written
bcostm 0:d83f1c8ca282 194 * @param uwDataSize: Size of written data from the memory
bcostm 0:d83f1c8ca282 195 * @retval SRAM status
bcostm 0:d83f1c8ca282 196 */
bcostm 0:d83f1c8ca282 197 uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 198 {
bcostm 0:d83f1c8ca282 199 if (HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 200 {
bcostm 0:d83f1c8ca282 201 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 202 }
bcostm 0:d83f1c8ca282 203 else
bcostm 0:d83f1c8ca282 204 {
bcostm 0:d83f1c8ca282 205 return SRAM_OK;
bcostm 0:d83f1c8ca282 206 }
bcostm 0:d83f1c8ca282 207 }
bcostm 0:d83f1c8ca282 208
bcostm 0:d83f1c8ca282 209 /**
bcostm 0:d83f1c8ca282 210 * @brief Writes an amount of data from the SRAM device in DMA mode.
bcostm 0:d83f1c8ca282 211 * @param uwStartAddress: Write start address
bcostm 0:d83f1c8ca282 212 * @param pData: Pointer to data to be written
bcostm 0:d83f1c8ca282 213 * @param uwDataSize: Size of written data from the memory
bcostm 0:d83f1c8ca282 214 * @retval SRAM status
bcostm 0:d83f1c8ca282 215 */
bcostm 0:d83f1c8ca282 216 uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
bcostm 0:d83f1c8ca282 217 {
bcostm 0:d83f1c8ca282 218 if (HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
bcostm 0:d83f1c8ca282 219 {
bcostm 0:d83f1c8ca282 220 return SRAM_ERROR;
bcostm 0:d83f1c8ca282 221 }
bcostm 0:d83f1c8ca282 222 else
bcostm 0:d83f1c8ca282 223 {
bcostm 0:d83f1c8ca282 224 return SRAM_OK;
bcostm 0:d83f1c8ca282 225 }
bcostm 0:d83f1c8ca282 226 }
bcostm 0:d83f1c8ca282 227
bcostm 0:d83f1c8ca282 228 /**
bcostm 0:d83f1c8ca282 229 * @brief Handles SRAM DMA transfer interrupt request.
bcostm 0:d83f1c8ca282 230 * @retval None
bcostm 0:d83f1c8ca282 231 */
bcostm 0:d83f1c8ca282 232 void BSP_SRAM_DMA_IRQHandler(void)
bcostm 0:d83f1c8ca282 233 {
bcostm 0:d83f1c8ca282 234 HAL_DMA_IRQHandler(sramHandle.hdma);
bcostm 0:d83f1c8ca282 235 }
bcostm 0:d83f1c8ca282 236
bcostm 0:d83f1c8ca282 237 /** @addtogroup STM32L476G_EVAL_SRAM_Private_Functions
bcostm 0:d83f1c8ca282 238 * @{
bcostm 0:d83f1c8ca282 239 */
bcostm 0:d83f1c8ca282 240
bcostm 0:d83f1c8ca282 241 /**
bcostm 0:d83f1c8ca282 242 * @brief Initializes SRAM MSP.
bcostm 0:d83f1c8ca282 243 * @retval None
bcostm 0:d83f1c8ca282 244 */
bcostm 0:d83f1c8ca282 245 static void SRAM_MspInit(void)
bcostm 0:d83f1c8ca282 246 {
bcostm 0:d83f1c8ca282 247 static DMA_HandleTypeDef dmaHandle;
bcostm 0:d83f1c8ca282 248 GPIO_InitTypeDef gpioinitstruct;
bcostm 0:d83f1c8ca282 249 SRAM_HandleTypeDef *hsram = &sramHandle;
bcostm 0:d83f1c8ca282 250
bcostm 0:d83f1c8ca282 251 /* Enable FMC clock */
bcostm 0:d83f1c8ca282 252 __HAL_RCC_FMC_CLK_ENABLE();
bcostm 0:d83f1c8ca282 253
bcostm 0:d83f1c8ca282 254 /* Enable chosen DMAx clock */
bcostm 0:d83f1c8ca282 255 SRAM_DMAx_CLK_ENABLE();
bcostm 0:d83f1c8ca282 256
bcostm 0:d83f1c8ca282 257 /* Enable GPIOs clock */
bcostm 0:d83f1c8ca282 258 __HAL_RCC_GPIOD_CLK_ENABLE();
bcostm 0:d83f1c8ca282 259 __HAL_RCC_GPIOE_CLK_ENABLE();
bcostm 0:d83f1c8ca282 260 __HAL_RCC_GPIOF_CLK_ENABLE();
bcostm 0:d83f1c8ca282 261 __HAL_RCC_GPIOG_CLK_ENABLE();
bcostm 0:d83f1c8ca282 262 __HAL_RCC_PWR_CLK_ENABLE();
bcostm 0:d83f1c8ca282 263 HAL_PWREx_EnableVddIO2();
bcostm 0:d83f1c8ca282 264
bcostm 0:d83f1c8ca282 265 /* Common GPIO configuration */
bcostm 0:d83f1c8ca282 266 gpioinitstruct.Mode = GPIO_MODE_AF_PP;
bcostm 0:d83f1c8ca282 267 gpioinitstruct.Pull = GPIO_NOPULL;
bcostm 0:d83f1c8ca282 268 gpioinitstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
bcostm 0:d83f1c8ca282 269 gpioinitstruct.Alternate = GPIO_AF12_FMC;
bcostm 0:d83f1c8ca282 270
bcostm 0:d83f1c8ca282 271 /*## Data Bus #######*/
bcostm 0:d83f1c8ca282 272 /* GPIOD configuration */
bcostm 0:d83f1c8ca282 273 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
bcostm 0:d83f1c8ca282 274 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:d83f1c8ca282 275 HAL_GPIO_Init(GPIOD, &gpioinitstruct);
bcostm 0:d83f1c8ca282 276
bcostm 0:d83f1c8ca282 277 /* GPIOE configuration */
bcostm 0:d83f1c8ca282 278 gpioinitstruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |
bcostm 0:d83f1c8ca282 279 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
bcostm 0:d83f1c8ca282 280 GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:d83f1c8ca282 281 HAL_GPIO_Init(GPIOE, &gpioinitstruct);
bcostm 0:d83f1c8ca282 282
bcostm 0:d83f1c8ca282 283 /*## Address Bus #######*/
bcostm 0:d83f1c8ca282 284 /* GPIOD configuration */
bcostm 0:d83f1c8ca282 285 gpioinitstruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
bcostm 0:d83f1c8ca282 286 HAL_GPIO_Init(GPIOD, &gpioinitstruct);
bcostm 0:d83f1c8ca282 287
bcostm 0:d83f1c8ca282 288 /* GPIOF configuration */
bcostm 0:d83f1c8ca282 289 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
bcostm 0:d83f1c8ca282 290 GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 |
bcostm 0:d83f1c8ca282 291 GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:d83f1c8ca282 292 HAL_GPIO_Init(GPIOF, &gpioinitstruct);
bcostm 0:d83f1c8ca282 293
bcostm 0:d83f1c8ca282 294 /* GPIOG configuration */
bcostm 0:d83f1c8ca282 295 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
bcostm 0:d83f1c8ca282 296 GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
bcostm 0:d83f1c8ca282 297 HAL_GPIO_Init(GPIOG, &gpioinitstruct);
bcostm 0:d83f1c8ca282 298
bcostm 0:d83f1c8ca282 299 /*## NOE and NWE configuration #######*/
bcostm 0:d83f1c8ca282 300 gpioinitstruct.Pull = GPIO_PULLUP;
bcostm 0:d83f1c8ca282 301 gpioinitstruct.Pin = GPIO_PIN_4 | GPIO_PIN_5;
bcostm 0:d83f1c8ca282 302 HAL_GPIO_Init(GPIOD, &gpioinitstruct);
bcostm 0:d83f1c8ca282 303 HAL_Delay(1);
bcostm 0:d83f1c8ca282 304
bcostm 0:d83f1c8ca282 305 /*## NBL0, NBL1 configuration #######*/
bcostm 0:d83f1c8ca282 306 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
bcostm 0:d83f1c8ca282 307 HAL_GPIO_Init(GPIOE, &gpioinitstruct);
bcostm 0:d83f1c8ca282 308
bcostm 0:d83f1c8ca282 309 /*## NE configuration #######*/
bcostm 0:d83f1c8ca282 310 gpioinitstruct.Pin = GPIO_PIN_9;
bcostm 0:d83f1c8ca282 311 HAL_GPIO_Init(GPIOG, &gpioinitstruct);
bcostm 0:d83f1c8ca282 312
bcostm 0:d83f1c8ca282 313 /* Configure common DMA parameters */
bcostm 0:d83f1c8ca282 314 dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;
bcostm 0:d83f1c8ca282 315 dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;
bcostm 0:d83f1c8ca282 316 dmaHandle.Init.MemInc = DMA_MINC_ENABLE;
bcostm 0:d83f1c8ca282 317 dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
bcostm 0:d83f1c8ca282 318 dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
bcostm 0:d83f1c8ca282 319 dmaHandle.Init.Mode = DMA_NORMAL;
bcostm 0:d83f1c8ca282 320 dmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
bcostm 0:d83f1c8ca282 321
bcostm 0:d83f1c8ca282 322 dmaHandle.Instance = SRAM_DMAx_CHANNEL;
bcostm 0:d83f1c8ca282 323
bcostm 0:d83f1c8ca282 324 /* Associate the DMA handle */
bcostm 0:d83f1c8ca282 325 __HAL_LINKDMA(hsram, hdma, dmaHandle);
bcostm 0:d83f1c8ca282 326
bcostm 0:d83f1c8ca282 327 /* Deinitialize the Stream for new transfer */
bcostm 0:d83f1c8ca282 328 HAL_DMA_DeInit(&dmaHandle);
bcostm 0:d83f1c8ca282 329
bcostm 0:d83f1c8ca282 330 /* Configure the DMA Stream */
bcostm 0:d83f1c8ca282 331 HAL_DMA_Init(&dmaHandle);
bcostm 0:d83f1c8ca282 332
bcostm 0:d83f1c8ca282 333 /* NVIC configuration for DMA transfer complete interrupt */
bcostm 0:d83f1c8ca282 334 HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 5, 0);
bcostm 0:d83f1c8ca282 335 HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
bcostm 0:d83f1c8ca282 336 }
bcostm 0:d83f1c8ca282 337
bcostm 0:d83f1c8ca282 338 /**
bcostm 0:d83f1c8ca282 339 * @}
bcostm 0:d83f1c8ca282 340 */
bcostm 0:d83f1c8ca282 341
bcostm 0:d83f1c8ca282 342 /**
bcostm 0:d83f1c8ca282 343 * @}
bcostm 0:d83f1c8ca282 344 */
bcostm 0:d83f1c8ca282 345
bcostm 0:d83f1c8ca282 346 /**
bcostm 0:d83f1c8ca282 347 * @}
bcostm 0:d83f1c8ca282 348 */
bcostm 0:d83f1c8ca282 349
bcostm 0:d83f1c8ca282 350 /**
bcostm 0:d83f1c8ca282 351 * @}
bcostm 0:d83f1c8ca282 352 */
bcostm 0:d83f1c8ca282 353
bcostm 0:d83f1c8ca282 354 /**
bcostm 0:d83f1c8ca282 355 * @}
bcostm 0:d83f1c8ca282 356 */
bcostm 0:d83f1c8ca282 357
bcostm 0:d83f1c8ca282 358 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/