ST / BSP_DISCO_L496AG

BSP driver for DISCO_L496AG

Dependents:   DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo

Drivers/BSP/Components/mfxstm32l152/mfxstm32l152.h@2:106c7b82e064, 2019-11-20 (annotated)

Committer:
Jerome Coutant
Date:
Wed Nov 20 16:48:24 2019 +0100
Revision:
2:106c7b82e064
Parent:
0:d83f1c8ca282 
Update BSP files with CubeL4 V1.14.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:d83f1c8ca282 1 /**
bcostm 0:d83f1c8ca282 2 ******************************************************************************
bcostm 0:d83f1c8ca282 3 * @file mfxstm32l152.h
bcostm 0:d83f1c8ca282 4 * @author MCD Application Team
bcostm 0:d83f1c8ca282 5 * @brief This file contains all the functions prototypes for the
bcostm 0:d83f1c8ca282 6 * mfxstm32l152.c IO expander driver.
bcostm 0:d83f1c8ca282 7 ******************************************************************************
bcostm 0:d83f1c8ca282 8 * @attention
bcostm 0:d83f1c8ca282 9 *
Jerome Coutant 2:106c7b82e064 10 * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
Jerome Coutant 2:106c7b82e064 11 * All rights reserved.</center></h2>
bcostm 0:d83f1c8ca282 12 *
Jerome Coutant 2:106c7b82e064 13 * This software component is licensed by ST under BSD 3-Clause license,
Jerome Coutant 2:106c7b82e064 14 * the "License"; You may not use this file except in compliance with the
Jerome Coutant 2:106c7b82e064 15 * License. You may obtain a copy of the License at:
Jerome Coutant 2:106c7b82e064 16 * opensource.org/licenses/BSD-3-Clause
bcostm 0:d83f1c8ca282 17 *
bcostm 0:d83f1c8ca282 18 ******************************************************************************
Jerome Coutant 2:106c7b82e064 19 */
bcostm 0:d83f1c8ca282 20
bcostm 0:d83f1c8ca282 21 /* Define to prevent recursive inclusion -------------------------------------*/
bcostm 0:d83f1c8ca282 22 #ifndef __MFXSTM32L152_H
bcostm 0:d83f1c8ca282 23 #define __MFXSTM32L152_H
bcostm 0:d83f1c8ca282 24
bcostm 0:d83f1c8ca282 25 #ifdef __cplusplus
bcostm 0:d83f1c8ca282 26 extern "C" {
Jerome Coutant 2:106c7b82e064 27 #endif
Jerome Coutant 2:106c7b82e064 28
bcostm 0:d83f1c8ca282 29 /* Includes ------------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 30 #include "../Common/ts.h"
bcostm 0:d83f1c8ca282 31 #include "../Common/io.h"
bcostm 0:d83f1c8ca282 32 #include "../Common/idd.h"
bcostm 0:d83f1c8ca282 33
bcostm 0:d83f1c8ca282 34 /** @addtogroup BSP
bcostm 0:d83f1c8ca282 35 * @{
Jerome Coutant 2:106c7b82e064 36 */
bcostm 0:d83f1c8ca282 37
bcostm 0:d83f1c8ca282 38 /** @addtogroup Component
bcostm 0:d83f1c8ca282 39 * @{
bcostm 0:d83f1c8ca282 40 */
Jerome Coutant 2:106c7b82e064 41
bcostm 0:d83f1c8ca282 42 /** @defgroup MFXSTM32L152
bcostm 0:d83f1c8ca282 43 * @{
Jerome Coutant 2:106c7b82e064 44 */
bcostm 0:d83f1c8ca282 45
bcostm 0:d83f1c8ca282 46 /* Exported types ------------------------------------------------------------*/
bcostm 0:d83f1c8ca282 47
bcostm 0:d83f1c8ca282 48 /** @defgroup MFXSTM32L152_Exported_Types
bcostm 0:d83f1c8ca282 49 * @{
Jerome Coutant 2:106c7b82e064 50 */
bcostm 0:d83f1c8ca282 51 typedef struct
bcostm 0:d83f1c8ca282 52 {
bcostm 0:d83f1c8ca282 53 uint8_t SYS_CTRL;
bcostm 0:d83f1c8ca282 54 uint8_t ERROR_SRC;
bcostm 0:d83f1c8ca282 55 uint8_t ERROR_MSG;
bcostm 0:d83f1c8ca282 56 uint8_t IRQ_OUT;
bcostm 0:d83f1c8ca282 57 uint8_t IRQ_SRC_EN;
bcostm 0:d83f1c8ca282 58 uint8_t IRQ_PENDING;
bcostm 0:d83f1c8ca282 59 uint8_t IDD_CTRL;
bcostm 0:d83f1c8ca282 60 uint8_t IDD_PRE_DELAY;
bcostm 0:d83f1c8ca282 61 uint8_t IDD_SHUNT0_MSB;
bcostm 0:d83f1c8ca282 62 uint8_t IDD_SHUNT0_LSB;
bcostm 0:d83f1c8ca282 63 uint8_t IDD_SHUNT1_MSB;
bcostm 0:d83f1c8ca282 64 uint8_t IDD_SHUNT1_LSB;
bcostm 0:d83f1c8ca282 65 uint8_t IDD_SHUNT2_MSB;
bcostm 0:d83f1c8ca282 66 uint8_t IDD_SHUNT2_LSB;
bcostm 0:d83f1c8ca282 67 uint8_t IDD_SHUNT3_MSB;
bcostm 0:d83f1c8ca282 68 uint8_t IDD_SHUNT3_LSB;
bcostm 0:d83f1c8ca282 69 uint8_t IDD_SHUNT4_MSB;
bcostm 0:d83f1c8ca282 70 uint8_t IDD_SHUNT4_LSB;
bcostm 0:d83f1c8ca282 71 uint8_t IDD_GAIN_MSB;
bcostm 0:d83f1c8ca282 72 uint8_t IDD_GAIN_LSB;
bcostm 0:d83f1c8ca282 73 uint8_t IDD_VDD_MIN_MSB;
bcostm 0:d83f1c8ca282 74 uint8_t IDD_VDD_MIN_LSB;
bcostm 0:d83f1c8ca282 75 uint8_t IDD_VALUE_MSB;
bcostm 0:d83f1c8ca282 76 uint8_t IDD_VALUE_MID;
bcostm 0:d83f1c8ca282 77 uint8_t IDD_VALUE_LSB;
bcostm 0:d83f1c8ca282 78 uint8_t IDD_CAL_OFFSET_MSB;
bcostm 0:d83f1c8ca282 79 uint8_t IDD_CAL_OFFSET_LSB;
bcostm 0:d83f1c8ca282 80 uint8_t IDD_SHUNT_USED;
bcostm 0:d83f1c8ca282 81 }IDD_dbgTypeDef;
bcostm 0:d83f1c8ca282 82
bcostm 0:d83f1c8ca282 83 /**
bcostm 0:d83f1c8ca282 84 * @}
bcostm 0:d83f1c8ca282 85 */
bcostm 0:d83f1c8ca282 86
bcostm 0:d83f1c8ca282 87 /* Exported constants --------------------------------------------------------*/
Jerome Coutant 2:106c7b82e064 88
bcostm 0:d83f1c8ca282 89 /** @defgroup MFXSTM32L152_Exported_Constants
bcostm 0:d83f1c8ca282 90 * @{
Jerome Coutant 2:106c7b82e064 91 */
bcostm 0:d83f1c8ca282 92
bcostm 0:d83f1c8ca282 93 /**
bcostm 0:d83f1c8ca282 94 * @brief MFX COMMON defines
bcostm 0:d83f1c8ca282 95 */
Jerome Coutant 2:106c7b82e064 96
bcostm 0:d83f1c8ca282 97 /**
bcostm 0:d83f1c8ca282 98 * @brief Register address: chip IDs (R)
bcostm 0:d83f1c8ca282 99 */
bcostm 0:d83f1c8ca282 100 #define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00)
bcostm 0:d83f1c8ca282 101 /**
bcostm 0:d83f1c8ca282 102 * @brief Register address: chip FW_VERSION (R)
bcostm 0:d83f1c8ca282 103 */
bcostm 0:d83f1c8ca282 104 #define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01)
bcostm 0:d83f1c8ca282 105 #define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00)
bcostm 0:d83f1c8ca282 106 /**
bcostm 0:d83f1c8ca282 107 * @brief Register address: System Control Register (R/W)
bcostm 0:d83f1c8ca282 108 */
bcostm 0:d83f1c8ca282 109 #define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40)
bcostm 0:d83f1c8ca282 110 /**
bcostm 0:d83f1c8ca282 111 * @brief Register address: Vdd monitoring (R)
bcostm 0:d83f1c8ca282 112 */
bcostm 0:d83f1c8ca282 113 #define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06)
bcostm 0:d83f1c8ca282 114 #define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07)
bcostm 0:d83f1c8ca282 115 /**
bcostm 0:d83f1c8ca282 116 * @brief Register address: Error source
bcostm 0:d83f1c8ca282 117 */
bcostm 0:d83f1c8ca282 118 #define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03)
bcostm 0:d83f1c8ca282 119 /**
bcostm 0:d83f1c8ca282 120 * @brief Register address: Error Message
bcostm 0:d83f1c8ca282 121 */
bcostm 0:d83f1c8ca282 122 #define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04)
bcostm 0:d83f1c8ca282 123
bcostm 0:d83f1c8ca282 124 /**
bcostm 0:d83f1c8ca282 125 * @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear
bcostm 0:d83f1c8ca282 126 */
bcostm 0:d83f1c8ca282 127 #define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41)
bcostm 0:d83f1c8ca282 128 /**
bcostm 0:d83f1c8ca282 129 * @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal
bcostm 0:d83f1c8ca282 130 */
bcostm 0:d83f1c8ca282 131 #define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42)
bcostm 0:d83f1c8ca282 132 /**
bcostm 0:d83f1c8ca282 133 * @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason
bcostm 0:d83f1c8ca282 134 */
bcostm 0:d83f1c8ca282 135 #define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08)
bcostm 0:d83f1c8ca282 136 /**
bcostm 0:d83f1c8ca282 137 * @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register
bcostm 0:d83f1c8ca282 138 */
bcostm 0:d83f1c8ca282 139 #define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44)
Jerome Coutant 2:106c7b82e064 140
bcostm 0:d83f1c8ca282 141 /**
bcostm 0:d83f1c8ca282 142 * @brief MFXSTM32L152_REG_ADR_ID choices
bcostm 0:d83f1c8ca282 143 */
bcostm 0:d83f1c8ca282 144 #define MFXSTM32L152_ID_1 ((uint8_t)0x7B)
bcostm 0:d83f1c8ca282 145 #define MFXSTM32L152_ID_2 ((uint8_t)0x79)
Jerome Coutant 2:106c7b82e064 146
bcostm 0:d83f1c8ca282 147 /**
bcostm 0:d83f1c8ca282 148 * @brief MFXSTM32L152_REG_ADR_SYS_CTRL choices
bcostm 0:d83f1c8ca282 149 */
bcostm 0:d83f1c8ca282 150 #define MFXSTM32L152_SWRST ((uint8_t)0x80)
bcostm 0:d83f1c8ca282 151 #define MFXSTM32L152_STANDBY ((uint8_t)0x40)
bcostm 0:d83f1c8ca282 152 #define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/
bcostm 0:d83f1c8ca282 153 #define MFXSTM32L152_IDD_EN ((uint8_t)0x04)
bcostm 0:d83f1c8ca282 154 #define MFXSTM32L152_TS_EN ((uint8_t)0x02)
bcostm 0:d83f1c8ca282 155 #define MFXSTM32L152_GPIO_EN ((uint8_t)0x01)
bcostm 0:d83f1c8ca282 156
bcostm 0:d83f1c8ca282 157 /**
bcostm 0:d83f1c8ca282 158 * @brief MFXSTM32L152_REG_ADR_ERROR_SRC choices
bcostm 0:d83f1c8ca282 159 */
bcostm 0:d83f1c8ca282 160 #define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */
bcostm 0:d83f1c8ca282 161 #define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */
bcostm 0:d83f1c8ca282 162 #define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */
bcostm 0:d83f1c8ca282 163
bcostm 0:d83f1c8ca282 164 /**
bcostm 0:d83f1c8ca282 165 * @brief MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices
bcostm 0:d83f1c8ca282 166 */
bcostm 0:d83f1c8ca282 167 #define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00)
bcostm 0:d83f1c8ca282 168 #define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01)
bcostm 0:d83f1c8ca282 169 #define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00)
bcostm 0:d83f1c8ca282 170 #define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02)
bcostm 0:d83f1c8ca282 171
bcostm 0:d83f1c8ca282 172 /**
bcostm 0:d83f1c8ca282 173 * @brief REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices
bcostm 0:d83f1c8ca282 174 */
bcostm 0:d83f1c8ca282 175 #define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/
bcostm 0:d83f1c8ca282 176 #define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/
bcostm 0:d83f1c8ca282 177 #define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/
bcostm 0:d83f1c8ca282 178 #define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/
bcostm 0:d83f1c8ca282 179 #define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/
bcostm 0:d83f1c8ca282 180 #define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */
bcostm 0:d83f1c8ca282 181 #define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */
bcostm 0:d83f1c8ca282 182 #define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */
bcostm 0:d83f1c8ca282 183 #define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */
Jerome Coutant 2:106c7b82e064 184 #define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF )
bcostm 0:d83f1c8ca282 185
Jerome Coutant 2:106c7b82e064 186
bcostm 0:d83f1c8ca282 187 /**
bcostm 0:d83f1c8ca282 188 * @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided
bcostm 0:d83f1c8ca282 189 */
bcostm 0:d83f1c8ca282 190
bcostm 0:d83f1c8ca282 191 /**
bcostm 0:d83f1c8ca282 192 * @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output.
bcostm 0:d83f1c8ca282 193 */
bcostm 0:d83f1c8ca282 194 #define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 195 #define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 196 #define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 197 /**
bcostm 0:d83f1c8ca282 198 * @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain.
bcostm 0:d83f1c8ca282 199 * If GPIO in input: (0) input without pull resistor, (1) input with pull resistor.
bcostm 0:d83f1c8ca282 200 */
bcostm 0:d83f1c8ca282 201 #define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 202 #define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 203 #define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 204 /**
bcostm 0:d83f1c8ca282 205 * @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude
bcostm 0:d83f1c8ca282 206 */
bcostm 0:d83f1c8ca282 207 #define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 208 #define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 209 #define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 210 /**
bcostm 0:d83f1c8ca282 211 * @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level.
bcostm 0:d83f1c8ca282 212 */
bcostm 0:d83f1c8ca282 213 #define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 214 #define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 215 #define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 216 /**
bcostm 0:d83f1c8ca282 217 * @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level.
bcostm 0:d83f1c8ca282 218 */
bcostm 0:d83f1c8ca282 219 #define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 220 #define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 221 #define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 222 /**
bcostm 0:d83f1c8ca282 223 * @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin.
bcostm 0:d83f1c8ca282 224 */
bcostm 0:d83f1c8ca282 225 #define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 226 #define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 227 #define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 228
bcostm 0:d83f1c8ca282 229 /**
bcostm 0:d83f1c8ca282 230 * @brief GPIO IRQ_GPIs
bcostm 0:d83f1c8ca282 231 */
bcostm 0:d83f1c8ca282 232 /* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */
bcostm 0:d83f1c8ca282 233 /* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */
bcostm 0:d83f1c8ca282 234 /**
bcostm 0:d83f1c8ca282 235 * @brief GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq
bcostm 0:d83f1c8ca282 236 */
bcostm 0:d83f1c8ca282 237 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 238 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 239 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 240 /**
bcostm 0:d83f1c8ca282 241 * @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1).
bcostm 0:d83f1c8ca282 242 */
bcostm 0:d83f1c8ca282 243 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 244 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 245 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 246 /**
bcostm 0:d83f1c8ca282 247 * @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge.
bcostm 0:d83f1c8ca282 248 */
bcostm 0:d83f1c8ca282 249 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 250 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 251 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 252 /**
bcostm 0:d83f1c8ca282 253 * @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs
bcostm 0:d83f1c8ca282 254 */
bcostm 0:d83f1c8ca282 255 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 256 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 257 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 258 /**
bcostm 0:d83f1c8ca282 259 * @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event
bcostm 0:d83f1c8ca282 260 */
bcostm 0:d83f1c8ca282 261 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */
bcostm 0:d83f1c8ca282 262 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */
bcostm 0:d83f1c8ca282 263 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */
bcostm 0:d83f1c8ca282 264
Jerome Coutant 2:106c7b82e064 265
bcostm 0:d83f1c8ca282 266 /**
bcostm 0:d83f1c8ca282 267 * @brief GPIO: IO Pins definition
bcostm 0:d83f1c8ca282 268 */
bcostm 0:d83f1c8ca282 269 #define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001)
bcostm 0:d83f1c8ca282 270 #define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002)
bcostm 0:d83f1c8ca282 271 #define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004)
bcostm 0:d83f1c8ca282 272 #define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008)
bcostm 0:d83f1c8ca282 273 #define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010)
bcostm 0:d83f1c8ca282 274 #define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020)
bcostm 0:d83f1c8ca282 275 #define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040)
bcostm 0:d83f1c8ca282 276 #define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080)
bcostm 0:d83f1c8ca282 277
Jerome Coutant 2:106c7b82e064 278 #define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100)
Jerome Coutant 2:106c7b82e064 279 #define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200)
Jerome Coutant 2:106c7b82e064 280 #define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400)
bcostm 0:d83f1c8ca282 281 #define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800)
Jerome Coutant 2:106c7b82e064 282 #define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000)
Jerome Coutant 2:106c7b82e064 283 #define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000)
Jerome Coutant 2:106c7b82e064 284 #define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000)
Jerome Coutant 2:106c7b82e064 285 #define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000)
bcostm 0:d83f1c8ca282 286
bcostm 0:d83f1c8ca282 287 #define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000)
bcostm 0:d83f1c8ca282 288 #define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000)
bcostm 0:d83f1c8ca282 289 #define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000)
bcostm 0:d83f1c8ca282 290 #define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000)
bcostm 0:d83f1c8ca282 291 #define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000)
bcostm 0:d83f1c8ca282 292 #define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000)
bcostm 0:d83f1c8ca282 293 #define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000)
bcostm 0:d83f1c8ca282 294 #define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000)
bcostm 0:d83f1c8ca282 295
bcostm 0:d83f1c8ca282 296 #define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16
bcostm 0:d83f1c8ca282 297 #define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17
bcostm 0:d83f1c8ca282 298 #define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18
bcostm 0:d83f1c8ca282 299 #define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19
bcostm 0:d83f1c8ca282 300 #define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20
bcostm 0:d83f1c8ca282 301 #define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21
bcostm 0:d83f1c8ca282 302 #define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22
bcostm 0:d83f1c8ca282 303 #define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23
bcostm 0:d83f1c8ca282 304
bcostm 0:d83f1c8ca282 305 #define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF)
bcostm 0:d83f1c8ca282 306
bcostm 0:d83f1c8ca282 307 /**
bcostm 0:d83f1c8ca282 308 * @brief GPIO: constant
bcostm 0:d83f1c8ca282 309 */
Jerome Coutant 2:106c7b82e064 310 #define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0)
Jerome Coutant 2:106c7b82e064 311 #define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1)
Jerome Coutant 2:106c7b82e064 312 #define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0)
Jerome Coutant 2:106c7b82e064 313 #define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1)
bcostm 0:d83f1c8ca282 314 #define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */
bcostm 0:d83f1c8ca282 315 #define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */
Jerome Coutant 2:106c7b82e064 316 #define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0)
Jerome Coutant 2:106c7b82e064 317 #define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1)
Jerome Coutant 2:106c7b82e064 318 #define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0)
Jerome Coutant 2:106c7b82e064 319 #define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1)
Jerome Coutant 2:106c7b82e064 320 #define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0)
Jerome Coutant 2:106c7b82e064 321 #define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1)
Jerome Coutant 2:106c7b82e064 322
Jerome Coutant 2:106c7b82e064 323
bcostm 0:d83f1c8ca282 324 /**
bcostm 0:d83f1c8ca282 325 * @brief TOUCH SCREEN Registers
bcostm 0:d83f1c8ca282 326 */
bcostm 0:d83f1c8ca282 327
bcostm 0:d83f1c8ca282 328 /**
bcostm 0:d83f1c8ca282 329 * @brief Touch Screen Registers
bcostm 0:d83f1c8ca282 330 */
bcostm 0:d83f1c8ca282 331 #define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0)
bcostm 0:d83f1c8ca282 332 #define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1)
bcostm 0:d83f1c8ca282 333 #define MFXSTM32L152_TS_AVE ((uint8_t)0xA2)
bcostm 0:d83f1c8ca282 334 #define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3)
bcostm 0:d83f1c8ca282 335 #define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4)
bcostm 0:d83f1c8ca282 336 #define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20)
bcostm 0:d83f1c8ca282 337 #define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21)
bcostm 0:d83f1c8ca282 338 #define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24)
bcostm 0:d83f1c8ca282 339
bcostm 0:d83f1c8ca282 340 /**
bcostm 0:d83f1c8ca282 341 * @brief TS registers masks
bcostm 0:d83f1c8ca282 342 */
bcostm 0:d83f1c8ca282 343 #define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08)
bcostm 0:d83f1c8ca282 344 #define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80)
bcostm 0:d83f1c8ca282 345
bcostm 0:d83f1c8ca282 346
bcostm 0:d83f1c8ca282 347 /**
bcostm 0:d83f1c8ca282 348 * @brief Register address: Idd control register (R/W)
bcostm 0:d83f1c8ca282 349 */
bcostm 0:d83f1c8ca282 350 #define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80)
bcostm 0:d83f1c8ca282 351
bcostm 0:d83f1c8ca282 352 /**
bcostm 0:d83f1c8ca282 353 * @brief Register address: Idd pre delay register (R/W)
bcostm 0:d83f1c8ca282 354 */
bcostm 0:d83f1c8ca282 355 #define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81)
bcostm 0:d83f1c8ca282 356
bcostm 0:d83f1c8ca282 357 /**
bcostm 0:d83f1c8ca282 358 * @brief Register address: Idd Shunt registers (R/W)
bcostm 0:d83f1c8ca282 359 */
bcostm 0:d83f1c8ca282 360 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82)
bcostm 0:d83f1c8ca282 361 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83)
bcostm 0:d83f1c8ca282 362 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84)
bcostm 0:d83f1c8ca282 363 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85)
bcostm 0:d83f1c8ca282 364 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86)
bcostm 0:d83f1c8ca282 365 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87)
bcostm 0:d83f1c8ca282 366 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88)
bcostm 0:d83f1c8ca282 367 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89)
bcostm 0:d83f1c8ca282 368 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A)
bcostm 0:d83f1c8ca282 369 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B)
bcostm 0:d83f1c8ca282 370
bcostm 0:d83f1c8ca282 371 /**
bcostm 0:d83f1c8ca282 372 * @brief Register address: Idd ampli gain register (R/W)
bcostm 0:d83f1c8ca282 373 */
bcostm 0:d83f1c8ca282 374 #define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C)
bcostm 0:d83f1c8ca282 375 #define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D)
bcostm 0:d83f1c8ca282 376
bcostm 0:d83f1c8ca282 377 /**
bcostm 0:d83f1c8ca282 378 * @brief Register address: Idd VDD min register (R/W)
bcostm 0:d83f1c8ca282 379 */
bcostm 0:d83f1c8ca282 380 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E)
bcostm 0:d83f1c8ca282 381 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F)
bcostm 0:d83f1c8ca282 382
bcostm 0:d83f1c8ca282 383 /**
bcostm 0:d83f1c8ca282 384 * @brief Register address: Idd value register (R)
bcostm 0:d83f1c8ca282 385 */
bcostm 0:d83f1c8ca282 386 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14)
bcostm 0:d83f1c8ca282 387 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15)
bcostm 0:d83f1c8ca282 388 #define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16)
bcostm 0:d83f1c8ca282 389
bcostm 0:d83f1c8ca282 390 /**
bcostm 0:d83f1c8ca282 391 * @brief Register address: Idd calibration offset register (R)
bcostm 0:d83f1c8ca282 392 */
bcostm 0:d83f1c8ca282 393 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18)
bcostm 0:d83f1c8ca282 394 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19)
bcostm 0:d83f1c8ca282 395
bcostm 0:d83f1c8ca282 396 /**
bcostm 0:d83f1c8ca282 397 * @brief Register address: Idd shunt used offset register (R)
bcostm 0:d83f1c8ca282 398 */
bcostm 0:d83f1c8ca282 399 #define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A)
bcostm 0:d83f1c8ca282 400
bcostm 0:d83f1c8ca282 401 /**
bcostm 0:d83f1c8ca282 402 * @brief Register address: shunt stabilisation delay registers (R/W)
bcostm 0:d83f1c8ca282 403 */
bcostm 0:d83f1c8ca282 404 #define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90)
bcostm 0:d83f1c8ca282 405 #define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91)
bcostm 0:d83f1c8ca282 406 #define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92)
bcostm 0:d83f1c8ca282 407 #define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93)
bcostm 0:d83f1c8ca282 408 #define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94)
bcostm 0:d83f1c8ca282 409
bcostm 0:d83f1c8ca282 410 /**
bcostm 0:d83f1c8ca282 411 * @brief Register address: Idd number of measurements register (R/W)
bcostm 0:d83f1c8ca282 412 */
bcostm 0:d83f1c8ca282 413 #define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96)
bcostm 0:d83f1c8ca282 414
bcostm 0:d83f1c8ca282 415 /**
bcostm 0:d83f1c8ca282 416 * @brief Register address: Idd delta delay between 2 measurements register (R/W)
bcostm 0:d83f1c8ca282 417 */
bcostm 0:d83f1c8ca282 418 #define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97)
bcostm 0:d83f1c8ca282 419
bcostm 0:d83f1c8ca282 420 /**
bcostm 0:d83f1c8ca282 421 * @brief Register address: Idd number of shunt on board register (R/W)
bcostm 0:d83f1c8ca282 422 */
bcostm 0:d83f1c8ca282 423 #define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98)
bcostm 0:d83f1c8ca282 424
Jerome Coutant 2:106c7b82e064 425
bcostm 0:d83f1c8ca282 426
bcostm 0:d83f1c8ca282 427 /** @defgroup IDD_Control_Register_Defines IDD Control Register Defines
bcostm 0:d83f1c8ca282 428 * @{
bcostm 0:d83f1c8ca282 429 */
bcostm 0:d83f1c8ca282 430 /**
bcostm 0:d83f1c8ca282 431 * @brief IDD control register masks
bcostm 0:d83f1c8ca282 432 */
bcostm 0:d83f1c8ca282 433 #define MFXSTM32L152_IDD_CTRL_REQ ((uint8_t)0x01)
bcostm 0:d83f1c8ca282 434 #define MFXSTM32L152_IDD_CTRL_SHUNT_NB ((uint8_t)0x0E)
bcostm 0:d83f1c8ca282 435 #define MFXSTM32L152_IDD_CTRL_VREF_DIS ((uint8_t)0x40)
bcostm 0:d83f1c8ca282 436 #define MFXSTM32L152_IDD_CTRL_CAL_DIS ((uint8_t)0x80)
bcostm 0:d83f1c8ca282 437
bcostm 0:d83f1c8ca282 438 /**
bcostm 0:d83f1c8ca282 439 * @brief IDD Shunt Number
bcostm 0:d83f1c8ca282 440 */
bcostm 0:d83f1c8ca282 441 #define MFXSTM32L152_IDD_SHUNT_NB_1 ((uint8_t) 0x01)
bcostm 0:d83f1c8ca282 442 #define MFXSTM32L152_IDD_SHUNT_NB_2 ((uint8_t) 0x02)
bcostm 0:d83f1c8ca282 443 #define MFXSTM32L152_IDD_SHUNT_NB_3 ((uint8_t) 0x03)
bcostm 0:d83f1c8ca282 444 #define MFXSTM32L152_IDD_SHUNT_NB_4 ((uint8_t) 0x04)
bcostm 0:d83f1c8ca282 445 #define MFXSTM32L152_IDD_SHUNT_NB_5 ((uint8_t) 0x05)
bcostm 0:d83f1c8ca282 446
bcostm 0:d83f1c8ca282 447 /**
bcostm 0:d83f1c8ca282 448 * @brief Vref Measurement
bcostm 0:d83f1c8ca282 449 */
bcostm 0:d83f1c8ca282 450 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE ((uint8_t) 0x00)
bcostm 0:d83f1c8ca282 451 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE ((uint8_t) 0x70)
bcostm 0:d83f1c8ca282 452
bcostm 0:d83f1c8ca282 453 /**
bcostm 0:d83f1c8ca282 454 * @brief IDD Calibration
bcostm 0:d83f1c8ca282 455 */
bcostm 0:d83f1c8ca282 456 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE ((uint8_t) 0x00)
bcostm 0:d83f1c8ca282 457 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE ((uint8_t) 0x80)
bcostm 0:d83f1c8ca282 458 /**
bcostm 0:d83f1c8ca282 459 * @}
bcostm 0:d83f1c8ca282 460 */
bcostm 0:d83f1c8ca282 461
bcostm 0:d83f1c8ca282 462 /** @defgroup IDD_PreDelay_Defines IDD PreDelay Defines
bcostm 0:d83f1c8ca282 463 * @{
bcostm 0:d83f1c8ca282 464 */
bcostm 0:d83f1c8ca282 465 /**
bcostm 0:d83f1c8ca282 466 * @brief IDD PreDelay masks
bcostm 0:d83f1c8ca282 467 */
bcostm 0:d83f1c8ca282 468 #define MFXSTM32L152_IDD_PREDELAY_UNIT ((uint8_t) 0x80)
bcostm 0:d83f1c8ca282 469 #define MFXSTM32L152_IDD_PREDELAY_VALUE ((uint8_t) 0x7F)
bcostm 0:d83f1c8ca282 470
bcostm 0:d83f1c8ca282 471
bcostm 0:d83f1c8ca282 472 /**
bcostm 0:d83f1c8ca282 473 * @brief IDD PreDelay unit
bcostm 0:d83f1c8ca282 474 */
bcostm 0:d83f1c8ca282 475 #define MFXSTM32L152_IDD_PREDELAY_0_5_MS ((uint8_t) 0x00)
bcostm 0:d83f1c8ca282 476 #define MFXSTM32L152_IDD_PREDELAY_20_MS ((uint8_t) 0x80)
bcostm 0:d83f1c8ca282 477 /**
bcostm 0:d83f1c8ca282 478 * @}
bcostm 0:d83f1c8ca282 479 */
bcostm 0:d83f1c8ca282 480
bcostm 0:d83f1c8ca282 481 /** @defgroup IDD_DeltaDelay_Defines IDD Delta DElay Defines
bcostm 0:d83f1c8ca282 482 * @{
bcostm 0:d83f1c8ca282 483 */
bcostm 0:d83f1c8ca282 484 /**
bcostm 0:d83f1c8ca282 485 * @brief IDD Delta Delay masks
bcostm 0:d83f1c8ca282 486 */
bcostm 0:d83f1c8ca282 487 #define MFXSTM32L152_IDD_DELTADELAY_UNIT ((uint8_t) 0x80)
bcostm 0:d83f1c8ca282 488 #define MFXSTM32L152_IDD_DELTADELAY_VALUE ((uint8_t) 0x7F)
bcostm 0:d83f1c8ca282 489
bcostm 0:d83f1c8ca282 490
bcostm 0:d83f1c8ca282 491 /**
bcostm 0:d83f1c8ca282 492 * @brief IDD Delta Delay unit
bcostm 0:d83f1c8ca282 493 */
bcostm 0:d83f1c8ca282 494 #define MFXSTM32L152_IDD_DELTADELAY_0_5_MS ((uint8_t) 0x00)
bcostm 0:d83f1c8ca282 495 #define MFXSTM32L152_IDD_DELTADELAY_20_MS ((uint8_t) 0x80)
bcostm 0:d83f1c8ca282 496
bcostm 0:d83f1c8ca282 497
bcostm 0:d83f1c8ca282 498 /**
bcostm 0:d83f1c8ca282 499 * @}
bcostm 0:d83f1c8ca282 500 */
bcostm 0:d83f1c8ca282 501
bcostm 0:d83f1c8ca282 502 /**
bcostm 0:d83f1c8ca282 503 * @}
bcostm 0:d83f1c8ca282 504 */
bcostm 0:d83f1c8ca282 505
Jerome Coutant 2:106c7b82e064 506
bcostm 0:d83f1c8ca282 507 /* Exported macro ------------------------------------------------------------*/
Jerome Coutant 2:106c7b82e064 508
bcostm 0:d83f1c8ca282 509 /** @defgroup MFXSTM32L152_Exported_Macros
bcostm 0:d83f1c8ca282 510 * @{
Jerome Coutant 2:106c7b82e064 511 */
bcostm 0:d83f1c8ca282 512
bcostm 0:d83f1c8ca282 513 /**
bcostm 0:d83f1c8ca282 514 * @}
Jerome Coutant 2:106c7b82e064 515 */
bcostm 0:d83f1c8ca282 516
bcostm 0:d83f1c8ca282 517 /* Exported functions --------------------------------------------------------*/
Jerome Coutant 2:106c7b82e064 518
bcostm 0:d83f1c8ca282 519 /** @defgroup MFXSTM32L152_Exported_Functions
bcostm 0:d83f1c8ca282 520 * @{
bcostm 0:d83f1c8ca282 521 */
bcostm 0:d83f1c8ca282 522
Jerome Coutant 2:106c7b82e064 523 /**
bcostm 0:d83f1c8ca282 524 * @brief MFXSTM32L152 Control functions
bcostm 0:d83f1c8ca282 525 */
bcostm 0:d83f1c8ca282 526 void mfxstm32l152_Init(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 527 void mfxstm32l152_DeInit(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 528 void mfxstm32l152_Reset(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 529 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 530 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 531 void mfxstm32l152_LowPower(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 532 void mfxstm32l152_WakeUp(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 533
bcostm 0:d83f1c8ca282 534 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source);
bcostm 0:d83f1c8ca282 535 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source);
bcostm 0:d83f1c8ca282 536 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source);
bcostm 0:d83f1c8ca282 537 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source);
bcostm 0:d83f1c8ca282 538
bcostm 0:d83f1c8ca282 539 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity);
bcostm 0:d83f1c8ca282 540 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type);
bcostm 0:d83f1c8ca282 541
bcostm 0:d83f1c8ca282 542
Jerome Coutant 2:106c7b82e064 543 /**
bcostm 0:d83f1c8ca282 544 * @brief MFXSTM32L152 IO functionalities functions
bcostm 0:d83f1c8ca282 545 */
bcostm 0:d83f1c8ca282 546 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin);
bcostm 0:d83f1c8ca282 547 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode);
bcostm 0:d83f1c8ca282 548 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState);
bcostm 0:d83f1c8ca282 549 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin);
bcostm 0:d83f1c8ca282 550 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 551 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 552 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin);
bcostm 0:d83f1c8ca282 553 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin);
bcostm 0:d83f1c8ca282 554
bcostm 0:d83f1c8ca282 555 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction);
bcostm 0:d83f1c8ca282 556 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 557 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 558 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type);
bcostm 0:d83f1c8ca282 559 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt);
bcostm 0:d83f1c8ca282 560 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
bcostm 0:d83f1c8ca282 561 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
bcostm 0:d83f1c8ca282 562
Jerome Coutant 2:106c7b82e064 563 /**
bcostm 0:d83f1c8ca282 564 * @brief MFXSTM32L152 Touch screen functionalities functions
bcostm 0:d83f1c8ca282 565 */
bcostm 0:d83f1c8ca282 566 void mfxstm32l152_TS_Start(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 567 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 568 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y);
bcostm 0:d83f1c8ca282 569 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 570 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 571 uint8_t mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 572 void mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 573
bcostm 0:d83f1c8ca282 574 /**
bcostm 0:d83f1c8ca282 575 * @brief MFXSTM32L152 IDD current measurement functionalities functions
bcostm 0:d83f1c8ca282 576 */
bcostm 0:d83f1c8ca282 577 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 578 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig);
bcostm 0:d83f1c8ca282 579 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit);
bcostm 0:d83f1c8ca282 580 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue);
bcostm 0:d83f1c8ca282 581 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 582 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 583 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 584 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 585 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 586
bcostm 0:d83f1c8ca282 587 /**
bcostm 0:d83f1c8ca282 588 * @brief MFXSTM32L152 Error management functions
bcostm 0:d83f1c8ca282 589 */
bcostm 0:d83f1c8ca282 590 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 591 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 592 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 593 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 594 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 595 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr);
bcostm 0:d83f1c8ca282 596
bcostm 0:d83f1c8ca282 597 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr);
bcostm 0:d83f1c8ca282 598 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value);
bcostm 0:d83f1c8ca282 599
bcostm 0:d83f1c8ca282 600
bcostm 0:d83f1c8ca282 601
Jerome Coutant 2:106c7b82e064 602 /**
bcostm 0:d83f1c8ca282 603 * @brief iobus prototypes (they should be defined in common/stm32_iobus.h)
bcostm 0:d83f1c8ca282 604 */
bcostm 0:d83f1c8ca282 605 void MFX_IO_Init(void);
bcostm 0:d83f1c8ca282 606 void MFX_IO_DeInit(void);
bcostm 0:d83f1c8ca282 607 void MFX_IO_ITConfig (void);
bcostm 0:d83f1c8ca282 608 void MFX_IO_EnableWakeupPin(void);
bcostm 0:d83f1c8ca282 609 void MFX_IO_Wakeup(void);
bcostm 0:d83f1c8ca282 610 void MFX_IO_Delay(uint32_t delay);
bcostm 0:d83f1c8ca282 611 void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value);
bcostm 0:d83f1c8ca282 612 uint8_t MFX_IO_Read(uint16_t addr, uint8_t reg);
bcostm 0:d83f1c8ca282 613 uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length);
bcostm 0:d83f1c8ca282 614
bcostm 0:d83f1c8ca282 615 /**
bcostm 0:d83f1c8ca282 616 * @}
Jerome Coutant 2:106c7b82e064 617 */
bcostm 0:d83f1c8ca282 618
bcostm 0:d83f1c8ca282 619 /* Touch screen driver structure */
bcostm 0:d83f1c8ca282 620 extern TS_DrvTypeDef mfxstm32l152_ts_drv;
bcostm 0:d83f1c8ca282 621
bcostm 0:d83f1c8ca282 622 /* IO driver structure */
bcostm 0:d83f1c8ca282 623 extern IO_DrvTypeDef mfxstm32l152_io_drv;
bcostm 0:d83f1c8ca282 624
bcostm 0:d83f1c8ca282 625 /* IDD driver structure */
bcostm 0:d83f1c8ca282 626 extern IDD_DrvTypeDef mfxstm32l152_idd_drv;
bcostm 0:d83f1c8ca282 627
bcostm 0:d83f1c8ca282 628
bcostm 0:d83f1c8ca282 629 #ifdef __cplusplus
bcostm 0:d83f1c8ca282 630 }
bcostm 0:d83f1c8ca282 631 #endif
bcostm 0:d83f1c8ca282 632 #endif /* __MFXSTM32L152_H */
bcostm 0:d83f1c8ca282 633
bcostm 0:d83f1c8ca282 634
bcostm 0:d83f1c8ca282 635 /**
bcostm 0:d83f1c8ca282 636 * @}
Jerome Coutant 2:106c7b82e064 637 */
bcostm 0:d83f1c8ca282 638
bcostm 0:d83f1c8ca282 639 /**
bcostm 0:d83f1c8ca282 640 * @}
bcostm 0:d83f1c8ca282 641 */
bcostm 0:d83f1c8ca282 642
bcostm 0:d83f1c8ca282 643 /**
bcostm 0:d83f1c8ca282 644 * @}
Jerome Coutant 2:106c7b82e064 645 */
bcostm 0:d83f1c8ca282 646
bcostm 0:d83f1c8ca282 647 /**
bcostm 0:d83f1c8ca282 648 * @}
Jerome Coutant 2:106c7b82e064 649 */
bcostm 0:d83f1c8ca282 650 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/