stm32f429i_discovery_sdram.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f429i_discovery_sdram.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the 
00006   *          stm32f429i_discovery_sdram.c driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00011   *
00012   * Redistribution and use in source and binary forms, with or without modification,
00013   * are permitted provided that the following conditions are met:
00014   *   1. Redistributions of source code must retain the above copyright notice,
00015   *      this list of conditions and the following disclaimer.
00016   *   2. Redistributions in binary form must reproduce the above copyright notice,
00017   *      this list of conditions and the following disclaimer in the documentation
00018   *      and/or other materials provided with the distribution.
00019   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00020   *      may be used to endorse or promote products derived from this software
00021   *      without specific prior written permission.
00022   *
00023   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00024   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00025   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00026   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00027   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00028   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00029   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00030   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00031   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00032   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00033   *
00034   ******************************************************************************
00035   */   
00036 
00037 /* Define to prevent recursive inclusion -------------------------------------*/
00038 #ifndef __STM32F429I_DISCOVERY_SDRAM_H
00039 #define __STM32F429I_DISCOVERY_SDRAM_H
00040 
00041 #ifdef __cplusplus
00042  extern "C" {
00043 #endif
00044 
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32f429i_discovery.h"
00047 
00048 /** @addtogroup BSP
00049   * @{
00050   */
00051   
00052 /** @addtogroup STM32F429I_DISCOVERY
00053   * @{
00054   */
00055  
00056 /** @addtogroup STM32F429I_DISCOVERY_SDRAM
00057   * @{
00058   */
00059   
00060 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Types STM32F429I DISCOVERY SDRAM Exported Types
00061   * @{
00062   */
00063 /**
00064   * @}
00065   */
00066 
00067 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Constants STM32F429I DISCOVERY SDRAM Exported Constants
00068   * @{
00069   */ 
00070 
00071 /**
00072   * @brief  SDRAM status structure definition
00073   */
00074 #define   SDRAM_OK         ((uint8_t)0x00)
00075 #define   SDRAM_ERROR      ((uint8_t)0x01)
00076   
00077 /**
00078   * @brief  FMC SDRAM Bank address
00079   */   
00080 #define SDRAM_DEVICE_ADDR         ((uint32_t)0xD0000000)
00081 #define SDRAM_DEVICE_SIZE         ((uint32_t)0x800000)  /* SDRAM device size in Bytes */
00082   
00083 /**
00084   * @brief  FMC SDRAM Memory Width
00085   */  
00086 /* #define SDRAM_MEMORY_WIDTH   FMC_SDRAM_MEM_BUS_WIDTH_8 */
00087 #define SDRAM_MEMORY_WIDTH      FMC_SDRAM_MEM_BUS_WIDTH_16
00088 
00089 /**
00090   * @brief  FMC SDRAM CAS Latency
00091   */  
00092 /* #define SDRAM_CAS_LATENCY    FMC_SDRAM_CAS_LATENCY_2 */
00093 #define SDRAM_CAS_LATENCY       FMC_SDRAM_CAS_LATENCY_3 
00094 
00095 /**
00096   * @brief  FMC SDRAM Memory clock period
00097   */  
00098 #define SDCLOCK_PERIOD          FMC_SDRAM_CLOCK_PERIOD_2    /* Default configuration used with LCD */
00099 /* #define SDCLOCK_PERIOD       FMC_SDRAM_CLOCK_PERIOD_3 */
00100 
00101 /**
00102   * @brief  FMC SDRAM Memory Read Burst feature
00103   */  
00104 #define SDRAM_READBURST         FMC_SDRAM_RBURST_DISABLE    /* Default configuration used with LCD */
00105 /* #define SDRAM_READBURST      FMC_SDRAM_RBURST_ENABLE */
00106 
00107 /**
00108   * @brief  FMC SDRAM Bank Remap
00109   */    
00110 /* #define SDRAM_BANK_REMAP */
00111 
00112 /* Set the refresh rate counter */
00113 /* (15.62 us x Freq) - 20 */
00114 #define REFRESH_COUNT           ((uint32_t)1386)   /* SDRAM refresh counter */
00115 #define SDRAM_TIMEOUT           ((uint32_t)0xFFFF)
00116 
00117 /* DMA definitions for SDRAM DMA transfer */
00118 #define __DMAx_CLK_ENABLE       __HAL_RCC_DMA2_CLK_ENABLE
00119 #define SDRAM_DMAx_CHANNEL      DMA_CHANNEL_0
00120 #define SDRAM_DMAx_STREAM       DMA2_Stream0
00121 #define SDRAM_DMAx_IRQn         DMA2_Stream0_IRQn
00122 #define SDRAM_DMAx_IRQHandler   DMA2_Stream0_IRQHandler
00123 
00124 /**
00125   * @brief  FMC SDRAM Mode definition register defines
00126   */
00127 #define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
00128 #define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
00129 #define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
00130 #define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
00131 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
00132 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
00133 #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
00134 #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
00135 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
00136 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
00137 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
00138 /**
00139   * @}
00140   */
00141   
00142 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Macro STM32F429I DISCOVERY SDRAM Exported Macro
00143   * @{
00144   */
00145 /**
00146   * @}
00147   */ 
00148 
00149 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Functions STM32F429I DISCOVERY SDRAM Exported Functions
00150   * @{
00151   */
00152 uint8_t           BSP_SDRAM_Init(void);
00153 void              BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
00154 uint8_t           BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
00155 uint8_t           BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
00156 uint8_t           BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
00157 uint8_t           BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
00158 uint8_t           BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
00159 void              BSP_SDRAM_DMA_IRQHandler(void);
00160 
00161 /* These function can be modified in case the current settings (e.g. DMA stream)
00162    need to be changed for specific application needs */
00163 void    BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
00164 void    BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
00165 
00166 /**
00167   * @}
00168   */
00169 
00170 /**
00171   * @}
00172   */
00173 
00174 /**
00175   * @}
00176   */   
00177 
00178 /**
00179   * @}
00180   */
00181 
00182 #ifdef __cplusplus
00183 }
00184 #endif
00185 
00186 #endif /* __STM32F429I_DISCOVERY_SDRAM_H */
00187 
00188 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/