l3gd20.h

00001 /**
00002   ******************************************************************************
00003   * @file    l3gd20.h
00004   * @author  MCD Application Team
00005   * @version V2.0.0
00006   * @date    26-June-2015
00007   * @brief   This file contains all the functions prototypes for the l3gd20.c driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037   
00038 
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __L3GD20_H
00041 #define __L3GD20_H
00042 
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046 
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "../Common/gyro.h"
00049 
00050 /** @addtogroup BSP
00051   * @{
00052   */ 
00053 
00054 /** @addtogroup Components
00055   * @{
00056   */ 
00057 
00058 /** @addtogroup L3GD20
00059   * @{
00060   */
00061   
00062 /** @defgroup L3GD20_Exported_Constants
00063   * @{
00064   */
00065 
00066 /******************************************************************************/
00067 /*************************** START REGISTER MAPPING  **************************/
00068 /******************************************************************************/
00069 #define L3GD20_WHO_AM_I_ADDR          0x0F  /* device identification register */
00070 #define L3GD20_CTRL_REG1_ADDR         0x20  /* Control register 1 */
00071 #define L3GD20_CTRL_REG2_ADDR         0x21  /* Control register 2 */
00072 #define L3GD20_CTRL_REG3_ADDR         0x22  /* Control register 3 */
00073 #define L3GD20_CTRL_REG4_ADDR         0x23  /* Control register 4 */
00074 #define L3GD20_CTRL_REG5_ADDR         0x24  /* Control register 5 */
00075 #define L3GD20_REFERENCE_REG_ADDR     0x25  /* Reference register */
00076 #define L3GD20_OUT_TEMP_ADDR          0x26  /* Out temp register */
00077 #define L3GD20_STATUS_REG_ADDR        0x27  /* Status register */
00078 #define L3GD20_OUT_X_L_ADDR           0x28  /* Output Register X */
00079 #define L3GD20_OUT_X_H_ADDR           0x29  /* Output Register X */
00080 #define L3GD20_OUT_Y_L_ADDR           0x2A  /* Output Register Y */
00081 #define L3GD20_OUT_Y_H_ADDR           0x2B  /* Output Register Y */
00082 #define L3GD20_OUT_Z_L_ADDR           0x2C  /* Output Register Z */
00083 #define L3GD20_OUT_Z_H_ADDR           0x2D  /* Output Register Z */ 
00084 #define L3GD20_FIFO_CTRL_REG_ADDR     0x2E  /* Fifo control Register */
00085 #define L3GD20_FIFO_SRC_REG_ADDR      0x2F  /* Fifo src Register */
00086 
00087 #define L3GD20_INT1_CFG_ADDR          0x30  /* Interrupt 1 configuration Register */
00088 #define L3GD20_INT1_SRC_ADDR          0x31  /* Interrupt 1 source Register */
00089 #define L3GD20_INT1_TSH_XH_ADDR       0x32  /* Interrupt 1 Threshold X register */
00090 #define L3GD20_INT1_TSH_XL_ADDR       0x33  /* Interrupt 1 Threshold X register */
00091 #define L3GD20_INT1_TSH_YH_ADDR       0x34  /* Interrupt 1 Threshold Y register */
00092 #define L3GD20_INT1_TSH_YL_ADDR       0x35  /* Interrupt 1 Threshold Y register */
00093 #define L3GD20_INT1_TSH_ZH_ADDR       0x36  /* Interrupt 1 Threshold Z register */
00094 #define L3GD20_INT1_TSH_ZL_ADDR       0x37  /* Interrupt 1 Threshold Z register */
00095 #define L3GD20_INT1_DURATION_ADDR     0x38  /* Interrupt 1 DURATION register */
00096 
00097 /******************************************************************************/
00098 /**************************** END REGISTER MAPPING  ***************************/
00099 /******************************************************************************/
00100 
00101 #define I_AM_L3GD20                 ((uint8_t)0xD4)
00102 #define I_AM_L3GD20_TR              ((uint8_t)0xD5)
00103 
00104 /** @defgroup Power_Mode_selection 
00105   * @{
00106   */
00107 #define L3GD20_MODE_POWERDOWN       ((uint8_t)0x00)
00108 #define L3GD20_MODE_ACTIVE          ((uint8_t)0x08)
00109 /**
00110   * @}
00111   */
00112 
00113 /** @defgroup OutPut_DataRate_Selection 
00114   * @{
00115   */
00116 #define L3GD20_OUTPUT_DATARATE_1    ((uint8_t)0x00)
00117 #define L3GD20_OUTPUT_DATARATE_2    ((uint8_t)0x40)
00118 #define L3GD20_OUTPUT_DATARATE_3    ((uint8_t)0x80)
00119 #define L3GD20_OUTPUT_DATARATE_4    ((uint8_t)0xC0)
00120 /**
00121   * @}
00122   */
00123 
00124 /** @defgroup Axes_Selection 
00125   * @{
00126   */
00127 #define L3GD20_X_ENABLE            ((uint8_t)0x02)
00128 #define L3GD20_Y_ENABLE            ((uint8_t)0x01)
00129 #define L3GD20_Z_ENABLE            ((uint8_t)0x04)
00130 #define L3GD20_AXES_ENABLE         ((uint8_t)0x07)
00131 #define L3GD20_AXES_DISABLE        ((uint8_t)0x00)
00132 /**
00133   * @}
00134   */
00135 
00136 /** @defgroup Bandwidth_Selection 
00137   * @{
00138   */
00139 #define L3GD20_BANDWIDTH_1         ((uint8_t)0x00)
00140 #define L3GD20_BANDWIDTH_2         ((uint8_t)0x10)
00141 #define L3GD20_BANDWIDTH_3         ((uint8_t)0x20)
00142 #define L3GD20_BANDWIDTH_4         ((uint8_t)0x30)
00143 /**
00144   * @}
00145   */
00146 
00147 /** @defgroup Full_Scale_Selection 
00148   * @{
00149   */
00150 #define L3GD20_FULLSCALE_250       ((uint8_t)0x00)
00151 #define L3GD20_FULLSCALE_500       ((uint8_t)0x10)
00152 #define L3GD20_FULLSCALE_2000      ((uint8_t)0x20) 
00153 #define L3GD20_FULLSCALE_SELECTION ((uint8_t)0x30)
00154 /**
00155   * @}
00156   */
00157 
00158 /** @defgroup Full_Scale_Sensitivity 
00159   * @{
00160   */
00161 #define L3GD20_SENSITIVITY_250DPS  ((float)8.75f)         /*!< gyroscope sensitivity with 250 dps full scale [DPS/LSB]  */
00162 #define L3GD20_SENSITIVITY_500DPS  ((float)17.50f)        /*!< gyroscope sensitivity with 500 dps full scale [DPS/LSB]  */
00163 #define L3GD20_SENSITIVITY_2000DPS ((float)70.00f)        /*!< gyroscope sensitivity with 2000 dps full scale [DPS/LSB] */
00164 /**
00165   * @}
00166   */
00167 
00168   
00169 /** @defgroup Block_Data_Update 
00170   * @{
00171   */  
00172 #define L3GD20_BlockDataUpdate_Continous   ((uint8_t)0x00)
00173 #define L3GD20_BlockDataUpdate_Single      ((uint8_t)0x80)
00174 /**
00175   * @}
00176   */
00177   
00178 /** @defgroup Endian_Data_selection
00179   * @{
00180   */  
00181 #define L3GD20_BLE_LSB                     ((uint8_t)0x00)
00182 #define L3GD20_BLE_MSB                     ((uint8_t)0x40)
00183 /**
00184   * @}
00185   */
00186   
00187 /** @defgroup High_Pass_Filter_status 
00188   * @{
00189   */   
00190 #define L3GD20_HIGHPASSFILTER_DISABLE      ((uint8_t)0x00)
00191 #define L3GD20_HIGHPASSFILTER_ENABLE         ((uint8_t)0x10)
00192 /**
00193   * @}
00194   */
00195 
00196 /** @defgroup INT1_INT2_selection 
00197   * @{
00198   */   
00199 #define L3GD20_INT1                        ((uint8_t)0x00)
00200 #define L3GD20_INT2                        ((uint8_t)0x01)
00201 /**
00202   * @}
00203   */
00204 
00205 /** @defgroup INT1_Interrupt_status 
00206   * @{
00207   */   
00208 #define L3GD20_INT1INTERRUPT_DISABLE       ((uint8_t)0x00)
00209 #define L3GD20_INT1INTERRUPT_ENABLE        ((uint8_t)0x80)
00210 /**
00211   * @}
00212   */
00213 
00214 /** @defgroup INT2_Interrupt_status 
00215   * @{
00216   */   
00217 #define L3GD20_INT2INTERRUPT_DISABLE       ((uint8_t)0x00)
00218 #define L3GD20_INT2INTERRUPT_ENABLE        ((uint8_t)0x08)
00219 /**
00220   * @}
00221   */
00222 
00223 /** @defgroup INT1_Interrupt_ActiveEdge 
00224   * @{
00225   */   
00226 #define L3GD20_INT1INTERRUPT_LOW_EDGE      ((uint8_t)0x20)
00227 #define L3GD20_INT1INTERRUPT_HIGH_EDGE     ((uint8_t)0x00)
00228 /**
00229   * @}
00230   */
00231   
00232 /** @defgroup Boot_Mode_selection 
00233   * @{
00234   */
00235 #define L3GD20_BOOT_NORMALMODE             ((uint8_t)0x00)
00236 #define L3GD20_BOOT_REBOOTMEMORY           ((uint8_t)0x80)
00237 /**
00238   * @}
00239   */  
00240  
00241 /** @defgroup High_Pass_Filter_Mode 
00242   * @{
00243   */   
00244 #define L3GD20_HPM_NORMAL_MODE_RES         ((uint8_t)0x00)
00245 #define L3GD20_HPM_REF_SIGNAL              ((uint8_t)0x10)
00246 #define L3GD20_HPM_NORMAL_MODE             ((uint8_t)0x20)
00247 #define L3GD20_HPM_AUTORESET_INT           ((uint8_t)0x30)
00248 /**
00249   * @}
00250   */
00251 
00252 /** @defgroup High_Pass_CUT OFF_Frequency 
00253   * @{
00254   */   
00255 #define L3GD20_HPFCF_0              0x00
00256 #define L3GD20_HPFCF_1              0x01
00257 #define L3GD20_HPFCF_2              0x02
00258 #define L3GD20_HPFCF_3              0x03
00259 #define L3GD20_HPFCF_4              0x04
00260 #define L3GD20_HPFCF_5              0x05
00261 #define L3GD20_HPFCF_6              0x06
00262 #define L3GD20_HPFCF_7              0x07
00263 #define L3GD20_HPFCF_8              0x08
00264 #define L3GD20_HPFCF_9              0x09
00265 /**
00266   * @}
00267   */
00268 
00269 /**
00270   * @}
00271   */
00272 /** @defgroup L3GD20_Exported_Functions
00273   * @{
00274   */
00275 /* Sensor Configuration Functions */ 
00276 void    L3GD20_Init(uint16_t InitStruct);
00277 void    L3GD20_DeInit(void);
00278 void    L3GD20_LowPower(uint16_t InitStruct);
00279 uint8_t L3GD20_ReadID(void);
00280 void    L3GD20_RebootCmd(void);
00281 
00282 /* Interrupt Configuration Functions */
00283 void    L3GD20_INT1InterruptConfig(uint16_t Int1Config);
00284 void    L3GD20_EnableIT(uint8_t IntSel);
00285 void    L3GD20_DisableIT(uint8_t IntSel);
00286 
00287 /* High Pass Filter Configuration Functions */
00288 void    L3GD20_FilterConfig(uint8_t FilterStruct);
00289 void    L3GD20_FilterCmd(uint8_t HighPassFilterState);
00290 void    L3GD20_ReadXYZAngRate(float *pfData);
00291 uint8_t L3GD20_GetDataStatus(void);
00292 
00293 /* Gyroscope IO functions */
00294 void    GYRO_IO_Init(void);
00295 void    GYRO_IO_DeInit(void);
00296 void    GYRO_IO_Write(uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
00297 void    GYRO_IO_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
00298 
00299 /* Gyroscope driver structure */
00300 extern GYRO_DrvTypeDef L3gd20Drv;
00301 
00302 /**
00303   * @}
00304   */
00305 
00306 /**
00307   * @}
00308   */
00309 
00310 /**
00311   * @}
00312   */ 
00313   
00314 /**
00315   * @}
00316   */ 
00317 
00318 #ifdef __cplusplus
00319   }
00320 #endif
00321   
00322 #endif /* __L3GD20_H */
00323 
00324 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/