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BSP_DISCO_F413ZH
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Drivers/BSP/Components/wm8994/wm8994.c@0:4af3ca173992, 2017-05-17 (annotated)
- Committer:
- arostm
- Date:
- Wed May 17 10:23:19 2017 +0200
- Revision:
- 0:4af3ca173992
creation of the DISCO_F413ZH BSP library
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| arostm | 0:4af3ca173992 | 1 | /** |
| arostm | 0:4af3ca173992 | 2 | ****************************************************************************** |
| arostm | 0:4af3ca173992 | 3 | * @file wm8994.c |
| arostm | 0:4af3ca173992 | 4 | * @author MCD Application Team |
| arostm | 0:4af3ca173992 | 5 | * @version V2.1.0 |
| arostm | 0:4af3ca173992 | 6 | * @date 22-February-2016 |
| arostm | 0:4af3ca173992 | 7 | * @brief This file provides the WM8994 Audio Codec driver. |
| arostm | 0:4af3ca173992 | 8 | ****************************************************************************** |
| arostm | 0:4af3ca173992 | 9 | * @attention |
| arostm | 0:4af3ca173992 | 10 | * |
| arostm | 0:4af3ca173992 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| arostm | 0:4af3ca173992 | 12 | * |
| arostm | 0:4af3ca173992 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| arostm | 0:4af3ca173992 | 14 | * are permitted provided that the following conditions are met: |
| arostm | 0:4af3ca173992 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| arostm | 0:4af3ca173992 | 16 | * this list of conditions and the following disclaimer. |
| arostm | 0:4af3ca173992 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| arostm | 0:4af3ca173992 | 18 | * this list of conditions and the following disclaimer in the documentation |
| arostm | 0:4af3ca173992 | 19 | * and/or other materials provided with the distribution. |
| arostm | 0:4af3ca173992 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| arostm | 0:4af3ca173992 | 21 | * may be used to endorse or promote products derived from this software |
| arostm | 0:4af3ca173992 | 22 | * without specific prior written permission. |
| arostm | 0:4af3ca173992 | 23 | * |
| arostm | 0:4af3ca173992 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| arostm | 0:4af3ca173992 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| arostm | 0:4af3ca173992 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| arostm | 0:4af3ca173992 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| arostm | 0:4af3ca173992 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| arostm | 0:4af3ca173992 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| arostm | 0:4af3ca173992 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| arostm | 0:4af3ca173992 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| arostm | 0:4af3ca173992 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| arostm | 0:4af3ca173992 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| arostm | 0:4af3ca173992 | 34 | * |
| arostm | 0:4af3ca173992 | 35 | ****************************************************************************** |
| arostm | 0:4af3ca173992 | 36 | */ |
| arostm | 0:4af3ca173992 | 37 | |
| arostm | 0:4af3ca173992 | 38 | /* Includes ------------------------------------------------------------------*/ |
| arostm | 0:4af3ca173992 | 39 | #include "wm8994.h" |
| arostm | 0:4af3ca173992 | 40 | |
| arostm | 0:4af3ca173992 | 41 | /** @addtogroup BSP |
| arostm | 0:4af3ca173992 | 42 | * @{ |
| arostm | 0:4af3ca173992 | 43 | */ |
| arostm | 0:4af3ca173992 | 44 | |
| arostm | 0:4af3ca173992 | 45 | /** @addtogroup Components |
| arostm | 0:4af3ca173992 | 46 | * @{ |
| arostm | 0:4af3ca173992 | 47 | */ |
| arostm | 0:4af3ca173992 | 48 | |
| arostm | 0:4af3ca173992 | 49 | /** @addtogroup wm8994 |
| arostm | 0:4af3ca173992 | 50 | * @brief This file provides a set of functions needed to drive the |
| arostm | 0:4af3ca173992 | 51 | * WM8994 audio codec. |
| arostm | 0:4af3ca173992 | 52 | * @{ |
| arostm | 0:4af3ca173992 | 53 | */ |
| arostm | 0:4af3ca173992 | 54 | |
| arostm | 0:4af3ca173992 | 55 | /** @defgroup WM8994_Private_Types |
| arostm | 0:4af3ca173992 | 56 | * @{ |
| arostm | 0:4af3ca173992 | 57 | */ |
| arostm | 0:4af3ca173992 | 58 | |
| arostm | 0:4af3ca173992 | 59 | /** |
| arostm | 0:4af3ca173992 | 60 | * @} |
| arostm | 0:4af3ca173992 | 61 | */ |
| arostm | 0:4af3ca173992 | 62 | |
| arostm | 0:4af3ca173992 | 63 | /** @defgroup WM8994_Private_Defines |
| arostm | 0:4af3ca173992 | 64 | * @{ |
| arostm | 0:4af3ca173992 | 65 | */ |
| arostm | 0:4af3ca173992 | 66 | /* Uncomment this line to enable verifying data sent to codec after each write |
| arostm | 0:4af3ca173992 | 67 | operation (for debug purpose) */ |
| arostm | 0:4af3ca173992 | 68 | #if !defined (VERIFY_WRITTENDATA) |
| arostm | 0:4af3ca173992 | 69 | /*#define VERIFY_WRITTENDATA*/ |
| arostm | 0:4af3ca173992 | 70 | #endif /* VERIFY_WRITTENDATA */ |
| arostm | 0:4af3ca173992 | 71 | /** |
| arostm | 0:4af3ca173992 | 72 | * @} |
| arostm | 0:4af3ca173992 | 73 | */ |
| arostm | 0:4af3ca173992 | 74 | |
| arostm | 0:4af3ca173992 | 75 | /** @defgroup WM8994_Private_Macros |
| arostm | 0:4af3ca173992 | 76 | * @{ |
| arostm | 0:4af3ca173992 | 77 | */ |
| arostm | 0:4af3ca173992 | 78 | |
| arostm | 0:4af3ca173992 | 79 | /** |
| arostm | 0:4af3ca173992 | 80 | * @} |
| arostm | 0:4af3ca173992 | 81 | */ |
| arostm | 0:4af3ca173992 | 82 | |
| arostm | 0:4af3ca173992 | 83 | /** @defgroup WM8994_Private_Variables |
| arostm | 0:4af3ca173992 | 84 | * @{ |
| arostm | 0:4af3ca173992 | 85 | */ |
| arostm | 0:4af3ca173992 | 86 | |
| arostm | 0:4af3ca173992 | 87 | /* Audio codec driver structure initialization */ |
| arostm | 0:4af3ca173992 | 88 | AUDIO_DrvTypeDef wm8994_drv = |
| arostm | 0:4af3ca173992 | 89 | { |
| arostm | 0:4af3ca173992 | 90 | wm8994_Init, |
| arostm | 0:4af3ca173992 | 91 | wm8994_DeInit, |
| arostm | 0:4af3ca173992 | 92 | wm8994_ReadID, |
| arostm | 0:4af3ca173992 | 93 | |
| arostm | 0:4af3ca173992 | 94 | wm8994_Play, |
| arostm | 0:4af3ca173992 | 95 | wm8994_Pause, |
| arostm | 0:4af3ca173992 | 96 | wm8994_Resume, |
| arostm | 0:4af3ca173992 | 97 | wm8994_Stop, |
| arostm | 0:4af3ca173992 | 98 | |
| arostm | 0:4af3ca173992 | 99 | wm8994_SetFrequency, |
| arostm | 0:4af3ca173992 | 100 | wm8994_SetVolume, |
| arostm | 0:4af3ca173992 | 101 | wm8994_SetMute, |
| arostm | 0:4af3ca173992 | 102 | wm8994_SetOutputMode, |
| arostm | 0:4af3ca173992 | 103 | |
| arostm | 0:4af3ca173992 | 104 | wm8994_Reset |
| arostm | 0:4af3ca173992 | 105 | }; |
| arostm | 0:4af3ca173992 | 106 | |
| arostm | 0:4af3ca173992 | 107 | static uint32_t outputEnabled = 0; |
| arostm | 0:4af3ca173992 | 108 | static uint32_t inputEnabled = 0; |
| arostm | 0:4af3ca173992 | 109 | /** |
| arostm | 0:4af3ca173992 | 110 | * @} |
| arostm | 0:4af3ca173992 | 111 | */ |
| arostm | 0:4af3ca173992 | 112 | |
| arostm | 0:4af3ca173992 | 113 | /** @defgroup WM8994_Function_Prototypes |
| arostm | 0:4af3ca173992 | 114 | * @{ |
| arostm | 0:4af3ca173992 | 115 | */ |
| arostm | 0:4af3ca173992 | 116 | static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value); |
| arostm | 0:4af3ca173992 | 117 | /** |
| arostm | 0:4af3ca173992 | 118 | * @} |
| arostm | 0:4af3ca173992 | 119 | */ |
| arostm | 0:4af3ca173992 | 120 | |
| arostm | 0:4af3ca173992 | 121 | /** @defgroup WM8994_Private_Functions |
| arostm | 0:4af3ca173992 | 122 | * @{ |
| arostm | 0:4af3ca173992 | 123 | */ |
| arostm | 0:4af3ca173992 | 124 | |
| arostm | 0:4af3ca173992 | 125 | /** |
| arostm | 0:4af3ca173992 | 126 | * @brief Initializes the audio codec and the control interface. |
| arostm | 0:4af3ca173992 | 127 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 128 | * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, |
| arostm | 0:4af3ca173992 | 129 | * OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1, |
| arostm | 0:4af3ca173992 | 130 | * INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_DIGITAL_MIC1_MIC2, |
| arostm | 0:4af3ca173992 | 131 | * INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2. |
| arostm | 0:4af3ca173992 | 132 | * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) |
| arostm | 0:4af3ca173992 | 133 | * @param AudioFreq: Audio Frequency |
| arostm | 0:4af3ca173992 | 134 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 135 | */ |
| arostm | 0:4af3ca173992 | 136 | uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq) |
| arostm | 0:4af3ca173992 | 137 | { |
| arostm | 0:4af3ca173992 | 138 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 139 | uint16_t output_device = OutputInputDevice & 0xFF; |
| arostm | 0:4af3ca173992 | 140 | uint16_t input_device = OutputInputDevice & 0xFF00; |
| arostm | 0:4af3ca173992 | 141 | uint16_t power_mgnt_reg_1 = 0; |
| arostm | 0:4af3ca173992 | 142 | |
| arostm | 0:4af3ca173992 | 143 | /* Initialize the Control interface of the Audio Codec */ |
| arostm | 0:4af3ca173992 | 144 | AUDIO_IO_Init(); |
| arostm | 0:4af3ca173992 | 145 | /* wm8994 Errata Work-Arounds */ |
| arostm | 0:4af3ca173992 | 146 | counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003); |
| arostm | 0:4af3ca173992 | 147 | counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000); |
| arostm | 0:4af3ca173992 | 148 | counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000); |
| arostm | 0:4af3ca173992 | 149 | |
| arostm | 0:4af3ca173992 | 150 | /* Enable VMID soft start (fast), Start-up Bias Current Enabled */ |
| arostm | 0:4af3ca173992 | 151 | counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C); |
| arostm | 0:4af3ca173992 | 152 | |
| arostm | 0:4af3ca173992 | 153 | /* Enable bias generator, Enable VMID */ |
| arostm | 0:4af3ca173992 | 154 | if (input_device > 0) |
| arostm | 0:4af3ca173992 | 155 | { |
| arostm | 0:4af3ca173992 | 156 | counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0013); |
| arostm | 0:4af3ca173992 | 157 | } |
| arostm | 0:4af3ca173992 | 158 | else |
| arostm | 0:4af3ca173992 | 159 | { |
| arostm | 0:4af3ca173992 | 160 | counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003); |
| arostm | 0:4af3ca173992 | 161 | } |
| arostm | 0:4af3ca173992 | 162 | |
| arostm | 0:4af3ca173992 | 163 | /* Add Delay */ |
| arostm | 0:4af3ca173992 | 164 | AUDIO_IO_Delay(50); |
| arostm | 0:4af3ca173992 | 165 | |
| arostm | 0:4af3ca173992 | 166 | /* Path Configurations for output */ |
| arostm | 0:4af3ca173992 | 167 | if (output_device > 0) |
| arostm | 0:4af3ca173992 | 168 | { |
| arostm | 0:4af3ca173992 | 169 | outputEnabled = 1; |
| arostm | 0:4af3ca173992 | 170 | switch (output_device) |
| arostm | 0:4af3ca173992 | 171 | { |
| arostm | 0:4af3ca173992 | 172 | case OUTPUT_DEVICE_SPEAKER: |
| arostm | 0:4af3ca173992 | 173 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 174 | Disable DAC2 (Left), Disable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 175 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C); |
| arostm | 0:4af3ca173992 | 176 | |
| arostm | 0:4af3ca173992 | 177 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 178 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000); |
| arostm | 0:4af3ca173992 | 179 | |
| arostm | 0:4af3ca173992 | 180 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 181 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000); |
| arostm | 0:4af3ca173992 | 182 | |
| arostm | 0:4af3ca173992 | 183 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 184 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| arostm | 0:4af3ca173992 | 185 | |
| arostm | 0:4af3ca173992 | 186 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 187 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| arostm | 0:4af3ca173992 | 188 | break; |
| arostm | 0:4af3ca173992 | 189 | |
| arostm | 0:4af3ca173992 | 190 | case OUTPUT_DEVICE_HEADPHONE: |
| arostm | 0:4af3ca173992 | 191 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 192 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 193 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| arostm | 0:4af3ca173992 | 194 | |
| arostm | 0:4af3ca173992 | 195 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 196 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| arostm | 0:4af3ca173992 | 197 | |
| arostm | 0:4af3ca173992 | 198 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 199 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| arostm | 0:4af3ca173992 | 200 | |
| arostm | 0:4af3ca173992 | 201 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 202 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| arostm | 0:4af3ca173992 | 203 | |
| arostm | 0:4af3ca173992 | 204 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 205 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| arostm | 0:4af3ca173992 | 206 | break; |
| arostm | 0:4af3ca173992 | 207 | |
| arostm | 0:4af3ca173992 | 208 | case OUTPUT_DEVICE_BOTH: |
| arostm | 0:4af3ca173992 | 209 | if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2) |
| arostm | 0:4af3ca173992 | 210 | { |
| arostm | 0:4af3ca173992 | 211 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 212 | also Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 213 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C); |
| arostm | 0:4af3ca173992 | 214 | |
| arostm | 0:4af3ca173992 | 215 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path |
| arostm | 0:4af3ca173992 | 216 | Enable the AIF1 Timeslot 1 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 217 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0003); |
| arostm | 0:4af3ca173992 | 218 | |
| arostm | 0:4af3ca173992 | 219 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path |
| arostm | 0:4af3ca173992 | 220 | Enable the AIF1 Timeslot 1 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 221 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0003); |
| arostm | 0:4af3ca173992 | 222 | |
| arostm | 0:4af3ca173992 | 223 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 2 (Left) mixer path |
| arostm | 0:4af3ca173992 | 224 | Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 225 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0003); |
| arostm | 0:4af3ca173992 | 226 | |
| arostm | 0:4af3ca173992 | 227 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 2 (Right) mixer path |
| arostm | 0:4af3ca173992 | 228 | Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 229 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0003); |
| arostm | 0:4af3ca173992 | 230 | } |
| arostm | 0:4af3ca173992 | 231 | else |
| arostm | 0:4af3ca173992 | 232 | { |
| arostm | 0:4af3ca173992 | 233 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 234 | also Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 235 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C); |
| arostm | 0:4af3ca173992 | 236 | |
| arostm | 0:4af3ca173992 | 237 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 238 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| arostm | 0:4af3ca173992 | 239 | |
| arostm | 0:4af3ca173992 | 240 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 241 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| arostm | 0:4af3ca173992 | 242 | |
| arostm | 0:4af3ca173992 | 243 | /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 244 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| arostm | 0:4af3ca173992 | 245 | |
| arostm | 0:4af3ca173992 | 246 | /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 247 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| arostm | 0:4af3ca173992 | 248 | } |
| arostm | 0:4af3ca173992 | 249 | break; |
| arostm | 0:4af3ca173992 | 250 | |
| arostm | 0:4af3ca173992 | 251 | case OUTPUT_DEVICE_AUTO : |
| arostm | 0:4af3ca173992 | 252 | default: |
| arostm | 0:4af3ca173992 | 253 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 254 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 255 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| arostm | 0:4af3ca173992 | 256 | |
| arostm | 0:4af3ca173992 | 257 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 258 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| arostm | 0:4af3ca173992 | 259 | |
| arostm | 0:4af3ca173992 | 260 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 261 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| arostm | 0:4af3ca173992 | 262 | |
| arostm | 0:4af3ca173992 | 263 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 264 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| arostm | 0:4af3ca173992 | 265 | |
| arostm | 0:4af3ca173992 | 266 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 267 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| arostm | 0:4af3ca173992 | 268 | break; |
| arostm | 0:4af3ca173992 | 269 | } |
| arostm | 0:4af3ca173992 | 270 | } |
| arostm | 0:4af3ca173992 | 271 | else |
| arostm | 0:4af3ca173992 | 272 | { |
| arostm | 0:4af3ca173992 | 273 | outputEnabled = 0; |
| arostm | 0:4af3ca173992 | 274 | } |
| arostm | 0:4af3ca173992 | 275 | |
| arostm | 0:4af3ca173992 | 276 | /* Path Configurations for input */ |
| arostm | 0:4af3ca173992 | 277 | if (input_device > 0) |
| arostm | 0:4af3ca173992 | 278 | { |
| arostm | 0:4af3ca173992 | 279 | inputEnabled = 1; |
| arostm | 0:4af3ca173992 | 280 | switch (input_device) |
| arostm | 0:4af3ca173992 | 281 | { |
| arostm | 0:4af3ca173992 | 282 | case INPUT_DEVICE_DIGITAL_MICROPHONE_2 : |
| arostm | 0:4af3ca173992 | 283 | /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right) |
| arostm | 0:4af3ca173992 | 284 | * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right) |
| arostm | 0:4af3ca173992 | 285 | * Enable Left ADC, Enable Right ADC */ |
| arostm | 0:4af3ca173992 | 286 | counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30); |
| arostm | 0:4af3ca173992 | 287 | |
| arostm | 0:4af3ca173992 | 288 | /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */ |
| arostm | 0:4af3ca173992 | 289 | counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB); |
| arostm | 0:4af3ca173992 | 290 | |
| arostm | 0:4af3ca173992 | 291 | /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */ |
| arostm | 0:4af3ca173992 | 292 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000); |
| arostm | 0:4af3ca173992 | 293 | |
| arostm | 0:4af3ca173992 | 294 | /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 295 | counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002); |
| arostm | 0:4af3ca173992 | 296 | |
| arostm | 0:4af3ca173992 | 297 | /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 298 | counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002); |
| arostm | 0:4af3ca173992 | 299 | |
| arostm | 0:4af3ca173992 | 300 | /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */ |
| arostm | 0:4af3ca173992 | 301 | counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E); |
| arostm | 0:4af3ca173992 | 302 | break; |
| arostm | 0:4af3ca173992 | 303 | |
| arostm | 0:4af3ca173992 | 304 | case INPUT_DEVICE_INPUT_LINE_1 : |
| arostm | 0:4af3ca173992 | 305 | /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */ |
| arostm | 0:4af3ca173992 | 306 | counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011); |
| arostm | 0:4af3ca173992 | 307 | |
| arostm | 0:4af3ca173992 | 308 | /* Disable mute on IN1L_TO_MIXINL and +30dB on IN1L PGA output */ |
| arostm | 0:4af3ca173992 | 309 | counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0035); |
| arostm | 0:4af3ca173992 | 310 | |
| arostm | 0:4af3ca173992 | 311 | /* Disable mute on IN1R_TO_MIXINL, Gain = +30dB */ |
| arostm | 0:4af3ca173992 | 312 | counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0035); |
| arostm | 0:4af3ca173992 | 313 | |
| arostm | 0:4af3ca173992 | 314 | /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) |
| arostm | 0:4af3ca173992 | 315 | * Enable Left ADC, Enable Right ADC */ |
| arostm | 0:4af3ca173992 | 316 | counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303); |
| arostm | 0:4af3ca173992 | 317 | |
| arostm | 0:4af3ca173992 | 318 | /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ |
| arostm | 0:4af3ca173992 | 319 | counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB); |
| arostm | 0:4af3ca173992 | 320 | |
| arostm | 0:4af3ca173992 | 321 | /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */ |
| arostm | 0:4af3ca173992 | 322 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350); |
| arostm | 0:4af3ca173992 | 323 | |
| arostm | 0:4af3ca173992 | 324 | /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 325 | counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002); |
| arostm | 0:4af3ca173992 | 326 | |
| arostm | 0:4af3ca173992 | 327 | /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 328 | counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002); |
| arostm | 0:4af3ca173992 | 329 | |
| arostm | 0:4af3ca173992 | 330 | /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ |
| arostm | 0:4af3ca173992 | 331 | counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D); |
| arostm | 0:4af3ca173992 | 332 | break; |
| arostm | 0:4af3ca173992 | 333 | |
| arostm | 0:4af3ca173992 | 334 | case INPUT_DEVICE_DIGITAL_MICROPHONE_1 : |
| arostm | 0:4af3ca173992 | 335 | /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) |
| arostm | 0:4af3ca173992 | 336 | * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right) |
| arostm | 0:4af3ca173992 | 337 | * Enable Left ADC, Enable Right ADC */ |
| arostm | 0:4af3ca173992 | 338 | counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x030C); |
| arostm | 0:4af3ca173992 | 339 | |
| arostm | 0:4af3ca173992 | 340 | /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ |
| arostm | 0:4af3ca173992 | 341 | counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB); |
| arostm | 0:4af3ca173992 | 342 | |
| arostm | 0:4af3ca173992 | 343 | /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */ |
| arostm | 0:4af3ca173992 | 344 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350); |
| arostm | 0:4af3ca173992 | 345 | |
| arostm | 0:4af3ca173992 | 346 | /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 347 | counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002); |
| arostm | 0:4af3ca173992 | 348 | |
| arostm | 0:4af3ca173992 | 349 | /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 350 | counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002); |
| arostm | 0:4af3ca173992 | 351 | |
| arostm | 0:4af3ca173992 | 352 | /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ |
| arostm | 0:4af3ca173992 | 353 | counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D); |
| arostm | 0:4af3ca173992 | 354 | break; |
| arostm | 0:4af3ca173992 | 355 | case INPUT_DEVICE_DIGITAL_MIC1_MIC2 : |
| arostm | 0:4af3ca173992 | 356 | /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right) |
| arostm | 0:4af3ca173992 | 357 | * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right) |
| arostm | 0:4af3ca173992 | 358 | * Enable Left ADC, Enable Right ADC */ |
| arostm | 0:4af3ca173992 | 359 | counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0F3C); |
| arostm | 0:4af3ca173992 | 360 | |
| arostm | 0:4af3ca173992 | 361 | /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */ |
| arostm | 0:4af3ca173992 | 362 | counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB); |
| arostm | 0:4af3ca173992 | 363 | |
| arostm | 0:4af3ca173992 | 364 | /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */ |
| arostm | 0:4af3ca173992 | 365 | counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB); |
| arostm | 0:4af3ca173992 | 366 | |
| arostm | 0:4af3ca173992 | 367 | /* Disable IN1L, IN1R, Enable IN2L, IN2R, Thermal sensor & shutdown */ |
| arostm | 0:4af3ca173992 | 368 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x63A0); |
| arostm | 0:4af3ca173992 | 369 | |
| arostm | 0:4af3ca173992 | 370 | /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 371 | counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002); |
| arostm | 0:4af3ca173992 | 372 | |
| arostm | 0:4af3ca173992 | 373 | /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 374 | counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002); |
| arostm | 0:4af3ca173992 | 375 | |
| arostm | 0:4af3ca173992 | 376 | /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 377 | counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002); |
| arostm | 0:4af3ca173992 | 378 | |
| arostm | 0:4af3ca173992 | 379 | /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 380 | counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002); |
| arostm | 0:4af3ca173992 | 381 | |
| arostm | 0:4af3ca173992 | 382 | /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */ |
| arostm | 0:4af3ca173992 | 383 | counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D); |
| arostm | 0:4af3ca173992 | 384 | break; |
| arostm | 0:4af3ca173992 | 385 | case INPUT_DEVICE_INPUT_LINE_2 : |
| arostm | 0:4af3ca173992 | 386 | default: |
| arostm | 0:4af3ca173992 | 387 | /* Actually, no other input devices supported */ |
| arostm | 0:4af3ca173992 | 388 | counter++; |
| arostm | 0:4af3ca173992 | 389 | break; |
| arostm | 0:4af3ca173992 | 390 | } |
| arostm | 0:4af3ca173992 | 391 | } |
| arostm | 0:4af3ca173992 | 392 | else |
| arostm | 0:4af3ca173992 | 393 | { |
| arostm | 0:4af3ca173992 | 394 | inputEnabled = 0; |
| arostm | 0:4af3ca173992 | 395 | } |
| arostm | 0:4af3ca173992 | 396 | |
| arostm | 0:4af3ca173992 | 397 | /* Clock Configurations */ |
| arostm | 0:4af3ca173992 | 398 | switch (AudioFreq) |
| arostm | 0:4af3ca173992 | 399 | { |
| arostm | 0:4af3ca173992 | 400 | case AUDIO_FREQUENCY_8K: |
| arostm | 0:4af3ca173992 | 401 | /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 402 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003); |
| arostm | 0:4af3ca173992 | 403 | break; |
| arostm | 0:4af3ca173992 | 404 | |
| arostm | 0:4af3ca173992 | 405 | case AUDIO_FREQUENCY_16K: |
| arostm | 0:4af3ca173992 | 406 | /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 407 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033); |
| arostm | 0:4af3ca173992 | 408 | break; |
| arostm | 0:4af3ca173992 | 409 | |
| arostm | 0:4af3ca173992 | 410 | case AUDIO_FREQUENCY_32K: |
| arostm | 0:4af3ca173992 | 411 | /* AIF1 Sample Rate = 32 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 412 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0063); |
| arostm | 0:4af3ca173992 | 413 | break; |
| arostm | 0:4af3ca173992 | 414 | |
| arostm | 0:4af3ca173992 | 415 | case AUDIO_FREQUENCY_48K: |
| arostm | 0:4af3ca173992 | 416 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 417 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| arostm | 0:4af3ca173992 | 418 | break; |
| arostm | 0:4af3ca173992 | 419 | |
| arostm | 0:4af3ca173992 | 420 | case AUDIO_FREQUENCY_96K: |
| arostm | 0:4af3ca173992 | 421 | /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 422 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3); |
| arostm | 0:4af3ca173992 | 423 | break; |
| arostm | 0:4af3ca173992 | 424 | |
| arostm | 0:4af3ca173992 | 425 | case AUDIO_FREQUENCY_11K: |
| arostm | 0:4af3ca173992 | 426 | /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 427 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013); |
| arostm | 0:4af3ca173992 | 428 | break; |
| arostm | 0:4af3ca173992 | 429 | |
| arostm | 0:4af3ca173992 | 430 | case AUDIO_FREQUENCY_22K: |
| arostm | 0:4af3ca173992 | 431 | /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 432 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043); |
| arostm | 0:4af3ca173992 | 433 | break; |
| arostm | 0:4af3ca173992 | 434 | |
| arostm | 0:4af3ca173992 | 435 | case AUDIO_FREQUENCY_44K: |
| arostm | 0:4af3ca173992 | 436 | /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 437 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073); |
| arostm | 0:4af3ca173992 | 438 | break; |
| arostm | 0:4af3ca173992 | 439 | |
| arostm | 0:4af3ca173992 | 440 | default: |
| arostm | 0:4af3ca173992 | 441 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 442 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| arostm | 0:4af3ca173992 | 443 | break; |
| arostm | 0:4af3ca173992 | 444 | } |
| arostm | 0:4af3ca173992 | 445 | |
| arostm | 0:4af3ca173992 | 446 | if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2) |
| arostm | 0:4af3ca173992 | 447 | { |
| arostm | 0:4af3ca173992 | 448 | /* AIF1 Word Length = 16-bits, AIF1 Format = DSP mode */ |
| arostm | 0:4af3ca173992 | 449 | counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4018); |
| arostm | 0:4af3ca173992 | 450 | } |
| arostm | 0:4af3ca173992 | 451 | else |
| arostm | 0:4af3ca173992 | 452 | { |
| arostm | 0:4af3ca173992 | 453 | /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */ |
| arostm | 0:4af3ca173992 | 454 | counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010); |
| arostm | 0:4af3ca173992 | 455 | } |
| arostm | 0:4af3ca173992 | 456 | |
| arostm | 0:4af3ca173992 | 457 | /* slave mode */ |
| arostm | 0:4af3ca173992 | 458 | counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000); |
| arostm | 0:4af3ca173992 | 459 | |
| arostm | 0:4af3ca173992 | 460 | /* Enable the DSP processing clock for AIF1, Enable the core clock */ |
| arostm | 0:4af3ca173992 | 461 | counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A); |
| arostm | 0:4af3ca173992 | 462 | |
| arostm | 0:4af3ca173992 | 463 | /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */ |
| arostm | 0:4af3ca173992 | 464 | counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001); |
| arostm | 0:4af3ca173992 | 465 | |
| arostm | 0:4af3ca173992 | 466 | if (output_device > 0) /* Audio output selected */ |
| arostm | 0:4af3ca173992 | 467 | { |
| arostm | 0:4af3ca173992 | 468 | /* Analog Output Configuration */ |
| arostm | 0:4af3ca173992 | 469 | |
| arostm | 0:4af3ca173992 | 470 | /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */ |
| arostm | 0:4af3ca173992 | 471 | counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300); |
| arostm | 0:4af3ca173992 | 472 | |
| arostm | 0:4af3ca173992 | 473 | /* Left Speaker Mixer Volume = 0dB */ |
| arostm | 0:4af3ca173992 | 474 | counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000); |
| arostm | 0:4af3ca173992 | 475 | |
| arostm | 0:4af3ca173992 | 476 | /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/ |
| arostm | 0:4af3ca173992 | 477 | counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000); |
| arostm | 0:4af3ca173992 | 478 | |
| arostm | 0:4af3ca173992 | 479 | /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path, |
| arostm | 0:4af3ca173992 | 480 | Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */ |
| arostm | 0:4af3ca173992 | 481 | counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300); |
| arostm | 0:4af3ca173992 | 482 | |
| arostm | 0:4af3ca173992 | 483 | /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */ |
| arostm | 0:4af3ca173992 | 484 | counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003); |
| arostm | 0:4af3ca173992 | 485 | |
| arostm | 0:4af3ca173992 | 486 | /* Headphone/Speaker Enable */ |
| arostm | 0:4af3ca173992 | 487 | |
| arostm | 0:4af3ca173992 | 488 | if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2) |
| arostm | 0:4af3ca173992 | 489 | { |
| arostm | 0:4af3ca173992 | 490 | /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslots 0 and 1 */ |
| arostm | 0:4af3ca173992 | 491 | counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0205); |
| arostm | 0:4af3ca173992 | 492 | } |
| arostm | 0:4af3ca173992 | 493 | else |
| arostm | 0:4af3ca173992 | 494 | { |
| arostm | 0:4af3ca173992 | 495 | /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */ |
| arostm | 0:4af3ca173992 | 496 | counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005); |
| arostm | 0:4af3ca173992 | 497 | } |
| arostm | 0:4af3ca173992 | 498 | |
| arostm | 0:4af3ca173992 | 499 | /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */ |
| arostm | 0:4af3ca173992 | 500 | /* idem for Speaker */ |
| arostm | 0:4af3ca173992 | 501 | power_mgnt_reg_1 |= 0x0303 | 0x3003; |
| arostm | 0:4af3ca173992 | 502 | counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1); |
| arostm | 0:4af3ca173992 | 503 | |
| arostm | 0:4af3ca173992 | 504 | /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */ |
| arostm | 0:4af3ca173992 | 505 | counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022); |
| arostm | 0:4af3ca173992 | 506 | |
| arostm | 0:4af3ca173992 | 507 | /* Enable Charge Pump */ |
| arostm | 0:4af3ca173992 | 508 | counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25); |
| arostm | 0:4af3ca173992 | 509 | |
| arostm | 0:4af3ca173992 | 510 | /* Add Delay */ |
| arostm | 0:4af3ca173992 | 511 | AUDIO_IO_Delay(15); |
| arostm | 0:4af3ca173992 | 512 | |
| arostm | 0:4af3ca173992 | 513 | /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */ |
| arostm | 0:4af3ca173992 | 514 | counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001); |
| arostm | 0:4af3ca173992 | 515 | |
| arostm | 0:4af3ca173992 | 516 | /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */ |
| arostm | 0:4af3ca173992 | 517 | counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001); |
| arostm | 0:4af3ca173992 | 518 | |
| arostm | 0:4af3ca173992 | 519 | /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */ |
| arostm | 0:4af3ca173992 | 520 | /* idem for SPKOUTL and SPKOUTR */ |
| arostm | 0:4af3ca173992 | 521 | counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300); |
| arostm | 0:4af3ca173992 | 522 | |
| arostm | 0:4af3ca173992 | 523 | /* Enable DC Servo and trigger start-up mode on left and right channels */ |
| arostm | 0:4af3ca173992 | 524 | counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033); |
| arostm | 0:4af3ca173992 | 525 | |
| arostm | 0:4af3ca173992 | 526 | /* Add Delay */ |
| arostm | 0:4af3ca173992 | 527 | AUDIO_IO_Delay(250); |
| arostm | 0:4af3ca173992 | 528 | |
| arostm | 0:4af3ca173992 | 529 | /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */ |
| arostm | 0:4af3ca173992 | 530 | counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE); |
| arostm | 0:4af3ca173992 | 531 | |
| arostm | 0:4af3ca173992 | 532 | /* Unmutes */ |
| arostm | 0:4af3ca173992 | 533 | |
| arostm | 0:4af3ca173992 | 534 | /* Unmute DAC 1 (Left) */ |
| arostm | 0:4af3ca173992 | 535 | counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0); |
| arostm | 0:4af3ca173992 | 536 | |
| arostm | 0:4af3ca173992 | 537 | /* Unmute DAC 1 (Right) */ |
| arostm | 0:4af3ca173992 | 538 | counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0); |
| arostm | 0:4af3ca173992 | 539 | |
| arostm | 0:4af3ca173992 | 540 | /* Unmute the AIF1 Timeslot 0 DAC path */ |
| arostm | 0:4af3ca173992 | 541 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000); |
| arostm | 0:4af3ca173992 | 542 | |
| arostm | 0:4af3ca173992 | 543 | /* Unmute DAC 2 (Left) */ |
| arostm | 0:4af3ca173992 | 544 | counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0); |
| arostm | 0:4af3ca173992 | 545 | |
| arostm | 0:4af3ca173992 | 546 | /* Unmute DAC 2 (Right) */ |
| arostm | 0:4af3ca173992 | 547 | counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0); |
| arostm | 0:4af3ca173992 | 548 | |
| arostm | 0:4af3ca173992 | 549 | /* Unmute the AIF1 Timeslot 1 DAC2 path */ |
| arostm | 0:4af3ca173992 | 550 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000); |
| arostm | 0:4af3ca173992 | 551 | |
| arostm | 0:4af3ca173992 | 552 | /* Volume Control */ |
| arostm | 0:4af3ca173992 | 553 | wm8994_SetVolume(DeviceAddr, Volume); |
| arostm | 0:4af3ca173992 | 554 | } |
| arostm | 0:4af3ca173992 | 555 | |
| arostm | 0:4af3ca173992 | 556 | if (input_device > 0) /* Audio input selected */ |
| arostm | 0:4af3ca173992 | 557 | { |
| arostm | 0:4af3ca173992 | 558 | if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2)) |
| arostm | 0:4af3ca173992 | 559 | { |
| arostm | 0:4af3ca173992 | 560 | /* Enable Microphone bias 1 generator, Enable VMID */ |
| arostm | 0:4af3ca173992 | 561 | power_mgnt_reg_1 |= 0x0013; |
| arostm | 0:4af3ca173992 | 562 | counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1); |
| arostm | 0:4af3ca173992 | 563 | |
| arostm | 0:4af3ca173992 | 564 | /* ADC oversample enable */ |
| arostm | 0:4af3ca173992 | 565 | counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002); |
| arostm | 0:4af3ca173992 | 566 | |
| arostm | 0:4af3ca173992 | 567 | /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ |
| arostm | 0:4af3ca173992 | 568 | counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800); |
| arostm | 0:4af3ca173992 | 569 | } |
| arostm | 0:4af3ca173992 | 570 | else if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2) |
| arostm | 0:4af3ca173992 | 571 | { |
| arostm | 0:4af3ca173992 | 572 | /* Enable Microphone bias 1 generator, Enable VMID */ |
| arostm | 0:4af3ca173992 | 573 | power_mgnt_reg_1 |= 0x0013; |
| arostm | 0:4af3ca173992 | 574 | counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1); |
| arostm | 0:4af3ca173992 | 575 | |
| arostm | 0:4af3ca173992 | 576 | /* ADC oversample enable */ |
| arostm | 0:4af3ca173992 | 577 | counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002); |
| arostm | 0:4af3ca173992 | 578 | |
| arostm | 0:4af3ca173992 | 579 | /* AIF ADC1 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ |
| arostm | 0:4af3ca173992 | 580 | counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800); |
| arostm | 0:4af3ca173992 | 581 | |
| arostm | 0:4af3ca173992 | 582 | /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */ |
| arostm | 0:4af3ca173992 | 583 | counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x1800); |
| arostm | 0:4af3ca173992 | 584 | } |
| arostm | 0:4af3ca173992 | 585 | else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2)) |
| arostm | 0:4af3ca173992 | 586 | { |
| arostm | 0:4af3ca173992 | 587 | |
| arostm | 0:4af3ca173992 | 588 | /* Disable mute on IN1L, IN1L Volume = +0dB */ |
| arostm | 0:4af3ca173992 | 589 | counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B); |
| arostm | 0:4af3ca173992 | 590 | |
| arostm | 0:4af3ca173992 | 591 | /* Disable mute on IN1R, IN1R Volume = +0dB */ |
| arostm | 0:4af3ca173992 | 592 | counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B); |
| arostm | 0:4af3ca173992 | 593 | |
| arostm | 0:4af3ca173992 | 594 | /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */ |
| arostm | 0:4af3ca173992 | 595 | counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800); |
| arostm | 0:4af3ca173992 | 596 | } |
| arostm | 0:4af3ca173992 | 597 | /* Volume Control */ |
| arostm | 0:4af3ca173992 | 598 | wm8994_SetVolume(DeviceAddr, Volume); |
| arostm | 0:4af3ca173992 | 599 | } |
| arostm | 0:4af3ca173992 | 600 | /* Return communication control value */ |
| arostm | 0:4af3ca173992 | 601 | return counter; |
| arostm | 0:4af3ca173992 | 602 | } |
| arostm | 0:4af3ca173992 | 603 | |
| arostm | 0:4af3ca173992 | 604 | /** |
| arostm | 0:4af3ca173992 | 605 | * @brief Deinitializes the audio codec. |
| arostm | 0:4af3ca173992 | 606 | * @param None |
| arostm | 0:4af3ca173992 | 607 | * @retval None |
| arostm | 0:4af3ca173992 | 608 | */ |
| arostm | 0:4af3ca173992 | 609 | void wm8994_DeInit(void) |
| arostm | 0:4af3ca173992 | 610 | { |
| arostm | 0:4af3ca173992 | 611 | /* Deinitialize Audio Codec interface */ |
| arostm | 0:4af3ca173992 | 612 | AUDIO_IO_DeInit(); |
| arostm | 0:4af3ca173992 | 613 | } |
| arostm | 0:4af3ca173992 | 614 | |
| arostm | 0:4af3ca173992 | 615 | /** |
| arostm | 0:4af3ca173992 | 616 | * @brief Get the WM8994 ID. |
| arostm | 0:4af3ca173992 | 617 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 618 | * @retval The WM8994 ID |
| arostm | 0:4af3ca173992 | 619 | */ |
| arostm | 0:4af3ca173992 | 620 | uint32_t wm8994_ReadID(uint16_t DeviceAddr) |
| arostm | 0:4af3ca173992 | 621 | { |
| arostm | 0:4af3ca173992 | 622 | /* Initialize the Control interface of the Audio Codec */ |
| arostm | 0:4af3ca173992 | 623 | AUDIO_IO_Init(); |
| arostm | 0:4af3ca173992 | 624 | |
| arostm | 0:4af3ca173992 | 625 | return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR)); |
| arostm | 0:4af3ca173992 | 626 | } |
| arostm | 0:4af3ca173992 | 627 | |
| arostm | 0:4af3ca173992 | 628 | /** |
| arostm | 0:4af3ca173992 | 629 | * @brief Start the audio Codec play feature. |
| arostm | 0:4af3ca173992 | 630 | * @note For this codec no Play options are required. |
| arostm | 0:4af3ca173992 | 631 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 632 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 633 | */ |
| arostm | 0:4af3ca173992 | 634 | uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size) |
| arostm | 0:4af3ca173992 | 635 | { |
| arostm | 0:4af3ca173992 | 636 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 637 | |
| arostm | 0:4af3ca173992 | 638 | /* Resumes the audio file playing */ |
| arostm | 0:4af3ca173992 | 639 | /* Unmute the output first */ |
| arostm | 0:4af3ca173992 | 640 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| arostm | 0:4af3ca173992 | 641 | |
| arostm | 0:4af3ca173992 | 642 | return counter; |
| arostm | 0:4af3ca173992 | 643 | } |
| arostm | 0:4af3ca173992 | 644 | |
| arostm | 0:4af3ca173992 | 645 | /** |
| arostm | 0:4af3ca173992 | 646 | * @brief Pauses playing on the audio codec. |
| arostm | 0:4af3ca173992 | 647 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 648 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 649 | */ |
| arostm | 0:4af3ca173992 | 650 | uint32_t wm8994_Pause(uint16_t DeviceAddr) |
| arostm | 0:4af3ca173992 | 651 | { |
| arostm | 0:4af3ca173992 | 652 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 653 | |
| arostm | 0:4af3ca173992 | 654 | /* Pause the audio file playing */ |
| arostm | 0:4af3ca173992 | 655 | /* Mute the output first */ |
| arostm | 0:4af3ca173992 | 656 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON); |
| arostm | 0:4af3ca173992 | 657 | |
| arostm | 0:4af3ca173992 | 658 | /* Put the Codec in Power save mode */ |
| arostm | 0:4af3ca173992 | 659 | counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01); |
| arostm | 0:4af3ca173992 | 660 | |
| arostm | 0:4af3ca173992 | 661 | return counter; |
| arostm | 0:4af3ca173992 | 662 | } |
| arostm | 0:4af3ca173992 | 663 | |
| arostm | 0:4af3ca173992 | 664 | /** |
| arostm | 0:4af3ca173992 | 665 | * @brief Resumes playing on the audio codec. |
| arostm | 0:4af3ca173992 | 666 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 667 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 668 | */ |
| arostm | 0:4af3ca173992 | 669 | uint32_t wm8994_Resume(uint16_t DeviceAddr) |
| arostm | 0:4af3ca173992 | 670 | { |
| arostm | 0:4af3ca173992 | 671 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 672 | |
| arostm | 0:4af3ca173992 | 673 | /* Resumes the audio file playing */ |
| arostm | 0:4af3ca173992 | 674 | /* Unmute the output first */ |
| arostm | 0:4af3ca173992 | 675 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| arostm | 0:4af3ca173992 | 676 | |
| arostm | 0:4af3ca173992 | 677 | return counter; |
| arostm | 0:4af3ca173992 | 678 | } |
| arostm | 0:4af3ca173992 | 679 | |
| arostm | 0:4af3ca173992 | 680 | /** |
| arostm | 0:4af3ca173992 | 681 | * @brief Stops audio Codec playing. It powers down the codec. |
| arostm | 0:4af3ca173992 | 682 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 683 | * @param CodecPdwnMode: selects the power down mode. |
| arostm | 0:4af3ca173992 | 684 | * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this |
| arostm | 0:4af3ca173992 | 685 | * mode the codec keeps the previous initialization |
| arostm | 0:4af3ca173992 | 686 | * (no need to re-Initialize the codec registers). |
| arostm | 0:4af3ca173992 | 687 | * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this |
| arostm | 0:4af3ca173992 | 688 | * mode, the codec is set to default configuration |
| arostm | 0:4af3ca173992 | 689 | * (user should re-Initialize the codec in order to |
| arostm | 0:4af3ca173992 | 690 | * play again the audio stream). |
| arostm | 0:4af3ca173992 | 691 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 692 | */ |
| arostm | 0:4af3ca173992 | 693 | uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode) |
| arostm | 0:4af3ca173992 | 694 | { |
| arostm | 0:4af3ca173992 | 695 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 696 | |
| arostm | 0:4af3ca173992 | 697 | if (outputEnabled != 0) |
| arostm | 0:4af3ca173992 | 698 | { |
| arostm | 0:4af3ca173992 | 699 | /* Mute the output first */ |
| arostm | 0:4af3ca173992 | 700 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON); |
| arostm | 0:4af3ca173992 | 701 | |
| arostm | 0:4af3ca173992 | 702 | if (CodecPdwnMode == CODEC_PDWN_SW) |
| arostm | 0:4af3ca173992 | 703 | { |
| arostm | 0:4af3ca173992 | 704 | /* Only output mute required*/ |
| arostm | 0:4af3ca173992 | 705 | } |
| arostm | 0:4af3ca173992 | 706 | else /* CODEC_PDWN_HW */ |
| arostm | 0:4af3ca173992 | 707 | { |
| arostm | 0:4af3ca173992 | 708 | /* Mute the AIF1 Timeslot 0 DAC1 path */ |
| arostm | 0:4af3ca173992 | 709 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200); |
| arostm | 0:4af3ca173992 | 710 | |
| arostm | 0:4af3ca173992 | 711 | /* Mute the AIF1 Timeslot 1 DAC2 path */ |
| arostm | 0:4af3ca173992 | 712 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200); |
| arostm | 0:4af3ca173992 | 713 | |
| arostm | 0:4af3ca173992 | 714 | /* Disable DAC1L_TO_HPOUT1L */ |
| arostm | 0:4af3ca173992 | 715 | counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000); |
| arostm | 0:4af3ca173992 | 716 | |
| arostm | 0:4af3ca173992 | 717 | /* Disable DAC1R_TO_HPOUT1R */ |
| arostm | 0:4af3ca173992 | 718 | counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000); |
| arostm | 0:4af3ca173992 | 719 | |
| arostm | 0:4af3ca173992 | 720 | /* Disable DAC1 and DAC2 */ |
| arostm | 0:4af3ca173992 | 721 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000); |
| arostm | 0:4af3ca173992 | 722 | |
| arostm | 0:4af3ca173992 | 723 | /* Reset Codec by writing in 0x0000 address register */ |
| arostm | 0:4af3ca173992 | 724 | counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000); |
| arostm | 0:4af3ca173992 | 725 | |
| arostm | 0:4af3ca173992 | 726 | outputEnabled = 0; |
| arostm | 0:4af3ca173992 | 727 | } |
| arostm | 0:4af3ca173992 | 728 | } |
| arostm | 0:4af3ca173992 | 729 | return counter; |
| arostm | 0:4af3ca173992 | 730 | } |
| arostm | 0:4af3ca173992 | 731 | |
| arostm | 0:4af3ca173992 | 732 | /** |
| arostm | 0:4af3ca173992 | 733 | * @brief Sets higher or lower the codec volume level. |
| arostm | 0:4af3ca173992 | 734 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 735 | * @param Volume: a byte value from 0 to 255 (refer to codec registers |
| arostm | 0:4af3ca173992 | 736 | * description for more details). |
| arostm | 0:4af3ca173992 | 737 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 738 | */ |
| arostm | 0:4af3ca173992 | 739 | uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume) |
| arostm | 0:4af3ca173992 | 740 | { |
| arostm | 0:4af3ca173992 | 741 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 742 | uint8_t convertedvol = VOLUME_CONVERT(Volume); |
| arostm | 0:4af3ca173992 | 743 | |
| arostm | 0:4af3ca173992 | 744 | /* Output volume */ |
| arostm | 0:4af3ca173992 | 745 | if (outputEnabled != 0) |
| arostm | 0:4af3ca173992 | 746 | { |
| arostm | 0:4af3ca173992 | 747 | if(convertedvol > 0x3E) |
| arostm | 0:4af3ca173992 | 748 | { |
| arostm | 0:4af3ca173992 | 749 | /* Unmute audio codec */ |
| arostm | 0:4af3ca173992 | 750 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| arostm | 0:4af3ca173992 | 751 | |
| arostm | 0:4af3ca173992 | 752 | /* Left Headphone Volume */ |
| arostm | 0:4af3ca173992 | 753 | counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140); |
| arostm | 0:4af3ca173992 | 754 | |
| arostm | 0:4af3ca173992 | 755 | /* Right Headphone Volume */ |
| arostm | 0:4af3ca173992 | 756 | counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140); |
| arostm | 0:4af3ca173992 | 757 | |
| arostm | 0:4af3ca173992 | 758 | /* Left Speaker Volume */ |
| arostm | 0:4af3ca173992 | 759 | counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140); |
| arostm | 0:4af3ca173992 | 760 | |
| arostm | 0:4af3ca173992 | 761 | /* Right Speaker Volume */ |
| arostm | 0:4af3ca173992 | 762 | counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140); |
| arostm | 0:4af3ca173992 | 763 | } |
| arostm | 0:4af3ca173992 | 764 | else if (Volume == 0) |
| arostm | 0:4af3ca173992 | 765 | { |
| arostm | 0:4af3ca173992 | 766 | /* Mute audio codec */ |
| arostm | 0:4af3ca173992 | 767 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON); |
| arostm | 0:4af3ca173992 | 768 | } |
| arostm | 0:4af3ca173992 | 769 | else |
| arostm | 0:4af3ca173992 | 770 | { |
| arostm | 0:4af3ca173992 | 771 | /* Unmute audio codec */ |
| arostm | 0:4af3ca173992 | 772 | counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF); |
| arostm | 0:4af3ca173992 | 773 | |
| arostm | 0:4af3ca173992 | 774 | /* Left Headphone Volume */ |
| arostm | 0:4af3ca173992 | 775 | counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140); |
| arostm | 0:4af3ca173992 | 776 | |
| arostm | 0:4af3ca173992 | 777 | /* Right Headphone Volume */ |
| arostm | 0:4af3ca173992 | 778 | counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140); |
| arostm | 0:4af3ca173992 | 779 | |
| arostm | 0:4af3ca173992 | 780 | /* Left Speaker Volume */ |
| arostm | 0:4af3ca173992 | 781 | counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140); |
| arostm | 0:4af3ca173992 | 782 | |
| arostm | 0:4af3ca173992 | 783 | /* Right Speaker Volume */ |
| arostm | 0:4af3ca173992 | 784 | counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140); |
| arostm | 0:4af3ca173992 | 785 | } |
| arostm | 0:4af3ca173992 | 786 | } |
| arostm | 0:4af3ca173992 | 787 | |
| arostm | 0:4af3ca173992 | 788 | /* Input volume */ |
| arostm | 0:4af3ca173992 | 789 | if (inputEnabled != 0) |
| arostm | 0:4af3ca173992 | 790 | { |
| arostm | 0:4af3ca173992 | 791 | convertedvol = VOLUME_IN_CONVERT(Volume); |
| arostm | 0:4af3ca173992 | 792 | |
| arostm | 0:4af3ca173992 | 793 | /* Left AIF1 ADC1 volume */ |
| arostm | 0:4af3ca173992 | 794 | counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100); |
| arostm | 0:4af3ca173992 | 795 | |
| arostm | 0:4af3ca173992 | 796 | /* Right AIF1 ADC1 volume */ |
| arostm | 0:4af3ca173992 | 797 | counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100); |
| arostm | 0:4af3ca173992 | 798 | |
| arostm | 0:4af3ca173992 | 799 | /* Left AIF1 ADC2 volume */ |
| arostm | 0:4af3ca173992 | 800 | counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100); |
| arostm | 0:4af3ca173992 | 801 | |
| arostm | 0:4af3ca173992 | 802 | /* Right AIF1 ADC2 volume */ |
| arostm | 0:4af3ca173992 | 803 | counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100); |
| arostm | 0:4af3ca173992 | 804 | } |
| arostm | 0:4af3ca173992 | 805 | return counter; |
| arostm | 0:4af3ca173992 | 806 | } |
| arostm | 0:4af3ca173992 | 807 | |
| arostm | 0:4af3ca173992 | 808 | /** |
| arostm | 0:4af3ca173992 | 809 | * @brief Enables or disables the mute feature on the audio codec. |
| arostm | 0:4af3ca173992 | 810 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 811 | * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the |
| arostm | 0:4af3ca173992 | 812 | * mute mode. |
| arostm | 0:4af3ca173992 | 813 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 814 | */ |
| arostm | 0:4af3ca173992 | 815 | uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd) |
| arostm | 0:4af3ca173992 | 816 | { |
| arostm | 0:4af3ca173992 | 817 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 818 | |
| arostm | 0:4af3ca173992 | 819 | if (outputEnabled != 0) |
| arostm | 0:4af3ca173992 | 820 | { |
| arostm | 0:4af3ca173992 | 821 | /* Set the Mute mode */ |
| arostm | 0:4af3ca173992 | 822 | if(Cmd == AUDIO_MUTE_ON) |
| arostm | 0:4af3ca173992 | 823 | { |
| arostm | 0:4af3ca173992 | 824 | /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */ |
| arostm | 0:4af3ca173992 | 825 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200); |
| arostm | 0:4af3ca173992 | 826 | |
| arostm | 0:4af3ca173992 | 827 | /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */ |
| arostm | 0:4af3ca173992 | 828 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200); |
| arostm | 0:4af3ca173992 | 829 | } |
| arostm | 0:4af3ca173992 | 830 | else /* AUDIO_MUTE_OFF Disable the Mute */ |
| arostm | 0:4af3ca173992 | 831 | { |
| arostm | 0:4af3ca173992 | 832 | /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */ |
| arostm | 0:4af3ca173992 | 833 | counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000); |
| arostm | 0:4af3ca173992 | 834 | |
| arostm | 0:4af3ca173992 | 835 | /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */ |
| arostm | 0:4af3ca173992 | 836 | counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000); |
| arostm | 0:4af3ca173992 | 837 | } |
| arostm | 0:4af3ca173992 | 838 | } |
| arostm | 0:4af3ca173992 | 839 | return counter; |
| arostm | 0:4af3ca173992 | 840 | } |
| arostm | 0:4af3ca173992 | 841 | |
| arostm | 0:4af3ca173992 | 842 | /** |
| arostm | 0:4af3ca173992 | 843 | * @brief Switch dynamically (while audio file is played) the output target |
| arostm | 0:4af3ca173992 | 844 | * (speaker or headphone). |
| arostm | 0:4af3ca173992 | 845 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 846 | * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER, |
| arostm | 0:4af3ca173992 | 847 | * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO |
| arostm | 0:4af3ca173992 | 848 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 849 | */ |
| arostm | 0:4af3ca173992 | 850 | uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output) |
| arostm | 0:4af3ca173992 | 851 | { |
| arostm | 0:4af3ca173992 | 852 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 853 | |
| arostm | 0:4af3ca173992 | 854 | switch (Output) |
| arostm | 0:4af3ca173992 | 855 | { |
| arostm | 0:4af3ca173992 | 856 | case OUTPUT_DEVICE_SPEAKER: |
| arostm | 0:4af3ca173992 | 857 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 858 | Disable DAC2 (Left), Disable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 859 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C); |
| arostm | 0:4af3ca173992 | 860 | |
| arostm | 0:4af3ca173992 | 861 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 862 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000); |
| arostm | 0:4af3ca173992 | 863 | |
| arostm | 0:4af3ca173992 | 864 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 865 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000); |
| arostm | 0:4af3ca173992 | 866 | |
| arostm | 0:4af3ca173992 | 867 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 868 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| arostm | 0:4af3ca173992 | 869 | |
| arostm | 0:4af3ca173992 | 870 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 871 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| arostm | 0:4af3ca173992 | 872 | break; |
| arostm | 0:4af3ca173992 | 873 | |
| arostm | 0:4af3ca173992 | 874 | case OUTPUT_DEVICE_HEADPHONE: |
| arostm | 0:4af3ca173992 | 875 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 876 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 877 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| arostm | 0:4af3ca173992 | 878 | |
| arostm | 0:4af3ca173992 | 879 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 880 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| arostm | 0:4af3ca173992 | 881 | |
| arostm | 0:4af3ca173992 | 882 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 883 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| arostm | 0:4af3ca173992 | 884 | |
| arostm | 0:4af3ca173992 | 885 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 886 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| arostm | 0:4af3ca173992 | 887 | |
| arostm | 0:4af3ca173992 | 888 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 889 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| arostm | 0:4af3ca173992 | 890 | break; |
| arostm | 0:4af3ca173992 | 891 | |
| arostm | 0:4af3ca173992 | 892 | case OUTPUT_DEVICE_BOTH: |
| arostm | 0:4af3ca173992 | 893 | /* Enable DAC1 (Left), Enable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 894 | also Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 895 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C); |
| arostm | 0:4af3ca173992 | 896 | |
| arostm | 0:4af3ca173992 | 897 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 898 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| arostm | 0:4af3ca173992 | 899 | |
| arostm | 0:4af3ca173992 | 900 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 901 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| arostm | 0:4af3ca173992 | 902 | |
| arostm | 0:4af3ca173992 | 903 | /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 904 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002); |
| arostm | 0:4af3ca173992 | 905 | |
| arostm | 0:4af3ca173992 | 906 | /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 907 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002); |
| arostm | 0:4af3ca173992 | 908 | break; |
| arostm | 0:4af3ca173992 | 909 | |
| arostm | 0:4af3ca173992 | 910 | default: |
| arostm | 0:4af3ca173992 | 911 | /* Disable DAC1 (Left), Disable DAC1 (Right), |
| arostm | 0:4af3ca173992 | 912 | Enable DAC2 (Left), Enable DAC2 (Right)*/ |
| arostm | 0:4af3ca173992 | 913 | counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303); |
| arostm | 0:4af3ca173992 | 914 | |
| arostm | 0:4af3ca173992 | 915 | /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 916 | counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001); |
| arostm | 0:4af3ca173992 | 917 | |
| arostm | 0:4af3ca173992 | 918 | /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 919 | counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001); |
| arostm | 0:4af3ca173992 | 920 | |
| arostm | 0:4af3ca173992 | 921 | /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */ |
| arostm | 0:4af3ca173992 | 922 | counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000); |
| arostm | 0:4af3ca173992 | 923 | |
| arostm | 0:4af3ca173992 | 924 | /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */ |
| arostm | 0:4af3ca173992 | 925 | counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000); |
| arostm | 0:4af3ca173992 | 926 | break; |
| arostm | 0:4af3ca173992 | 927 | } |
| arostm | 0:4af3ca173992 | 928 | return counter; |
| arostm | 0:4af3ca173992 | 929 | } |
| arostm | 0:4af3ca173992 | 930 | |
| arostm | 0:4af3ca173992 | 931 | /** |
| arostm | 0:4af3ca173992 | 932 | * @brief Sets new frequency. |
| arostm | 0:4af3ca173992 | 933 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 934 | * @param AudioFreq: Audio frequency used to play the audio stream. |
| arostm | 0:4af3ca173992 | 935 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 936 | */ |
| arostm | 0:4af3ca173992 | 937 | uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq) |
| arostm | 0:4af3ca173992 | 938 | { |
| arostm | 0:4af3ca173992 | 939 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 940 | |
| arostm | 0:4af3ca173992 | 941 | /* Clock Configurations */ |
| arostm | 0:4af3ca173992 | 942 | switch (AudioFreq) |
| arostm | 0:4af3ca173992 | 943 | { |
| arostm | 0:4af3ca173992 | 944 | case AUDIO_FREQUENCY_8K: |
| arostm | 0:4af3ca173992 | 945 | /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 946 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003); |
| arostm | 0:4af3ca173992 | 947 | break; |
| arostm | 0:4af3ca173992 | 948 | |
| arostm | 0:4af3ca173992 | 949 | case AUDIO_FREQUENCY_16K: |
| arostm | 0:4af3ca173992 | 950 | /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 951 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033); |
| arostm | 0:4af3ca173992 | 952 | break; |
| arostm | 0:4af3ca173992 | 953 | |
| arostm | 0:4af3ca173992 | 954 | case AUDIO_FREQUENCY_48K: |
| arostm | 0:4af3ca173992 | 955 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 956 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| arostm | 0:4af3ca173992 | 957 | break; |
| arostm | 0:4af3ca173992 | 958 | |
| arostm | 0:4af3ca173992 | 959 | case AUDIO_FREQUENCY_96K: |
| arostm | 0:4af3ca173992 | 960 | /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 961 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3); |
| arostm | 0:4af3ca173992 | 962 | break; |
| arostm | 0:4af3ca173992 | 963 | |
| arostm | 0:4af3ca173992 | 964 | case AUDIO_FREQUENCY_11K: |
| arostm | 0:4af3ca173992 | 965 | /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 966 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013); |
| arostm | 0:4af3ca173992 | 967 | break; |
| arostm | 0:4af3ca173992 | 968 | |
| arostm | 0:4af3ca173992 | 969 | case AUDIO_FREQUENCY_22K: |
| arostm | 0:4af3ca173992 | 970 | /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 971 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043); |
| arostm | 0:4af3ca173992 | 972 | break; |
| arostm | 0:4af3ca173992 | 973 | |
| arostm | 0:4af3ca173992 | 974 | case AUDIO_FREQUENCY_44K: |
| arostm | 0:4af3ca173992 | 975 | /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 976 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073); |
| arostm | 0:4af3ca173992 | 977 | break; |
| arostm | 0:4af3ca173992 | 978 | |
| arostm | 0:4af3ca173992 | 979 | default: |
| arostm | 0:4af3ca173992 | 980 | /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ |
| arostm | 0:4af3ca173992 | 981 | counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083); |
| arostm | 0:4af3ca173992 | 982 | break; |
| arostm | 0:4af3ca173992 | 983 | } |
| arostm | 0:4af3ca173992 | 984 | return counter; |
| arostm | 0:4af3ca173992 | 985 | } |
| arostm | 0:4af3ca173992 | 986 | |
| arostm | 0:4af3ca173992 | 987 | /** |
| arostm | 0:4af3ca173992 | 988 | * @brief Resets wm8994 registers. |
| arostm | 0:4af3ca173992 | 989 | * @param DeviceAddr: Device address on communication Bus. |
| arostm | 0:4af3ca173992 | 990 | * @retval 0 if correct communication, else wrong communication |
| arostm | 0:4af3ca173992 | 991 | */ |
| arostm | 0:4af3ca173992 | 992 | uint32_t wm8994_Reset(uint16_t DeviceAddr) |
| arostm | 0:4af3ca173992 | 993 | { |
| arostm | 0:4af3ca173992 | 994 | uint32_t counter = 0; |
| arostm | 0:4af3ca173992 | 995 | |
| arostm | 0:4af3ca173992 | 996 | /* Reset Codec by writing in 0x0000 address register */ |
| arostm | 0:4af3ca173992 | 997 | counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000); |
| arostm | 0:4af3ca173992 | 998 | outputEnabled = 0; |
| arostm | 0:4af3ca173992 | 999 | inputEnabled=0; |
| arostm | 0:4af3ca173992 | 1000 | |
| arostm | 0:4af3ca173992 | 1001 | return counter; |
| arostm | 0:4af3ca173992 | 1002 | } |
| arostm | 0:4af3ca173992 | 1003 | |
| arostm | 0:4af3ca173992 | 1004 | /** |
| arostm | 0:4af3ca173992 | 1005 | * @brief Writes/Read a single data. |
| arostm | 0:4af3ca173992 | 1006 | * @param Addr: I2C address |
| arostm | 0:4af3ca173992 | 1007 | * @param Reg: Reg address |
| arostm | 0:4af3ca173992 | 1008 | * @param Value: Data to be written |
| arostm | 0:4af3ca173992 | 1009 | * @retval None |
| arostm | 0:4af3ca173992 | 1010 | */ |
| arostm | 0:4af3ca173992 | 1011 | static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value) |
| arostm | 0:4af3ca173992 | 1012 | { |
| arostm | 0:4af3ca173992 | 1013 | uint32_t result = 0; |
| arostm | 0:4af3ca173992 | 1014 | |
| arostm | 0:4af3ca173992 | 1015 | AUDIO_IO_Write(Addr, Reg, Value); |
| arostm | 0:4af3ca173992 | 1016 | |
| arostm | 0:4af3ca173992 | 1017 | #ifdef VERIFY_WRITTENDATA |
| arostm | 0:4af3ca173992 | 1018 | /* Verify that the data has been correctly written */ |
| arostm | 0:4af3ca173992 | 1019 | result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1; |
| arostm | 0:4af3ca173992 | 1020 | #endif /* VERIFY_WRITTENDATA */ |
| arostm | 0:4af3ca173992 | 1021 | |
| arostm | 0:4af3ca173992 | 1022 | return result; |
| arostm | 0:4af3ca173992 | 1023 | } |
| arostm | 0:4af3ca173992 | 1024 | |
| arostm | 0:4af3ca173992 | 1025 | /** |
| arostm | 0:4af3ca173992 | 1026 | * @} |
| arostm | 0:4af3ca173992 | 1027 | */ |
| arostm | 0:4af3ca173992 | 1028 | |
| arostm | 0:4af3ca173992 | 1029 | /** |
| arostm | 0:4af3ca173992 | 1030 | * @} |
| arostm | 0:4af3ca173992 | 1031 | */ |
| arostm | 0:4af3ca173992 | 1032 | |
| arostm | 0:4af3ca173992 | 1033 | /** |
| arostm | 0:4af3ca173992 | 1034 | * @} |
| arostm | 0:4af3ca173992 | 1035 | */ |
| arostm | 0:4af3ca173992 | 1036 | |
| arostm | 0:4af3ca173992 | 1037 | /** |
| arostm | 0:4af3ca173992 | 1038 | * @} |
| arostm | 0:4af3ca173992 | 1039 | */ |
| arostm | 0:4af3ca173992 | 1040 | |
| arostm | 0:4af3ca173992 | 1041 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |