S5info_H14 / Mbed 2 deprecated APP3

Problematique

Dependencies:   mbed mbed-rtos

main.cpp@1:261bb31628e8, 2014-02-10 (annotated)

Committer:
RufflesAllD
Date:
Mon Feb 10 15:47:25 2014 +0000
Revision:
1:261bb31628e8
Parent:
0:dc7095ab4963
Child:
2:db7c8378b324
hey ho, let's go!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
joGenie 0:dc7095ab4963 1 #include "mbed.h"
RufflesAllD 1:261bb31628e8 2 #include "rtos.h"
RufflesAllD 1:261bb31628e8 3 #include <bitset>
joGenie 0:dc7095ab4963 4
joGenie 0:dc7095ab4963 5 Serial pc(USBTX, USBRX);
joGenie 0:dc7095ab4963 6
joGenie 0:dc7095ab4963 7 //const bool preambule[8] = {false, true, false, true, false, true, false, true};
joGenie 0:dc7095ab4963 8 //const bool start_end[8] = {false, true, true, true, true, true, true, false};
joGenie 0:dc7095ab4963 9
joGenie 0:dc7095ab4963 10 bool Trame[16] = {false, true, false, true, true, true, true, false, false, false, true, false, false, true, true, true};
joGenie 0:dc7095ab4963 11
joGenie 0:dc7095ab4963 12 void readTrame()
joGenie 0:dc7095ab4963 13 {
joGenie 0:dc7095ab4963 14 pc.printf("Duree impulsion : %d microsecondes.\n\r", LPC_TIM2->CR1/(SystemCoreClock/1000000));
joGenie 0:dc7095ab4963 15
joGenie 0:dc7095ab4963 16 LPC_TIM2->IR = 0xFF;
joGenie 0:dc7095ab4963 17 }
joGenie 0:dc7095ab4963 18
joGenie 0:dc7095ab4963 19 void sendTrame(bool *trame)
joGenie 0:dc7095ab4963 20 {
RufflesAllD 1:261bb31628e8 21 for (int a = 0; a < 5; a++)
joGenie 0:dc7095ab4963 22 {
joGenie 0:dc7095ab4963 23 if (trame[a])
joGenie 0:dc7095ab4963 24 {
joGenie 0:dc7095ab4963 25 LPC_PWM1->MR1 = 1;
joGenie 0:dc7095ab4963 26 LPC_PWM1->MR2 = SystemCoreClock/2;
joGenie 0:dc7095ab4963 27 }
joGenie 0:dc7095ab4963 28 else
joGenie 0:dc7095ab4963 29 {
joGenie 0:dc7095ab4963 30 LPC_PWM1->MR1 = SystemCoreClock/2;
joGenie 0:dc7095ab4963 31 LPC_PWM1->MR2 = 1;
joGenie 0:dc7095ab4963 32 }
joGenie 0:dc7095ab4963 33
joGenie 0:dc7095ab4963 34 pc.printf("trame: %d\n\r", trame[a]);
joGenie 0:dc7095ab4963 35
joGenie 0:dc7095ab4963 36 while(LPC_PWM1->IR != 0x01);
joGenie 0:dc7095ab4963 37
joGenie 0:dc7095ab4963 38 LPC_PWM1->IR = 0xFF;
joGenie 0:dc7095ab4963 39 }
RufflesAllD 1:261bb31628e8 40
RufflesAllD 1:261bb31628e8 41 LPC_PWM1->TCR = 0x0;
RufflesAllD 1:261bb31628e8 42 }
RufflesAllD 1:261bb31628e8 43
RufflesAllD 1:261bb31628e8 44 void send(void const *args) {
RufflesAllD 1:261bb31628e8 45 sendTrame(Trame);
joGenie 0:dc7095ab4963 46 }
joGenie 0:dc7095ab4963 47
joGenie 0:dc7095ab4963 48 void initialize()
joGenie 0:dc7095ab4963 49 {
joGenie 0:dc7095ab4963 50 // Set system control
joGenie 0:dc7095ab4963 51 LPC_SC->PCONP |= (1 << 22) | (1 << 6); // Enable Timer2 et PWM
joGenie 0:dc7095ab4963 52 LPC_SC->PCLKSEL0 |= (1 << 12); // PClk PWM = CCLK
joGenie 0:dc7095ab4963 53 LPC_SC->PCLKSEL1 |= (1 << 12); // PClk Timer2 = CCLK
joGenie 0:dc7095ab4963 54
joGenie 0:dc7095ab4963 55 // Set pin connection
joGenie 0:dc7095ab4963 56 LPC_PINCON->PINSEL0 |= (3 << 10); // Pin 29 Capture
joGenie 0:dc7095ab4963 57 LPC_PINCON->PINSEL4 |= (1 << 2); // Pin 25 PWM
joGenie 0:dc7095ab4963 58
joGenie 0:dc7095ab4963 59 //Initialize Timer2 for capture
RufflesAllD 1:261bb31628e8 60 NVIC_SetVector(TIMER2_IRQn, (uint32_t)&readTrame);
RufflesAllD 1:261bb31628e8 61 NVIC_EnableIRQ(TIMER2_IRQn);
joGenie 0:dc7095ab4963 62
joGenie 0:dc7095ab4963 63 LPC_TIM2->TC = 0; // Initialize Time Counter
joGenie 0:dc7095ab4963 64 LPC_TIM2->PC = 0; // Initialize Prescale Counter
joGenie 0:dc7095ab4963 65 LPC_TIM2->PR = 0; // Initialize Prescale Register
joGenie 0:dc7095ab4963 66 LPC_TIM2->TCR |= (1 << 1); // Reset Timer Control Register
joGenie 0:dc7095ab4963 67 LPC_TIM2->IR = 0xFF; // Reset Interrupt Register
RufflesAllD 1:261bb31628e8 68 LPC_TIM2->CCR |= (1 << 5) | (1 << 4) | (1 << 3); // Initialize Capture Control Register
RufflesAllD 1:261bb31628e8 69 LPC_TIM2->CTCR |= (1 << 0); // TC is incremented on rising edge
joGenie 0:dc7095ab4963 70
joGenie 0:dc7095ab4963 71 LPC_TIM2->TCR = 0x01; // Start Timer Control Register
joGenie 0:dc7095ab4963 72
joGenie 0:dc7095ab4963 73 //Initialize PWM
joGenie 0:dc7095ab4963 74 LPC_PWM1->MCR |= (1 << 1) | (1 << 0); // Initialize Match Control Register Interrupt/Reset
joGenie 0:dc7095ab4963 75 LPC_PWM1->PCR |= (1 << 10) | (1 << 2); // Initialize PWM Control Register Output/Double-edge
joGenie 0:dc7095ab4963 76
joGenie 0:dc7095ab4963 77 LPC_PWM1->MR0 = SystemCoreClock; // Period
joGenie 0:dc7095ab4963 78 LPC_PWM1->LER |= (1 << 2) | (1 << 1); // Initialize Latch Enable Register
joGenie 0:dc7095ab4963 79 LPC_PWM1->TCR |= (1 << 0); // Enable counter
joGenie 0:dc7095ab4963 80
RufflesAllD 1:261bb31628e8 81 LPC_PWM1->IR = 0xFF; // Reset Interrupt Registe
joGenie 0:dc7095ab4963 82 }
joGenie 0:dc7095ab4963 83
joGenie 0:dc7095ab4963 84 int main()
joGenie 0:dc7095ab4963 85 {
joGenie 0:dc7095ab4963 86 initialize();
joGenie 0:dc7095ab4963 87
RufflesAllD 1:261bb31628e8 88 Thread thread1(send);
RufflesAllD 1:261bb31628e8 89 //thread1.set_priority(osPriorityHigh);
joGenie 0:dc7095ab4963 90
RufflesAllD 1:261bb31628e8 91 while(true) {
RufflesAllD 1:261bb31628e8 92 while (LPC_TIM2->IR != 0x0);
RufflesAllD 1:261bb31628e8 93 pc.printf("borne 1\n\r");
RufflesAllD 1:261bb31628e8 94
RufflesAllD 1:261bb31628e8 95 LPC_TIM2->IR = 0xFF;
RufflesAllD 1:261bb31628e8 96 pc.printf("borne 2\n\r");
RufflesAllD 1:261bb31628e8 97 NVIC_EnableIRQ(TIMER2_IRQn);
RufflesAllD 1:261bb31628e8 98 pc.printf("borne 3\n\r");
RufflesAllD 1:261bb31628e8 99 NVIC_DisableIRQ(TIMER2_IRQn);
RufflesAllD 1:261bb31628e8 100 pc.printf("borne 4\n\r");
RufflesAllD 1:261bb31628e8 101 //NVIC_DisableIRQ(TIMER2_IRQn);
RufflesAllD 1:261bb31628e8 102
RufflesAllD 1:261bb31628e8 103 pc.printf("borne 5\n\r");
RufflesAllD 1:261bb31628e8 104 }
joGenie 0:dc7095ab4963 105 }