RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.
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SSIF
The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.
Hello World!
Import program
00001 #include "mbed.h" 00002 #include "R_BSP_Ssif.h" 00003 #include "sine_data_tbl.h" 00004 00005 //I2S send only, The upper limit of write buffer is 8. 00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0); 00007 00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) { 00009 if (result < 0) { 00010 printf("ssif write callback error %d\n", result); 00011 } 00012 } 00013 00014 int main() { 00015 rbsp_data_conf_t ssif_write_end_conf = {&callback_ssif_write_end, NULL}; 00016 ssif_channel_cfg_t ssif_cfg; 00017 int32_t result; 00018 00019 //I2S Master, 44.1kHz, 16bit, 2ch 00020 ssif_cfg.enabled = true; 00021 ssif_cfg.int_level = 0x78; 00022 ssif_cfg.slave_mode = false; 00023 ssif_cfg.sample_freq = 44100u; 00024 ssif_cfg.clk_select = SSIF_CFG_CKS_AUDIO_X1; 00025 ssif_cfg.multi_ch = SSIF_CFG_MULTI_CH_1; 00026 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_16; 00027 ssif_cfg.system_word = SSIF_CFG_SYSTEM_WORD_32; 00028 ssif_cfg.bclk_pol = SSIF_CFG_FALLING; 00029 ssif_cfg.ws_pol = SSIF_CFG_WS_LOW; 00030 ssif_cfg.padding_pol = SSIF_CFG_PADDING_LOW; 00031 ssif_cfg.serial_alignment = SSIF_CFG_DATA_FIRST; 00032 ssif_cfg.parallel_alignment = SSIF_CFG_LEFT; 00033 ssif_cfg.ws_delay = SSIF_CFG_DELAY; 00034 ssif_cfg.noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL; 00035 ssif_cfg.tdm_mode = SSIF_CFG_DISABLE_TDM; 00036 ssif_cfg.romdec_direct.mode = SSIF_CFG_DISABLE_ROMDEC_DIRECT; 00037 ssif_cfg.romdec_direct.p_cbfunc = NULL; 00038 result = ssif.ConfigChannel(&ssif_cfg); 00039 if (result < 0) { 00040 printf("ssif config error %d\n", result); 00041 } 00042 00043 while (1) { 00044 //The upper limit of write buffer is 8. 00045 result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 00046 sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf); 00047 if (result < 0) { 00048 printf("ssif write api error %d\n", result); 00049 } 00050 } 00051 }
API
Import library
Public Member Functions |
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R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16) | |
Constructor.
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virtual | ~R_BSP_Ssif () |
Destructor.
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int32_t | GetSsifChNo (void) |
Get a value of SSIF channel number.
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bool | ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg) |
Save configuration to the SSIF driver.
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bool | GetStatus (uint32_t *const p_status) |
Get a value of SSISR register.
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int32_t | write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Write count bytes to the file associated.
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int32_t | read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Read count bytes to the file associated.
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Protected Member Functions |
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void | write_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Write init.
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void | read_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Read init.
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Interface
See the Pinout page for more details
SCUX
The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.
Hello World!
Import program
00001 #include "mbed.h" 00002 #include "R_BSP_Scux.h" 00003 #include "USBHostMSD.h" 00004 00005 R_BSP_Scux scux(SCUX_CH_0); 00006 00007 #define WRITE_SAMPLE_NUM (128) 00008 #define READ_SAMPLE_NUM (2048) 00009 00010 const short sin_data[WRITE_SAMPLE_NUM] = { 00011 0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528 00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133 00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2 00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61 00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C 00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1 00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56 00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C 00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8 00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD 00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E 00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F 00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584 00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F 00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA 00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374 00027 }; 00028 00029 #if defined(__ICCARM__) 00030 #pragma data_alignment=4 00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram"; 00032 #pragma data_alignment=4 00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram"; 00034 #else 00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4))); 00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4))); 00037 #endif 00038 00039 void scux_setup(void); 00040 void write_task(void const*); 00041 void file_output_to_usb(void); 00042 00043 int main(void) { 00044 // set up SRC parameters. 00045 scux_setup(); 00046 00047 printf("Sampling rate conversion Start.\n"); 00048 // start accepting transmit/receive requests. 00049 scux.TransStart(); 00050 00051 // create a new thread to write to SCUX. 00052 Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4); 00053 00054 // receive request to the SCUX driver. 00055 scux.read(read_buff, sizeof(read_buff)); 00056 printf("Sampling rate conversion End.\n"); 00057 00058 // output binary file to USB port 0. 00059 file_output_to_usb(); 00060 } 00061 00062 void scux_setup(void) { 00063 scux_src_usr_cfg_t src_cfg; 00064 00065 src_cfg.src_enable = true; 00066 src_cfg.word_len = SCUX_DATA_LEN_16; 00067 src_cfg.mode_sync = true; 00068 src_cfg.input_rate = SAMPLING_RATE_48000HZ; 00069 src_cfg.output_rate = SAMPLING_RATE_96000HZ; 00070 src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0; 00071 src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1; 00072 00073 scux.SetSrcCfg(&src_cfg); 00074 } 00075 00076 void scux_flush_callback(int scux_ch) { 00077 // do nothing 00078 } 00079 00080 void write_task(void const*) { 00081 memcpy(write_buff, sin_data, sizeof(write_buff)); 00082 // send request to the SCUX driver. 00083 scux.write(write_buff, sizeof(write_buff)); 00084 00085 // stop the acceptance of transmit/receive requests. 00086 scux.FlushStop(&scux_flush_callback); 00087 } 00088 00089 void file_output_to_usb(void) { 00090 FILE * fp = NULL; 00091 int i; 00092 00093 USBHostMSD msd("usb"); 00094 00095 // try to connect a MSD device 00096 for(i = 0; i < 10; i++) { 00097 if (msd.connect()) { 00098 break; 00099 } 00100 wait(0.5); 00101 } 00102 00103 if (msd.connected()) { 00104 fp = fopen("/usb/scux_input.dat", "rb"); 00105 if (fp == NULL) { 00106 fp = fopen("/usb/scux_input.dat", "wb"); 00107 if (fp != NULL) { 00108 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp); 00109 fclose(fp); 00110 printf("Output binary file(Input data) to USB.\n"); 00111 } else { 00112 printf("Failed to output binary file(Input data).\n"); 00113 } 00114 } else { 00115 printf("Binary file(Input data) exists.\n"); 00116 fclose(fp); 00117 } 00118 00119 fp = fopen("/usb/scux_output.dat", "rb"); 00120 if (fp == NULL) { 00121 fp = fopen("/usb/scux_output.dat", "wb"); 00122 if (fp != NULL) { 00123 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp); 00124 fclose(fp); 00125 printf("Output binary file(Output data) to USB.\n"); 00126 } else { 00127 printf("Failed to output binary file(Output data).\n"); 00128 } 00129 } else { 00130 printf("Binary file(Output data) exists.\n"); 00131 fclose(fp); 00132 } 00133 } else { 00134 printf("Failed to connect to the USB device.\n"); 00135 } 00136 }
API
Import library
Public Member Functions |
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R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16) | |
Constructor: Initializes and opens the channel designated by the SCUX driver.
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virtual | ~R_BSP_Scux (void) |
Destructor: Closes the channel designated by the SCUX driver and exits.
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bool | TransStart (void) |
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
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bool | FlushStop (void(*const callback)(int32_t)) |
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
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bool | ClearStop (void) |
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
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bool | SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param) |
Sets up SRC parameters.
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bool | GetWriteStat (uint32_t *const p_write_stat) |
Obtains the state information of the write request.
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bool | GetReadStat (uint32_t *const p_read_stat) |
Obtains the state information of the read request.
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int32_t | write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Write count bytes to the file associated.
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int32_t | read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Read count bytes to the file associated.
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Protected Member Functions |
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void | write_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Write init.
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void | read_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Read init.
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Write request state transition diagram
Read request state transition diagram
Diff: RenesasBSP/drv_src/ssif/ssif.c
- Revision:
- 0:702bf7b2b7d8
- Child:
- 5:1390bfcb667c
diff -r 000000000000 -r 702bf7b2b7d8 RenesasBSP/drv_src/ssif/ssif.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/RenesasBSP/drv_src/ssif/ssif.c Mon Jun 01 08:33:21 2015 +0000 @@ -0,0 +1,1429 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +/******************************************************************************* +* File Name : ssif.c +* $Rev: 891 $ +* $Date:: 2014-06-27 10:40:52 +0900#$ +* Description : SSIF driver functions +******************************************************************************/ + +/******************************************************************************* +Includes <System Includes>, "Project Includes" +*******************************************************************************/ +#include "ssif.h" +#include "iodefine.h" +#include "ssif_int.h" +#include "Renesas_RZ_A1.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +/* ->MISRA 8.8, MISRA 8.10, IPA M2.2.2 : These declare statements are dependent on CMSIS-RTOS */ +osSemaphoreDef(ssif_ch0_access); +osSemaphoreDef(ssif_ch1_access); +osSemaphoreDef(ssif_ch2_access); +osSemaphoreDef(ssif_ch3_access); +osSemaphoreDef(ssif_ch4_access); +osSemaphoreDef(ssif_ch5_access); +/* <-MISRA 8.8, MISRA 8.10, IPA M2.2.2 */ + +ssif_info_drv_t g_ssif_info_drv; + +volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS] = SSIF_ADDRESS_LIST; + +/******************************************************************************* +Private global variables and functions +*******************************************************************************/ +static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch); +static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch); +static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch, + const ssif_channel_cfg_t* const p_ch_cfg); +static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch); +static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg); +static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch); +static void SSIF_Reset(const uint32_t ssif_ch); + +static const uint32_t gb_cpg_stbcr_bit[SSIF_NUM_CHANS] = +{ + CPG_STBCR11_BIT_MSTP115, /* SSIF0 */ + CPG_STBCR11_BIT_MSTP114, /* SSIF1 */ + CPG_STBCR11_BIT_MSTP113, /* SSIF2 */ + CPG_STBCR11_BIT_MSTP112, /* SSIF3 */ + CPG_STBCR11_BIT_MSTP111, /* SSIF4 */ + CPG_STBCR11_BIT_MSTP110 /* SSIF5 */ +}; + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +* Function Name: SSIF_Initialise +* @brief Initialize the SSIF driver's internal data +* +* Description:<br> +* +* @param[in] p_cfg_data :pointer of several parameters array per channels +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +#if(1) /* mbed */ +int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data) +{ + int_t ercd = ESUCCESS; + ssif_info_ch_t* p_info_ch; + + if (NULL == p_cfg_data) + { + ercd = EFAULT; + } + else if (false == p_cfg_data->enabled) + { + ercd = EFAULT; + } + else + { + p_info_ch = &g_ssif_info_drv.info_ch[channel]; + p_info_ch->channel = channel; + p_info_ch->enabled = p_cfg_data->enabled; + + /* copy config data to channel info */ + ercd = SSIF_UpdateChannelConfig(p_info_ch, p_cfg_data); + + if (ESUCCESS == ercd) + { + ercd = SSIF_InitChannel(p_info_ch); + } + + if (ESUCCESS == ercd) + { + SSIF_InterruptInit(channel, p_cfg_data->int_level); + } + } + + return ercd; +} + +#else +int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data) +{ + uint32_t ssif_ch; + int_t ercd = ESUCCESS; + ssif_info_ch_t* p_info_ch; + + if (NULL == p_cfg_data) + { + ercd = EFAULT; + } + else + { + for (ssif_ch = 0; (ssif_ch < SSIF_NUM_CHANS) && (ESUCCESS == ercd); ssif_ch++) + { + p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch]; + p_info_ch->channel = ssif_ch; + p_info_ch->enabled = p_cfg_data[ssif_ch].enabled; + + if (false != p_info_ch->enabled) + { + /* copy config data to channel info */ + ercd = SSIF_UpdateChannelConfig(p_info_ch, &p_cfg_data[ssif_ch]); + + if (ESUCCESS == ercd) + { + ercd = SSIF_InitChannel(p_info_ch); + } + } + } + + if (ESUCCESS == ercd) + { + for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++) + { + p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch]; + + if (false != p_info_ch->enabled) + { + SSIF_InterruptInit(ssif_ch, p_cfg_data[ssif_ch].int_level); + } + } + } + } + + return ercd; +} +#endif + +/****************************************************************************** +* Function Name: SSIF_UnInitialise +* @brief UnInitialize the SSIF driver's internal data +* +* Description:<br> +* +* @param none +* @retval ESUCCESS :Success. +******************************************************************************/ +#if(1) /* mbed */ +int_t SSIF_UnInitialiseOne(const int_t channel) +{ + const int_t ercd = ESUCCESS; + ssif_info_ch_t* p_info_ch; + + p_info_ch = &g_ssif_info_drv.info_ch[channel]; + + if (false != p_info_ch->enabled) + { + SSIF_UnInitChannel(p_info_ch); + } + + return ercd; +} +#else +int_t SSIF_UnInitialise(void) +{ + uint32_t ssif_ch; + const int_t ercd = ESUCCESS; + ssif_info_ch_t* p_info_ch; + + for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++) + { + p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch]; + + if (false != p_info_ch->enabled) + { + SSIF_UnInitChannel(p_info_ch); + } + } + + return ercd; +} +#endif + +/****************************************************************************** +* Function Name: SSIF_EnableChannel +* @brief Enable the SSIF channel +* +* Description:<br> +* +* @param[in,out] p_info_ch :channel object +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch) +{ + int_t ercd = ESUCCESS; + int_t was_masked; + uint32_t ssif_ch; + + if (NULL == p_info_ch) + { + ercd = EFAULT; + } + else + { + ssif_ch = p_info_ch->channel; + + if (ssif_ch >= SSIF_NUM_CHANS) + { + ercd = EFAULT; + } + else + { + /* check channel open flag(duplex) */ + if ((O_RDWR == p_info_ch->openflag) + && (false == p_info_ch->is_full_duplex)) + { + ercd = EINVAL; + } + + /* check channel open flag(romdec direct input) */ + if (ESUCCESS == ercd) + { + if ((O_RDONLY != p_info_ch->openflag) + && (SSIF_CFG_ENABLE_ROMDEC_DIRECT + == p_info_ch->romdec_direct.mode)) + { + ercd = EINVAL; + } + } + + /* enable the SSIF clock */ + if (ESUCCESS == ercd) + { + was_masked = __disable_irq(); + + /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */ + CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_stbcr_bit[ssif_ch]); + /* <-IPA R2.4.2 */ + + if (0 == was_masked) + { + __enable_irq(); + } + } + + /* configure channel hardware */ + if (ESUCCESS == ercd) + { + /* software reset */ + SSIF_Reset(ssif_ch); + + /* Set control parameters */ + ercd = SSIF_SetCtrlParams(p_info_ch); + } + + /* allocate and setup/start DMA transfer */ + if (ESUCCESS == ercd) + { + ercd = SSIF_InitDMA(p_info_ch); + } + } + } + + return ercd; +} + +/****************************************************************************** +* Function Name: SSIF_DisableChannel +* @brief Disable the SSIF channel +* +* Description:<br> +* +* @param[in,out] p_info_ch :channel object +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch) +{ + uint32_t dummy_read; + int_t was_masked; + int_t ret = ESUCCESS; + uint32_t ssif_ch; + + if (NULL == p_info_ch) + { + ret = EFAULT; + } + else + { + ssif_ch = p_info_ch->channel; + + if (ssif_ch >= SSIF_NUM_CHANS) + { + ret = EFAULT; + } + else + { + SSIF_DisableErrorInterrupt(ssif_ch); + + /* TEN and REN are disable */ + g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN); + + /* Reset FIFO */ + g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST); + dummy_read = g_ssireg[ssif_ch]->SSIFCR; + UNUSED_ARG(dummy_read); + g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST); + + /* free DMA resources */ + SSIF_UnInitDMA(p_info_ch); + + /* clear status reg */ + g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */ + + /* disable ssif clock */ + was_masked = __disable_irq(); + + /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */ + CPGSTBCR11 |= (uint8_t)gb_cpg_stbcr_bit[ssif_ch]; + /* <-IPA R2.4.2 */ + + if (0 == was_masked) + { + __enable_irq(); + } + + /* cancel event to ongoing request */ + if (NULL != p_info_ch->p_aio_tx_curr) + { + p_info_ch->p_aio_tx_curr->aio_return = ECANCELED; + ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr); + p_info_ch->p_aio_tx_curr = NULL; + } + if (NULL != p_info_ch->p_aio_tx_next) + { + p_info_ch->p_aio_tx_next->aio_return = ECANCELED; + ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next); + p_info_ch->p_aio_tx_next = NULL; + } + if (NULL != p_info_ch->p_aio_rx_curr) + { + p_info_ch->p_aio_rx_curr->aio_return = ECANCELED; + ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr); + p_info_ch->p_aio_rx_curr = NULL; + } + if (NULL != p_info_ch->p_aio_rx_next) + { + p_info_ch->p_aio_rx_next->aio_return = ECANCELED; + ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next); + p_info_ch->p_aio_rx_next = NULL; + } + } + } + + return ret; +} + +/****************************************************************************** +* Function Name: SSIF_ErrorRecovery +* @brief Restart the SSIF channel +* +* Description:<br> +* When normal mode<br> +* Stop and restart DMA transfer.<br> +* When ROMDEC direct input mode<br> +* Stop DMA transfer, and execute callback function.<br> +* Note: This function execute in interrupt context. +* @param[in,out] p_info_ch :channel object +* @retval none +******************************************************************************/ +void SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch) +{ + uint32_t dummy_read; + int_t ercd = ESUCCESS; + uint32_t ssif_ch; + + if (NULL == p_info_ch) + { + ercd = EFAULT; + } + else + { + ssif_ch = p_info_ch->channel; + + if (ssif_ch >= SSIF_NUM_CHANS) + { + ercd = EFAULT; + } + else + { + /* disable DMA end interrupt */ + g_ssireg[ssif_ch]->SSIFCR &= ~((uint32_t)SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE); + + SSIF_DisableErrorInterrupt(ssif_ch); + + /* TEN and REN are disable */ + g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN); + + /* Reset FIFO */ + g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST); + dummy_read = g_ssireg[ssif_ch]->SSIFCR; + UNUSED_ARG(dummy_read); + g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST); + + /* pause DMA transfer */ + SSIF_CancelDMA(p_info_ch); + + /* clear status reg */ + g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */ + + /* cancel event to ongoing request */ + if (NULL != p_info_ch->p_aio_tx_curr) + { + p_info_ch->p_aio_tx_curr->aio_return = EIO; + ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr); + p_info_ch->p_aio_tx_curr = NULL; + } + if (NULL != p_info_ch->p_aio_tx_next) + { + p_info_ch->p_aio_tx_next->aio_return = EIO; + ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next); + p_info_ch->p_aio_tx_next = NULL; + } + if (NULL != p_info_ch->p_aio_rx_curr) + { + p_info_ch->p_aio_rx_curr->aio_return = EIO; + ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr); + p_info_ch->p_aio_rx_curr = NULL; + } + if (NULL != p_info_ch->p_aio_rx_next) + { + p_info_ch->p_aio_rx_next->aio_return = EIO; + ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next); + p_info_ch->p_aio_rx_next = NULL; + } + } + + /* configure channel hardware */ + if (ESUCCESS == ercd) + { + /* software reset */ + SSIF_Reset(ssif_ch); + + /* Set control parameters */ + ercd = SSIF_SetCtrlParams(p_info_ch); + } + + if (ESUCCESS == ercd) + { + if (SSIF_CFG_ENABLE_ROMDEC_DIRECT + != p_info_ch->romdec_direct.mode) + { + /* setup/restart DMA transfer */ + ercd = SSIF_RestartDMA(p_info_ch); + } + else + { + /* execute callback function */ + if (NULL != p_info_ch->romdec_direct.p_cbfunc) + { + (*p_info_ch->romdec_direct.p_cbfunc)(); + } + } + } + } + + if (ESUCCESS != ercd) + { + /* NON_NOTICE_ASSERT: cannot restart channel */ + } + + return; +} + +/****************************************************************************** +* Function Name: SSIF_PostAsyncIo +* @brief Enqueue asynchronous read/write request +* +* Description:<br> +* +* @param[in,out] p_info_ch :channel object +* @param[in,out] p_aio :aio control block of read/write request +* @retval none +******************************************************************************/ +void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio) +{ + if ((NULL == p_info_ch) || (NULL == p_aio)) + { + /* NON_NOTICE_ASSERT: illegal pointer */ + } + else + { + if (SSIF_ASYNC_W == p_aio->aio_return) + { + ahf_addtail(&p_info_ch->tx_que, p_aio); + } + else if (SSIF_ASYNC_R == p_aio->aio_return) + { + ahf_addtail(&p_info_ch->rx_que, p_aio); + } + else + { + /* NON_NOTICE_ASSERT: illegal request type */ + } + } + + return; +} + +/****************************************************************************** +* Function Name: SSIF_PostAsyncCancel +* @brief Cancel read or write request(s) +* +* Description:<br> +* +* @param[in,out] p_info_ch :channel object +* @param[in,out] p_aio :aio control block to cancel or NULL to cancel all. +* @retval none +******************************************************************************/ +void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio) +{ + int32_t ioif_ret; + + if (NULL == p_info_ch) + { + /* NON_NOTICE_ASSERT: illegal pointer */ + } + else + { + if (NULL == p_aio) + { + ahf_cancelall(&p_info_ch->tx_que); + ahf_cancelall(&p_info_ch->rx_que); + } + else + { + ioif_ret = ahf_cancel(&p_info_ch->tx_que, p_aio); + if (ESUCCESS != ioif_ret) + { + /* NON_NOTICE_ASSERT: unexpected aioif error */ + } + + ioif_ret = ahf_cancel(&p_info_ch->rx_que, p_aio); + if (ESUCCESS != ioif_ret) + { + /* NON_NOTICE_ASSERT: unexpected aioif error */ + } + } + } + + return; +} + +/****************************************************************************** +* Function Name: SSIF_IOCTL_ConfigChannel +* @brief Save configuration to the SSIF driver. +* +* Description:<br> +* Update channel object. +* @param[in,out] p_info_ch :channel object +* @param[in] p_ch_cfg :SSIF channel configuration parameter +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch, + const ssif_channel_cfg_t* const p_ch_cfg) +{ + int_t ercd; + + if ((NULL == p_info_ch) || (NULL == p_ch_cfg)) + { + ercd = EFAULT; + } + else + { + /* stop DMA transfer */ + ercd = SSIF_DisableChannel(p_info_ch); + + if (ESUCCESS == ercd) + { + /* copy config data to channel info */ + ercd = SSIF_UpdateChannelConfig(p_info_ch, p_ch_cfg); + } + + if (ESUCCESS == ercd) + { + /* restart DMA transfer */ + ercd = SSIF_EnableChannel(p_info_ch); + } + } + + return ercd; +} + +/****************************************************************************** +* Function Name: SSIF_IOCTL_GetStatus +* @brief Get a value of SSISR register. +* +* Description:<br> +* +* @param[in] p_info_ch :channel object +* @param[in,out] p_status :pointer of status value +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status) +{ + int_t ret = ESUCCESS; + + if ((NULL == p_info_ch) || (NULL == p_status)) + { + ret = EFAULT; + } + else + { + *p_status = g_ssireg[p_info_ch->channel]->SSISR; + } + + return ret; +} + +/****************************************************************************** +* Function Name: SSIF_SWLtoLen +* @brief Convert SSICR:SWL bits to system word length +* +* Description:<br> +* +* @param[in] ssicr_swl :SSICR register SWL field value(0 to 7) +* @retval 8 to 256 :system word length(byte) +******************************************************************************/ +int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl) +{ + /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */ + static const int_t decode_enum_swl[SSIF_CFG_SYSTEM_WORD_256+1] = { + 8, /* SSIF_CFG_SYSTEM_WORD_8 */ + 16, /* SSIF_CFG_SYSTEM_WORD_16 */ + 24, /* SSIF_CFG_SYSTEM_WORD_24 */ + 32, /* SSIF_CFG_SYSTEM_WORD_32 */ + 48, /* SSIF_CFG_SYSTEM_WORD_48 */ + 64, /* SSIF_CFG_SYSTEM_WORD_64 */ + 128, /* SSIF_CFG_SYSTEM_WORD_128 */ + 256 /* SSIF_CFG_SYSTEM_WORD_256 */ + }; + /* <- IPA M1.10.1 */ + + return decode_enum_swl[ssicr_swl]; +} + +/****************************************************************************** +* Function Name: SSIF_DWLtoLen +* @brief Convert SSICR:DWL bits to data word length +* +* Description:<br> +* +* @param[in] ssicr_dwl :SSICR register DWL field value(0 to 6) +* @retval 8 to 32 :data word length(byte) +******************************************************************************/ +int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl) +{ + /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */ + static const int_t decode_enum_dwl[SSIF_CFG_DATA_WORD_32+1] = { + 8, /* SSIF_CFG_DATA_WORD_8 */ + 16, /* SSIF_CFG_DATA_WORD_16 */ + 18, /* SSIF_CFG_DATA_WORD_18 */ + 20, /* SSIF_CFG_DATA_WORD_20 */ + 22, /* SSIF_CFG_DATA_WORD_22 */ + 24, /* SSIF_CFG_DATA_WORD_24 */ + 32 /* SSIF_CFG_DATA_WORD_32 */ + }; + /* <- IPA M1.10.1 */ + + return decode_enum_dwl[ssicr_dwl]; +} + +/****************************************************************************** +Private functions +******************************************************************************/ + +/****************************************************************************** +* Function Name: SSIF_InitChannel +* @brief Initialize for the SSIF channel +* +* Description:<br> +* Create semaphore and queue for channel.<br> +* And setup SSIF pin. +* @param[in,out] p_info_ch :channel object +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch) +{ + int32_t os_ret; + uint32_t ssif_ch; + int_t ercd = ESUCCESS; + static const osSemaphoreDef_t* semdef_access[SSIF_NUM_CHANS] = + { + osSemaphore(ssif_ch0_access), + osSemaphore(ssif_ch1_access), + osSemaphore(ssif_ch2_access), + osSemaphore(ssif_ch3_access), + osSemaphore(ssif_ch4_access), + osSemaphore(ssif_ch5_access) + }; + static const bool_t is_duplex_ch[SSIF_NUM_CHANS] = + { + true, /* SSIF0 is full duplex channel */ + true, /* SSIF1 is full duplex channel */ + false, /* SSIF2 is half duplex channel */ + true, /* SSIF3 is full duplex channel */ + false, /* SSIF4 is half duplex channel */ + true /* SSIF5 is full duplex channel */ + }; + + if (NULL == p_info_ch) + { + ercd = EFAULT; + } + else + { + ssif_ch = p_info_ch->channel; + + p_info_ch->is_full_duplex = is_duplex_ch[ssif_ch]; + + /* Create sem_access semaphore */ + p_info_ch->sem_access = osSemaphoreCreate(semdef_access[ssif_ch], 1); + + if (NULL == p_info_ch->sem_access) + { + ercd = ENOMEM; + } + + if (ESUCCESS == ercd) + { + ercd = ahf_create(&p_info_ch->tx_que, AHF_LOCKINT); + if (ESUCCESS != ercd) + { + ercd = ENOMEM; + } + } + + if (ESUCCESS == ercd) + { + ercd = ahf_create(&p_info_ch->rx_que, AHF_LOCKINT); + if (ESUCCESS != ercd) + { + ercd = ENOMEM; + } + } + + if (ESUCCESS == ercd) + { + /* set channel initialize */ + p_info_ch->openflag = 0; + + p_info_ch->p_aio_tx_curr = NULL; /* tx request pointer */ + p_info_ch->p_aio_tx_next = NULL; /* tx request pointer */ + p_info_ch->p_aio_rx_curr = NULL; /* rx request pointer */ + p_info_ch->p_aio_rx_next = NULL; /* rx request pointer */ + } + + if (ESUCCESS == ercd) + { + ercd = R_SSIF_Userdef_InitPinMux(ssif_ch); + } + + if (ESUCCESS == ercd) + { + p_info_ch->ch_stat = SSIF_CHSTS_INIT; + } + else + { + if (NULL != p_info_ch->sem_access) + { + os_ret = osSemaphoreDelete(p_info_ch->sem_access); + if (osOK != os_ret) + { + /* NON_NOTICE_ASSERT: unexpected semaphore error */ + } + p_info_ch->sem_access = NULL; + } + } + } + + return ercd; +} + +/****************************************************************************** +* Function Name: SSIF_UnInitChannel +* @brief Uninitialise the SSIF channel. +* +* Description:<br> +* +* @param[in,out] p_info_ch :channel object +* @retval none +******************************************************************************/ +static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch) +{ + int32_t os_ret; + int_t was_masked; + uint32_t ssif_ch; + + if (NULL == p_info_ch) + { + /* NON_NOTICE_ASSERT: illegal pointer */ + } + else + { + ssif_ch = p_info_ch->channel; + + if (SSIF_CHSTS_INIT != p_info_ch->ch_stat) + { + /* NON_NOTICE_ASSERT: unexpected channel status */ + } + + p_info_ch->ch_stat = SSIF_CHSTS_UNINIT; + + SSIF_DisableErrorInterrupt(ssif_ch); + + was_masked = __disable_irq(); + + /* delete the tx queue */ + ahf_cancelall(&p_info_ch->tx_que); + ahf_destroy(&p_info_ch->tx_que); + + /* delete the rx queue */ + ahf_cancelall(&p_info_ch->rx_que); + ahf_destroy(&p_info_ch->rx_que); + + /* delete the private semaphore */ + os_ret = osSemaphoreDelete(p_info_ch->sem_access); + if (osOK != os_ret) + { + /* NON_NOTICE_ASSERT: unexpected semaphore error */ + } + + SSIF_InterruptShutdown(ssif_ch); + + if (0 == was_masked) + { + __enable_irq(); + } + } + + return; +} + +/****************************************************************************** +* Function Name: SSIF_UpdateChannelConfig +* @brief Save configuration to the SSIF driver. +* +* Description:<br> +* Update channel object. +* @param[in,out] p_info_ch :channel object +* @param[in] p_ch_cfg :SSIF channel configuration parameter +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch, + const ssif_channel_cfg_t* const p_ch_cfg) +{ + int_t ercd; + + if ((NULL == p_info_ch) || (NULL == p_ch_cfg)) + { + ercd = EFAULT; + } + else + { + ercd = SSIF_CheckChannelCfg(p_ch_cfg); + + if (ESUCCESS == ercd) + { + p_info_ch->slave_mode = p_ch_cfg->slave_mode; + + if (false != p_info_ch->slave_mode) + { + /* slave mode */ + p_info_ch->clock_direction = SSIF_CFG_CLOCK_IN; + p_info_ch->ws_direction = SSIF_CFG_WS_IN; + } + else + { + /* master mode */ + p_info_ch->clock_direction = SSIF_CFG_CLOCK_OUT; + p_info_ch->ws_direction = SSIF_CFG_WS_OUT; + + /* when master mode, always disable noise cancel */ + p_info_ch->noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL; + } + + p_info_ch->sample_freq = p_ch_cfg->sample_freq; + + p_info_ch->clk_select = p_ch_cfg->clk_select; + p_info_ch->multi_ch = p_ch_cfg->multi_ch; + p_info_ch->data_word = p_ch_cfg->data_word; + p_info_ch->system_word = p_ch_cfg->system_word; + p_info_ch->bclk_pol = p_ch_cfg->bclk_pol; + p_info_ch->ws_pol = p_ch_cfg->ws_pol; + p_info_ch->padding_pol = p_ch_cfg->padding_pol; + p_info_ch->serial_alignment = p_ch_cfg->serial_alignment; + p_info_ch->parallel_alignment = p_ch_cfg->parallel_alignment; + p_info_ch->ws_delay = p_ch_cfg->ws_delay; + p_info_ch->noise_cancel = p_ch_cfg->noise_cancel; + p_info_ch->tdm_mode = p_ch_cfg->tdm_mode; + p_info_ch->romdec_direct.mode = p_ch_cfg->romdec_direct.mode; + p_info_ch->romdec_direct.p_cbfunc = p_ch_cfg->romdec_direct.p_cbfunc; + + if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode) + { + /* check combination of parameters */ + if ((SSIF_CFG_MULTI_CH_1 == p_info_ch->multi_ch) + || (SSIF_CFG_WS_HIGH == p_info_ch->ws_pol)) + { + ercd = EINVAL; + } + } + } + + if (ESUCCESS == ercd) + { + ercd = SSIF_CheckWordSize(p_info_ch); + } + + if (ESUCCESS == ercd) + { + if (false == p_info_ch->slave_mode) + { + /* Master: call user own clock setting function */ + ercd = R_SSIF_Userdef_SetClockDiv(p_ch_cfg, &p_info_ch->clk_div); + } + else + { + /* Slave: set dummy value for clear */ + p_info_ch->clk_div = SSIF_CFG_CKDV_BITS_1; + } + } + } + + return ercd; +} + +/****************************************************************************** +* Function Name: SSIF_SetCtrlParams +* @brief Set SSIF configuration to hardware. +* +* Description:<br> +* Update SSICR register. +* @param[in] p_info_ch :channel object +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch) +{ + int_t ret = ESUCCESS; + int_t was_masked; + uint32_t ssif_ch; + static const uint32_t gpio_sncr_bit[SSIF_NUM_CHANS] = + { + GPIO_SNCR_BIT_SSI0NCE, /* SSIF0 */ + GPIO_SNCR_BIT_SSI1NCE, /* SSIF1 */ + GPIO_SNCR_BIT_SSI2NCE, /* SSIF2 */ + GPIO_SNCR_BIT_SSI3NCE, /* SSIF3 */ + GPIO_SNCR_BIT_SSI4NCE, /* SSIF4 */ + GPIO_SNCR_BIT_SSI5NCE /* SSIF5 */ + }; + + if (NULL == p_info_ch) + { + ret = EFAULT; + } + else + { + ssif_ch = p_info_ch->channel; + + /* ALL CLEAR */ + g_ssireg[ssif_ch]->SSICR = 0u; + g_ssireg[ssif_ch]->SSISR = 0u; + g_ssireg[ssif_ch]->SSIFCCR = 0u; + + g_ssireg[ssif_ch]->SSICR = (uint32_t)( + ((uint32_t)(p_info_ch->clk_select) << SSIF_CR_SHIFT_CKS) | + ((uint32_t)(p_info_ch->multi_ch) << SSIF_CR_SHIFT_CHNL) | + ((uint32_t)(p_info_ch->data_word) << SSIF_CR_SHIFT_DWL) | + ((uint32_t)(p_info_ch->system_word) << SSIF_CR_SHIFT_SWL) | + ((uint32_t)(p_info_ch->bclk_pol) << SSIF_CR_SHIFT_SCKP) | + ((uint32_t)(p_info_ch->ws_pol) << SSIF_CR_SHIFT_SWSP) | + ((uint32_t)(p_info_ch->padding_pol) << SSIF_CR_SHIFT_SPDP) | + ((uint32_t)(p_info_ch->serial_alignment) << SSIF_CR_SHIFT_SDTA) | + ((uint32_t)(p_info_ch->parallel_alignment) << SSIF_CR_SHIFT_PDTA) | + ((uint32_t)(p_info_ch->ws_delay) << SSIF_CR_SHIFT_DEL) | + ((uint32_t)(p_info_ch->clock_direction) << SSIF_CR_SHIFT_SCKD) | + ((uint32_t)(p_info_ch->ws_direction) << SSIF_CR_SHIFT_SWSD) | + ((uint32_t)(p_info_ch->clk_div) << SSIF_CR_SHIFT_CKDV) + ); + + g_ssireg[ssif_ch]->SSITDMR = ((uint32_t)(p_info_ch->tdm_mode) << SSIF_TDMR_SHIFT_TDM); + + /* change SNCR register: enter exclusive */ + was_masked = __disable_irq(); + + if ((SSIF_CFG_ENABLE_NOISE_CANCEL == p_info_ch->noise_cancel) + && (false != p_info_ch->slave_mode)) + { + /* ENABLE_NOISE_CANCEL && slave mode */ + GPIO.SNCR |= (uint32_t)gpio_sncr_bit[ssif_ch]; + } + else + { + /* DISABLE_NOISE_CANCEL || master mode */ + GPIO.SNCR &= ~((uint32_t)gpio_sncr_bit[ssif_ch]); + } + + /* change SNCR register: exit exclusive */ + if (0 == was_masked) + { + __enable_irq(); + } + } + + return ret; +} + +/****************************************************************************** +* Function Name: SSIF_CheckChannelCfg +* @brief Check channel configuration parameters are valid or not. +* +* Description:<br> +* +* @param[in] p_ch_cfg :channel configuration +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg) +{ + int_t ret = ESUCCESS; + + if (NULL == p_ch_cfg) + { + ret = EFAULT; + } + else + { + switch (p_ch_cfg->clk_select) + { + case SSIF_CFG_CKS_AUDIO_X1: + /* fall through */ + case SSIF_CFG_CKS_AUDIO_CLK: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->multi_ch) + { + case SSIF_CFG_MULTI_CH_1: + /* fall through */ + case SSIF_CFG_MULTI_CH_2: + /* fall through */ + case SSIF_CFG_MULTI_CH_3: + /* fall through */ + case SSIF_CFG_MULTI_CH_4: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->data_word) + { + case SSIF_CFG_DATA_WORD_8: + /* fall through */ + case SSIF_CFG_DATA_WORD_16: + /* fall through */ + case SSIF_CFG_DATA_WORD_18: + /* fall through */ + case SSIF_CFG_DATA_WORD_20: + /* fall through */ + case SSIF_CFG_DATA_WORD_22: + /* fall through */ + case SSIF_CFG_DATA_WORD_24: + /* fall through */ + case SSIF_CFG_DATA_WORD_32: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->system_word) + { + case SSIF_CFG_SYSTEM_WORD_8: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_16: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_24: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_32: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_48: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_64: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_128: + /* fall through */ + case SSIF_CFG_SYSTEM_WORD_256: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->bclk_pol) + { + case SSIF_CFG_FALLING: + /* fall through */ + case SSIF_CFG_RISING: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->ws_pol) + { + case SSIF_CFG_WS_LOW: + /* fall through */ + case SSIF_CFG_WS_HIGH: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->padding_pol) + { + case SSIF_CFG_PADDING_LOW: + /* fall through */ + case SSIF_CFG_PADDING_HIGH: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->serial_alignment) + { + case SSIF_CFG_DATA_FIRST: + /* fall through */ + case SSIF_CFG_PADDING_FIRST: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->parallel_alignment) + { + case SSIF_CFG_LEFT: + /* fall through */ + case SSIF_CFG_RIGHT: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->ws_delay) + { + case SSIF_CFG_DELAY: + /* fall through */ + case SSIF_CFG_NO_DELAY: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->noise_cancel) + { + case SSIF_CFG_DISABLE_NOISE_CANCEL: + /* fall through */ + case SSIF_CFG_ENABLE_NOISE_CANCEL: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->tdm_mode) + { + case SSIF_CFG_DISABLE_TDM: + /* fall through */ + case SSIF_CFG_ENABLE_TDM: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + + if (ESUCCESS == ret) + { + switch (p_ch_cfg->romdec_direct.mode) + { + case SSIF_CFG_DISABLE_ROMDEC_DIRECT: + /* fall through */ + case SSIF_CFG_ENABLE_ROMDEC_DIRECT: + /* do nothing */ + break; + default: + ret = EINVAL; + break; + } + } + } + + return ret; +} + +/****************************************************************************** +* Function Name: SSIF_CheckWordSize +* @brief Check system word size whether that is valid or not. +* +* Description:<br> +* if system_words couldn't involve specified number of<br> +* data_words then error. +* @param[in] p_info_ch :channel object +* @retval ESUCCESS :Success. +* @retval error code :Failure. +******************************************************************************/ +static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch) +{ + uint32_t ssicr_chnl; + uint32_t dw_per_sw; + uint32_t datawd_len; + uint32_t syswd_len; + int_t ret = ESUCCESS; + + if (NULL == p_info_ch) + { + ret = EFAULT; + } + else + { + ssicr_chnl = p_info_ch->multi_ch; + /* ->MISRA 13.7 : This is verbose error check by way of precaution */ + if (SSIF_CFG_MULTI_CH_4 < ssicr_chnl) + /* <-MISRA 13.7 */ + { + ret = EINVAL; + } + else + { + /* data_words number per system_words */ + if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode) + { + /* When TDM Mode data_word number per system_words fixed to 1 */ + dw_per_sw = 1u; + } + else + { + /* When not TDM data_word number per system_words depends CHNL */ + dw_per_sw = ssicr_chnl + 1u; + } + + /* size of data_words */ + datawd_len = (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word); + + if (0u == datawd_len) + { + ret = EINVAL; + } + else + { + /* size of system_words */ + syswd_len = (uint32_t)SSIF_SWLtoLen(p_info_ch->system_word); + + if (syswd_len < (datawd_len * dw_per_sw)) + { + ret = EINVAL; + } + } + } + } + + return ret; +} + +/****************************************************************************** +* Function Name: SSIF_Reset +* @brief SSIF software reset +* +* Description:<br> +* +* @param[in] ssif_ch :SSIF channel +* @retval none +******************************************************************************/ +static void SSIF_Reset(const uint32_t ssif_ch) +{ + int_t was_masked; + uint8_t dummy_read_u8; + static const uint32_t cpg_swrst_bit[SSIF_NUM_CHANS] = + { + CPG_SWRSTCR1_BIT_SRST16, /* SSIF0 */ + CPG_SWRSTCR1_BIT_SRST15, /* SSIF1 */ + CPG_SWRSTCR1_BIT_SRST14, /* SSIF2 */ + CPG_SWRSTCR1_BIT_SRST13, /* SSIF3 */ + CPG_SWRSTCR1_BIT_SRST12, /* SSIF4 */ + CPG_SWRSTCR1_BIT_SRST11 /* SSIF5 */ + }; + + /* change register: enter exclusive */ + was_masked = __disable_irq(); + + /* SW Reset ON */ + /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */ + CPGSWRSTCR1 |= (uint8_t)cpg_swrst_bit[ssif_ch]; + dummy_read_u8 = CPGSWRSTCR1; + /* <-IPA R2.4.2 */ + UNUSED_ARG(dummy_read_u8); + + /* SW Reset OFF */ + /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */ + CPGSWRSTCR1 &= (uint8_t)~((uint8_t)cpg_swrst_bit[ssif_ch]); + dummy_read_u8 = CPGSWRSTCR1; + /* <-IPA R2.4.2 */ + UNUSED_ARG(dummy_read_u8); + + /* change register: exit exclusive */ + if (0 == was_masked) + { + __enable_irq(); + } + + return; +} +