RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Revision:
0:702bf7b2b7d8
Child:
5:1390bfcb667c
diff -r 000000000000 -r 702bf7b2b7d8 RenesasBSP/drv_src/dma/dma_if.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RenesasBSP/drv_src/dma/dma_if.c	Mon Jun 01 08:33:21 2015 +0000
@@ -0,0 +1,1346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.c
+* $Rev: 1317 $
+* $Date:: 2014-12-04 10:43:59 +0900#$
+* @brief        DMA Driver interface functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+/******************************************************************************
+Private global driver semaphore information
+******************************************************************************/
+
+/* driver semaphore define */
+/* ->MISRA 8.8, 8.10, IPA M2.2.2 There is no problem in the description of declaration of 
+OS resource itself */
+osSemaphoreDef(sem_dma_drv);
+/* <-MISRA 8.8, 8.10, IPA M2.2.2 */
+
+/******************************************************************************
+* Function Name: R_DMA_Init
+* Description : Init DMA driver.
+*               Making driver semaphore and check parameter in this function.
+* Arguments : *p_dma_init_param -
+*                  Point of driver init parameter.
+*             *p_errno-
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Registering handler failed.
+*                     ENOMEM : Making semaphore failed.
+*                     EPERM : Pointer of callback function which called in DMA 
+*                             error interrupt handler is NULL.
+*                     EFAULT : dma_init_param is NULL.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called.  */
+int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t         retval = ESUCCESS;
+    int_t         result_init;
+    osSemaphoreId sem_drv_create_id;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    sem_drv_create_id = NULL;
+    
+    if (NULL == p_dma_init_param)
+    {
+        /* set error return value */
+        retval = (EERROR);
+        DMA_SetErrCode(EFAULT, p_errno);
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+        if (NULL == p_dma_init_param->p_aio)
+        /* <-MISRA 1.2 */
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(EPERM, p_errno);
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* makeing driver semaphore */
+        /* make semaphore */
+        sem_drv_create_id = osSemaphoreCreate(osSemaphore(sem_dma_drv), 1);
+        if (NULL == sem_drv_create_id)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(ENOMEM, p_errno);
+        }
+    }
+    
+    if ((ESUCCESS == retval) && (NULL != sem_drv_create_id))
+    {
+        result_init = DMA_Initialize(p_dma_init_param, sem_drv_create_id);
+        if (ESUCCESS != result_init)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(result_init, p_errno);
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Init
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_UnInit
+* Description : UnInit DMA driver.
+*               Delete driver semaphore and check parameter in this function.
+* Arguments : *p_errno-
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Unegistering handler failed.
+*                     OS error num : Semaphore release failed.
+*                     OS error num : Semaphore delete failed.
+*                     EACCES : Driver status isn't DMA_DRV_INIT.
+*                     EBUSY : It has been allocated already in channel.
+*                     EFAULT : Wait semaphore failed.
+*                              Channel status is besides the status definded in 
+*                              dma_stat_ch_t.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_UnInit(int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    int_t          result_uninit;
+    dma_info_drv_t *dma_info_drv;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          ch_count;
+    int32_t        sem_wait_status;
+    osStatus       sem_status;
+    bool_t         ch_stat_check_flag;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    dma_info_drv = DMA_GetDrvInstance();
+    
+    /* start semaphore wait forever */
+    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+    sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
+    /* <-MISRA 10.6 */
+    /* semaphore error check */
+    if ((-1) == sem_wait_status)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(EFAULT, p_errno);
+    }
+    
+    /* check driver status */
+    if (ESUCCESS == retval)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EACCES, p_errno);
+        }
+        else
+        {
+            ch_stat_check_flag = false;
+            ch_count = 0;
+            while (false == ch_stat_check_flag)
+            {
+                /* check channel status */
+                dma_info_ch = DMA_GetDrvChInfo(ch_count);
+                if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
+                    (DMA_CH_INIT != dma_info_ch->ch_stat))
+                {
+                    /*  set error return value */
+                    retval = EERROR;
+                    /* check channel status is busy */
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        /* These 2 cases are intentionally combined. */
+                        case DMA_CH_OPEN:
+                        case DMA_CH_TRANSFER:
+                            DMA_SetErrCode(EBUSY, p_errno); 
+                        break;
+                        
+                        default:
+                            DMA_SetErrCode(EFAULT, p_errno);
+                        break;
+                    }
+                }
+                
+                if ((DMA_CH_NUM - 1) == ch_count)
+                {
+                    /* channel status check end */
+                    ch_stat_check_flag = true;
+                }
+                ch_count++;
+            }
+        }
+        /* uninitialize DMA */
+        if (ESUCCESS == retval)
+        {
+            result_uninit = DMA_UnInitialize();
+            if (ESUCCESS != result_uninit)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(result_uninit, p_errno);
+            }
+        }
+        /* semaphore release */
+        sem_status = osSemaphoreRelease(dma_info_drv->sem_drv);
+        if (osOK != sem_status)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode((int_t)sem_status, p_errno);
+        }
+        
+        if ((osOK == sem_status) && (ESUCCESS == retval))
+        {
+            /* semaphore delete */
+            sem_status = osSemaphoreDelete(dma_info_drv->sem_drv);
+            if (osOK != sem_status)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode((int_t)sem_status, p_errno);
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_UnInit
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Alloc
+* Description : Open DMA channel.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Open channel number.
+*                  If channel is (-1), it looking for free chanel and allocate.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
+*                     EACCES : Driver status isn't DMA_DRV_INIT.
+*                     EBUSY : It has been allocated already in channel.
+*                     EMFILE : When looking for a free channel, but a free channel
+*                              didn't exist.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    int_t           ercd = ESUCCESS;
+    int_t           get_ch_num;
+    dma_info_drv_t  *dma_info_drv;
+    int_t           sem_wait_status;
+    osStatus        sem_release_status;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check driver status */
+    dma_info_drv = DMA_GetDrvInstance();
+    
+    /* start semaphore wait forever */
+    /* check carrying out on the task (0) */
+    if (0 == R_ExceptionalMode())
+    {
+        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+        sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
+        /* <-MISRA 10.6 */
+        /* semaphore error check */
+        if ((-1) == sem_wait_status)
+        {
+            ercd = EFAULT;
+        }
+    }
+    
+    if (ESUCCESS == ercd)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            ercd =  EACCES;
+        }
+        else
+        {
+            /* check channel of argment */
+            if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
+            {
+                if (DMA_ALLOC_CH == channel)
+                {
+                    get_ch_num = DMA_GetFreeChannel();
+                }
+                else
+                {
+                    get_ch_num = DMA_GetFixedChannel(channel);
+                }
+                
+                /* check return number or error number */
+                if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
+                {
+                    /* set channel number to return value */
+                    retval = get_ch_num;
+                }
+                else
+                {
+                    /* set error code to error value */
+                    ercd = get_ch_num;
+                }
+            }
+            else
+            {
+                /* set error return value */
+                ercd =  EINVAL;
+            }
+        }
+        /* semaphore release */
+        /* check carrying out on the task (0) */
+        if (0 == R_ExceptionalMode())
+        {
+            sem_release_status = osSemaphoreRelease(dma_info_drv->sem_drv);
+            if (osOK != sem_release_status)
+            {
+                /* set error return value */
+                ercd = (int_t)sem_release_status;
+            }
+        }
+    }
+    
+    /* occured error check */
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(ercd, p_errno);
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Alloc
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Free
+* Description : Close DMA channel.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Close channel number.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EACCES : Driver status isn't DMA_DRV_INIT.
+*                     EBUSY : It has been start DMA transfer in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    dma_info_drv_t  *dma_info_drv;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           sem_wait_status;
+    osStatus        sem_release_status;
+    int_t           error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+         /* check driver status */
+        dma_info_drv = DMA_GetDrvInstance();
+        
+        /* start semaphore wait forever */
+        /* check carrying out on the task (0) */
+        if (0 == R_ExceptionalMode())
+        {
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_status = osSemaphoreWait(dma_info_drv->sem_drv, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_status)
+            {
+                retval = EERROR;
+                DMA_SetErrCode(EFAULT, p_errno);
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check driver status */
+            if (DMA_DRV_INIT == dma_info_drv->drv_stat)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* start semaphore wait forever */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        DMA_CloseChannel(channel);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                            
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                            
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                            
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                    /* semaphore release */
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode())
+                    {
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+            else
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EACCES, p_errno);
+            
+            }
+            /* semaphore release */
+            /* check carrying out on the task (0) */
+            if (0 == R_ExceptionalMode())
+            {
+                sem_release_status = osSemaphoreRelease(dma_info_drv->sem_drv);
+                if (osOK != sem_release_status)
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                }
+            }
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Free
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Setup
+* Description : Setup DMA transfer parameter.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Setup channel number.
+*             *p_ch_setup -
+*                  Set up parameters.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EBUSY : It has been start DMA transfer in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EPERM : The value in p_ch_setup isn't in the right range.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_ch_setup is NULL.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t            retval = ESUCCESS;
+    dma_info_ch_t    *dma_info_ch;
+    int_t            sem_wait_status;
+    osStatus         sem_release_status;
+    int_t            error_code;
+    uint32_t         cfg_table_count;
+    dma_ch_cfg_t     ch_cfg_set_table;
+    uint32_t         set_reqd;
+    bool_t           check_table_flag;
+    
+    /* Resouce Configure Set Table */
+    static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
+    {
+        {DMA_RS_OSTIM0,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_OSTIM1,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI0A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI1A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI2A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI3A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI4A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_USB0_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB0_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_ADEND,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTD,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTV,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IREADY,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_FLDT,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SDHI_0T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_0R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SDHI_1T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_1R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_MMCT,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MMCR,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI4,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI5,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI5,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPDIFTXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPDIFRXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_CMI1,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_CMI2,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MLBCI,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SGDEI0,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI1,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI2,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI3,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  }
+    };
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    /* dummy init set_reqd */
+    set_reqd = CHCFG_REQD_UNDEFINED;
+    ch_cfg_set_table = ch_cfg_table[0];
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_ch_setup)
+        {
+            /* check setup parameter */
+            /* check AIOCB pointer */
+            if (NULL == p_ch_setup->p_aio)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for destination */
+                if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) || 
+                    ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for source */
+                if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) || 
+                    ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for destination */
+                if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) || 
+                    ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for source */
+                if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) || 
+                    ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer direction */
+                if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) || 
+                    ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer resouce */
+                check_table_flag = false;
+                cfg_table_count = 0;
+                while (false == check_table_flag)
+                {
+                    if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
+                    {
+                        /* check reqd is undefined */ 
+                        if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
+                        {
+                            /* set reqd value on fixed value */
+                            if (DMA_REQ_SRC == p_ch_setup->direction)
+                            {
+                                set_reqd = CHCFG_SET_REQD_SRC;
+                            }
+                            else 
+                            {
+                                set_reqd = CHCFG_SET_REQD_DST;
+                            }
+                        }
+                        else
+                        {
+                            /* set reqd value in channel config table */
+                            set_reqd = ch_cfg_table[cfg_table_count].reqd;
+                        }
+                        /* set channel config table address for DMA_SetParam() */
+                        ch_cfg_set_table = ch_cfg_table[cfg_table_count];
+                        check_table_flag = true;
+                    }
+                    if (false == check_table_flag)
+                    {
+                        /* resource value did not exist in channel config table */
+                        if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EPERM, p_errno);
+                            check_table_flag = true;
+                        }
+                        cfg_table_count++;
+                    }
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* start semaphore wait forever */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set up parameter */
+                        DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                             
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                        
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                        
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                    /* semaphore release */
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode())
+                    {
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_DMA_SetParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Start
+* Description : Start DMA transfer.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  DMA start channel number.
+*             *p_dma_data -
+*                  DMA address parameters.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EBUSY : It has been start DMA transfer in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EPERM : The value in p_ch_setup isn't in the right range.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_dma_data is NULL.
+*                             Wait semaphore release.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          sem_wait_status;
+    osStatus       sem_release_status;
+    int_t          error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* start semaphore wait forever */
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set bus paramter for DMA */
+                        DMA_BusParam(channel, p_dma_data);
+                        /* set up address parameter */
+                        /* Next register set is 0 */
+                        DMA_SetData(channel, p_dma_data, 0);
+                        /* DMA transfer start */
+                        DMA_Start(channel, false);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                             break;
+                             
+                             case DMA_CH_INIT:
+                                error_code = EBADF;
+                             break;
+                        
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                        
+                            default:
+                                error_code = EFAULT; 
+                             break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                    /* semaphore release */
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode())
+                    {
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_DMA_Start
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_NextData
+* Description : Set continous DMA mode.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Continuous DMA channel number.
+*             *p_dma_data -
+*                  DMA address parameters.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT.
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     EBUSY : It has been set continous DMA transfer.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EPERM : The value in p_ch_setup isn't in the right range.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_dma_data is NULL.
+*                             Wait semaphore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                     int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          sem_wait_status;
+    osStatus       sem_release_status;
+    int_t          error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                /* check carrying out on the task (0) */
+                if (0 == R_ExceptionalMode())
+                {
+                    /* start semaphore wait forever */
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode(EFAULT, p_errno);
+                    }
+                }
+                    
+                if (ESUCCESS == retval)
+                {
+                    if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
+                        (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
+                    {
+                        if (false == dma_info_ch->next_dma_flag)
+                        {
+                            /* set up address parameter for continous DMA*/
+                            DMA_SetNextData(channel, p_dma_data);
+                        }
+                        else
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EBUSY, p_errno);
+                        }
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                            
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                            
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+
+                    /* check carrying out on the task (0) */
+                    if (0 == R_ExceptionalMode()) 
+                    {
+                        /* semaphore release */
+                        sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                        /* semaphore error check */
+                        if (osOK != sem_release_status)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_DMA_NextData
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_Cancel
+* Description : Cancel DMA transfer.
+*               Check parameter in this function mainly.
+* Arguments : channel -
+*                  Cancel DMA channel number.
+*             *p_remain -
+*                  Remain data size of DMA transfer when it stopping.
+*             *p_errno -
+*                  Pointer of error code.
+*                  When pointer is NULL, it isn't set error code.
+*                  error code -
+*                     OS error num : Semaphore release failed.
+*                     EBADF : Channel status is DMA_CH_INIT or DMA_CH_OPEN.
+*                             (DMA stopped)
+*                     EINVAL : Value of the ch is outside the range of 
+*                              (-1) < ch < (DMA_CH_NUM + 1).
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+*                             p_remain is NULL.
+*                             Wait semaphhore failed.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          sem_wait_status;
+    osStatus       sem_release_status;
+    int_t          error_code;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        /* check whether p_remain is NULL */
+        if (NULL != p_remain)
+        {
+            dma_info_ch = DMA_GetDrvChInfo(channel);
+            
+            if (0 == R_ExceptionalMode())
+            {
+                /* start semaphore wait forever */
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_status = osSemaphoreWait(dma_info_ch->sem_ch, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_status)
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EFAULT, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
+                {
+                    /* set up address parameter for continous DMA*/
+                    DMA_Stop(channel, p_remain);
+                }
+                else
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        case DMA_CH_UNINIT:
+                            error_code = ENOTSUP; 
+                        break;
+                        
+                        case DMA_CH_INIT:
+                            error_code = EBADF;
+                        break;
+                        
+                        case DMA_CH_OPEN:
+                            error_code = EBADF;
+                        break;
+                        
+                        default:
+                            error_code = EFAULT; 
+                        break;
+                    }
+                    DMA_SetErrCode(error_code, p_errno);
+                }
+                
+                if (0 == R_ExceptionalMode())
+                {
+                    /* semaphore release */
+                    sem_release_status = osSemaphoreRelease(dma_info_ch->sem_ch);
+                    /* semaphore error check */
+                    if (osOK != sem_release_status)
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        DMA_SetErrCode((int_t)sem_release_status, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Cancel
+******************************************************************************/
+