RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Mon Jun 01 08:33:21 2015 +0000
Revision:
0:702bf7b2b7d8
first comit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma_if.h
dkato 0:702bf7b2b7d8 26 * $Rev: 1318 $
dkato 0:702bf7b2b7d8 27 * $Date:: 2014-12-04 10:45:12 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver interface headers
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 #ifndef DMA_IF_H
dkato 0:702bf7b2b7d8 37 #define DMA_IF_H
dkato 0:702bf7b2b7d8 38
dkato 0:702bf7b2b7d8 39 /******************************************************************************
dkato 0:702bf7b2b7d8 40 Includes <System Includes> , "Project Includes"
dkato 0:702bf7b2b7d8 41 ******************************************************************************/
dkato 0:702bf7b2b7d8 42
dkato 0:702bf7b2b7d8 43 #include "cmsis_os.h"
dkato 0:702bf7b2b7d8 44 #include "r_errno.h"
dkato 0:702bf7b2b7d8 45 #include "r_typedefs.h"
dkato 0:702bf7b2b7d8 46 #include "ioif_aio.h"
dkato 0:702bf7b2b7d8 47
dkato 0:702bf7b2b7d8 48
dkato 0:702bf7b2b7d8 49 #ifdef __cplusplus
dkato 0:702bf7b2b7d8 50 extern "C"
dkato 0:702bf7b2b7d8 51 {
dkato 0:702bf7b2b7d8 52 #endif /* __cplusplus */
dkato 0:702bf7b2b7d8 53
dkato 0:702bf7b2b7d8 54
dkato 0:702bf7b2b7d8 55 /*************************************************************************
dkato 0:702bf7b2b7d8 56 User Includes
dkato 0:702bf7b2b7d8 57 *************************************************************************/
dkato 0:702bf7b2b7d8 58
dkato 0:702bf7b2b7d8 59 /*************************************************************************
dkato 0:702bf7b2b7d8 60 Defines
dkato 0:702bf7b2b7d8 61 *************************************************************************/
dkato 0:702bf7b2b7d8 62
dkato 0:702bf7b2b7d8 63 /* for searching free channel */
dkato 0:702bf7b2b7d8 64 #define DMA_ALLOC_CH (-1)
dkato 0:702bf7b2b7d8 65
dkato 0:702bf7b2b7d8 66 /*************************************************************************
dkato 0:702bf7b2b7d8 67 Enumerated Types
dkato 0:702bf7b2b7d8 68 *************************************************************************/
dkato 0:702bf7b2b7d8 69
dkato 0:702bf7b2b7d8 70 /* Number od DMA channel */
dkato 0:702bf7b2b7d8 71 typedef enum
dkato 0:702bf7b2b7d8 72 {
dkato 0:702bf7b2b7d8 73 DMA_CH_0 = 0,
dkato 0:702bf7b2b7d8 74 DMA_CH_1 = 1,
dkato 0:702bf7b2b7d8 75 DMA_CH_2 = 2,
dkato 0:702bf7b2b7d8 76 DMA_CH_3 = 3,
dkato 0:702bf7b2b7d8 77 DMA_CH_4 = 4,
dkato 0:702bf7b2b7d8 78 DMA_CH_5 = 5,
dkato 0:702bf7b2b7d8 79 DMA_CH_6 = 6,
dkato 0:702bf7b2b7d8 80 DMA_CH_7 = 7,
dkato 0:702bf7b2b7d8 81 DMA_CH_8 = 8,
dkato 0:702bf7b2b7d8 82 DMA_CH_9 = 9,
dkato 0:702bf7b2b7d8 83 DMA_CH_10 = 10,
dkato 0:702bf7b2b7d8 84 DMA_CH_11 = 11,
dkato 0:702bf7b2b7d8 85 DMA_CH_12 = 12,
dkato 0:702bf7b2b7d8 86 DMA_CH_13 = 13,
dkato 0:702bf7b2b7d8 87 DMA_CH_14 = 14,
dkato 0:702bf7b2b7d8 88 DMA_CH_15 = 15,
dkato 0:702bf7b2b7d8 89 DMA_CH_NUM = 16 /* Number of DMA channel */
dkato 0:702bf7b2b7d8 90 } dma_ch_num_t;
dkato 0:702bf7b2b7d8 91
dkato 0:702bf7b2b7d8 92 /* Unit Size of DMA transfer */
dkato 0:702bf7b2b7d8 93 typedef enum
dkato 0:702bf7b2b7d8 94 {
dkato 0:702bf7b2b7d8 95 DMA_UNIT_MIN =(-1),
dkato 0:702bf7b2b7d8 96 DMA_UNIT_1 = 0, /* Unit Size of DMA transfer = 1byte */
dkato 0:702bf7b2b7d8 97 DMA_UNIT_2 = 1, /* Unit Size of DMA transfer = 2byte */
dkato 0:702bf7b2b7d8 98 DMA_UNIT_4 = 2, /* Unit Size of DMA transfer = 4byte */
dkato 0:702bf7b2b7d8 99 DMA_UNIT_8 = 3, /* Unit Size of DMA transfer = 8byte */
dkato 0:702bf7b2b7d8 100 DMA_UNIT_16 = 4, /* Unit Size of DMA transfer = 16byte */
dkato 0:702bf7b2b7d8 101 DMA_UNIT_32 = 5, /* Unit Size of DMA transfer = 32byte */
dkato 0:702bf7b2b7d8 102 DMA_UNIT_64 = 6, /* Unit Size of DMA transfer = 64byte */
dkato 0:702bf7b2b7d8 103 DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */
dkato 0:702bf7b2b7d8 104 DMA_UNIT_MAX = 8
dkato 0:702bf7b2b7d8 105 } dma_unit_size_t;
dkato 0:702bf7b2b7d8 106
dkato 0:702bf7b2b7d8 107 /* DMA transfer resource */
dkato 0:702bf7b2b7d8 108 typedef enum
dkato 0:702bf7b2b7d8 109 {
dkato 0:702bf7b2b7d8 110 DMA_RS_OSTIM0 = 0x023, /* OS Timer ch0 */
dkato 0:702bf7b2b7d8 111 DMA_RS_OSTIM1 = 0x027, /* OS Timer ch1 */
dkato 0:702bf7b2b7d8 112 DMA_RS_TGI0A = 0x043, /* Multi Function Timer Pulse Unit2 ch0 */
dkato 0:702bf7b2b7d8 113 DMA_RS_TGI1A = 0x047, /* Multi Function Timer Pulse Unit2 ch1 */
dkato 0:702bf7b2b7d8 114 DMA_RS_TGI2A = 0x04B, /* Multi Function Timer Pulse Unit2 ch2 */
dkato 0:702bf7b2b7d8 115 DMA_RS_TGI3A = 0x04F, /* Multi Function Timer Pulse Unit2 ch3 */
dkato 0:702bf7b2b7d8 116 DMA_RS_TGI4A = 0x053, /* Multi Function Timer Pulse Unit2 ch4 */
dkato 0:702bf7b2b7d8 117 DMA_RS_TXI0 = 0x061, /* FIFO Serial Communication Interface ch0 (TX) */
dkato 0:702bf7b2b7d8 118 DMA_RS_RXI0 = 0x062, /* FIFO Serial Communication Interface ch0 (RX) */
dkato 0:702bf7b2b7d8 119 DMA_RS_TXI1 = 0x065, /* FIFO Serial Communication Interface ch1 (TX) */
dkato 0:702bf7b2b7d8 120 DMA_RS_RXI1 = 0x066, /* FIFO Serial Communication Interface ch1 (RX) */
dkato 0:702bf7b2b7d8 121 DMA_RS_TXI2 = 0x069, /* FIFO Serial Communication Interface ch2 (TX) */
dkato 0:702bf7b2b7d8 122 DMA_RS_RXI2 = 0x06A, /* FIFO Serial Communication Interface ch2 (RX) */
dkato 0:702bf7b2b7d8 123 DMA_RS_TXI3 = 0x06D, /* FIFO Serial Communication Interface ch3 (TX) */
dkato 0:702bf7b2b7d8 124 DMA_RS_RXI3 = 0x06E, /* FIFO Serial Communication Interface ch3 (RX) */
dkato 0:702bf7b2b7d8 125 DMA_RS_TXI4 = 0x071, /* FIFO Serial Communication Interface ch4 (TX) */
dkato 0:702bf7b2b7d8 126 DMA_RS_RXI4 = 0x072, /* FIFO Serial Communication Interface ch4 (RX) */
dkato 0:702bf7b2b7d8 127 DMA_RS_TXI5 = 0x075, /* FIFO Serial Communication Interface ch5 (TX) */
dkato 0:702bf7b2b7d8 128 DMA_RS_RXI5 = 0x076, /* FIFO Serial Communication Interface ch5 (RX) */
dkato 0:702bf7b2b7d8 129 DMA_RS_TXI6 = 0x079, /* FIFO Serial Communication Interface ch6 (TX) */
dkato 0:702bf7b2b7d8 130 DMA_RS_RXI6 = 0x07A, /* FIFO Serial Communication Interface ch6 (RX) */
dkato 0:702bf7b2b7d8 131 DMA_RS_TXI7 = 0x07D, /* FIFO Serial Communication Interface ch7 (TX) */
dkato 0:702bf7b2b7d8 132 DMA_RS_RXI7 = 0x07E, /* FIFO Serial Communication Interface ch7 (RX) */
dkato 0:702bf7b2b7d8 133 DMA_RS_USB0_DMA0 = 0x083, /* USB Module0 ch0 */
dkato 0:702bf7b2b7d8 134 DMA_RS_USB0_DMA1 = 0x087, /* USB Module0 ch1 */
dkato 0:702bf7b2b7d8 135 DMA_RS_USB1_DMA0 = 0x08B, /* USB Module1 ch0 */
dkato 0:702bf7b2b7d8 136 DMA_RS_USB1_DMA1 = 0x08F, /* USB Module1 ch1 */
dkato 0:702bf7b2b7d8 137 DMA_RS_ADEND = 0x093, /* A/D Converter */
dkato 0:702bf7b2b7d8 138 DMA_RS_IEBBTD = 0x0A3, /* IEBus Controller (Data interrupt) */
dkato 0:702bf7b2b7d8 139 DMA_RS_IEBBTV = 0x0A7, /* IEBus Controller (Vector interrupt) */
dkato 0:702bf7b2b7d8 140 DMA_RS_IREADY = 0x0AB, /* CD-Rom Decoder */
dkato 0:702bf7b2b7d8 141 DMA_RS_FLDT = 0x0B3, /* NAND Memory Controller (Data) */
dkato 0:702bf7b2b7d8 142 DMA_RS_SDHI_0T = 0x0C1, /* SD Host Interface0 (TX) */
dkato 0:702bf7b2b7d8 143 DMA_RS_SDHI_0R = 0x0C2, /* SD Host Interface0 (RX) */
dkato 0:702bf7b2b7d8 144 DMA_RS_SDHI_1T = 0x0C5, /* SD Host Interface1 (RX) */
dkato 0:702bf7b2b7d8 145 DMA_RS_SDHI_1R = 0x0C6, /* SD Host Interface1 (TX) */
dkato 0:702bf7b2b7d8 146 DMA_RS_MMCT = 0x0C9, /* MMC Host Interface (TX) */
dkato 0:702bf7b2b7d8 147 DMA_RS_MMCR = 0x0CA, /* MMC Host Interface (RX) */
dkato 0:702bf7b2b7d8 148 DMA_RS_SSITXI0 = 0x0E1, /* SSIF0 (TX) */
dkato 0:702bf7b2b7d8 149 DMA_RS_SSIRXI0 = 0x0E2, /* SSIF0 (RX) */
dkato 0:702bf7b2b7d8 150 DMA_RS_SSITXI1 = 0x0E5, /* SSIF1 (TX) */
dkato 0:702bf7b2b7d8 151 DMA_RS_SSIRXI1 = 0x0E6, /* SSIF1 (RX) */
dkato 0:702bf7b2b7d8 152 DMA_RS_SSIRTI2 = 0x0EB, /* SSIF2 (TX) */
dkato 0:702bf7b2b7d8 153 DMA_RS_SSITXI3 = 0x0ED, /* SSIF2 (RTX) */
dkato 0:702bf7b2b7d8 154 DMA_RS_SSIRXI3 = 0x0EE, /* SSIF3 (TX) */
dkato 0:702bf7b2b7d8 155 DMA_RS_SSIRTI4 = 0x0F3, /* SSIF4 (RTX) */
dkato 0:702bf7b2b7d8 156 DMA_RS_SSITXI5 = 0x0F5, /* SSIF5 (TX) */
dkato 0:702bf7b2b7d8 157 DMA_RS_SSIRXI5 = 0x0F6, /* SSIF5 (RX) */
dkato 0:702bf7b2b7d8 158 DMA_RS_SCUTXI0 = 0x101, /* SCUX (FFD0) */
dkato 0:702bf7b2b7d8 159 DMA_RS_SCURXI0 = 0x102, /* SCUX (FFU0) */
dkato 0:702bf7b2b7d8 160 DMA_RS_SCUTXI1 = 0x105, /* SCUX (FFD1) */
dkato 0:702bf7b2b7d8 161 DMA_RS_SCURXI1 = 0x106, /* SCUX (FFU1) */
dkato 0:702bf7b2b7d8 162 DMA_RS_SCUTXI2 = 0x109, /* SCUX (FFD2) */
dkato 0:702bf7b2b7d8 163 DMA_RS_SCURXI2 = 0x10A, /* SCUX (FFU2) */
dkato 0:702bf7b2b7d8 164 DMA_RS_SCUTXI3 = 0x10D, /* SCUX (FFD3) */
dkato 0:702bf7b2b7d8 165 DMA_RS_SCURXI3 = 0x10E, /* SCUX (FFU3) */
dkato 0:702bf7b2b7d8 166 DMA_RS_SPTI0 = 0x121, /* SPI0 (TX) */
dkato 0:702bf7b2b7d8 167 DMA_RS_SPRI0 = 0x122, /* SPI0 (RX) */
dkato 0:702bf7b2b7d8 168 DMA_RS_SPTI1 = 0x125, /* SPI1 (TX) */
dkato 0:702bf7b2b7d8 169 DMA_RS_SPRI1 = 0x126, /* SPI1 (RX) */
dkato 0:702bf7b2b7d8 170 DMA_RS_SPTI2 = 0x129, /* SPI2 (TX) */
dkato 0:702bf7b2b7d8 171 DMA_RS_SPRI2 = 0x12A, /* SPI2 (RX) */
dkato 0:702bf7b2b7d8 172 DMA_RS_SPTI3 = 0x12B, /* SPI3 (TX) */
dkato 0:702bf7b2b7d8 173 DMA_RS_SPRI3 = 0x12E, /* SPI3 (RX) */
dkato 0:702bf7b2b7d8 174 DMA_RS_SPTI4 = 0x131, /* SPI4 (TX) */
dkato 0:702bf7b2b7d8 175 DMA_RS_SPRI4 = 0x132, /* SPI4 (RX) */
dkato 0:702bf7b2b7d8 176 DMA_RS_SPDIFTXI = 0x141, /* SPDIF (TX) */
dkato 0:702bf7b2b7d8 177 DMA_RS_SPDIFRXI = 0x142, /* SPDIF (RX) */
dkato 0:702bf7b2b7d8 178 DMA_RS_CMI1 = 0x147, /* Motor Control PWM Timer ch1 */
dkato 0:702bf7b2b7d8 179 DMA_RS_CMI2 = 0x14B, /* Motor Control PWM Timer ch2 */
dkato 0:702bf7b2b7d8 180 DMA_RS_MLBCI = 0x14F, /* Media Local Bus */
dkato 0:702bf7b2b7d8 181 DMA_RS_SGDEI0 = 0x153, /* Sound Generator0 */
dkato 0:702bf7b2b7d8 182 DMA_RS_SGDEI1 = 0x157, /* Sound Generator1 */
dkato 0:702bf7b2b7d8 183 DMA_RS_SGDEI2 = 0x15B, /* Sound Generator2 */
dkato 0:702bf7b2b7d8 184 DMA_RS_SGDEI3 = 0x15F, /* Sound Generator3 */
dkato 0:702bf7b2b7d8 185 DMA_RS_SCITXI0 = 0x169, /* Serial Communication Interface ch0 (TX) */
dkato 0:702bf7b2b7d8 186 DMA_RS_SCIRXI0 = 0x16A, /* Serial Communication Interface ch0 (RX) */
dkato 0:702bf7b2b7d8 187 DMA_RS_SCITXI1 = 0x16D, /* Serial Communication Interface ch1 (TX) */
dkato 0:702bf7b2b7d8 188 DMA_RS_SCIRXI1 = 0x16E, /* Serial Communication Interface ch1 (RX) */
dkato 0:702bf7b2b7d8 189 DMA_RS_TI0 = 0x181, /* IIC ch0 (TX) */
dkato 0:702bf7b2b7d8 190 DMA_RS_RI0 = 0x182, /* IIC ch0 (RX) */
dkato 0:702bf7b2b7d8 191 DMA_RS_TI1 = 0x185, /* IIC ch1 (TX) */
dkato 0:702bf7b2b7d8 192 DMA_RS_RI1 = 0x186, /* IIC ch1 (RX) */
dkato 0:702bf7b2b7d8 193 DMA_RS_TI2 = 0x189, /* IIC ch2 (TX) */
dkato 0:702bf7b2b7d8 194 DMA_RS_RI2 = 0x18A, /* IIC ch2 (RX) */
dkato 0:702bf7b2b7d8 195 DMA_RS_TI3 = 0x18D, /* IIC ch3 (TX) */
dkato 0:702bf7b2b7d8 196 DMA_RS_RI3 = 0x18E, /* IIC ch3 (RX) */
dkato 0:702bf7b2b7d8 197 DMA_RS_LIN0_INT_T = 0x1A1, /* LIN0 (TX) */
dkato 0:702bf7b2b7d8 198 DMA_RS_LIN0_INT_R = 0x1A2, /* LIN0 (RX) */
dkato 0:702bf7b2b7d8 199 DMA_RS_LIN1_INT_T = 0x1A5, /* LIN1 (TX) */
dkato 0:702bf7b2b7d8 200 DMA_RS_LIN1_INT_R = 0x1A6, /* LIN1 (RX) */
dkato 0:702bf7b2b7d8 201 DMA_RS_IFEI0 = 0x1B1, /* Pixel Format Converter ch0 (TX) */
dkato 0:702bf7b2b7d8 202 DMA_RS_OFFI0 = 0x1B2, /* Pixel Format Converter ch0 (TX) */
dkato 0:702bf7b2b7d8 203 DMA_RS_IFEI1 = 0x1B5, /* Pixel Format Converter ch1 (RX) */
dkato 0:702bf7b2b7d8 204 DMA_RS_OFFI1 = 0x1B6 /* Pixel Format Converter ch1 (TX) */
dkato 0:702bf7b2b7d8 205 } dma_res_select_t;
dkato 0:702bf7b2b7d8 206
dkato 0:702bf7b2b7d8 207 /* DMA transfer direction */
dkato 0:702bf7b2b7d8 208 typedef enum
dkato 0:702bf7b2b7d8 209 {
dkato 0:702bf7b2b7d8 210 DMA_REQ_MIN =(-1),
dkato 0:702bf7b2b7d8 211 DMA_REQ_SRC = 0, /* Read DMA */
dkato 0:702bf7b2b7d8 212 DMA_REQ_DES = 1, /* Write DMA */
dkato 0:702bf7b2b7d8 213 DMA_REQ_MAX = 2
dkato 0:702bf7b2b7d8 214 } dma_req_dir_t;
dkato 0:702bf7b2b7d8 215
dkato 0:702bf7b2b7d8 216 /* Address count direction */
dkato 0:702bf7b2b7d8 217 typedef enum
dkato 0:702bf7b2b7d8 218 {
dkato 0:702bf7b2b7d8 219 DMA_ADDR_MIN = (-1),
dkato 0:702bf7b2b7d8 220 DMA_ADDR_INCREMENT = 0, /* Address Count Increment */
dkato 0:702bf7b2b7d8 221 DMA_ADDR_FIX = 1, /* Address Count Fix */
dkato 0:702bf7b2b7d8 222 DMA_ADDR_MAX = 2
dkato 0:702bf7b2b7d8 223 } dma_addr_cnt_t;
dkato 0:702bf7b2b7d8 224
dkato 0:702bf7b2b7d8 225
dkato 0:702bf7b2b7d8 226 /*************************************************************************
dkato 0:702bf7b2b7d8 227 Structures
dkato 0:702bf7b2b7d8 228 *************************************************************************/
dkato 0:702bf7b2b7d8 229
dkato 0:702bf7b2b7d8 230 /* DMA Init Parameter */
dkato 0:702bf7b2b7d8 231 typedef struct
dkato 0:702bf7b2b7d8 232 {
dkato 0:702bf7b2b7d8 233 bool_t channel[DMA_CH_NUM]; /* Set enable channel */
dkato 0:702bf7b2b7d8 234 AIOCB *p_aio; /* set callback function (DMA error interrupt) */
dkato 0:702bf7b2b7d8 235 }dma_drv_init_t;
dkato 0:702bf7b2b7d8 236
dkato 0:702bf7b2b7d8 237 /* DMA Setup Parameter */
dkato 0:702bf7b2b7d8 238 typedef struct
dkato 0:702bf7b2b7d8 239 {
dkato 0:702bf7b2b7d8 240 dma_res_select_t resource; /* DMA Transfer Resource */
dkato 0:702bf7b2b7d8 241 dma_req_dir_t direction; /* DMA Transfer Direction */
dkato 0:702bf7b2b7d8 242 dma_unit_size_t dst_width; /* DMA Transfer Unit Size (Destination) */
dkato 0:702bf7b2b7d8 243 dma_unit_size_t src_width; /* DMA Transfer Unit Size (Source) */
dkato 0:702bf7b2b7d8 244 dma_addr_cnt_t dst_cnt; /* DMA Address Count (Destination) */
dkato 0:702bf7b2b7d8 245 dma_addr_cnt_t src_cnt; /* DMA Address Count (Source) */
dkato 0:702bf7b2b7d8 246 AIOCB *p_aio; /* set callback function (DMA end interrupt) */
dkato 0:702bf7b2b7d8 247 } dma_ch_setup_t;
dkato 0:702bf7b2b7d8 248
dkato 0:702bf7b2b7d8 249 /* DMA Transfer Paramter */
dkato 0:702bf7b2b7d8 250 typedef struct
dkato 0:702bf7b2b7d8 251 {
dkato 0:702bf7b2b7d8 252 void *src_addr; /* Sorce Address */
dkato 0:702bf7b2b7d8 253 void *dst_addr; /* Destination Address */
dkato 0:702bf7b2b7d8 254 uint32_t count; /* DMA Transfer Size */
dkato 0:702bf7b2b7d8 255 } dma_trans_data_t;
dkato 0:702bf7b2b7d8 256
dkato 0:702bf7b2b7d8 257 /***********************************************************************************
dkato 0:702bf7b2b7d8 258 Function Prototypes
dkato 0:702bf7b2b7d8 259 ***********************************************************************************/
dkato 0:702bf7b2b7d8 260
dkato 0:702bf7b2b7d8 261 /***********************************************************************************
dkato 0:702bf7b2b7d8 262 * ingroup API
dkato 0:702bf7b2b7d8 263 * This function initializes the driver and must be called at system start
dkato 0:702bf7b2b7d8 264 * up, prior to any required DMA functionality being available. This function
dkato 0:702bf7b2b7d8 265 * also sets the enable or disable for each DMA channel and DMA error call back
dkato 0:702bf7b2b7d8 266 * function.
dkato 0:702bf7b2b7d8 267 *
dkato 0:702bf7b2b7d8 268 * param [in] p_dma_init_param - parameter of ch enable and DMA error callback function.
dkato 0:702bf7b2b7d8 269 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 270 *
dkato 0:702bf7b2b7d8 271 * retval ESUCCESS - successfully initialized.
dkato 0:702bf7b2b7d8 272 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 273 ***********************************************************************************/
dkato 0:702bf7b2b7d8 274
dkato 0:702bf7b2b7d8 275 extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno);
dkato 0:702bf7b2b7d8 276
dkato 0:702bf7b2b7d8 277 /***********************************************************************************
dkato 0:702bf7b2b7d8 278 * ingroup API
dkato 0:702bf7b2b7d8 279 * This function shutdown the driver, making DMA functionality is no longer available.
dkato 0:702bf7b2b7d8 280 * It can be carried out only in calse of all channel free.
dkato 0:702bf7b2b7d8 281 *
dkato 0:702bf7b2b7d8 282 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 283 *
dkato 0:702bf7b2b7d8 284 * retval ESUCCESS - successfully uninitialized.
dkato 0:702bf7b2b7d8 285 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 286 ***********************************************************************************/
dkato 0:702bf7b2b7d8 287
dkato 0:702bf7b2b7d8 288 extern int_t R_DMA_UnInit(int32_t * const p_errno);
dkato 0:702bf7b2b7d8 289
dkato 0:702bf7b2b7d8 290 /***********************************************************************************
dkato 0:702bf7b2b7d8 291 * ingroup API
dkato 0:702bf7b2b7d8 292 * This function allocates a DMA channel.
dkato 0:702bf7b2b7d8 293 * When channel is (-1), it looking for a free channel
dkato 0:702bf7b2b7d8 294 * When set channel to DMA channel number, a set channel is allocated
dkato 0:702bf7b2b7d8 295 *
dkato 0:702bf7b2b7d8 296 * param [in] channel - allocate channel. (when channel is (-1), it looking for a
dkato 0:702bf7b2b7d8 297 * free channel.)
dkato 0:702bf7b2b7d8 298 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 299 *
dkato 0:702bf7b2b7d8 300 * retval channel number - successfully allocated.
dkato 0:702bf7b2b7d8 301 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 302 ***********************************************************************************/
dkato 0:702bf7b2b7d8 303
dkato 0:702bf7b2b7d8 304 extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno);
dkato 0:702bf7b2b7d8 305
dkato 0:702bf7b2b7d8 306 /***********************************************************************************
dkato 0:702bf7b2b7d8 307 * ingroup API
dkato 0:702bf7b2b7d8 308 * This function close a DMA channel.
dkato 0:702bf7b2b7d8 309 *
dkato 0:702bf7b2b7d8 310 * param [in] channel - close channel.
dkato 0:702bf7b2b7d8 311 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 312 *
dkato 0:702bf7b2b7d8 313 * retval ESUCCESS - successfully allocate.
dkato 0:702bf7b2b7d8 314 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 315 ***********************************************************************************/
dkato 0:702bf7b2b7d8 316
dkato 0:702bf7b2b7d8 317 extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno);
dkato 0:702bf7b2b7d8 318
dkato 0:702bf7b2b7d8 319 /***********************************************************************************
dkato 0:702bf7b2b7d8 320 * ingroup API
dkato 0:702bf7b2b7d8 321 * This function set up a DMA transfer parameter.
dkato 0:702bf7b2b7d8 322 * before calling R_DMA_Start(), please carry out this function.
dkato 0:702bf7b2b7d8 323 *
dkato 0:702bf7b2b7d8 324 * param [in] channel - set up channel.
dkato 0:702bf7b2b7d8 325 * param [in] p_ch_setup - DMA transfer parameters.
dkato 0:702bf7b2b7d8 326 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 327 *
dkato 0:702bf7b2b7d8 328 * retval ESUCCESS - successfully setup.
dkato 0:702bf7b2b7d8 329 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 330 ***********************************************************************************/
dkato 0:702bf7b2b7d8 331
dkato 0:702bf7b2b7d8 332 extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
dkato 0:702bf7b2b7d8 333 int32_t * const p_errno);
dkato 0:702bf7b2b7d8 334
dkato 0:702bf7b2b7d8 335 /***********************************************************************************
dkato 0:702bf7b2b7d8 336 * ingroup API
dkato 0:702bf7b2b7d8 337 * This function set up a DMA transfer address and start DMA.
dkato 0:702bf7b2b7d8 338 *
dkato 0:702bf7b2b7d8 339 * param [in] channel - DMA start channel.
dkato 0:702bf7b2b7d8 340 * param [in] p_ch_setup - DMA address parameters.
dkato 0:702bf7b2b7d8 341 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 342 *
dkato 0:702bf7b2b7d8 343 * retval ESUCCESS - successfully DMA start.
dkato 0:702bf7b2b7d8 344 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 345 ***********************************************************************************/
dkato 0:702bf7b2b7d8 346
dkato 0:702bf7b2b7d8 347 extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 348 int32_t * const p_errno);
dkato 0:702bf7b2b7d8 349
dkato 0:702bf7b2b7d8 350 /***********************************************************************************
dkato 0:702bf7b2b7d8 351 * ingroup API
dkato 0:702bf7b2b7d8 352 * This function set up a continous DMA transfer address and start continuous DMA.
dkato 0:702bf7b2b7d8 353 *
dkato 0:702bf7b2b7d8 354 * param [in] channel - continuous DMA start channel.
dkato 0:702bf7b2b7d8 355 * param [in] p_ch_setup - continuous DMA address parameters.
dkato 0:702bf7b2b7d8 356 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 357 *
dkato 0:702bf7b2b7d8 358 * retval ESUCCESS - successfully continuous DMA start.
dkato 0:702bf7b2b7d8 359 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 360 ***********************************************************************************/
dkato 0:702bf7b2b7d8 361
dkato 0:702bf7b2b7d8 362 extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 363 int32_t * const p_errno);
dkato 0:702bf7b2b7d8 364
dkato 0:702bf7b2b7d8 365 /***********************************************************************************
dkato 0:702bf7b2b7d8 366 * ingroup API
dkato 0:702bf7b2b7d8 367 * This function cancel DMA transfer.
dkato 0:702bf7b2b7d8 368 * Continous DMA also stops at the same time.
dkato 0:702bf7b2b7d8 369 * Please call this function during DMA transfer.
dkato 0:702bf7b2b7d8 370 *
dkato 0:702bf7b2b7d8 371 * param [in] channel - chancel DMA start channel.
dkato 0:702bf7b2b7d8 372 * param [out] p_remain - remain sizei of DMA transfer.
dkato 0:702bf7b2b7d8 373 * param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
dkato 0:702bf7b2b7d8 374 *
dkato 0:702bf7b2b7d8 375 * retval ESUCCESS - successfully cancel.
dkato 0:702bf7b2b7d8 376 * retval -1 - error occured.
dkato 0:702bf7b2b7d8 377 ***********************************************************************************/
dkato 0:702bf7b2b7d8 378
dkato 0:702bf7b2b7d8 379 extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno);
dkato 0:702bf7b2b7d8 380
dkato 0:702bf7b2b7d8 381
dkato 0:702bf7b2b7d8 382 /***********************************************************************************
dkato 0:702bf7b2b7d8 383 * ingroup API
dkato 0:702bf7b2b7d8 384 * This function get DMA driver version.
dkato 0:702bf7b2b7d8 385 *
dkato 0:702bf7b2b7d8 386 * param none
dkato 0:702bf7b2b7d8 387 *
dkato 0:702bf7b2b7d8 388 * retval driver version
dkato 0:702bf7b2b7d8 389 ***********************************************************************************/
dkato 0:702bf7b2b7d8 390
dkato 0:702bf7b2b7d8 391 extern uint16_t R_DMA_GetVersion(void);
dkato 0:702bf7b2b7d8 392
dkato 0:702bf7b2b7d8 393 #ifdef __cplusplus
dkato 0:702bf7b2b7d8 394 }
dkato 0:702bf7b2b7d8 395 #endif /* __cplusplus */
dkato 0:702bf7b2b7d8 396
dkato 0:702bf7b2b7d8 397 #endif /* DMA_IF_H */