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RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

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Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program
R_BSP_SSIF_HelloWorld - main.cpp

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library
R_BSP - R_BSP_Ssif Class Reference

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details

SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program
R_BSP_SCUX_HelloWorld - main.cpp

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 }

API

Import library
R_BSP - R_BSP_Scux Class Reference

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

RenesasBSP/drv_inc/dma_if.h

Committer:
dkato
Date:
2015-06-01
Revision:
0:702bf7b2b7d8

File content as of revision 0:702bf7b2b7d8:

/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/

/**************************************************************************//**
* @file         dma_if.h
* $Rev: 1318 $
* $Date:: 2014-12-04 10:45:12 +0900#$
* @brief        DMA Driver interface headers
******************************************************************************/

/*****************************************************************************
* History : DD.MM.YYYY Version Description
* : 15.01.2013 1.00 First Release
******************************************************************************/

#ifndef DMA_IF_H
#define DMA_IF_H

/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/

#include "cmsis_os.h"
#include "r_errno.h"
#include "r_typedefs.h"
#include "ioif_aio.h"


#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */


/*************************************************************************
 User Includes
*************************************************************************/

/*************************************************************************
 Defines
*************************************************************************/

/* for searching free channel */
#define DMA_ALLOC_CH  (-1)

/*************************************************************************
 Enumerated Types
*************************************************************************/

/* Number od DMA channel */
typedef enum
{
    DMA_CH_0 = 0,
    DMA_CH_1 = 1,
    DMA_CH_2 = 2,
    DMA_CH_3 = 3,
    DMA_CH_4 = 4,
    DMA_CH_5 = 5,
    DMA_CH_6 = 6,
    DMA_CH_7 = 7,
    DMA_CH_8 = 8,
    DMA_CH_9 = 9,
    DMA_CH_10 = 10,
    DMA_CH_11 = 11,
    DMA_CH_12 = 12,
    DMA_CH_13 = 13,
    DMA_CH_14 = 14,
    DMA_CH_15 = 15,
    DMA_CH_NUM = 16  /* Number of DMA channel */
} dma_ch_num_t;

/* Unit Size of DMA transfer */
typedef enum
{
    DMA_UNIT_MIN =(-1),
    DMA_UNIT_1 = 0,   /* Unit Size of DMA transfer = 1byte */
    DMA_UNIT_2 = 1,   /* Unit Size of DMA transfer = 2byte */
    DMA_UNIT_4 = 2,   /* Unit Size of DMA transfer = 4byte */
    DMA_UNIT_8 = 3,   /* Unit Size of DMA transfer = 8byte */
    DMA_UNIT_16 = 4,  /* Unit Size of DMA transfer = 16byte */
    DMA_UNIT_32 = 5,  /* Unit Size of DMA transfer = 32byte */
    DMA_UNIT_64 = 6,  /* Unit Size of DMA transfer = 64byte */
    DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */
    DMA_UNIT_MAX = 8
} dma_unit_size_t;

/* DMA transfer resource */
typedef enum
{
    DMA_RS_OSTIM0     = 0x023,   /* OS Timer ch0 */
    DMA_RS_OSTIM1     = 0x027,   /* OS Timer ch1 */
    DMA_RS_TGI0A      = 0x043,   /* Multi Function Timer Pulse Unit2 ch0 */
    DMA_RS_TGI1A      = 0x047,   /* Multi Function Timer Pulse Unit2 ch1  */
    DMA_RS_TGI2A      = 0x04B,   /* Multi Function Timer Pulse Unit2 ch2  */
    DMA_RS_TGI3A      = 0x04F,   /* Multi Function Timer Pulse Unit2 ch3  */
    DMA_RS_TGI4A      = 0x053,   /* Multi Function Timer Pulse Unit2 ch4  */
    DMA_RS_TXI0       = 0x061,   /* FIFO Serial Communication Interface ch0 (TX) */
    DMA_RS_RXI0       = 0x062,   /* FIFO Serial Communication Interface ch0 (RX) */
    DMA_RS_TXI1       = 0x065,   /* FIFO Serial Communication Interface ch1 (TX) */
    DMA_RS_RXI1       = 0x066,   /* FIFO Serial Communication Interface ch1 (RX) */
    DMA_RS_TXI2       = 0x069,   /* FIFO Serial Communication Interface ch2 (TX) */
    DMA_RS_RXI2       = 0x06A,   /* FIFO Serial Communication Interface ch2 (RX) */
    DMA_RS_TXI3       = 0x06D,   /* FIFO Serial Communication Interface ch3 (TX) */
    DMA_RS_RXI3       = 0x06E,   /* FIFO Serial Communication Interface ch3 (RX) */
    DMA_RS_TXI4       = 0x071,   /* FIFO Serial Communication Interface ch4 (TX) */
    DMA_RS_RXI4       = 0x072,   /* FIFO Serial Communication Interface ch4 (RX) */
    DMA_RS_TXI5       = 0x075,   /* FIFO Serial Communication Interface ch5 (TX) */
    DMA_RS_RXI5       = 0x076,   /* FIFO Serial Communication Interface ch5 (RX) */
    DMA_RS_TXI6       = 0x079,   /* FIFO Serial Communication Interface ch6 (TX) */
    DMA_RS_RXI6       = 0x07A,   /* FIFO Serial Communication Interface ch6 (RX) */
    DMA_RS_TXI7       = 0x07D,   /* FIFO Serial Communication Interface ch7 (TX) */
    DMA_RS_RXI7       = 0x07E,   /* FIFO Serial Communication Interface ch7 (RX) */
    DMA_RS_USB0_DMA0  = 0x083,   /* USB Module0 ch0 */
    DMA_RS_USB0_DMA1  = 0x087,   /* USB Module0 ch1 */
    DMA_RS_USB1_DMA0  = 0x08B,   /* USB Module1 ch0 */
    DMA_RS_USB1_DMA1  = 0x08F,   /* USB Module1 ch1 */
    DMA_RS_ADEND      = 0x093,   /* A/D Converter */
    DMA_RS_IEBBTD     = 0x0A3,   /* IEBus Controller (Data interrupt) */
    DMA_RS_IEBBTV     = 0x0A7,   /* IEBus Controller (Vector interrupt) */
    DMA_RS_IREADY     = 0x0AB,   /* CD-Rom Decoder */
    DMA_RS_FLDT       = 0x0B3,   /* NAND Memory Controller (Data) */
    DMA_RS_SDHI_0T    = 0x0C1,   /* SD Host Interface0 (TX) */
    DMA_RS_SDHI_0R    = 0x0C2,   /* SD Host Interface0 (RX) */
    DMA_RS_SDHI_1T    = 0x0C5,   /* SD Host Interface1 (RX) */
    DMA_RS_SDHI_1R    = 0x0C6,   /* SD Host Interface1 (TX) */
    DMA_RS_MMCT       = 0x0C9,   /* MMC Host Interface (TX) */
    DMA_RS_MMCR       = 0x0CA,   /* MMC Host Interface (RX) */
    DMA_RS_SSITXI0    = 0x0E1,   /* SSIF0 (TX) */
    DMA_RS_SSIRXI0    = 0x0E2,   /* SSIF0 (RX) */
    DMA_RS_SSITXI1    = 0x0E5,   /* SSIF1 (TX) */
    DMA_RS_SSIRXI1    = 0x0E6,   /* SSIF1 (RX) */
    DMA_RS_SSIRTI2    = 0x0EB,   /* SSIF2 (TX) */
    DMA_RS_SSITXI3    = 0x0ED,   /* SSIF2 (RTX) */
    DMA_RS_SSIRXI3    = 0x0EE,   /* SSIF3 (TX) */
    DMA_RS_SSIRTI4    = 0x0F3,   /* SSIF4 (RTX) */
    DMA_RS_SSITXI5    = 0x0F5,   /* SSIF5 (TX) */
    DMA_RS_SSIRXI5    = 0x0F6,   /* SSIF5 (RX) */
    DMA_RS_SCUTXI0    = 0x101,   /* SCUX (FFD0) */
    DMA_RS_SCURXI0    = 0x102,   /* SCUX (FFU0) */
    DMA_RS_SCUTXI1    = 0x105,   /* SCUX (FFD1) */
    DMA_RS_SCURXI1    = 0x106,   /* SCUX (FFU1) */
    DMA_RS_SCUTXI2    = 0x109,   /* SCUX (FFD2) */
    DMA_RS_SCURXI2    = 0x10A,   /* SCUX (FFU2) */
    DMA_RS_SCUTXI3    = 0x10D,   /* SCUX (FFD3) */
    DMA_RS_SCURXI3    = 0x10E,   /* SCUX (FFU3) */
    DMA_RS_SPTI0      = 0x121,   /* SPI0 (TX) */
    DMA_RS_SPRI0      = 0x122,   /* SPI0 (RX) */
    DMA_RS_SPTI1      = 0x125,   /* SPI1 (TX) */
    DMA_RS_SPRI1      = 0x126,   /* SPI1 (RX) */
    DMA_RS_SPTI2      = 0x129,   /* SPI2 (TX) */
    DMA_RS_SPRI2      = 0x12A,   /* SPI2 (RX) */
    DMA_RS_SPTI3      = 0x12B,   /* SPI3 (TX) */
    DMA_RS_SPRI3      = 0x12E,   /* SPI3 (RX) */
    DMA_RS_SPTI4      = 0x131,   /* SPI4 (TX) */
    DMA_RS_SPRI4      = 0x132,   /* SPI4 (RX) */
    DMA_RS_SPDIFTXI   = 0x141,   /* SPDIF (TX) */
    DMA_RS_SPDIFRXI   = 0x142,   /* SPDIF (RX) */
    DMA_RS_CMI1       = 0x147,   /* Motor Control PWM Timer ch1 */
    DMA_RS_CMI2       = 0x14B,   /* Motor Control PWM Timer ch2 */
    DMA_RS_MLBCI      = 0x14F,   /* Media Local Bus */
    DMA_RS_SGDEI0     = 0x153,   /* Sound Generator0 */
    DMA_RS_SGDEI1     = 0x157,   /* Sound Generator1 */
    DMA_RS_SGDEI2     = 0x15B,   /* Sound Generator2 */
    DMA_RS_SGDEI3     = 0x15F,   /* Sound Generator3 */
    DMA_RS_SCITXI0    = 0x169,   /* Serial Communication Interface ch0 (TX) */
    DMA_RS_SCIRXI0    = 0x16A,   /* Serial Communication Interface ch0 (RX) */
    DMA_RS_SCITXI1    = 0x16D,   /* Serial Communication Interface ch1 (TX) */
    DMA_RS_SCIRXI1    = 0x16E,   /* Serial Communication Interface ch1 (RX) */
    DMA_RS_TI0        = 0x181,   /* IIC ch0 (TX) */
    DMA_RS_RI0        = 0x182,   /* IIC ch0 (RX) */
    DMA_RS_TI1        = 0x185,   /* IIC ch1 (TX) */
    DMA_RS_RI1        = 0x186,   /* IIC ch1 (RX) */
    DMA_RS_TI2        = 0x189,   /* IIC ch2 (TX) */
    DMA_RS_RI2        = 0x18A,   /* IIC ch2 (RX) */
    DMA_RS_TI3        = 0x18D,   /* IIC ch3 (TX) */
    DMA_RS_RI3        = 0x18E,   /* IIC ch3 (RX) */
    DMA_RS_LIN0_INT_T = 0x1A1,   /* LIN0 (TX) */
    DMA_RS_LIN0_INT_R = 0x1A2,   /* LIN0 (RX) */
    DMA_RS_LIN1_INT_T = 0x1A5,   /* LIN1 (TX) */
    DMA_RS_LIN1_INT_R = 0x1A6,   /* LIN1 (RX) */
    DMA_RS_IFEI0      = 0x1B1,   /* Pixel Format Converter ch0 (TX) */
    DMA_RS_OFFI0      = 0x1B2,   /* Pixel Format Converter ch0 (TX) */
    DMA_RS_IFEI1      = 0x1B5,   /* Pixel Format Converter ch1 (RX) */
    DMA_RS_OFFI1      = 0x1B6    /* Pixel Format Converter ch1 (TX) */
} dma_res_select_t;

/* DMA transfer direction */
typedef enum
{
    DMA_REQ_MIN =(-1),
    DMA_REQ_SRC = 0, /* Read DMA */
    DMA_REQ_DES = 1, /* Write DMA */
    DMA_REQ_MAX = 2
} dma_req_dir_t;

/* Address count direction */
typedef enum
{
    DMA_ADDR_MIN = (-1),
    DMA_ADDR_INCREMENT = 0, /* Address Count Increment */
    DMA_ADDR_FIX = 1,       /* Address Count Fix */
    DMA_ADDR_MAX = 2
} dma_addr_cnt_t;


/*************************************************************************
 Structures
*************************************************************************/

/* DMA Init Parameter */
typedef struct
{
    bool_t   channel[DMA_CH_NUM]; /* Set enable channel */
    AIOCB    *p_aio;              /* set callback function (DMA error interrupt) */
}dma_drv_init_t;

/* DMA Setup Parameter */
typedef struct
{
    dma_res_select_t   resource;     /* DMA Transfer Resource */
    dma_req_dir_t      direction;    /* DMA Transfer Direction */
    dma_unit_size_t    dst_width;    /* DMA Transfer Unit Size (Destination) */
    dma_unit_size_t    src_width;    /* DMA Transfer Unit Size (Source) */
    dma_addr_cnt_t     dst_cnt;      /* DMA Address Count (Destination) */
    dma_addr_cnt_t     src_cnt;      /* DMA Address Count (Source) */
    AIOCB              *p_aio;       /* set callback function (DMA end interrupt) */
} dma_ch_setup_t;

/* DMA Transfer Paramter */
typedef struct
{
    void       *src_addr;    /* Sorce Address */
    void       *dst_addr;    /* Destination Address */
    uint32_t   count;        /* DMA Transfer Size */
} dma_trans_data_t;

/***********************************************************************************
 Function Prototypes
***********************************************************************************/

/***********************************************************************************
* ingroup API
* This function initializes the driver and must be called at system start
* up, prior to any required DMA functionality being available. This function
* also sets the enable or disable for each DMA channel and DMA error call back 
* function.
*
* param [in] p_dma_init_param - parameter of ch enable and DMA error callback function.
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully initialized.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno);

/***********************************************************************************
* ingroup API
* This function shutdown the driver, making DMA functionality is no longer available.
* It can be carried out only in calse of all channel free.
*
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully uninitialized.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_UnInit(int32_t * const p_errno);

/***********************************************************************************
* ingroup API
* This function allocates a DMA channel.
* When channel is (-1), it looking for a free channel
* When set channel to DMA channel number, a set channel is allocated
*
* param [in] channel     - allocate channel. (when channel is (-1), it looking for a 
*                           free channel.)
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval channel number - successfully allocated.
* retval -1             - error occured.
***********************************************************************************/

extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno);

/***********************************************************************************
* ingroup API
* This function close a DMA channel.
*
* param [in] channel     - close channel.
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully allocate.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno);

/***********************************************************************************
* ingroup API
* This function set up a DMA transfer parameter.
* before calling R_DMA_Start(), please carry out this function.
*
* param [in] channel     - set up channel.
* param [in] p_ch_setup  - DMA transfer parameters.
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully setup.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 
                         int32_t * const p_errno);

/***********************************************************************************
* ingroup API
* This function set up a DMA transfer address and start DMA.
*
* param [in] channel     - DMA start channel.
* param [in] p_ch_setup  - DMA address parameters.
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully DMA start.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 
                         int32_t * const p_errno);

/***********************************************************************************
* ingroup API
* This function set up a continous DMA transfer address and start continuous DMA.
*
* param [in] channel     - continuous DMA start channel.
* param [in] p_ch_setup  - continuous DMA address parameters.
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully continuous DMA start.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
                            int32_t * const p_errno);
                            
/***********************************************************************************
* ingroup API
* This function cancel DMA transfer.
* Continous DMA also stops at the same time.
* Please call this function during DMA transfer.
*
* param [in] channel     - chancel DMA start channel.
* param [out] p_remain   - remain sizei of DMA transfer.
* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
*
* retval ESUCCESS - successfully cancel.
* retval -1       - error occured.
***********************************************************************************/

extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno);


/***********************************************************************************
* ingroup API
* This function get DMA driver version.
*
* param none
*
* retval driver version
***********************************************************************************/

extern uint16_t R_DMA_GetVersion(void);

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* DMA_IF_H */