RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Mon Apr 18 08:15:32 2016 +0000
Revision:
10:c5c630882b90
Parent:
7:30ebba78fff0
Supports IAR.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 6:aa1fc6a5cc2a 1 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 2 * DISCLAIMER
dkato 6:aa1fc6a5cc2a 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 6:aa1fc6a5cc2a 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 6:aa1fc6a5cc2a 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 6:aa1fc6a5cc2a 6 * all applicable laws, including copyright laws.
dkato 6:aa1fc6a5cc2a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 6:aa1fc6a5cc2a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 6:aa1fc6a5cc2a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 6:aa1fc6a5cc2a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 6:aa1fc6a5cc2a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 6:aa1fc6a5cc2a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 6:aa1fc6a5cc2a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 6:aa1fc6a5cc2a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 6:aa1fc6a5cc2a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 6:aa1fc6a5cc2a 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 6:aa1fc6a5cc2a 17 * and to discontinue the availability of this software. By using this software,
dkato 6:aa1fc6a5cc2a 18 * you agree to the additional terms and conditions found by accessing the
dkato 6:aa1fc6a5cc2a 19 * following link:
dkato 6:aa1fc6a5cc2a 20 * http://www.renesas.com/disclaimer
dkato 6:aa1fc6a5cc2a 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
dkato 6:aa1fc6a5cc2a 22 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 23
dkato 6:aa1fc6a5cc2a 24 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 25 * @file scux.c
dkato 6:aa1fc6a5cc2a 26 * $Rev: 1674 $
dkato 6:aa1fc6a5cc2a 27 * $Date:: 2015-05-29 16:35:57 +0900#$
dkato 6:aa1fc6a5cc2a 28 * @brief SCUX Driver functions
dkato 6:aa1fc6a5cc2a 29 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 30
dkato 6:aa1fc6a5cc2a 31 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 32 Includes <System Includes>, "Project Includes"
dkato 6:aa1fc6a5cc2a 33 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 34
dkato 6:aa1fc6a5cc2a 35 #include "scux.h"
dkato 6:aa1fc6a5cc2a 36
dkato 6:aa1fc6a5cc2a 37 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 38 /******************************************************************************
dkato 6:aa1fc6a5cc2a 39 Macro definitions
dkato 6:aa1fc6a5cc2a 40 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 41 #define INIT_WAIT_TIME_MSEC (1)
dkato 6:aa1fc6a5cc2a 42 #define INIT_WAIT_NUM (1000U)
dkato 6:aa1fc6a5cc2a 43
dkato 6:aa1fc6a5cc2a 44 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 45 /******************************************************************************
dkato 6:aa1fc6a5cc2a 46 Exported global variables (to be accessed by other files)
dkato 6:aa1fc6a5cc2a 47 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 48
dkato 6:aa1fc6a5cc2a 49 /* ->MISRA 8.8 This description is based on the way to fill out OS defined. */
dkato 6:aa1fc6a5cc2a 50 /* ->IPA M2.2.2, MISRA 8.10 This description is based on the way to fill out OS defined. */
dkato 6:aa1fc6a5cc2a 51 osSemaphoreDef(scux_ch0_access);
dkato 6:aa1fc6a5cc2a 52 osSemaphoreDef(scux_ch1_access);
dkato 6:aa1fc6a5cc2a 53 osSemaphoreDef(scux_ch2_access);
dkato 6:aa1fc6a5cc2a 54 osSemaphoreDef(scux_ch3_access);
dkato 6:aa1fc6a5cc2a 55
dkato 6:aa1fc6a5cc2a 56 osSemaphoreDef(scux_ssif_ch0_access);
dkato 6:aa1fc6a5cc2a 57 osSemaphoreDef(scux_ssif_ch1_access);
dkato 6:aa1fc6a5cc2a 58 osSemaphoreDef(scux_ssif_ch2_access);
dkato 6:aa1fc6a5cc2a 59 osSemaphoreDef(scux_ssif_ch3_access);
dkato 6:aa1fc6a5cc2a 60 osSemaphoreDef(scux_ssif_ch4_access);
dkato 6:aa1fc6a5cc2a 61 osSemaphoreDef(scux_ssif_ch5_access);
dkato 6:aa1fc6a5cc2a 62
dkato 6:aa1fc6a5cc2a 63 osSemaphoreDef(scux_shared_access);
dkato 6:aa1fc6a5cc2a 64 /* <-MISRA 8.10, IPA M2.2.2 */
dkato 6:aa1fc6a5cc2a 65 /* <-MISRA 8.8 */
dkato 6:aa1fc6a5cc2a 66
dkato 6:aa1fc6a5cc2a 67 /******************************************************************************
dkato 6:aa1fc6a5cc2a 68 Private global driver management information
dkato 6:aa1fc6a5cc2a 69 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 70
dkato 6:aa1fc6a5cc2a 71 /* driver management infrmation */
dkato 6:aa1fc6a5cc2a 72 static scux_info_drv_t gb_scux_info_drv = {
dkato 6:aa1fc6a5cc2a 73 SCUX_DRV_UNINIT,
dkato 6:aa1fc6a5cc2a 74 {
dkato 6:aa1fc6a5cc2a 75 {SCUX_CH_0, false, 0, SCUX_CH_UNINIT}, /* ch0 */
dkato 6:aa1fc6a5cc2a 76 {SCUX_CH_1, false, 0, SCUX_CH_UNINIT}, /* ch1 */
dkato 6:aa1fc6a5cc2a 77 {SCUX_CH_2, false, 0, SCUX_CH_UNINIT}, /* ch2 */
dkato 6:aa1fc6a5cc2a 78 {SCUX_CH_3, false, 0, SCUX_CH_UNINIT} /* ch3 */
dkato 6:aa1fc6a5cc2a 79 }
dkato 6:aa1fc6a5cc2a 80 };
dkato 6:aa1fc6a5cc2a 81
dkato 6:aa1fc6a5cc2a 82 /* SSIF management information */
dkato 6:aa1fc6a5cc2a 83 static scux_ssif_info_t gb_scux_ssif_info[SCUX_SSIF_CH_NUM];
dkato 6:aa1fc6a5cc2a 84
dkato 6:aa1fc6a5cc2a 85 /* ->MISRA 11.3, 11.4 11.5 This cast is needed for register access. */
dkato 6:aa1fc6a5cc2a 86 /* address table of register set for each SCUX channel */
dkato 6:aa1fc6a5cc2a 87 static scux_reg_info_t p_scux_ch_reg_addr_table[SCUX_CH_NUM] = {
dkato 6:aa1fc6a5cc2a 88 {
dkato 6:aa1fc6a5cc2a 89 &SCUX_FROM_DVUIR_DVU0_0,
dkato 6:aa1fc6a5cc2a 90 &SCUX_FROM_SRCIR0_2SRC0_0,
dkato 6:aa1fc6a5cc2a 91 &SCUX_FROM_FFUIR_FFU0_0,
dkato 6:aa1fc6a5cc2a 92 &SCUX_FROM_FFDIR_FFD0_0,
dkato 6:aa1fc6a5cc2a 93 &SCUX_FROM_OPCIR_OPC0_0,
dkato 6:aa1fc6a5cc2a 94 &SCUX_FROM_IPCIR_IPC0_0,
dkato 6:aa1fc6a5cc2a 95 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 96 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 97 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 98 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 99 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 100 &SCUXMDBAR_MIX0_0,
dkato 6:aa1fc6a5cc2a 101 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 102 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 103 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 104 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 105 &SCUXDMATD0_CIM,
dkato 6:aa1fc6a5cc2a 106 &SCUXDMATU0_CIM,
dkato 6:aa1fc6a5cc2a 107 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 108 &SCUXFDTSEL0_CIM,
dkato 6:aa1fc6a5cc2a 109 &SCUXFUTSEL0_CIM,
dkato 6:aa1fc6a5cc2a 110 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 111 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 112 &SCUXSRCRSEL0_CIM,
dkato 6:aa1fc6a5cc2a 113 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 114 },
dkato 6:aa1fc6a5cc2a 115 {
dkato 6:aa1fc6a5cc2a 116 &SCUX_FROM_DVUIR_DVU0_1,
dkato 6:aa1fc6a5cc2a 117 &SCUX_FROM_SRCIR0_2SRC0_0,
dkato 6:aa1fc6a5cc2a 118 &SCUX_FROM_FFUIR_FFU0_1,
dkato 6:aa1fc6a5cc2a 119 &SCUX_FROM_FFDIR_FFD0_1,
dkato 6:aa1fc6a5cc2a 120 &SCUX_FROM_OPCIR_OPC0_1,
dkato 6:aa1fc6a5cc2a 121 &SCUX_FROM_IPCIR_IPC0_1,
dkato 6:aa1fc6a5cc2a 122 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 123 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 124 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 125 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 126 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 127 &SCUXMDBBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 128 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 129 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 130 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 131 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 132 &SCUXDMATD1_CIM,
dkato 6:aa1fc6a5cc2a 133 &SCUXDMATU1_CIM,
dkato 6:aa1fc6a5cc2a 134 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 135 &SCUXFDTSEL1_CIM,
dkato 6:aa1fc6a5cc2a 136 &SCUXFUTSEL1_CIM,
dkato 6:aa1fc6a5cc2a 137 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 138 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 139 &SCUXSRCRSEL1_CIM,
dkato 6:aa1fc6a5cc2a 140 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 141 },
dkato 6:aa1fc6a5cc2a 142 {
dkato 6:aa1fc6a5cc2a 143 &SCUX_FROM_DVUIR_DVU0_2,
dkato 6:aa1fc6a5cc2a 144 &SCUX_FROM_SRCIR0_2SRC0_1,
dkato 6:aa1fc6a5cc2a 145 &SCUX_FROM_FFUIR_FFU0_2,
dkato 6:aa1fc6a5cc2a 146 &SCUX_FROM_FFDIR_FFD0_2,
dkato 6:aa1fc6a5cc2a 147 &SCUX_FROM_OPCIR_OPC0_2,
dkato 6:aa1fc6a5cc2a 148 &SCUX_FROM_IPCIR_IPC0_2,
dkato 6:aa1fc6a5cc2a 149 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 150 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 151 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 152 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 153 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 154 &SCUXMDBCR_MIX0_0,
dkato 6:aa1fc6a5cc2a 155 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 156 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 157 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 158 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 159 &SCUXDMATD2_CIM,
dkato 6:aa1fc6a5cc2a 160 &SCUXDMATU2_CIM,
dkato 6:aa1fc6a5cc2a 161 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 162 &SCUXFDTSEL2_CIM,
dkato 6:aa1fc6a5cc2a 163 &SCUXFUTSEL2_CIM,
dkato 6:aa1fc6a5cc2a 164 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 165 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 166 &SCUXSRCRSEL2_CIM,
dkato 6:aa1fc6a5cc2a 167 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 168 },
dkato 6:aa1fc6a5cc2a 169 {
dkato 6:aa1fc6a5cc2a 170 &SCUX_FROM_DVUIR_DVU0_3,
dkato 6:aa1fc6a5cc2a 171 &SCUX_FROM_SRCIR0_2SRC0_1,
dkato 6:aa1fc6a5cc2a 172 &SCUX_FROM_FFUIR_FFU0_3,
dkato 6:aa1fc6a5cc2a 173 &SCUX_FROM_FFDIR_FFD0_3,
dkato 6:aa1fc6a5cc2a 174 &SCUX_FROM_OPCIR_OPC0_3,
dkato 6:aa1fc6a5cc2a 175 &SCUX_FROM_IPCIR_IPC0_3,
dkato 6:aa1fc6a5cc2a 176 &SCUXMIXIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 177 &SCUXMADIR_MIX0_0,
dkato 6:aa1fc6a5cc2a 178 &SCUXMIXBR_MIX0_0,
dkato 6:aa1fc6a5cc2a 179 &SCUXMIXMR_MIX0_0,
dkato 6:aa1fc6a5cc2a 180 &SCUXMVPDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 181 &SCUXMDBDR_MIX0_0,
dkato 6:aa1fc6a5cc2a 182 &SCUXMDBER_MIX0_0,
dkato 6:aa1fc6a5cc2a 183 &SCUXMIXSR_MIX0_0,
dkato 6:aa1fc6a5cc2a 184 &SCUXSWRSR_CIM,
dkato 6:aa1fc6a5cc2a 185 &SCUXDMACR_CIM,
dkato 6:aa1fc6a5cc2a 186 &SCUXDMATD3_CIM,
dkato 6:aa1fc6a5cc2a 187 &SCUXDMATU3_CIM,
dkato 6:aa1fc6a5cc2a 188 &SCUXSSIRSEL_CIM,
dkato 6:aa1fc6a5cc2a 189 &SCUXFDTSEL3_CIM,
dkato 6:aa1fc6a5cc2a 190 &SCUXFUTSEL3_CIM,
dkato 6:aa1fc6a5cc2a 191 &SCUXSSIPMD_CIM,
dkato 6:aa1fc6a5cc2a 192 &SCUXSSICTRL_CIM,
dkato 6:aa1fc6a5cc2a 193 &SCUXSRCRSEL3_CIM,
dkato 6:aa1fc6a5cc2a 194 &SCUXMIXRSEL_CIM
dkato 6:aa1fc6a5cc2a 195 }
dkato 6:aa1fc6a5cc2a 196 };
dkato 6:aa1fc6a5cc2a 197 /* <-MISRA 11.3, 11.4 11.5 */
dkato 6:aa1fc6a5cc2a 198
dkato 6:aa1fc6a5cc2a 199 /* ->MISRA 11.3 This cast is needed for register access. */
dkato 6:aa1fc6a5cc2a 200 /* address table of register set for each SSIF channel */
dkato 6:aa1fc6a5cc2a 201 static volatile struct st_ssif * const p_scux_ssif_ch_reg_addr[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 202 {
dkato 6:aa1fc6a5cc2a 203 &SSIF0,
dkato 6:aa1fc6a5cc2a 204 &SSIF1,
dkato 6:aa1fc6a5cc2a 205 &SSIF2,
dkato 6:aa1fc6a5cc2a 206 &SSIF3,
dkato 6:aa1fc6a5cc2a 207 &SSIF4,
dkato 6:aa1fc6a5cc2a 208 &SSIF5
dkato 6:aa1fc6a5cc2a 209 };
dkato 6:aa1fc6a5cc2a 210 /* <-MISRA 11.3 */
dkato 6:aa1fc6a5cc2a 211
dkato 6:aa1fc6a5cc2a 212 /* SCUX semaphore table define */
dkato 6:aa1fc6a5cc2a 213 static const osSemaphoreDef_t * const p_semdef_ch_scux_access[SCUX_CH_NUM] =
dkato 6:aa1fc6a5cc2a 214 {
dkato 6:aa1fc6a5cc2a 215 osSemaphore(scux_ch0_access),
dkato 6:aa1fc6a5cc2a 216 osSemaphore(scux_ch1_access),
dkato 6:aa1fc6a5cc2a 217 osSemaphore(scux_ch2_access),
dkato 6:aa1fc6a5cc2a 218 osSemaphore(scux_ch3_access)
dkato 6:aa1fc6a5cc2a 219 };
dkato 6:aa1fc6a5cc2a 220
dkato 6:aa1fc6a5cc2a 221 /* SSIF semaphore table define */
dkato 6:aa1fc6a5cc2a 222 static const osSemaphoreDef_t * const p_semdef_ch_scux_ssif_access[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 223 {
dkato 6:aa1fc6a5cc2a 224 osSemaphore(scux_ssif_ch0_access),
dkato 6:aa1fc6a5cc2a 225 osSemaphore(scux_ssif_ch1_access),
dkato 6:aa1fc6a5cc2a 226 osSemaphore(scux_ssif_ch2_access),
dkato 6:aa1fc6a5cc2a 227 osSemaphore(scux_ssif_ch3_access),
dkato 6:aa1fc6a5cc2a 228 osSemaphore(scux_ssif_ch4_access),
dkato 6:aa1fc6a5cc2a 229 osSemaphore(scux_ssif_ch5_access)
dkato 6:aa1fc6a5cc2a 230 };
dkato 6:aa1fc6a5cc2a 231
dkato 6:aa1fc6a5cc2a 232 /* write DMA resource define */
dkato 6:aa1fc6a5cc2a 233 static const dma_res_select_t gb_dma_res_select_tx[SCUX_CH_NUM] =
dkato 6:aa1fc6a5cc2a 234 {
dkato 6:aa1fc6a5cc2a 235 DMA_RS_SCUTXI0,
dkato 6:aa1fc6a5cc2a 236 DMA_RS_SCUTXI1,
dkato 6:aa1fc6a5cc2a 237 DMA_RS_SCUTXI2,
dkato 6:aa1fc6a5cc2a 238 DMA_RS_SCUTXI3
dkato 6:aa1fc6a5cc2a 239 };
dkato 6:aa1fc6a5cc2a 240
dkato 6:aa1fc6a5cc2a 241 /* read DMA resource define */
dkato 6:aa1fc6a5cc2a 242 static const dma_res_select_t gb_dma_res_select_rx[SCUX_CH_NUM] =
dkato 6:aa1fc6a5cc2a 243 {
dkato 6:aa1fc6a5cc2a 244 DMA_RS_SCURXI0,
dkato 6:aa1fc6a5cc2a 245 DMA_RS_SCURXI1,
dkato 6:aa1fc6a5cc2a 246 DMA_RS_SCURXI2,
dkato 6:aa1fc6a5cc2a 247 DMA_RS_SCURXI3
dkato 6:aa1fc6a5cc2a 248 };
dkato 6:aa1fc6a5cc2a 249
dkato 6:aa1fc6a5cc2a 250 /* write dummy data buffer */
dkato 6:aa1fc6a5cc2a 251 static uint8_t gb_scux_write_dummy_buf[SCUX_DUMMY_BUF_SIZE];
dkato 6:aa1fc6a5cc2a 252
dkato 6:aa1fc6a5cc2a 253 /* read dummy data buffer */
dkato 6:aa1fc6a5cc2a 254 static uint8_t gb_scux_read_dummy_buf[SCUX_DUMMY_BUF_SIZE];
dkato 6:aa1fc6a5cc2a 255
dkato 6:aa1fc6a5cc2a 256 /******************************************************************************
dkato 6:aa1fc6a5cc2a 257 Function prototypes
dkato 6:aa1fc6a5cc2a 258 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 259
dkato 6:aa1fc6a5cc2a 260 static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT]);
dkato 6:aa1fc6a5cc2a 261 static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 262 static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag);
dkato 6:aa1fc6a5cc2a 263 static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 264 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 265 static int_t SCUX_CmnUnInitialize(void);
dkato 6:aa1fc6a5cc2a 266 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 267
dkato 6:aa1fc6a5cc2a 268 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 269 * Function Name: SCUX_GetDrvInstance
dkato 6:aa1fc6a5cc2a 270 * @brief Get pointer of gb_scux_info_drv.
dkato 6:aa1fc6a5cc2a 271 *
dkato 6:aa1fc6a5cc2a 272 * Description:<br>
dkato 6:aa1fc6a5cc2a 273 *
dkato 6:aa1fc6a5cc2a 274 * @param None.
dkato 6:aa1fc6a5cc2a 275 * @retval pointer of gb_scux_info_drv -
dkato 6:aa1fc6a5cc2a 276 * driver instance.
dkato 6:aa1fc6a5cc2a 277 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 278
dkato 6:aa1fc6a5cc2a 279 scux_info_drv_t *SCUX_GetDrvInstance(void)
dkato 6:aa1fc6a5cc2a 280 {
dkato 6:aa1fc6a5cc2a 281
dkato 6:aa1fc6a5cc2a 282 return &gb_scux_info_drv;
dkato 6:aa1fc6a5cc2a 283 }
dkato 6:aa1fc6a5cc2a 284
dkato 6:aa1fc6a5cc2a 285 /******************************************************************************
dkato 6:aa1fc6a5cc2a 286 End of function SCUX_GetDrv_Instance
dkato 6:aa1fc6a5cc2a 287 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 288
dkato 6:aa1fc6a5cc2a 289 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 290 * Function Name: SCUX_GetDrvChInfo
dkato 6:aa1fc6a5cc2a 291 * @brief gb_scux_info_drv.info_ch[channel].
dkato 6:aa1fc6a5cc2a 292 *
dkato 6:aa1fc6a5cc2a 293 * Description:<br>
dkato 6:aa1fc6a5cc2a 294 *
dkato 6:aa1fc6a5cc2a 295 * @param[in] channel information number.
dkato 6:aa1fc6a5cc2a 296 * @retval pointer of gb_scux_info_drv -
dkato 6:aa1fc6a5cc2a 297 * pointer of channel information.
dkato 6:aa1fc6a5cc2a 298 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 299
dkato 6:aa1fc6a5cc2a 300 scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel)
dkato 6:aa1fc6a5cc2a 301 {
dkato 6:aa1fc6a5cc2a 302
dkato 6:aa1fc6a5cc2a 303 return &gb_scux_info_drv.info_ch[channel];
dkato 6:aa1fc6a5cc2a 304 }
dkato 6:aa1fc6a5cc2a 305
dkato 6:aa1fc6a5cc2a 306 /******************************************************************************
dkato 6:aa1fc6a5cc2a 307 End of function SCUX_GetDrvChInfo
dkato 6:aa1fc6a5cc2a 308 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 309
dkato 6:aa1fc6a5cc2a 310 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 311 * Function Name: SCUX_GetSsifChInfo
dkato 6:aa1fc6a5cc2a 312 * @brief gb_scux_ssif_info.channel.
dkato 6:aa1fc6a5cc2a 313 *
dkato 6:aa1fc6a5cc2a 314 * Description:<br>
dkato 6:aa1fc6a5cc2a 315 *
dkato 6:aa1fc6a5cc2a 316 * @param[in] SSIF channel number.
dkato 6:aa1fc6a5cc2a 317 * @retval pointer of gb_scux_ssif_info -
dkato 6:aa1fc6a5cc2a 318 * pointer of SSIF information.
dkato 6:aa1fc6a5cc2a 319 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 320
dkato 6:aa1fc6a5cc2a 321 scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel)
dkato 6:aa1fc6a5cc2a 322 {
dkato 6:aa1fc6a5cc2a 323
dkato 6:aa1fc6a5cc2a 324 return &gb_scux_ssif_info[channel];
dkato 6:aa1fc6a5cc2a 325 }
dkato 6:aa1fc6a5cc2a 326
dkato 6:aa1fc6a5cc2a 327 /******************************************************************************
dkato 6:aa1fc6a5cc2a 328 End of function SCUX_GetSsifChInfo
dkato 6:aa1fc6a5cc2a 329 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 330
dkato 6:aa1fc6a5cc2a 331 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 332 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 333 * Function Name: SCUX_InitializeOne
dkato 6:aa1fc6a5cc2a 334 * @brief Init SCUX driver.
dkato 6:aa1fc6a5cc2a 335 *
dkato 6:aa1fc6a5cc2a 336 * Description:<br>
dkato 6:aa1fc6a5cc2a 337 *
dkato 6:aa1fc6a5cc2a 338 * @param[in] channel :initialize channel number.
dkato 6:aa1fc6a5cc2a 339 * @param[in] p_scux_init_param :Initialize parameter for SCUX.
dkato 6:aa1fc6a5cc2a 340 * @retval ESUCCESS -
dkato 6:aa1fc6a5cc2a 341 * Operation successful.
dkato 6:aa1fc6a5cc2a 342 * EERROR -
dkato 6:aa1fc6a5cc2a 343 * Error occured.
dkato 6:aa1fc6a5cc2a 344 * error code -
dkato 6:aa1fc6a5cc2a 345 * ENOMEM : Making semaphore is failed.
dkato 6:aa1fc6a5cc2a 346 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 347 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 348 int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param)
dkato 6:aa1fc6a5cc2a 349 {
dkato 6:aa1fc6a5cc2a 350 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 351 osStatus sem_ercd;
dkato 6:aa1fc6a5cc2a 352 int_t scux_ch_count;
dkato 6:aa1fc6a5cc2a 353 int_t audio_ch_count;
dkato 6:aa1fc6a5cc2a 354 scux_ssif_ch_num_t ssif_ch_count;
dkato 6:aa1fc6a5cc2a 355 uint32_t cpg_value;
dkato 6:aa1fc6a5cc2a 356 bool_t init_shared_flag = false;
dkato 6:aa1fc6a5cc2a 357 int_t was_masked;
dkato 6:aa1fc6a5cc2a 358 volatile uint8_t dummy_buf;
dkato 6:aa1fc6a5cc2a 359 uint32_t scux_init_count;
dkato 6:aa1fc6a5cc2a 360 int_t uninit_ercd;
dkato 6:aa1fc6a5cc2a 361 bool_t init_start_flag = false;
dkato 6:aa1fc6a5cc2a 362 bool_t uninit_all_flag = false;
dkato 6:aa1fc6a5cc2a 363 uint32_t i;
dkato 6:aa1fc6a5cc2a 364
dkato 6:aa1fc6a5cc2a 365 if (NULL == p_scux_init_param)
dkato 6:aa1fc6a5cc2a 366 {
dkato 6:aa1fc6a5cc2a 367 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 368 }
dkato 6:aa1fc6a5cc2a 369 else if (false == p_scux_init_param->enabled)
dkato 6:aa1fc6a5cc2a 370 {
dkato 6:aa1fc6a5cc2a 371 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 372 }
dkato 6:aa1fc6a5cc2a 373 else
dkato 6:aa1fc6a5cc2a 374 {
dkato 6:aa1fc6a5cc2a 375 /* init channel management information */
dkato 6:aa1fc6a5cc2a 376 scux_ch_count = channel;
dkato 6:aa1fc6a5cc2a 377
dkato 6:aa1fc6a5cc2a 378 for (i = 0; ((i < INIT_WAIT_NUM) && (false == init_start_flag)); i++)
dkato 6:aa1fc6a5cc2a 379 {
dkato 10:c5c630882b90 380 #if defined (__ICCARM__)
dkato 10:c5c630882b90 381 was_masked = __disable_irq_iar();
dkato 10:c5c630882b90 382 #else
dkato 6:aa1fc6a5cc2a 383 was_masked = __disable_irq();
dkato 10:c5c630882b90 384 #endif
dkato 6:aa1fc6a5cc2a 385
dkato 6:aa1fc6a5cc2a 386 if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
dkato 6:aa1fc6a5cc2a 387 {
dkato 6:aa1fc6a5cc2a 388 /* already scux driver shared information is initialized */
dkato 6:aa1fc6a5cc2a 389 init_shared_flag = true;
dkato 6:aa1fc6a5cc2a 390
dkato 6:aa1fc6a5cc2a 391 /* enable the channel */
dkato 6:aa1fc6a5cc2a 392 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
dkato 6:aa1fc6a5cc2a 393
dkato 6:aa1fc6a5cc2a 394 init_start_flag = true;
dkato 6:aa1fc6a5cc2a 395 }
dkato 6:aa1fc6a5cc2a 396 else if (SCUX_DRV_UNINIT == gb_scux_info_drv.drv_stat)
dkato 6:aa1fc6a5cc2a 397 {
dkato 6:aa1fc6a5cc2a 398 /* change the status to scux initialization running */
dkato 6:aa1fc6a5cc2a 399 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
dkato 6:aa1fc6a5cc2a 400
dkato 6:aa1fc6a5cc2a 401 for (scux_init_count = SCUX_CH_0; scux_init_count < SCUX_CH_NUM; scux_init_count++)
dkato 6:aa1fc6a5cc2a 402 {
dkato 6:aa1fc6a5cc2a 403 gb_scux_info_drv.info_ch[scux_init_count].enabled = false;
dkato 6:aa1fc6a5cc2a 404 gb_scux_info_drv.info_ch[scux_init_count].ch_stat = SCUX_CH_UNINIT;
dkato 6:aa1fc6a5cc2a 405
dkato 6:aa1fc6a5cc2a 406 gb_scux_info_drv.info_ch[scux_init_count].sem_ch_scux_access = NULL;
dkato 6:aa1fc6a5cc2a 407 }
dkato 6:aa1fc6a5cc2a 408
dkato 6:aa1fc6a5cc2a 409 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 410 {
dkato 6:aa1fc6a5cc2a 411 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
dkato 6:aa1fc6a5cc2a 412 }
dkato 6:aa1fc6a5cc2a 413
dkato 6:aa1fc6a5cc2a 414 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
dkato 6:aa1fc6a5cc2a 415
dkato 6:aa1fc6a5cc2a 416 /* enable the channel */
dkato 6:aa1fc6a5cc2a 417 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
dkato 6:aa1fc6a5cc2a 418
dkato 6:aa1fc6a5cc2a 419 init_start_flag = true;
dkato 6:aa1fc6a5cc2a 420 }
dkato 6:aa1fc6a5cc2a 421 else
dkato 6:aa1fc6a5cc2a 422 {
dkato 6:aa1fc6a5cc2a 423 /* do nothing : SCUX_DRV_INIT_RUNNING */
dkato 6:aa1fc6a5cc2a 424 }
dkato 6:aa1fc6a5cc2a 425
dkato 6:aa1fc6a5cc2a 426 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 427 {
dkato 6:aa1fc6a5cc2a 428 __enable_irq();
dkato 6:aa1fc6a5cc2a 429 }
dkato 6:aa1fc6a5cc2a 430
dkato 6:aa1fc6a5cc2a 431 if (false == init_start_flag)
dkato 6:aa1fc6a5cc2a 432 {
dkato 6:aa1fc6a5cc2a 433 /* wait for the change of drv_stat to SCUX_DRV_INIT */
dkato 6:aa1fc6a5cc2a 434 (void)osDelay(INIT_WAIT_TIME_MSEC);
dkato 6:aa1fc6a5cc2a 435 }
dkato 6:aa1fc6a5cc2a 436 }
dkato 6:aa1fc6a5cc2a 437
dkato 6:aa1fc6a5cc2a 438 if (false == init_start_flag)
dkato 6:aa1fc6a5cc2a 439 {
dkato 6:aa1fc6a5cc2a 440 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 441 }
dkato 6:aa1fc6a5cc2a 442 else
dkato 6:aa1fc6a5cc2a 443 {
dkato 6:aa1fc6a5cc2a 444 {
dkato 6:aa1fc6a5cc2a 445
dkato 6:aa1fc6a5cc2a 446 /* copy parameter */
dkato 6:aa1fc6a5cc2a 447 /* set interrupt parameter */
dkato 6:aa1fc6a5cc2a 448 gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param->int_level;
dkato 6:aa1fc6a5cc2a 449
dkato 6:aa1fc6a5cc2a 450 /* set route parameter */
dkato 6:aa1fc6a5cc2a 451 gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param->route;
dkato 6:aa1fc6a5cc2a 452
dkato 6:aa1fc6a5cc2a 453 /* set SRC paramter */
dkato 6:aa1fc6a5cc2a 454 SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param->src_cfg);
dkato 6:aa1fc6a5cc2a 455
dkato 6:aa1fc6a5cc2a 456 /* init SCUX parameter */
dkato 6:aa1fc6a5cc2a 457 if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
dkato 6:aa1fc6a5cc2a 458 {
dkato 6:aa1fc6a5cc2a 459 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
dkato 6:aa1fc6a5cc2a 460 }
dkato 6:aa1fc6a5cc2a 461 else
dkato 6:aa1fc6a5cc2a 462 {
dkato 6:aa1fc6a5cc2a 463 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
dkato 6:aa1fc6a5cc2a 464 }
dkato 6:aa1fc6a5cc2a 465 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
dkato 6:aa1fc6a5cc2a 466 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
dkato 6:aa1fc6a5cc2a 467 gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 468 gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
dkato 6:aa1fc6a5cc2a 469
dkato 6:aa1fc6a5cc2a 470 /* init DVU parameter */
dkato 6:aa1fc6a5cc2a 471 for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
dkato 6:aa1fc6a5cc2a 472 {
dkato 6:aa1fc6a5cc2a 473 gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false;
dkato 6:aa1fc6a5cc2a 474 }
dkato 6:aa1fc6a5cc2a 475 gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
dkato 6:aa1fc6a5cc2a 476
dkato 6:aa1fc6a5cc2a 477 if (false == init_shared_flag)
dkato 6:aa1fc6a5cc2a 478 {
dkato 6:aa1fc6a5cc2a 479 /* init MIX parameter */
dkato 6:aa1fc6a5cc2a 480 gb_scux_info_drv.shared_info.mix_setup = false;
dkato 6:aa1fc6a5cc2a 481 gb_scux_info_drv.shared_info.mix_run_ch = 0U;
dkato 6:aa1fc6a5cc2a 482 gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
dkato 6:aa1fc6a5cc2a 483
dkato 6:aa1fc6a5cc2a 484 /* init SSIF parameter */
dkato 6:aa1fc6a5cc2a 485 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 486 {
dkato 6:aa1fc6a5cc2a 487 gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
dkato 6:aa1fc6a5cc2a 488 gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
dkato 6:aa1fc6a5cc2a 489 gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
dkato 6:aa1fc6a5cc2a 490 gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
dkato 6:aa1fc6a5cc2a 491 }
dkato 6:aa1fc6a5cc2a 492
dkato 6:aa1fc6a5cc2a 493 /* init regsiter store value */
dkato 6:aa1fc6a5cc2a 494 gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 495 }
dkato 6:aa1fc6a5cc2a 496
dkato 6:aa1fc6a5cc2a 497 /* set register address */
dkato 6:aa1fc6a5cc2a 498 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
dkato 6:aa1fc6a5cc2a 499
dkato 6:aa1fc6a5cc2a 500 if (false == init_shared_flag) {
dkato 6:aa1fc6a5cc2a 501 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 502 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 503 #else
dkato 6:aa1fc6a5cc2a 504 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 505 #endif
dkato 6:aa1fc6a5cc2a 506
dkato 6:aa1fc6a5cc2a 507 /* supply clock for SCUX */
dkato 6:aa1fc6a5cc2a 508 cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
dkato 6:aa1fc6a5cc2a 509 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 6:aa1fc6a5cc2a 510 dummy_buf = CPG.STBCR8;
dkato 6:aa1fc6a5cc2a 511
dkato 6:aa1fc6a5cc2a 512 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 513 {
dkato 6:aa1fc6a5cc2a 514 __enable_irq();
dkato 6:aa1fc6a5cc2a 515 }
dkato 6:aa1fc6a5cc2a 516
dkato 6:aa1fc6a5cc2a 517 /* software reset */
dkato 6:aa1fc6a5cc2a 518 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 6:aa1fc6a5cc2a 519 SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
dkato 6:aa1fc6a5cc2a 520 }
dkato 6:aa1fc6a5cc2a 521
dkato 6:aa1fc6a5cc2a 522 /* init DVU register */
dkato 6:aa1fc6a5cc2a 523 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 524 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 525 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 526 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 527 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 528 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 529 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 530 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 531 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 532 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 533 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 534 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 535 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 536 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 537 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 538 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 539 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 540 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 541 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 542 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 543
dkato 6:aa1fc6a5cc2a 544 /* init SRC register */
dkato 6:aa1fc6a5cc2a 545 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 546 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 547 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 548 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 549 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 550 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 6:aa1fc6a5cc2a 551 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 552 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 553 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 554 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 555 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 556 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 557 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 558 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 559 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 560 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 561 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 6:aa1fc6a5cc2a 562 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 563 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 564 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 565 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 566 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 567 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 568 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 569
dkato 6:aa1fc6a5cc2a 570 /* init FFU register */
dkato 6:aa1fc6a5cc2a 571 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 572 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 573 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 574 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 575 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 576 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 577
dkato 6:aa1fc6a5cc2a 578 /* init FFD register */
dkato 6:aa1fc6a5cc2a 579 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 580 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 581 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 582 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 583 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 584 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 585 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 586
dkato 6:aa1fc6a5cc2a 587 /* init OPC register */
dkato 6:aa1fc6a5cc2a 588 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 589 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 590
dkato 6:aa1fc6a5cc2a 591 /* init IPC register */
dkato 6:aa1fc6a5cc2a 592 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 593 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 594
dkato 6:aa1fc6a5cc2a 595 /* init MIX register for each channel */
dkato 6:aa1fc6a5cc2a 596 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 597
dkato 6:aa1fc6a5cc2a 598 /* init CIM register for each channel */
dkato 6:aa1fc6a5cc2a 599 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 600 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 601 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 602
dkato 6:aa1fc6a5cc2a 603 /* init shared register */
dkato 6:aa1fc6a5cc2a 604 if (false == init_shared_flag)
dkato 6:aa1fc6a5cc2a 605 {
dkato 6:aa1fc6a5cc2a 606 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 607 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 608 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 609 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 610 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 611 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 612 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 613 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 614 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 615 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 616 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 617 }
dkato 6:aa1fc6a5cc2a 618
dkato 6:aa1fc6a5cc2a 619 if (false == init_shared_flag)
dkato 6:aa1fc6a5cc2a 620 {
dkato 6:aa1fc6a5cc2a 621 /* set SSIF register */
dkato 6:aa1fc6a5cc2a 622 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 623 {
dkato 6:aa1fc6a5cc2a 624 gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
dkato 6:aa1fc6a5cc2a 625 }
dkato 6:aa1fc6a5cc2a 626 }
dkato 6:aa1fc6a5cc2a 627
dkato 6:aa1fc6a5cc2a 628 /* set semaphore parameter */
dkato 6:aa1fc6a5cc2a 629 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
dkato 6:aa1fc6a5cc2a 630 if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 6:aa1fc6a5cc2a 631 {
dkato 6:aa1fc6a5cc2a 632 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 633 }
dkato 6:aa1fc6a5cc2a 634 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 6:aa1fc6a5cc2a 635 {
dkato 6:aa1fc6a5cc2a 636 for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 637 {
dkato 6:aa1fc6a5cc2a 638 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
dkato 6:aa1fc6a5cc2a 639 if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 6:aa1fc6a5cc2a 640 {
dkato 6:aa1fc6a5cc2a 641 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 642 }
dkato 6:aa1fc6a5cc2a 643 }
dkato 6:aa1fc6a5cc2a 644 }
dkato 6:aa1fc6a5cc2a 645 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 6:aa1fc6a5cc2a 646 {
dkato 6:aa1fc6a5cc2a 647 gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
dkato 6:aa1fc6a5cc2a 648 if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
dkato 6:aa1fc6a5cc2a 649 {
dkato 6:aa1fc6a5cc2a 650 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 651 }
dkato 6:aa1fc6a5cc2a 652 }
dkato 6:aa1fc6a5cc2a 653
dkato 6:aa1fc6a5cc2a 654
dkato 6:aa1fc6a5cc2a 655 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
dkato 6:aa1fc6a5cc2a 656 }
dkato 6:aa1fc6a5cc2a 657
dkato 6:aa1fc6a5cc2a 658 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 659 {
dkato 6:aa1fc6a5cc2a 660 /* uninit each resouces */
dkato 6:aa1fc6a5cc2a 661 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 6:aa1fc6a5cc2a 662
dkato 6:aa1fc6a5cc2a 663 if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 6:aa1fc6a5cc2a 664 {
dkato 6:aa1fc6a5cc2a 665 /* semaphore delete */
dkato 6:aa1fc6a5cc2a 666 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 6:aa1fc6a5cc2a 667 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 668 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 669 {
dkato 6:aa1fc6a5cc2a 670 /* set error return value */
dkato 6:aa1fc6a5cc2a 671 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 672 }
dkato 6:aa1fc6a5cc2a 673
dkato 6:aa1fc6a5cc2a 674 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
dkato 6:aa1fc6a5cc2a 675 }
dkato 6:aa1fc6a5cc2a 676
dkato 10:c5c630882b90 677 #if defined (__ICCARM__)
dkato 10:c5c630882b90 678 was_masked = __disable_irq_iar();
dkato 10:c5c630882b90 679 #else
dkato 6:aa1fc6a5cc2a 680 was_masked = __disable_irq();
dkato 10:c5c630882b90 681 #endif
dkato 6:aa1fc6a5cc2a 682
dkato 6:aa1fc6a5cc2a 683 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 6:aa1fc6a5cc2a 684
dkato 6:aa1fc6a5cc2a 685 for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
dkato 6:aa1fc6a5cc2a 686 {
dkato 6:aa1fc6a5cc2a 687 if (false != gb_scux_info_drv.info_ch[i].enabled)
dkato 6:aa1fc6a5cc2a 688 {
dkato 6:aa1fc6a5cc2a 689 break;
dkato 6:aa1fc6a5cc2a 690 }
dkato 6:aa1fc6a5cc2a 691 }
dkato 6:aa1fc6a5cc2a 692
dkato 6:aa1fc6a5cc2a 693 if (SCUX_CH_NUM == i)
dkato 6:aa1fc6a5cc2a 694 {
dkato 6:aa1fc6a5cc2a 695 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
dkato 6:aa1fc6a5cc2a 696 uninit_all_flag = true;
dkato 6:aa1fc6a5cc2a 697 }
dkato 6:aa1fc6a5cc2a 698
dkato 6:aa1fc6a5cc2a 699 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 700 {
dkato 6:aa1fc6a5cc2a 701 __enable_irq();
dkato 6:aa1fc6a5cc2a 702 }
dkato 6:aa1fc6a5cc2a 703
dkato 6:aa1fc6a5cc2a 704 if (false != uninit_all_flag)
dkato 6:aa1fc6a5cc2a 705 {
dkato 6:aa1fc6a5cc2a 706 /* uninitialize driver infomation */
dkato 6:aa1fc6a5cc2a 707 uninit_ercd = SCUX_CmnUnInitialize();
dkato 6:aa1fc6a5cc2a 708 if (ESUCCESS != uninit_ercd)
dkato 6:aa1fc6a5cc2a 709 {
dkato 6:aa1fc6a5cc2a 710 retval = uninit_ercd;
dkato 6:aa1fc6a5cc2a 711 }
dkato 6:aa1fc6a5cc2a 712
dkato 6:aa1fc6a5cc2a 713 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 6:aa1fc6a5cc2a 714 }
dkato 6:aa1fc6a5cc2a 715 }
dkato 6:aa1fc6a5cc2a 716 else
dkato 6:aa1fc6a5cc2a 717 {
dkato 6:aa1fc6a5cc2a 718 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
dkato 6:aa1fc6a5cc2a 719 }
dkato 6:aa1fc6a5cc2a 720 }
dkato 6:aa1fc6a5cc2a 721 }
dkato 6:aa1fc6a5cc2a 722
dkato 6:aa1fc6a5cc2a 723 return retval;
dkato 6:aa1fc6a5cc2a 724 }
dkato 6:aa1fc6a5cc2a 725
dkato 6:aa1fc6a5cc2a 726 /******************************************************************************
dkato 6:aa1fc6a5cc2a 727 End of function SCUX_InitializeOne
dkato 6:aa1fc6a5cc2a 728 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 729
dkato 6:aa1fc6a5cc2a 730 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 731 * Function Name: SCUX_UnInitializeOne
dkato 6:aa1fc6a5cc2a 732 * @brief Uninit SCUX driver.
dkato 6:aa1fc6a5cc2a 733 *
dkato 6:aa1fc6a5cc2a 734 * Description:<br>
dkato 6:aa1fc6a5cc2a 735 *
dkato 6:aa1fc6a5cc2a 736 * @param[in] channel :unInitialize channel number.
dkato 6:aa1fc6a5cc2a 737 * @retval None.
dkato 6:aa1fc6a5cc2a 738 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 739 void SCUX_UnInitializeOne(const int_t channel)
dkato 6:aa1fc6a5cc2a 740 {
dkato 6:aa1fc6a5cc2a 741 osStatus sem_ercd;
dkato 6:aa1fc6a5cc2a 742 int_t ercd;
dkato 6:aa1fc6a5cc2a 743 int_t scux_ch_count;
dkato 6:aa1fc6a5cc2a 744 int_t ssif_ch_count;
dkato 6:aa1fc6a5cc2a 745 bool_t uninit_all_flag = false;
dkato 6:aa1fc6a5cc2a 746 uint32_t i;
dkato 6:aa1fc6a5cc2a 747 int_t was_masked;
dkato 6:aa1fc6a5cc2a 748
dkato 6:aa1fc6a5cc2a 749 scux_ch_count = channel;
dkato 7:30ebba78fff0 750 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 6:aa1fc6a5cc2a 751 {
dkato 7:30ebba78fff0 752 /* check ch_stat whether going transfer */
dkato 7:30ebba78fff0 753 if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 754 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 755 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
dkato 6:aa1fc6a5cc2a 756 {
dkato 7:30ebba78fff0 757 /* The exclusive access control (interrupt disabled) starts */
dkato 6:aa1fc6a5cc2a 758 #if defined (__ICCARM__)
dkato 7:30ebba78fff0 759 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 760 #else
dkato 7:30ebba78fff0 761 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 762 #endif
dkato 6:aa1fc6a5cc2a 763
dkato 7:30ebba78fff0 764 /* This exclusive access control ends in the SCUX_IoctlClearStop */
dkato 7:30ebba78fff0 765 /* call the __enable_irq in the SCUX_IoctlClearStop */
dkato 7:30ebba78fff0 766 ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
dkato 7:30ebba78fff0 767 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 768 {
dkato 7:30ebba78fff0 769 /* NON_NOTICE_ASSERT: SCUX stop failed */
dkato 7:30ebba78fff0 770 }
dkato 7:30ebba78fff0 771
dkato 7:30ebba78fff0 772 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
dkato 7:30ebba78fff0 773 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 774 {
dkato 7:30ebba78fff0 775 /* NON_NOTICE_ASSERT: DMA release failed */
dkato 6:aa1fc6a5cc2a 776 }
dkato 6:aa1fc6a5cc2a 777 }
dkato 6:aa1fc6a5cc2a 778 }
dkato 6:aa1fc6a5cc2a 779
dkato 7:30ebba78fff0 780 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 6:aa1fc6a5cc2a 781 {
dkato 7:30ebba78fff0 782 if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
dkato 6:aa1fc6a5cc2a 783 {
dkato 7:30ebba78fff0 784 /* NON_NOTICE_ASSERT: abnormal status */
dkato 7:30ebba78fff0 785 }
dkato 7:30ebba78fff0 786
dkato 7:30ebba78fff0 787 /* uninit each resouces */
dkato 7:30ebba78fff0 788 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 789
dkato 7:30ebba78fff0 790 if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 7:30ebba78fff0 791 {
dkato 6:aa1fc6a5cc2a 792 /* delete each semaphore */
dkato 6:aa1fc6a5cc2a 793 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 6:aa1fc6a5cc2a 794 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 795 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 796 {
dkato 6:aa1fc6a5cc2a 797 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 798 }
dkato 7:30ebba78fff0 799
dkato 6:aa1fc6a5cc2a 800 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 6:aa1fc6a5cc2a 801 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 802 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 803 {
dkato 6:aa1fc6a5cc2a 804 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 805 }
dkato 7:30ebba78fff0 806
dkato 6:aa1fc6a5cc2a 807 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
dkato 6:aa1fc6a5cc2a 808 }
dkato 7:30ebba78fff0 809
dkato 7:30ebba78fff0 810 /* delete queue */
dkato 7:30ebba78fff0 811 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 812 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 813 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 7:30ebba78fff0 814 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 6:aa1fc6a5cc2a 815 }
dkato 6:aa1fc6a5cc2a 816
dkato 10:c5c630882b90 817 #if defined (__ICCARM__)
dkato 10:c5c630882b90 818 was_masked = __disable_irq_iar();
dkato 10:c5c630882b90 819 #else
dkato 6:aa1fc6a5cc2a 820 was_masked = __disable_irq();
dkato 10:c5c630882b90 821 #endif
dkato 6:aa1fc6a5cc2a 822
dkato 6:aa1fc6a5cc2a 823 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 6:aa1fc6a5cc2a 824
dkato 6:aa1fc6a5cc2a 825 for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
dkato 6:aa1fc6a5cc2a 826 {
dkato 6:aa1fc6a5cc2a 827 if (false != gb_scux_info_drv.info_ch[i].enabled)
dkato 6:aa1fc6a5cc2a 828 {
dkato 6:aa1fc6a5cc2a 829 break;
dkato 6:aa1fc6a5cc2a 830 }
dkato 6:aa1fc6a5cc2a 831 }
dkato 6:aa1fc6a5cc2a 832
dkato 6:aa1fc6a5cc2a 833 if (SCUX_CH_NUM == i)
dkato 6:aa1fc6a5cc2a 834 {
dkato 6:aa1fc6a5cc2a 835 if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
dkato 6:aa1fc6a5cc2a 836 {
dkato 6:aa1fc6a5cc2a 837 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
dkato 6:aa1fc6a5cc2a 838 uninit_all_flag = true;
dkato 6:aa1fc6a5cc2a 839 }
dkato 6:aa1fc6a5cc2a 840 }
dkato 6:aa1fc6a5cc2a 841
dkato 6:aa1fc6a5cc2a 842 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 843 {
dkato 6:aa1fc6a5cc2a 844 __enable_irq();
dkato 6:aa1fc6a5cc2a 845 }
dkato 6:aa1fc6a5cc2a 846
dkato 6:aa1fc6a5cc2a 847 if (false != uninit_all_flag)
dkato 6:aa1fc6a5cc2a 848 {
dkato 6:aa1fc6a5cc2a 849 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 850 {
dkato 6:aa1fc6a5cc2a 851 if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 6:aa1fc6a5cc2a 852 {
dkato 6:aa1fc6a5cc2a 853 sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 854 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 855 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 856 {
dkato 6:aa1fc6a5cc2a 857 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 858 }
dkato 6:aa1fc6a5cc2a 859 }
dkato 6:aa1fc6a5cc2a 860 }
dkato 6:aa1fc6a5cc2a 861
dkato 6:aa1fc6a5cc2a 862 if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
dkato 6:aa1fc6a5cc2a 863 {
dkato 6:aa1fc6a5cc2a 864 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 865 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 866 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 867 {
dkato 6:aa1fc6a5cc2a 868 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 869 }
dkato 6:aa1fc6a5cc2a 870 }
dkato 6:aa1fc6a5cc2a 871
dkato 6:aa1fc6a5cc2a 872 /* uninitialize driver infomation */
dkato 6:aa1fc6a5cc2a 873 (void)SCUX_CmnUnInitialize();
dkato 6:aa1fc6a5cc2a 874
dkato 6:aa1fc6a5cc2a 875 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 6:aa1fc6a5cc2a 876 }
dkato 7:30ebba78fff0 877 }
dkato 7:30ebba78fff0 878
dkato 7:30ebba78fff0 879 /******************************************************************************
dkato 7:30ebba78fff0 880 End of function SCUX_UnInitializeOne
dkato 7:30ebba78fff0 881 ******************************************************************************/
dkato 7:30ebba78fff0 882 #endif /* end mbed */
dkato 7:30ebba78fff0 883
dkato 7:30ebba78fff0 884 /**************************************************************************//**
dkato 7:30ebba78fff0 885 * Function Name: SCUX_Initialize
dkato 7:30ebba78fff0 886 * @brief Init SCUX driver.
dkato 7:30ebba78fff0 887 *
dkato 7:30ebba78fff0 888 * Description:<br>
dkato 7:30ebba78fff0 889 *
dkato 7:30ebba78fff0 890 * @param[in] p_scux_init_param :Initialize parameter for SCUX.
dkato 7:30ebba78fff0 891 * @retval ESUCCESS -
dkato 7:30ebba78fff0 892 * Operation successful.
dkato 7:30ebba78fff0 893 * EERROR -
dkato 7:30ebba78fff0 894 * Error occured.
dkato 7:30ebba78fff0 895 * error code -
dkato 7:30ebba78fff0 896 * ENOMEM : Making semaphore is failed.
dkato 7:30ebba78fff0 897 * EFAULT : Internal error is occured.
dkato 7:30ebba78fff0 898 ******************************************************************************/
dkato 7:30ebba78fff0 899 int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param)
dkato 7:30ebba78fff0 900 {
dkato 7:30ebba78fff0 901 int_t retval = ESUCCESS;
dkato 7:30ebba78fff0 902 osStatus sem_ercd;
dkato 7:30ebba78fff0 903 int_t scux_ch_count;
dkato 7:30ebba78fff0 904 int_t audio_ch_count;
dkato 7:30ebba78fff0 905 scux_ssif_ch_num_t ssif_ch_count;
dkato 7:30ebba78fff0 906 uint32_t cpg_value;
dkato 7:30ebba78fff0 907 bool_t init_shared_flag = false;
dkato 7:30ebba78fff0 908 int_t was_masked;
dkato 7:30ebba78fff0 909 volatile uint8_t dummy_buf;
dkato 7:30ebba78fff0 910
dkato 7:30ebba78fff0 911 if (NULL == p_scux_init_param)
dkato 7:30ebba78fff0 912 {
dkato 7:30ebba78fff0 913 retval = EFAULT;
dkato 7:30ebba78fff0 914 }
dkato 7:30ebba78fff0 915 else
dkato 7:30ebba78fff0 916 {
dkato 7:30ebba78fff0 917 /* init channel management information */
dkato 7:30ebba78fff0 918 for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 919 {
dkato 7:30ebba78fff0 920 if (false == p_scux_init_param[scux_ch_count].enabled)
dkato 7:30ebba78fff0 921 {
dkato 7:30ebba78fff0 922 /* set disable parameter */
dkato 7:30ebba78fff0 923 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 7:30ebba78fff0 924 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 925 }
dkato 7:30ebba78fff0 926 else
dkato 7:30ebba78fff0 927 {
dkato 7:30ebba78fff0 928 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
dkato 7:30ebba78fff0 929
dkato 7:30ebba78fff0 930 /* copy parameter */
dkato 7:30ebba78fff0 931 /* set interrupt parameter */
dkato 7:30ebba78fff0 932 gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param[scux_ch_count].int_level;
dkato 7:30ebba78fff0 933
dkato 7:30ebba78fff0 934 /* set route parameter */
dkato 7:30ebba78fff0 935 gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param[scux_ch_count].route;
dkato 7:30ebba78fff0 936
dkato 7:30ebba78fff0 937 /* set SRC paramter */
dkato 7:30ebba78fff0 938 SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param[scux_ch_count].src_cfg);
dkato 7:30ebba78fff0 939
dkato 7:30ebba78fff0 940 /* init SCUX parameter */
dkato 7:30ebba78fff0 941 if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
dkato 7:30ebba78fff0 942 {
dkato 7:30ebba78fff0 943 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
dkato 7:30ebba78fff0 944 }
dkato 7:30ebba78fff0 945 else
dkato 7:30ebba78fff0 946 {
dkato 7:30ebba78fff0 947 gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
dkato 7:30ebba78fff0 948 }
dkato 7:30ebba78fff0 949 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
dkato 7:30ebba78fff0 950 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
dkato 7:30ebba78fff0 951 gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 952 gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
dkato 7:30ebba78fff0 953
dkato 7:30ebba78fff0 954 /* init DVU parameter */
dkato 7:30ebba78fff0 955 for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
dkato 7:30ebba78fff0 956 {
dkato 7:30ebba78fff0 957 gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false;
dkato 7:30ebba78fff0 958 }
dkato 7:30ebba78fff0 959 gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
dkato 7:30ebba78fff0 960
dkato 7:30ebba78fff0 961 if (false == init_shared_flag)
dkato 7:30ebba78fff0 962 {
dkato 7:30ebba78fff0 963 /* init MIX parameter */
dkato 7:30ebba78fff0 964 gb_scux_info_drv.shared_info.mix_setup = false;
dkato 7:30ebba78fff0 965 gb_scux_info_drv.shared_info.mix_run_ch = 0U;
dkato 7:30ebba78fff0 966 gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
dkato 7:30ebba78fff0 967
dkato 7:30ebba78fff0 968 /* init SSIF parameter */
dkato 7:30ebba78fff0 969 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 7:30ebba78fff0 970 {
dkato 7:30ebba78fff0 971 gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
dkato 7:30ebba78fff0 972 gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
dkato 7:30ebba78fff0 973 gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
dkato 7:30ebba78fff0 974 gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
dkato 7:30ebba78fff0 975 }
dkato 7:30ebba78fff0 976
dkato 7:30ebba78fff0 977 /* init regsiter store value */
dkato 7:30ebba78fff0 978 gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 979 }
dkato 7:30ebba78fff0 980
dkato 7:30ebba78fff0 981 /* set register address */
dkato 7:30ebba78fff0 982 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
dkato 7:30ebba78fff0 983
dkato 7:30ebba78fff0 984 if (false == init_shared_flag) {
dkato 7:30ebba78fff0 985 #if defined (__ICCARM__)
dkato 7:30ebba78fff0 986 was_masked = __disable_irq_iar();
dkato 7:30ebba78fff0 987 #else
dkato 7:30ebba78fff0 988 was_masked = __disable_irq();
dkato 7:30ebba78fff0 989 #endif
dkato 7:30ebba78fff0 990
dkato 7:30ebba78fff0 991 /* supply clock for SCUX */
dkato 7:30ebba78fff0 992 cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
dkato 7:30ebba78fff0 993 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 7:30ebba78fff0 994 dummy_buf = CPG.STBCR8;
dkato 7:30ebba78fff0 995
dkato 7:30ebba78fff0 996 if (0 == was_masked)
dkato 7:30ebba78fff0 997 {
dkato 7:30ebba78fff0 998 __enable_irq();
dkato 7:30ebba78fff0 999 }
dkato 7:30ebba78fff0 1000
dkato 7:30ebba78fff0 1001 /* software reset */
dkato 7:30ebba78fff0 1002 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 7:30ebba78fff0 1003 SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
dkato 7:30ebba78fff0 1004 }
dkato 7:30ebba78fff0 1005
dkato 7:30ebba78fff0 1006 /* init DVU register */
dkato 7:30ebba78fff0 1007 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1008 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1009 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1010 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1011 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1012 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1013 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1014 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1015 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1016 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1017 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1018 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1019 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1020 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1021 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1022 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1023 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1024 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1025 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1026 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
dkato 7:30ebba78fff0 1027
dkato 7:30ebba78fff0 1028 /* init SRC register */
dkato 7:30ebba78fff0 1029 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1030 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1031 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1032 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1033 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1034 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 7:30ebba78fff0 1035 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1036 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1037 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1038 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1039 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1040 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1041 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1042 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1043 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1044 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1045 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 7:30ebba78fff0 1046 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1047 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1048 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1049 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1050 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1051 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1052 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
dkato 7:30ebba78fff0 1053
dkato 7:30ebba78fff0 1054 /* init FFU register */
dkato 7:30ebba78fff0 1055 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1056 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1057 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1058 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1059 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1060 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
dkato 7:30ebba78fff0 1061
dkato 7:30ebba78fff0 1062 /* init FFD register */
dkato 7:30ebba78fff0 1063 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1064 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1065 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1066 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1067 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1068 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1069 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 7:30ebba78fff0 1070
dkato 7:30ebba78fff0 1071 /* init OPC register */
dkato 7:30ebba78fff0 1072 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1073 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1074
dkato 7:30ebba78fff0 1075 /* init IPC register */
dkato 7:30ebba78fff0 1076 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1077 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
dkato 7:30ebba78fff0 1078
dkato 7:30ebba78fff0 1079 /* init MIX register for each channel */
dkato 7:30ebba78fff0 1080 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1081
dkato 7:30ebba78fff0 1082 /* init CIM register for each channel */
dkato 7:30ebba78fff0 1083 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1084 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1085 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1086
dkato 7:30ebba78fff0 1087 /* init shared register */
dkato 7:30ebba78fff0 1088 if (false == init_shared_flag)
dkato 7:30ebba78fff0 1089 {
dkato 7:30ebba78fff0 1090 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1091 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1092 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1093 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1094 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1095 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
dkato 7:30ebba78fff0 1096 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1097 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1098 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1099 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1100 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
dkato 7:30ebba78fff0 1101 }
dkato 7:30ebba78fff0 1102
dkato 7:30ebba78fff0 1103 if (false == init_shared_flag)
dkato 7:30ebba78fff0 1104 {
dkato 7:30ebba78fff0 1105 /* set SSIF register */
dkato 7:30ebba78fff0 1106 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 7:30ebba78fff0 1107 {
dkato 7:30ebba78fff0 1108 gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
dkato 7:30ebba78fff0 1109 }
dkato 7:30ebba78fff0 1110 }
dkato 7:30ebba78fff0 1111
dkato 7:30ebba78fff0 1112 /* set semaphore parameter */
dkato 7:30ebba78fff0 1113 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
dkato 7:30ebba78fff0 1114 if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
dkato 7:30ebba78fff0 1115 {
dkato 7:30ebba78fff0 1116 retval = ENOMEM;
dkato 7:30ebba78fff0 1117 }
dkato 7:30ebba78fff0 1118 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 7:30ebba78fff0 1119 {
dkato 7:30ebba78fff0 1120 for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++)
dkato 7:30ebba78fff0 1121 {
dkato 7:30ebba78fff0 1122 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
dkato 7:30ebba78fff0 1123 if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 7:30ebba78fff0 1124 {
dkato 7:30ebba78fff0 1125 retval = ENOMEM;
dkato 7:30ebba78fff0 1126 }
dkato 7:30ebba78fff0 1127 }
dkato 7:30ebba78fff0 1128 }
dkato 7:30ebba78fff0 1129 if ((ESUCCESS == retval) && (false == init_shared_flag))
dkato 7:30ebba78fff0 1130 {
dkato 7:30ebba78fff0 1131 gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
dkato 7:30ebba78fff0 1132 if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
dkato 7:30ebba78fff0 1133 {
dkato 7:30ebba78fff0 1134 retval = ENOMEM;
dkato 7:30ebba78fff0 1135 }
dkato 7:30ebba78fff0 1136 }
dkato 7:30ebba78fff0 1137
dkato 7:30ebba78fff0 1138 if (false == init_shared_flag)
dkato 7:30ebba78fff0 1139 {
dkato 7:30ebba78fff0 1140 init_shared_flag = true;
dkato 7:30ebba78fff0 1141 }
dkato 7:30ebba78fff0 1142
dkato 7:30ebba78fff0 1143 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
dkato 7:30ebba78fff0 1144 }
dkato 7:30ebba78fff0 1145 }
dkato 7:30ebba78fff0 1146 }
dkato 7:30ebba78fff0 1147
dkato 7:30ebba78fff0 1148 if (ESUCCESS != retval)
dkato 7:30ebba78fff0 1149 {
dkato 7:30ebba78fff0 1150 for (scux_ch_count = SCUX_SSIF_CH_0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 1151 {
dkato 7:30ebba78fff0 1152 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 7:30ebba78fff0 1153 {
dkato 7:30ebba78fff0 1154 /* semaphore delete */
dkato 7:30ebba78fff0 1155 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 7:30ebba78fff0 1156 /* semaphore error check */
dkato 7:30ebba78fff0 1157 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1158 {
dkato 7:30ebba78fff0 1159 /* set error return value */
dkato 7:30ebba78fff0 1160 retval = EFAULT;
dkato 7:30ebba78fff0 1161 }
dkato 7:30ebba78fff0 1162
dkato 7:30ebba78fff0 1163 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
dkato 7:30ebba78fff0 1164 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 1165 }
dkato 7:30ebba78fff0 1166 }
dkato 7:30ebba78fff0 1167
dkato 7:30ebba78fff0 1168 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 7:30ebba78fff0 1169 {
dkato 7:30ebba78fff0 1170 sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 7:30ebba78fff0 1171 /* semaphore error check */
dkato 7:30ebba78fff0 1172 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1173 {
dkato 7:30ebba78fff0 1174 /* set error return value */
dkato 7:30ebba78fff0 1175 retval = EFAULT;
dkato 7:30ebba78fff0 1176 }
dkato 7:30ebba78fff0 1177 }
dkato 7:30ebba78fff0 1178
dkato 7:30ebba78fff0 1179 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 7:30ebba78fff0 1180 /* semaphore error check */
dkato 7:30ebba78fff0 1181 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1182 {
dkato 7:30ebba78fff0 1183 /* set error return value */
dkato 7:30ebba78fff0 1184 retval = EFAULT;
dkato 7:30ebba78fff0 1185 }
dkato 7:30ebba78fff0 1186
dkato 7:30ebba78fff0 1187 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 7:30ebba78fff0 1188 }
dkato 7:30ebba78fff0 1189 else
dkato 7:30ebba78fff0 1190 {
dkato 7:30ebba78fff0 1191 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
dkato 7:30ebba78fff0 1192 }
dkato 7:30ebba78fff0 1193
dkato 7:30ebba78fff0 1194 return retval;
dkato 7:30ebba78fff0 1195 }
dkato 7:30ebba78fff0 1196
dkato 7:30ebba78fff0 1197 /******************************************************************************
dkato 7:30ebba78fff0 1198 End of function SCUX_Initialize
dkato 7:30ebba78fff0 1199 ******************************************************************************/
dkato 7:30ebba78fff0 1200
dkato 7:30ebba78fff0 1201 /**************************************************************************//**
dkato 7:30ebba78fff0 1202 * Function Name: SCUX_UnInitialize
dkato 7:30ebba78fff0 1203 * @brief Uninit SCUX driver.
dkato 7:30ebba78fff0 1204 *
dkato 7:30ebba78fff0 1205 * Description:<br>
dkato 7:30ebba78fff0 1206 *
dkato 7:30ebba78fff0 1207 * @param[in] None.
dkato 7:30ebba78fff0 1208 * @retval None.
dkato 7:30ebba78fff0 1209 ******************************************************************************/
dkato 7:30ebba78fff0 1210 void SCUX_UnInitialize(void)
dkato 7:30ebba78fff0 1211 {
dkato 7:30ebba78fff0 1212 osStatus sem_ercd;
dkato 7:30ebba78fff0 1213 int_t ercd;
dkato 7:30ebba78fff0 1214 int_t scux_ch_count;
dkato 7:30ebba78fff0 1215 int_t ssif_ch_count;
dkato 7:30ebba78fff0 1216 uint32_t cpg_value;
dkato 7:30ebba78fff0 1217 int_t was_masked;
dkato 7:30ebba78fff0 1218
dkato 7:30ebba78fff0 1219 for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 1220 {
dkato 7:30ebba78fff0 1221 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 7:30ebba78fff0 1222 {
dkato 7:30ebba78fff0 1223 /* check ch_stat whether going transfer */
dkato 7:30ebba78fff0 1224 if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 1225 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
dkato 7:30ebba78fff0 1226 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
dkato 7:30ebba78fff0 1227 {
dkato 7:30ebba78fff0 1228 #if defined (__ICCARM__)
dkato 7:30ebba78fff0 1229 was_masked = __disable_irq_iar();
dkato 7:30ebba78fff0 1230 #else
dkato 7:30ebba78fff0 1231 was_masked = __disable_irq();
dkato 7:30ebba78fff0 1232 #endif
dkato 7:30ebba78fff0 1233
dkato 7:30ebba78fff0 1234 /* This exclusive access control ends in the SCUX_IoctlClearStop */
dkato 7:30ebba78fff0 1235 ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
dkato 7:30ebba78fff0 1236 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 1237 {
dkato 7:30ebba78fff0 1238 /* NON_NOTICE_ASSERT: SCUX stop failed */
dkato 7:30ebba78fff0 1239 }
dkato 7:30ebba78fff0 1240
dkato 7:30ebba78fff0 1241 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
dkato 7:30ebba78fff0 1242 if (ESUCCESS != ercd)
dkato 7:30ebba78fff0 1243 {
dkato 7:30ebba78fff0 1244 /* NON_NOTICE_ASSERT: DMA release failed */
dkato 7:30ebba78fff0 1245 }
dkato 7:30ebba78fff0 1246 }
dkato 7:30ebba78fff0 1247 }
dkato 7:30ebba78fff0 1248 }
dkato 7:30ebba78fff0 1249
dkato 7:30ebba78fff0 1250 /* software reset */
dkato 7:30ebba78fff0 1251 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 7:30ebba78fff0 1252
dkato 7:30ebba78fff0 1253 for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
dkato 7:30ebba78fff0 1254 {
dkato 7:30ebba78fff0 1255 if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
dkato 7:30ebba78fff0 1256 {
dkato 7:30ebba78fff0 1257 if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
dkato 7:30ebba78fff0 1258 {
dkato 7:30ebba78fff0 1259 /* NON_NOTICE_ASSERT: abnormal status */
dkato 7:30ebba78fff0 1260 }
dkato 7:30ebba78fff0 1261
dkato 7:30ebba78fff0 1262 /* uninit each resouces */
dkato 7:30ebba78fff0 1263 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
dkato 7:30ebba78fff0 1264
dkato 7:30ebba78fff0 1265 /* delete each semaphore */
dkato 7:30ebba78fff0 1266 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 7:30ebba78fff0 1267 /* semaphore error check */
dkato 7:30ebba78fff0 1268 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1269 {
dkato 7:30ebba78fff0 1270 /* NON_NOTICE_ASSERT: semaphore error */
dkato 7:30ebba78fff0 1271 }
dkato 7:30ebba78fff0 1272
dkato 7:30ebba78fff0 1273 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
dkato 7:30ebba78fff0 1274 /* semaphore error check */
dkato 7:30ebba78fff0 1275 if (osOK != sem_ercd)
dkato 7:30ebba78fff0 1276 {
dkato 7:30ebba78fff0 1277 /* NON_NOTICE_ASSERT: semaphore error */
dkato 7:30ebba78fff0 1278 }
dkato 7:30ebba78fff0 1279
dkato 7:30ebba78fff0 1280 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
dkato 7:30ebba78fff0 1281
dkato 7:30ebba78fff0 1282 /* delete queue */
dkato 7:30ebba78fff0 1283 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 1284 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
dkato 7:30ebba78fff0 1285 ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 7:30ebba78fff0 1286 ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
dkato 7:30ebba78fff0 1287 }
dkato 7:30ebba78fff0 1288 }
dkato 7:30ebba78fff0 1289
dkato 6:aa1fc6a5cc2a 1290 for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 1291 {
dkato 6:aa1fc6a5cc2a 1292 sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 1293 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1294 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1295 {
dkato 6:aa1fc6a5cc2a 1296 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1297 }
dkato 6:aa1fc6a5cc2a 1298
dkato 6:aa1fc6a5cc2a 1299 sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 1300 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1301 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1302 {
dkato 6:aa1fc6a5cc2a 1303 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1304 }
dkato 6:aa1fc6a5cc2a 1305
dkato 6:aa1fc6a5cc2a 1306 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
dkato 6:aa1fc6a5cc2a 1307 }
dkato 6:aa1fc6a5cc2a 1308
dkato 6:aa1fc6a5cc2a 1309 sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 1310 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1311 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1312 {
dkato 6:aa1fc6a5cc2a 1313 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1314 }
dkato 6:aa1fc6a5cc2a 1315
dkato 6:aa1fc6a5cc2a 1316 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 1317 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 1318 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 1319 {
dkato 6:aa1fc6a5cc2a 1320 /* NON_NOTICE_ASSERT: semaphore error */
dkato 6:aa1fc6a5cc2a 1321 }
dkato 6:aa1fc6a5cc2a 1322
dkato 6:aa1fc6a5cc2a 1323 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
dkato 6:aa1fc6a5cc2a 1324
dkato 6:aa1fc6a5cc2a 1325 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 1326 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 1327 #else
dkato 6:aa1fc6a5cc2a 1328 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 1329 #endif
dkato 6:aa1fc6a5cc2a 1330
dkato 6:aa1fc6a5cc2a 1331 /* stop clock for SCUX */
dkato 6:aa1fc6a5cc2a 1332 cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
dkato 6:aa1fc6a5cc2a 1333 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 6:aa1fc6a5cc2a 1334
dkato 6:aa1fc6a5cc2a 1335 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 1336 {
dkato 6:aa1fc6a5cc2a 1337 /* enable all irq */
dkato 6:aa1fc6a5cc2a 1338 __enable_irq();
dkato 6:aa1fc6a5cc2a 1339 }
dkato 6:aa1fc6a5cc2a 1340
dkato 6:aa1fc6a5cc2a 1341 gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
dkato 6:aa1fc6a5cc2a 1342 }
dkato 6:aa1fc6a5cc2a 1343
dkato 6:aa1fc6a5cc2a 1344 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1345 End of function SCUX_UnInitialize
dkato 6:aa1fc6a5cc2a 1346 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1347
dkato 6:aa1fc6a5cc2a 1348 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1349 * Function Name: SCUX_OpenChannel
dkato 6:aa1fc6a5cc2a 1350 * @brief Open SCUX driver channel.
dkato 6:aa1fc6a5cc2a 1351 *
dkato 6:aa1fc6a5cc2a 1352 * Description:<br>
dkato 6:aa1fc6a5cc2a 1353 *
dkato 6:aa1fc6a5cc2a 1354 * @param[in] channel:open channel number.
dkato 6:aa1fc6a5cc2a 1355 * @param[in] flags:specifies the access mode whether the channel is
dkato 6:aa1fc6a5cc2a 1356 * opened for a read or a write
dkato 6:aa1fc6a5cc2a 1357 * @retval ESUCCESS: Operation successful.
dkato 6:aa1fc6a5cc2a 1358 * ENOMEM: Create queue is failed.
dkato 6:aa1fc6a5cc2a 1359 * EMFILE: Allocate DMA ch for write is failed.
dkato 6:aa1fc6a5cc2a 1360 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1361
dkato 6:aa1fc6a5cc2a 1362 int_t SCUX_OpenChannel(const int_t channel, const int_t flags)
dkato 6:aa1fc6a5cc2a 1363 {
dkato 6:aa1fc6a5cc2a 1364 int_t retval;
dkato 6:aa1fc6a5cc2a 1365
dkato 6:aa1fc6a5cc2a 1366 /* create write request queue */
dkato 6:aa1fc6a5cc2a 1367 retval = ahf_create(&gb_scux_info_drv.info_ch[channel].tx_que, AHF_LOCKINT);
dkato 6:aa1fc6a5cc2a 1368 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 1369 {
dkato 6:aa1fc6a5cc2a 1370 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 1371 }
dkato 6:aa1fc6a5cc2a 1372 else
dkato 6:aa1fc6a5cc2a 1373 {
dkato 6:aa1fc6a5cc2a 1374 /* create read request queue */
dkato 6:aa1fc6a5cc2a 1375 retval = ahf_create(&gb_scux_info_drv.info_ch[channel].rx_que, AHF_LOCKINT);
dkato 6:aa1fc6a5cc2a 1376 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 1377 {
dkato 6:aa1fc6a5cc2a 1378 retval = ENOMEM;
dkato 6:aa1fc6a5cc2a 1379 }
dkato 6:aa1fc6a5cc2a 1380 }
dkato 6:aa1fc6a5cc2a 1381
dkato 6:aa1fc6a5cc2a 1382 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1383 {
dkato 6:aa1fc6a5cc2a 1384 SCUX_InterruptInit(channel);
dkato 6:aa1fc6a5cc2a 1385
dkato 6:aa1fc6a5cc2a 1386 /* init channel information parameter */
dkato 6:aa1fc6a5cc2a 1387 gb_scux_info_drv.info_ch[channel].open_flags = flags;
dkato 6:aa1fc6a5cc2a 1388 gb_scux_info_drv.info_ch[channel].p_tx_aio = NULL;
dkato 6:aa1fc6a5cc2a 1389 gb_scux_info_drv.info_ch[channel].p_tx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 1390 gb_scux_info_drv.info_ch[channel].p_rx_aio = NULL;
dkato 6:aa1fc6a5cc2a 1391 gb_scux_info_drv.info_ch[channel].p_rx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 1392 gb_scux_info_drv.info_ch[channel].p_ssif_info1 = NULL;
dkato 6:aa1fc6a5cc2a 1393 gb_scux_info_drv.info_ch[channel].p_ssif_info2 = NULL;
dkato 6:aa1fc6a5cc2a 1394 gb_scux_info_drv.info_ch[channel].p_ssif_info3 = NULL;
dkato 6:aa1fc6a5cc2a 1395 gb_scux_info_drv.info_ch[channel].p_flush_callback = NULL;
dkato 6:aa1fc6a5cc2a 1396 gb_scux_info_drv.info_ch[channel].p_tx_dummy_data = &gb_scux_write_dummy_buf[0];
dkato 6:aa1fc6a5cc2a 1397 gb_scux_info_drv.info_ch[channel].p_rx_dummy_data = &gb_scux_read_dummy_buf[0];
dkato 6:aa1fc6a5cc2a 1398
dkato 6:aa1fc6a5cc2a 1399 /* get DMA channel for write */
dkato 6:aa1fc6a5cc2a 1400 gb_scux_info_drv.info_ch[channel].dma_tx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
dkato 6:aa1fc6a5cc2a 1401 if (EERROR == gb_scux_info_drv.info_ch[channel].dma_tx_ch)
dkato 6:aa1fc6a5cc2a 1402 {
dkato 6:aa1fc6a5cc2a 1403 retval = EMFILE;
dkato 6:aa1fc6a5cc2a 1404 }
dkato 6:aa1fc6a5cc2a 1405 else
dkato 6:aa1fc6a5cc2a 1406 {
dkato 6:aa1fc6a5cc2a 1407 gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_STOP;
dkato 6:aa1fc6a5cc2a 1408 }
dkato 6:aa1fc6a5cc2a 1409
dkato 6:aa1fc6a5cc2a 1410 }
dkato 6:aa1fc6a5cc2a 1411
dkato 6:aa1fc6a5cc2a 1412 return retval;
dkato 6:aa1fc6a5cc2a 1413 }
dkato 6:aa1fc6a5cc2a 1414
dkato 6:aa1fc6a5cc2a 1415 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1416 End of function SCUX_OpenChannel
dkato 6:aa1fc6a5cc2a 1417 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1418
dkato 6:aa1fc6a5cc2a 1419 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1420 * Function Name: SCUX_CloseChannel
dkato 6:aa1fc6a5cc2a 1421 * @brief Close SCUX driver channel.
dkato 6:aa1fc6a5cc2a 1422 *
dkato 6:aa1fc6a5cc2a 1423 * Description:<br>
dkato 6:aa1fc6a5cc2a 1424 *
dkato 6:aa1fc6a5cc2a 1425 * @param[in] channel: SCUX channel number.
dkato 6:aa1fc6a5cc2a 1426 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 1427 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 1428 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1429
dkato 6:aa1fc6a5cc2a 1430 int_t SCUX_CloseChannel(const int_t channel)
dkato 6:aa1fc6a5cc2a 1431 {
dkato 6:aa1fc6a5cc2a 1432 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1433 int_t ercd;
dkato 6:aa1fc6a5cc2a 1434 int_t was_masked;
dkato 6:aa1fc6a5cc2a 1435
dkato 6:aa1fc6a5cc2a 1436 /* check ch_stat whether going transfer */
dkato 6:aa1fc6a5cc2a 1437 if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
dkato 6:aa1fc6a5cc2a 1438 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
dkato 6:aa1fc6a5cc2a 1439 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[channel].ch_stat))
dkato 6:aa1fc6a5cc2a 1440 {
dkato 6:aa1fc6a5cc2a 1441 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 1442 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 1443 #else
dkato 6:aa1fc6a5cc2a 1444 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 1445 #endif
dkato 6:aa1fc6a5cc2a 1446
dkato 6:aa1fc6a5cc2a 1447 /* This exclusive access control ends in the SCUX_IoctlClearStop */
dkato 6:aa1fc6a5cc2a 1448 ercd = SCUX_IoctlClearStop(channel, was_masked);
dkato 6:aa1fc6a5cc2a 1449 if (ESUCCESS != ercd)
dkato 6:aa1fc6a5cc2a 1450 {
dkato 6:aa1fc6a5cc2a 1451 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1452 }
dkato 6:aa1fc6a5cc2a 1453 }
dkato 6:aa1fc6a5cc2a 1454
dkato 6:aa1fc6a5cc2a 1455 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1456 {
dkato 6:aa1fc6a5cc2a 1457 /* delete queue */
dkato 6:aa1fc6a5cc2a 1458 ahf_cancelall(&gb_scux_info_drv.info_ch[channel].tx_que);
dkato 6:aa1fc6a5cc2a 1459 ahf_destroy(&gb_scux_info_drv.info_ch[channel].tx_que);
dkato 6:aa1fc6a5cc2a 1460 ahf_cancelall(&gb_scux_info_drv.info_ch[channel].rx_que);
dkato 6:aa1fc6a5cc2a 1461 ahf_destroy(&gb_scux_info_drv.info_ch[channel].rx_que);
dkato 6:aa1fc6a5cc2a 1462
dkato 6:aa1fc6a5cc2a 1463 SCUX_InterruptUninit(channel);
dkato 6:aa1fc6a5cc2a 1464
dkato 6:aa1fc6a5cc2a 1465 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[channel].dma_tx_ch, NULL);
dkato 6:aa1fc6a5cc2a 1466 if (ESUCCESS != ercd)
dkato 6:aa1fc6a5cc2a 1467 {
dkato 6:aa1fc6a5cc2a 1468 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1469 }
dkato 6:aa1fc6a5cc2a 1470 else
dkato 6:aa1fc6a5cc2a 1471 {
dkato 6:aa1fc6a5cc2a 1472 /* reset error status */
dkato 6:aa1fc6a5cc2a 1473 gb_scux_info_drv.info_ch[channel].err_stat_backup = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1474 /* set channel status to open */
dkato 6:aa1fc6a5cc2a 1475 gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_INIT;
dkato 6:aa1fc6a5cc2a 1476 }
dkato 6:aa1fc6a5cc2a 1477 }
dkato 6:aa1fc6a5cc2a 1478
dkato 6:aa1fc6a5cc2a 1479 return retval;
dkato 6:aa1fc6a5cc2a 1480 }
dkato 6:aa1fc6a5cc2a 1481
dkato 6:aa1fc6a5cc2a 1482 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1483 End of function SCUX_CloseChannel
dkato 6:aa1fc6a5cc2a 1484 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1485
dkato 6:aa1fc6a5cc2a 1486
dkato 6:aa1fc6a5cc2a 1487 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1488 * Function Name: SCUX_CheckParam
dkato 6:aa1fc6a5cc2a 1489 * @brief Check SCUX parameter.
dkato 6:aa1fc6a5cc2a 1490 *
dkato 6:aa1fc6a5cc2a 1491 * Description:<br>
dkato 6:aa1fc6a5cc2a 1492 *
dkato 6:aa1fc6a5cc2a 1493 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 1494 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 1495 * EACCES : DVU setting isn't performed when DVU is used.
dkato 6:aa1fc6a5cc2a 1496 * EACCES : MIX setting isn't performed when MIX is used.
dkato 6:aa1fc6a5cc2a 1497 * EACCES : SSIF setting isn't performed when SSIF is used.
dkato 6:aa1fc6a5cc2a 1498 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 1499 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 1500 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1501
dkato 6:aa1fc6a5cc2a 1502 int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1503 {
dkato 6:aa1fc6a5cc2a 1504 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1505 uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT] = {SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH};
dkato 6:aa1fc6a5cc2a 1506 bool_t use_mix_flag = false;
dkato 6:aa1fc6a5cc2a 1507
dkato 6:aa1fc6a5cc2a 1508 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1509 {
dkato 6:aa1fc6a5cc2a 1510 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1511 }
dkato 6:aa1fc6a5cc2a 1512 else
dkato 6:aa1fc6a5cc2a 1513 {
dkato 6:aa1fc6a5cc2a 1514 /* check route parameter */
dkato 6:aa1fc6a5cc2a 1515 if (((SCUX_ROUTE_SRC_MEM_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MEM_MAX <= p_scux_info_ch->route_set)) &&
dkato 6:aa1fc6a5cc2a 1516 ((SCUX_ROUTE_SRC_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_SSIF_MAX <= p_scux_info_ch->route_set)) &&
dkato 6:aa1fc6a5cc2a 1517 ((SCUX_ROUTE_SRC_MIX_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MIX_SSIF_MAX <= p_scux_info_ch->route_set)))
dkato 6:aa1fc6a5cc2a 1518 {
dkato 6:aa1fc6a5cc2a 1519 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1520 }
dkato 6:aa1fc6a5cc2a 1521 else
dkato 6:aa1fc6a5cc2a 1522 {
dkato 6:aa1fc6a5cc2a 1523 /* check route whether include SCUX channel */
dkato 6:aa1fc6a5cc2a 1524 switch (p_scux_info_ch->channel)
dkato 6:aa1fc6a5cc2a 1525 {
dkato 6:aa1fc6a5cc2a 1526 case SCUX_CH_0:
dkato 6:aa1fc6a5cc2a 1527 if ((SCUX_ROUTE_SRC0_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1528 (SCUX_ROUTE_SRC0_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1529 (SCUX_ROUTE_SRC0_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1530 (SCUX_ROUTE_SRC0_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1531 (SCUX_ROUTE_SRC0_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1532 (SCUX_ROUTE_SRC0_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1533 (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1534 (SCUX_ROUTE_SRC0_SSIF345 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1535 (SCUX_ROUTE_SRC0_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1536 {
dkato 6:aa1fc6a5cc2a 1537 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1538 }
dkato 6:aa1fc6a5cc2a 1539 break;
dkato 6:aa1fc6a5cc2a 1540
dkato 6:aa1fc6a5cc2a 1541 case SCUX_CH_1:
dkato 6:aa1fc6a5cc2a 1542 if ((SCUX_ROUTE_SRC1_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1543 (SCUX_ROUTE_SRC1_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1544 (SCUX_ROUTE_SRC1_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1545 (SCUX_ROUTE_SRC1_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1546 (SCUX_ROUTE_SRC1_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1547 (SCUX_ROUTE_SRC1_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1548 (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1549 (SCUX_ROUTE_SRC1_SSIF345 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1550 (SCUX_ROUTE_SRC1_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1551 {
dkato 6:aa1fc6a5cc2a 1552 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1553 }
dkato 6:aa1fc6a5cc2a 1554 break;
dkato 6:aa1fc6a5cc2a 1555
dkato 6:aa1fc6a5cc2a 1556 case SCUX_CH_2:
dkato 6:aa1fc6a5cc2a 1557 if ((SCUX_ROUTE_SRC2_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1558 (SCUX_ROUTE_SRC2_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1559 (SCUX_ROUTE_SRC2_SSIF1 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1560 (SCUX_ROUTE_SRC2_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1561 (SCUX_ROUTE_SRC2_SSIF4 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1562 (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1563 (SCUX_ROUTE_SRC2_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1564 {
dkato 6:aa1fc6a5cc2a 1565 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1566 }
dkato 6:aa1fc6a5cc2a 1567 break;
dkato 6:aa1fc6a5cc2a 1568
dkato 6:aa1fc6a5cc2a 1569 case SCUX_CH_3:
dkato 6:aa1fc6a5cc2a 1570 if ((SCUX_ROUTE_SRC3_MEM != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1571 (SCUX_ROUTE_SRC3_MIX_SSIF0 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1572 (SCUX_ROUTE_SRC3_SSIF2 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1573 (SCUX_ROUTE_SRC3_MIX_SSIF3 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1574 (SCUX_ROUTE_SRC3_SSIF5 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1575 (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set) &&
dkato 6:aa1fc6a5cc2a 1576 (SCUX_ROUTE_SRC3_MIX_SSIF345 != p_scux_info_ch->route_set))
dkato 6:aa1fc6a5cc2a 1577 {
dkato 6:aa1fc6a5cc2a 1578 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1579 }
dkato 6:aa1fc6a5cc2a 1580 break;
dkato 6:aa1fc6a5cc2a 1581
dkato 6:aa1fc6a5cc2a 1582 default :
dkato 6:aa1fc6a5cc2a 1583 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1584 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1585 break;
dkato 6:aa1fc6a5cc2a 1586
dkato 6:aa1fc6a5cc2a 1587 }
dkato 6:aa1fc6a5cc2a 1588 }
dkato 6:aa1fc6a5cc2a 1589
dkato 6:aa1fc6a5cc2a 1590 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1591 {
dkato 6:aa1fc6a5cc2a 1592 /* set using SSIF channel and MIX information */
dkato 6:aa1fc6a5cc2a 1593 switch (p_scux_info_ch->route_set)
dkato 6:aa1fc6a5cc2a 1594 {
dkato 6:aa1fc6a5cc2a 1595 case SCUX_ROUTE_SRC0_MEM :
dkato 6:aa1fc6a5cc2a 1596 /* fall through */
dkato 6:aa1fc6a5cc2a 1597 case SCUX_ROUTE_SRC1_MEM :
dkato 6:aa1fc6a5cc2a 1598 /* fall through */
dkato 6:aa1fc6a5cc2a 1599 case SCUX_ROUTE_SRC2_MEM :
dkato 6:aa1fc6a5cc2a 1600 /* fall through */
dkato 6:aa1fc6a5cc2a 1601 case SCUX_ROUTE_SRC3_MEM :
dkato 6:aa1fc6a5cc2a 1602 /* do nothing, when mem to mem route is setting */
dkato 6:aa1fc6a5cc2a 1603 break;
dkato 6:aa1fc6a5cc2a 1604
dkato 6:aa1fc6a5cc2a 1605 case SCUX_ROUTE_SRC0_SSIF0 :
dkato 6:aa1fc6a5cc2a 1606 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1607 break;
dkato 6:aa1fc6a5cc2a 1608
dkato 6:aa1fc6a5cc2a 1609 case SCUX_ROUTE_SRC0_SSIF012 :
dkato 6:aa1fc6a5cc2a 1610 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1611 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
dkato 6:aa1fc6a5cc2a 1612 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
dkato 6:aa1fc6a5cc2a 1613 break;
dkato 6:aa1fc6a5cc2a 1614
dkato 6:aa1fc6a5cc2a 1615 case SCUX_ROUTE_SRC0_SSIF3 :
dkato 6:aa1fc6a5cc2a 1616 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1617 break;
dkato 6:aa1fc6a5cc2a 1618
dkato 6:aa1fc6a5cc2a 1619 case SCUX_ROUTE_SRC0_SSIF345 :
dkato 6:aa1fc6a5cc2a 1620 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1621 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
dkato 6:aa1fc6a5cc2a 1622 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
dkato 6:aa1fc6a5cc2a 1623 break;
dkato 6:aa1fc6a5cc2a 1624
dkato 6:aa1fc6a5cc2a 1625 case SCUX_ROUTE_SRC1_SSIF0 :
dkato 6:aa1fc6a5cc2a 1626 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1627 break;
dkato 6:aa1fc6a5cc2a 1628
dkato 6:aa1fc6a5cc2a 1629 case SCUX_ROUTE_SRC1_SSIF012 :
dkato 6:aa1fc6a5cc2a 1630 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
dkato 6:aa1fc6a5cc2a 1631 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
dkato 6:aa1fc6a5cc2a 1632 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
dkato 6:aa1fc6a5cc2a 1633 break;
dkato 6:aa1fc6a5cc2a 1634
dkato 6:aa1fc6a5cc2a 1635 case SCUX_ROUTE_SRC1_SSIF3 :
dkato 6:aa1fc6a5cc2a 1636 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1637 break;
dkato 6:aa1fc6a5cc2a 1638
dkato 6:aa1fc6a5cc2a 1639 case SCUX_ROUTE_SRC1_SSIF345 :
dkato 6:aa1fc6a5cc2a 1640 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
dkato 6:aa1fc6a5cc2a 1641 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
dkato 6:aa1fc6a5cc2a 1642 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
dkato 6:aa1fc6a5cc2a 1643 break;
dkato 6:aa1fc6a5cc2a 1644
dkato 6:aa1fc6a5cc2a 1645 case SCUX_ROUTE_SRC2_SSIF1 :
dkato 6:aa1fc6a5cc2a 1646 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_1;
dkato 6:aa1fc6a5cc2a 1647 break;
dkato 6:aa1fc6a5cc2a 1648
dkato 6:aa1fc6a5cc2a 1649 case SCUX_ROUTE_SRC2_SSIF4 :
dkato 6:aa1fc6a5cc2a 1650 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_4;
dkato 6:aa1fc6a5cc2a 1651 break;
dkato 6:aa1fc6a5cc2a 1652
dkato 6:aa1fc6a5cc2a 1653 case SCUX_ROUTE_SRC3_SSIF2 :
dkato 6:aa1fc6a5cc2a 1654 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_2;
dkato 6:aa1fc6a5cc2a 1655 break;
dkato 6:aa1fc6a5cc2a 1656
dkato 6:aa1fc6a5cc2a 1657 case SCUX_ROUTE_SRC3_SSIF5 :
dkato 6:aa1fc6a5cc2a 1658 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_5;
dkato 6:aa1fc6a5cc2a 1659 break;
dkato 6:aa1fc6a5cc2a 1660
dkato 6:aa1fc6a5cc2a 1661 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1662 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1663 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1664 break;
dkato 6:aa1fc6a5cc2a 1665
dkato 6:aa1fc6a5cc2a 1666 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1667 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1668 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1669 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1670 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1671 break;
dkato 6:aa1fc6a5cc2a 1672
dkato 6:aa1fc6a5cc2a 1673 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1674 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1675 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1676 break;
dkato 6:aa1fc6a5cc2a 1677
dkato 6:aa1fc6a5cc2a 1678 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1679 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1680 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1681 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1682 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1683 break;
dkato 6:aa1fc6a5cc2a 1684
dkato 6:aa1fc6a5cc2a 1685 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1686 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1687 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1688 break;
dkato 6:aa1fc6a5cc2a 1689
dkato 6:aa1fc6a5cc2a 1690 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1691 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1692 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1693 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1694 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1695 break;
dkato 6:aa1fc6a5cc2a 1696
dkato 6:aa1fc6a5cc2a 1697 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1698 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1699 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1700 break;
dkato 6:aa1fc6a5cc2a 1701
dkato 6:aa1fc6a5cc2a 1702 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1703 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1704 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1705 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1706 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1707 break;
dkato 6:aa1fc6a5cc2a 1708
dkato 6:aa1fc6a5cc2a 1709 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1710 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1711 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1712 break;
dkato 6:aa1fc6a5cc2a 1713
dkato 6:aa1fc6a5cc2a 1714 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1715 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1716 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1717 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1718 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1719 break;
dkato 6:aa1fc6a5cc2a 1720
dkato 6:aa1fc6a5cc2a 1721 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1722 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1723 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1724 break;
dkato 6:aa1fc6a5cc2a 1725
dkato 6:aa1fc6a5cc2a 1726 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1727 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1728 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1729 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1730 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1731 break;
dkato 6:aa1fc6a5cc2a 1732
dkato 6:aa1fc6a5cc2a 1733 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1734 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1735 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1736 break;
dkato 6:aa1fc6a5cc2a 1737
dkato 6:aa1fc6a5cc2a 1738 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1739 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
dkato 6:aa1fc6a5cc2a 1740 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
dkato 6:aa1fc6a5cc2a 1741 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
dkato 6:aa1fc6a5cc2a 1742 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1743 break;
dkato 6:aa1fc6a5cc2a 1744
dkato 6:aa1fc6a5cc2a 1745 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1746 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1747 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1748 break;
dkato 6:aa1fc6a5cc2a 1749
dkato 6:aa1fc6a5cc2a 1750 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1751 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
dkato 6:aa1fc6a5cc2a 1752 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
dkato 6:aa1fc6a5cc2a 1753 ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
dkato 6:aa1fc6a5cc2a 1754 use_mix_flag = true;
dkato 6:aa1fc6a5cc2a 1755 break;
dkato 6:aa1fc6a5cc2a 1756
dkato 6:aa1fc6a5cc2a 1757 default :
dkato 6:aa1fc6a5cc2a 1758 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1759 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1760 break;
dkato 6:aa1fc6a5cc2a 1761 }
dkato 6:aa1fc6a5cc2a 1762 }
dkato 6:aa1fc6a5cc2a 1763
dkato 6:aa1fc6a5cc2a 1764 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1765 {
dkato 6:aa1fc6a5cc2a 1766 if (false != p_scux_info_ch->src_cfg.src_enable)
dkato 6:aa1fc6a5cc2a 1767 {
dkato 6:aa1fc6a5cc2a 1768 retval = SCUX_CheckSrcParam(p_scux_info_ch, ssif_ch);
dkato 6:aa1fc6a5cc2a 1769 }
dkato 6:aa1fc6a5cc2a 1770 else
dkato 6:aa1fc6a5cc2a 1771 {
dkato 6:aa1fc6a5cc2a 1772 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1773 {
dkato 6:aa1fc6a5cc2a 1774 /* src disable is async mode only */
dkato 6:aa1fc6a5cc2a 1775 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1776 }
dkato 6:aa1fc6a5cc2a 1777 }
dkato 6:aa1fc6a5cc2a 1778 }
dkato 6:aa1fc6a5cc2a 1779
dkato 6:aa1fc6a5cc2a 1780 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
dkato 6:aa1fc6a5cc2a 1781 {
dkato 6:aa1fc6a5cc2a 1782 /* check parameter for SSIF direct route */
dkato 6:aa1fc6a5cc2a 1783 if ((ESUCCESS == retval) && (false != p_scux_info_ch->dvu_cfg.dvu_enable))
dkato 6:aa1fc6a5cc2a 1784 {
dkato 6:aa1fc6a5cc2a 1785 retval = SCUX_CheckDvuParam(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1786 }
dkato 6:aa1fc6a5cc2a 1787
dkato 6:aa1fc6a5cc2a 1788 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1789 {
dkato 6:aa1fc6a5cc2a 1790 retval = SCUX_CheckSsifParam(p_scux_info_ch, ssif_ch, use_mix_flag);
dkato 6:aa1fc6a5cc2a 1791 }
dkato 6:aa1fc6a5cc2a 1792
dkato 6:aa1fc6a5cc2a 1793 if ((ESUCCESS == retval) && (false != use_mix_flag))
dkato 6:aa1fc6a5cc2a 1794 {
dkato 6:aa1fc6a5cc2a 1795 retval = SCUX_CheckMixParam(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1796 }
dkato 6:aa1fc6a5cc2a 1797 }
dkato 6:aa1fc6a5cc2a 1798 }
dkato 6:aa1fc6a5cc2a 1799
dkato 6:aa1fc6a5cc2a 1800 return retval;
dkato 6:aa1fc6a5cc2a 1801 }
dkato 6:aa1fc6a5cc2a 1802
dkato 6:aa1fc6a5cc2a 1803 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1804 End of function SCUX_CheckParam
dkato 6:aa1fc6a5cc2a 1805 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1806
dkato 6:aa1fc6a5cc2a 1807 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1808 * Function Name: SCUX_CheckSrcParam
dkato 6:aa1fc6a5cc2a 1809 * @brief Check SRC parameter and set rate parameter to SCUX information.
dkato 6:aa1fc6a5cc2a 1810 *
dkato 6:aa1fc6a5cc2a 1811 * Description:<br>
dkato 6:aa1fc6a5cc2a 1812 *
dkato 6:aa1fc6a5cc2a 1813 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 1814 * @param[in] ssif_ch : Used ssif channel number.
dkato 6:aa1fc6a5cc2a 1815 * @param[in] use_mix_flag : Flag of Using MIX .
dkato 6:aa1fc6a5cc2a 1816 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 1817 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 1818 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 1819 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1820
dkato 6:aa1fc6a5cc2a 1821 static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT])
dkato 6:aa1fc6a5cc2a 1822 {
dkato 6:aa1fc6a5cc2a 1823 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 1824 uint32_t ssif_arrange_num;
dkato 6:aa1fc6a5cc2a 1825 uint32_t rate_sample_ratio;
dkato 6:aa1fc6a5cc2a 1826 uint32_t max_conv_rate;
dkato 6:aa1fc6a5cc2a 1827 uint32_t min_conv_rate = 0;
dkato 6:aa1fc6a5cc2a 1828 uint32_t freq_value = 0;
dkato 6:aa1fc6a5cc2a 1829 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 1830 uint32_t max_rate;
dkato 6:aa1fc6a5cc2a 1831
dkato 6:aa1fc6a5cc2a 1832 if ((NULL == p_scux_info_ch) || (NULL == ssif_ch))
dkato 6:aa1fc6a5cc2a 1833 {
dkato 6:aa1fc6a5cc2a 1834 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 1835 }
dkato 6:aa1fc6a5cc2a 1836 else
dkato 6:aa1fc6a5cc2a 1837 {
dkato 6:aa1fc6a5cc2a 1838 /* check use ch */
dkato 6:aa1fc6a5cc2a 1839 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_1 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 1840 {
dkato 6:aa1fc6a5cc2a 1841 if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1842 (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1843 (SCUX_USE_CH_4 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1844 (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1845 (SCUX_USE_CH_8 != p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1846 {
dkato 6:aa1fc6a5cc2a 1847 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1848 }
dkato 6:aa1fc6a5cc2a 1849 }
dkato 6:aa1fc6a5cc2a 1850 else
dkato 6:aa1fc6a5cc2a 1851 {
dkato 6:aa1fc6a5cc2a 1852 /* on SCUX2, SCUX3, enable audio channel is only 1ch and 2ch */
dkato 6:aa1fc6a5cc2a 1853 if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1854 {
dkato 6:aa1fc6a5cc2a 1855 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1856 }
dkato 6:aa1fc6a5cc2a 1857 }
dkato 6:aa1fc6a5cc2a 1858
dkato 6:aa1fc6a5cc2a 1859 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1860 {
dkato 6:aa1fc6a5cc2a 1861 /* if using SSIF, 1ch audio channel is disabled */
dkato 6:aa1fc6a5cc2a 1862 if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]) && (SCUX_USE_CH_1 == p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1863 {
dkato 6:aa1fc6a5cc2a 1864 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1865 }
dkato 6:aa1fc6a5cc2a 1866 }
dkato 6:aa1fc6a5cc2a 1867
dkato 6:aa1fc6a5cc2a 1868 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1869 {
dkato 6:aa1fc6a5cc2a 1870 /* if mutiple SSIF channel and enable TDM mode, only 2ch audio channel is enabled */
dkato 6:aa1fc6a5cc2a 1871 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 1872 {
dkato 6:aa1fc6a5cc2a 1873 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 1874 {
dkato 6:aa1fc6a5cc2a 1875 if (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm)
dkato 6:aa1fc6a5cc2a 1876 {
dkato 6:aa1fc6a5cc2a 1877 if (SCUX_USE_CH_2 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 1878 {
dkato 6:aa1fc6a5cc2a 1879 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1880 }
dkato 6:aa1fc6a5cc2a 1881 }
dkato 6:aa1fc6a5cc2a 1882 }
dkato 6:aa1fc6a5cc2a 1883 }
dkato 6:aa1fc6a5cc2a 1884 }
dkato 6:aa1fc6a5cc2a 1885
dkato 6:aa1fc6a5cc2a 1886 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1887 {
dkato 6:aa1fc6a5cc2a 1888 /* multiple SSIF ch check (multiple SSIF is used SSIF2) */
dkato 6:aa1fc6a5cc2a 1889 if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) && (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1890 {
dkato 6:aa1fc6a5cc2a 1891 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1892 }
dkato 6:aa1fc6a5cc2a 1893 }
dkato 6:aa1fc6a5cc2a 1894
dkato 6:aa1fc6a5cc2a 1895 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1896 {
dkato 6:aa1fc6a5cc2a 1897 /* check word length */
dkato 6:aa1fc6a5cc2a 1898 if ((SCUX_DATA_LEN_MIN >= p_scux_info_ch->src_cfg.word_len) || (SCUX_DATA_LEN_MAX <= p_scux_info_ch->src_cfg.word_len))
dkato 6:aa1fc6a5cc2a 1899 {
dkato 6:aa1fc6a5cc2a 1900 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1901 }
dkato 6:aa1fc6a5cc2a 1902 }
dkato 6:aa1fc6a5cc2a 1903
dkato 6:aa1fc6a5cc2a 1904 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1905 {
dkato 6:aa1fc6a5cc2a 1906 /* check delay mode */
dkato 6:aa1fc6a5cc2a 1907 if ((SCUX_DELAY_MIN >= p_scux_info_ch->src_cfg.delay_mode) || (SCUX_DELAY_MAX <= p_scux_info_ch->src_cfg.delay_mode))
dkato 6:aa1fc6a5cc2a 1908 {
dkato 6:aa1fc6a5cc2a 1909 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1910 }
dkato 6:aa1fc6a5cc2a 1911 else
dkato 6:aa1fc6a5cc2a 1912 {
dkato 6:aa1fc6a5cc2a 1913 /* enable audio channel is less than 2ch when delay mode is enabled */
dkato 6:aa1fc6a5cc2a 1914 if ((SCUX_DELAY_NORMAL != p_scux_info_ch->src_cfg.delay_mode) && (SCUX_USE_CH_2 < p_scux_info_ch->src_cfg.use_ch))
dkato 6:aa1fc6a5cc2a 1915 {
dkato 6:aa1fc6a5cc2a 1916 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1917 }
dkato 6:aa1fc6a5cc2a 1918 }
dkato 6:aa1fc6a5cc2a 1919 }
dkato 6:aa1fc6a5cc2a 1920
dkato 6:aa1fc6a5cc2a 1921 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1922 {
dkato 6:aa1fc6a5cc2a 1923 /* check rate setting */
dkato 6:aa1fc6a5cc2a 1924 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1925 {
dkato 6:aa1fc6a5cc2a 1926 /* check input rate */
dkato 6:aa1fc6a5cc2a 1927 if ((SCUX_SYNC_RATE_8 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1928 (SCUX_SYNC_RATE_11_025 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1929 (SCUX_SYNC_RATE_12 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1930 (SCUX_SYNC_RATE_16 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1931 (SCUX_SYNC_RATE_22_05 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1932 (SCUX_SYNC_RATE_24 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1933 (SCUX_SYNC_RATE_32 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1934 (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1935 (SCUX_SYNC_RATE_48 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1936 (SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1937 (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1938 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync))
dkato 6:aa1fc6a5cc2a 1939 {
dkato 6:aa1fc6a5cc2a 1940 /* enable rate is less than 66KHz on 6ch */
dkato 6:aa1fc6a5cc2a 1941 if ((SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1942 ((SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1943 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
dkato 6:aa1fc6a5cc2a 1944 {
dkato 6:aa1fc6a5cc2a 1945 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1946 }
dkato 6:aa1fc6a5cc2a 1947
dkato 6:aa1fc6a5cc2a 1948 /* enable rate is less than 49KHz on 8ch */
dkato 6:aa1fc6a5cc2a 1949 if ((SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1950 ((SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1951 (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1952 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
dkato 6:aa1fc6a5cc2a 1953 {
dkato 6:aa1fc6a5cc2a 1954 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1955 }
dkato 6:aa1fc6a5cc2a 1956 }
dkato 6:aa1fc6a5cc2a 1957 else
dkato 6:aa1fc6a5cc2a 1958 {
dkato 6:aa1fc6a5cc2a 1959 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1960 }
dkato 6:aa1fc6a5cc2a 1961
dkato 6:aa1fc6a5cc2a 1962 if (ESUCCESS == retval) {
dkato 6:aa1fc6a5cc2a 1963 /* check output rate */
dkato 6:aa1fc6a5cc2a 1964 if ((SCUX_SYNC_RATE_8 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1965 (SCUX_SYNC_RATE_16 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1966 (SCUX_SYNC_RATE_24 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1967 (SCUX_SYNC_RATE_32 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1968 (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1969 (SCUX_SYNC_RATE_48 == p_scux_info_ch->src_cfg.output_rate_sync) ||
dkato 6:aa1fc6a5cc2a 1970 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
dkato 6:aa1fc6a5cc2a 1971 {
dkato 6:aa1fc6a5cc2a 1972 /* enable rate is less than 66KHz on 6ch, enable rate is less than 49KHz on 8ch */
dkato 6:aa1fc6a5cc2a 1973 if ((SCUX_USE_CH_6 <= p_scux_info_ch->src_cfg.use_ch) &&
dkato 6:aa1fc6a5cc2a 1974 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
dkato 6:aa1fc6a5cc2a 1975 {
dkato 6:aa1fc6a5cc2a 1976 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1977 }
dkato 6:aa1fc6a5cc2a 1978 }
dkato 6:aa1fc6a5cc2a 1979 else
dkato 6:aa1fc6a5cc2a 1980 {
dkato 6:aa1fc6a5cc2a 1981 retval = EPERM;
dkato 6:aa1fc6a5cc2a 1982 }
dkato 6:aa1fc6a5cc2a 1983 }
dkato 6:aa1fc6a5cc2a 1984
dkato 6:aa1fc6a5cc2a 1985 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 1986 {
dkato 6:aa1fc6a5cc2a 1987 p_scux_info_ch->input_rate = p_scux_info_ch->src_cfg.input_rate_sync;
dkato 6:aa1fc6a5cc2a 1988 p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_rate_sync;
dkato 6:aa1fc6a5cc2a 1989 }
dkato 6:aa1fc6a5cc2a 1990 }
dkato 6:aa1fc6a5cc2a 1991 else
dkato 6:aa1fc6a5cc2a 1992 {
dkato 6:aa1fc6a5cc2a 1993 /* async mode */
dkato 6:aa1fc6a5cc2a 1994 /* check input rate */
dkato 6:aa1fc6a5cc2a 1995 /* get input source clock */
dkato 6:aa1fc6a5cc2a 1996 switch (p_scux_info_ch->src_cfg.input_clk_async)
dkato 6:aa1fc6a5cc2a 1997 {
dkato 6:aa1fc6a5cc2a 1998 case SCUX_CLK_AUDIO_CLK :
dkato 6:aa1fc6a5cc2a 1999 freq_value = SCUX_AUDIO_CLK;
dkato 6:aa1fc6a5cc2a 2000 break;
dkato 6:aa1fc6a5cc2a 2001
dkato 6:aa1fc6a5cc2a 2002 case SCUX_CLK_AUDIO_X1 :
dkato 6:aa1fc6a5cc2a 2003 freq_value = SCUX_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 2004 break;
dkato 6:aa1fc6a5cc2a 2005
dkato 6:aa1fc6a5cc2a 2006 case SCUX_CLK_MLB_CLK :
dkato 6:aa1fc6a5cc2a 2007 freq_value = SCUX_MLB_CLK;
dkato 6:aa1fc6a5cc2a 2008 break;
dkato 6:aa1fc6a5cc2a 2009
dkato 6:aa1fc6a5cc2a 2010 case SCUX_CLK_USB_X1 :
dkato 6:aa1fc6a5cc2a 2011 freq_value = SCUX_USB_X1;
dkato 6:aa1fc6a5cc2a 2012 break;
dkato 6:aa1fc6a5cc2a 2013
dkato 6:aa1fc6a5cc2a 2014 case SCUX_CLK_CLKP1_2 :
dkato 6:aa1fc6a5cc2a 2015 freq_value = SCUX_CLKLP1_DIV2;
dkato 6:aa1fc6a5cc2a 2016 break;
dkato 6:aa1fc6a5cc2a 2017
dkato 6:aa1fc6a5cc2a 2018 case SCUX_CLK_MTU_TIOC3A :
dkato 6:aa1fc6a5cc2a 2019 freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
dkato 6:aa1fc6a5cc2a 2020 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2021 {
dkato 6:aa1fc6a5cc2a 2022 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2023 }
dkato 6:aa1fc6a5cc2a 2024 break;
dkato 6:aa1fc6a5cc2a 2025
dkato 6:aa1fc6a5cc2a 2026 case SCUX_CLK_MTU_TIOC4A :
dkato 6:aa1fc6a5cc2a 2027 freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
dkato 6:aa1fc6a5cc2a 2028 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2029 {
dkato 6:aa1fc6a5cc2a 2030 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2031 }
dkato 6:aa1fc6a5cc2a 2032 break;
dkato 6:aa1fc6a5cc2a 2033
dkato 6:aa1fc6a5cc2a 2034 case SCUX_CLK_SSIF0_WS :
dkato 6:aa1fc6a5cc2a 2035 /* fall through */
dkato 6:aa1fc6a5cc2a 2036 case SCUX_CLK_SSIF1_WS :
dkato 6:aa1fc6a5cc2a 2037 /* fall through */
dkato 6:aa1fc6a5cc2a 2038 case SCUX_CLK_SSIF2_WS :
dkato 6:aa1fc6a5cc2a 2039 /* fall through */
dkato 6:aa1fc6a5cc2a 2040 case SCUX_CLK_SSIF3_WS :
dkato 6:aa1fc6a5cc2a 2041 /* fall through */
dkato 6:aa1fc6a5cc2a 2042 case SCUX_CLK_SSIF4_WS :
dkato 6:aa1fc6a5cc2a 2043 /* fall through */
dkato 6:aa1fc6a5cc2a 2044 case SCUX_CLK_SSIF5_WS :
dkato 6:aa1fc6a5cc2a 2045 freq_value = p_scux_info_ch->src_cfg.input_ws;
dkato 6:aa1fc6a5cc2a 2046 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2047 {
dkato 6:aa1fc6a5cc2a 2048 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2049 }
dkato 6:aa1fc6a5cc2a 2050 break;
dkato 6:aa1fc6a5cc2a 2051
dkato 6:aa1fc6a5cc2a 2052 default :
dkato 6:aa1fc6a5cc2a 2053 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2054 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2055 break;
dkato 6:aa1fc6a5cc2a 2056 }
dkato 6:aa1fc6a5cc2a 2057
dkato 6:aa1fc6a5cc2a 2058 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2059 {
dkato 6:aa1fc6a5cc2a 2060 /* check devide rate and devide source clock */
dkato 6:aa1fc6a5cc2a 2061 /* check source clock isn't SSIF WS signal */
dkato 6:aa1fc6a5cc2a 2062 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2063 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2064 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2065 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2066 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 2067 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
dkato 6:aa1fc6a5cc2a 2068 {
dkato 6:aa1fc6a5cc2a 2069 if ((0U != (p_scux_info_ch->src_cfg.input_div_async % SCUX_EVEN_VALUE_DIV)) ||
dkato 6:aa1fc6a5cc2a 2070 (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.input_div_async))
dkato 6:aa1fc6a5cc2a 2071 {
dkato 6:aa1fc6a5cc2a 2072 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2073 }
dkato 6:aa1fc6a5cc2a 2074 else
dkato 6:aa1fc6a5cc2a 2075 {
dkato 6:aa1fc6a5cc2a 2076 if (0U == p_scux_info_ch->src_cfg.input_div_async)
dkato 6:aa1fc6a5cc2a 2077 {
dkato 6:aa1fc6a5cc2a 2078 /* 0 is a same size */
dkato 6:aa1fc6a5cc2a 2079 p_scux_info_ch->input_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2080 }
dkato 6:aa1fc6a5cc2a 2081 else{
dkato 6:aa1fc6a5cc2a 2082 p_scux_info_ch->input_rate = freq_value / p_scux_info_ch->src_cfg.input_div_async;
dkato 6:aa1fc6a5cc2a 2083 }
dkato 6:aa1fc6a5cc2a 2084 }
dkato 6:aa1fc6a5cc2a 2085 }
dkato 6:aa1fc6a5cc2a 2086 else
dkato 6:aa1fc6a5cc2a 2087 {
dkato 6:aa1fc6a5cc2a 2088 p_scux_info_ch->input_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2089 }
dkato 6:aa1fc6a5cc2a 2090
dkato 6:aa1fc6a5cc2a 2091 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2092 {
dkato 6:aa1fc6a5cc2a 2093 /* check input frequency is enable range */
dkato 6:aa1fc6a5cc2a 2094 if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2095 {
dkato 6:aa1fc6a5cc2a 2096 max_rate = SCUX_MAX_FREQ_CH6;
dkato 6:aa1fc6a5cc2a 2097 }
dkato 6:aa1fc6a5cc2a 2098 else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2099 {
dkato 6:aa1fc6a5cc2a 2100 max_rate = SCUX_MAX_FREQ_CH8;
dkato 6:aa1fc6a5cc2a 2101 }
dkato 6:aa1fc6a5cc2a 2102 else
dkato 6:aa1fc6a5cc2a 2103 {
dkato 6:aa1fc6a5cc2a 2104 max_rate = SCUX_MAX_FREQ_CH1_4;
dkato 6:aa1fc6a5cc2a 2105 }
dkato 6:aa1fc6a5cc2a 2106
dkato 6:aa1fc6a5cc2a 2107 if ((SCUX_MIN_FREQ > p_scux_info_ch->input_rate) ||
dkato 6:aa1fc6a5cc2a 2108 (max_rate < p_scux_info_ch->input_rate))
dkato 6:aa1fc6a5cc2a 2109 {
dkato 6:aa1fc6a5cc2a 2110 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2111 }
dkato 6:aa1fc6a5cc2a 2112 }
dkato 6:aa1fc6a5cc2a 2113 }
dkato 6:aa1fc6a5cc2a 2114
dkato 6:aa1fc6a5cc2a 2115 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2116 {
dkato 6:aa1fc6a5cc2a 2117 /* if output route is SSIF direct route ,WS signal frequency is used */
dkato 6:aa1fc6a5cc2a 2118 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
dkato 6:aa1fc6a5cc2a 2119 {
dkato 6:aa1fc6a5cc2a 2120 if ((SCUX_SYNC_RATE_8 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2121 (SCUX_SYNC_RATE_11_025 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2122 (SCUX_SYNC_RATE_12 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2123 (SCUX_SYNC_RATE_16 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2124 (SCUX_SYNC_RATE_22_05 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2125 (SCUX_SYNC_RATE_24 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2126 (SCUX_SYNC_RATE_32 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2127 (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2128 (SCUX_SYNC_RATE_48 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2129 (SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2130 (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.output_ws) ||
dkato 6:aa1fc6a5cc2a 2131 (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_ws))
dkato 6:aa1fc6a5cc2a 2132 {
dkato 6:aa1fc6a5cc2a 2133 p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_ws;
dkato 6:aa1fc6a5cc2a 2134 }
dkato 6:aa1fc6a5cc2a 2135 else
dkato 6:aa1fc6a5cc2a 2136 {
dkato 6:aa1fc6a5cc2a 2137 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2138 }
dkato 6:aa1fc6a5cc2a 2139 }
dkato 6:aa1fc6a5cc2a 2140 else
dkato 6:aa1fc6a5cc2a 2141 {
dkato 6:aa1fc6a5cc2a 2142 /* check output rate (mem to mem)*/
dkato 6:aa1fc6a5cc2a 2143 /* get output source clock */
dkato 6:aa1fc6a5cc2a 2144 switch (p_scux_info_ch->src_cfg.output_clk_async)
dkato 6:aa1fc6a5cc2a 2145 {
dkato 6:aa1fc6a5cc2a 2146 case SCUX_CLK_AUDIO_CLK :
dkato 6:aa1fc6a5cc2a 2147 freq_value = SCUX_AUDIO_CLK;
dkato 6:aa1fc6a5cc2a 2148 break;
dkato 6:aa1fc6a5cc2a 2149
dkato 6:aa1fc6a5cc2a 2150 case SCUX_CLK_AUDIO_X1 :
dkato 6:aa1fc6a5cc2a 2151 freq_value = SCUX_AUDIO_X1;
dkato 6:aa1fc6a5cc2a 2152 break;
dkato 6:aa1fc6a5cc2a 2153
dkato 6:aa1fc6a5cc2a 2154 case SCUX_CLK_MLB_CLK :
dkato 6:aa1fc6a5cc2a 2155 freq_value = SCUX_MLB_CLK;
dkato 6:aa1fc6a5cc2a 2156 break;
dkato 6:aa1fc6a5cc2a 2157
dkato 6:aa1fc6a5cc2a 2158 case SCUX_CLK_USB_X1 :
dkato 6:aa1fc6a5cc2a 2159 freq_value = SCUX_USB_X1;
dkato 6:aa1fc6a5cc2a 2160 break;
dkato 6:aa1fc6a5cc2a 2161
dkato 6:aa1fc6a5cc2a 2162 case SCUX_CLK_CLKP1_2 :
dkato 6:aa1fc6a5cc2a 2163 freq_value = SCUX_CLKLP1_DIV2;
dkato 6:aa1fc6a5cc2a 2164 break;
dkato 6:aa1fc6a5cc2a 2165
dkato 6:aa1fc6a5cc2a 2166 case SCUX_CLK_MTU_TIOC3A :
dkato 6:aa1fc6a5cc2a 2167 freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
dkato 6:aa1fc6a5cc2a 2168 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2169 {
dkato 6:aa1fc6a5cc2a 2170 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2171 }
dkato 6:aa1fc6a5cc2a 2172 break;
dkato 6:aa1fc6a5cc2a 2173
dkato 6:aa1fc6a5cc2a 2174 case SCUX_CLK_MTU_TIOC4A :
dkato 6:aa1fc6a5cc2a 2175 freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
dkato 6:aa1fc6a5cc2a 2176 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2177 {
dkato 6:aa1fc6a5cc2a 2178 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2179 }
dkato 6:aa1fc6a5cc2a 2180 break;
dkato 6:aa1fc6a5cc2a 2181
dkato 6:aa1fc6a5cc2a 2182 case SCUX_CLK_SSIF0_WS :
dkato 6:aa1fc6a5cc2a 2183 /* fall through */
dkato 6:aa1fc6a5cc2a 2184 case SCUX_CLK_SSIF1_WS :
dkato 6:aa1fc6a5cc2a 2185 /* fall through */
dkato 6:aa1fc6a5cc2a 2186 case SCUX_CLK_SSIF2_WS :
dkato 6:aa1fc6a5cc2a 2187 /* fall through */
dkato 6:aa1fc6a5cc2a 2188 case SCUX_CLK_SSIF3_WS :
dkato 6:aa1fc6a5cc2a 2189 /* fall through */
dkato 6:aa1fc6a5cc2a 2190 case SCUX_CLK_SSIF4_WS :
dkato 6:aa1fc6a5cc2a 2191 /* fall through */
dkato 6:aa1fc6a5cc2a 2192 case SCUX_CLK_SSIF5_WS :
dkato 6:aa1fc6a5cc2a 2193 freq_value = p_scux_info_ch->src_cfg.output_ws;
dkato 6:aa1fc6a5cc2a 2194 if (0U == freq_value)
dkato 6:aa1fc6a5cc2a 2195 {
dkato 6:aa1fc6a5cc2a 2196 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2197 }
dkato 6:aa1fc6a5cc2a 2198 break;
dkato 6:aa1fc6a5cc2a 2199
dkato 6:aa1fc6a5cc2a 2200 default :
dkato 6:aa1fc6a5cc2a 2201 /* error check is gone when route is other than SSIF */
dkato 6:aa1fc6a5cc2a 2202 if (SCUX_ROUTE_SSIF != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2203 {
dkato 6:aa1fc6a5cc2a 2204 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2205 }
dkato 6:aa1fc6a5cc2a 2206 break;
dkato 6:aa1fc6a5cc2a 2207 }
dkato 6:aa1fc6a5cc2a 2208 }
dkato 6:aa1fc6a5cc2a 2209
dkato 6:aa1fc6a5cc2a 2210 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2211 {
dkato 6:aa1fc6a5cc2a 2212 /* check devide rate on only except for SSIF route, MISRA R1.1 mesure */
dkato 6:aa1fc6a5cc2a 2213 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2214 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2215 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2216 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2217 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2218 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
dkato 6:aa1fc6a5cc2a 2219 {
dkato 6:aa1fc6a5cc2a 2220 if ((0U != (p_scux_info_ch->src_cfg.output_div_async % SCUX_EVEN_VALUE_DIV)) ||
dkato 6:aa1fc6a5cc2a 2221 (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.output_div_async))
dkato 6:aa1fc6a5cc2a 2222 {
dkato 6:aa1fc6a5cc2a 2223 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2224 }
dkato 6:aa1fc6a5cc2a 2225 }
dkato 6:aa1fc6a5cc2a 2226 }
dkato 6:aa1fc6a5cc2a 2227
dkato 6:aa1fc6a5cc2a 2228 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2229 {
dkato 6:aa1fc6a5cc2a 2230 /* check source clock isn't SSIF WS signal */
dkato 6:aa1fc6a5cc2a 2231 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2232 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2233 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2234 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2235 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
dkato 6:aa1fc6a5cc2a 2236 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
dkato 6:aa1fc6a5cc2a 2237 {
dkato 6:aa1fc6a5cc2a 2238 if (0U == p_scux_info_ch->src_cfg.output_div_async)
dkato 6:aa1fc6a5cc2a 2239 {
dkato 6:aa1fc6a5cc2a 2240 /* 0 is a same size */
dkato 6:aa1fc6a5cc2a 2241 p_scux_info_ch->output_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2242 }
dkato 6:aa1fc6a5cc2a 2243 else
dkato 6:aa1fc6a5cc2a 2244 {
dkato 6:aa1fc6a5cc2a 2245 p_scux_info_ch->output_rate = freq_value / p_scux_info_ch->src_cfg.output_div_async;
dkato 6:aa1fc6a5cc2a 2246 }
dkato 6:aa1fc6a5cc2a 2247 }
dkato 6:aa1fc6a5cc2a 2248 else
dkato 6:aa1fc6a5cc2a 2249 {
dkato 6:aa1fc6a5cc2a 2250 p_scux_info_ch->output_rate = freq_value;
dkato 6:aa1fc6a5cc2a 2251 }
dkato 6:aa1fc6a5cc2a 2252 /* check input frequency is enable range */
dkato 6:aa1fc6a5cc2a 2253 if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2254 {
dkato 6:aa1fc6a5cc2a 2255 max_rate = SCUX_MAX_FREQ_CH6;
dkato 6:aa1fc6a5cc2a 2256 }
dkato 6:aa1fc6a5cc2a 2257 else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2258 {
dkato 6:aa1fc6a5cc2a 2259 max_rate = SCUX_MAX_FREQ_CH8;
dkato 6:aa1fc6a5cc2a 2260 }
dkato 6:aa1fc6a5cc2a 2261 else
dkato 6:aa1fc6a5cc2a 2262 {
dkato 6:aa1fc6a5cc2a 2263 max_rate = SCUX_MAX_FREQ_CH1_4;
dkato 6:aa1fc6a5cc2a 2264 }
dkato 6:aa1fc6a5cc2a 2265
dkato 6:aa1fc6a5cc2a 2266 if ((SCUX_MIN_FREQ > p_scux_info_ch->output_rate) ||
dkato 6:aa1fc6a5cc2a 2267 (max_rate < p_scux_info_ch->output_rate))
dkato 6:aa1fc6a5cc2a 2268 {
dkato 6:aa1fc6a5cc2a 2269 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2270 }
dkato 6:aa1fc6a5cc2a 2271
dkato 6:aa1fc6a5cc2a 2272 }
dkato 6:aa1fc6a5cc2a 2273 }
dkato 6:aa1fc6a5cc2a 2274 }
dkato 6:aa1fc6a5cc2a 2275
dkato 6:aa1fc6a5cc2a 2276 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2277 {
dkato 6:aa1fc6a5cc2a 2278 /* check convert rate range */
dkato 6:aa1fc6a5cc2a 2279 max_conv_rate = SCUX_MAX_CONV_RATE;
dkato 6:aa1fc6a5cc2a 2280 switch (p_scux_info_ch->src_cfg.delay_mode)
dkato 6:aa1fc6a5cc2a 2281 {
dkato 6:aa1fc6a5cc2a 2282 case SCUX_DELAY_NORMAL :
dkato 6:aa1fc6a5cc2a 2283 switch (p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2284 {
dkato 6:aa1fc6a5cc2a 2285 case SCUX_USE_CH_1 :
dkato 6:aa1fc6a5cc2a 2286 /* fall through */
dkato 6:aa1fc6a5cc2a 2287 case SCUX_USE_CH_2 :
dkato 6:aa1fc6a5cc2a 2288 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH1_2;
dkato 6:aa1fc6a5cc2a 2289 break;
dkato 6:aa1fc6a5cc2a 2290
dkato 6:aa1fc6a5cc2a 2291 case SCUX_USE_CH_4 :
dkato 6:aa1fc6a5cc2a 2292 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH4;
dkato 6:aa1fc6a5cc2a 2293 break;
dkato 6:aa1fc6a5cc2a 2294
dkato 6:aa1fc6a5cc2a 2295 case SCUX_USE_CH_6 :
dkato 6:aa1fc6a5cc2a 2296 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH6;
dkato 6:aa1fc6a5cc2a 2297 break;
dkato 6:aa1fc6a5cc2a 2298
dkato 6:aa1fc6a5cc2a 2299 case SCUX_USE_CH_8 :
dkato 6:aa1fc6a5cc2a 2300 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH8;
dkato 6:aa1fc6a5cc2a 2301 break;
dkato 6:aa1fc6a5cc2a 2302
dkato 6:aa1fc6a5cc2a 2303 default :
dkato 6:aa1fc6a5cc2a 2304 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2305 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2306 break;
dkato 6:aa1fc6a5cc2a 2307 }
dkato 6:aa1fc6a5cc2a 2308 break;
dkato 6:aa1fc6a5cc2a 2309
dkato 6:aa1fc6a5cc2a 2310 case SCUX_DELAY_LOW_DELAY1 :
dkato 6:aa1fc6a5cc2a 2311 min_conv_rate = SCUX_MIN_CONV_RATE_DELAY1;
dkato 6:aa1fc6a5cc2a 2312 break;
dkato 6:aa1fc6a5cc2a 2313
dkato 6:aa1fc6a5cc2a 2314 case SCUX_DELAY_LOW_DELAY2 :
dkato 6:aa1fc6a5cc2a 2315 min_conv_rate = SCUX_MIN_CONV_RATE_DELAY2;
dkato 6:aa1fc6a5cc2a 2316 break;
dkato 6:aa1fc6a5cc2a 2317
dkato 6:aa1fc6a5cc2a 2318 default :
dkato 6:aa1fc6a5cc2a 2319 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2320 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2321 break;
dkato 6:aa1fc6a5cc2a 2322 }
dkato 6:aa1fc6a5cc2a 2323
dkato 6:aa1fc6a5cc2a 2324 rate_sample_ratio = ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate);
dkato 6:aa1fc6a5cc2a 2325 if ((min_conv_rate > rate_sample_ratio) || (max_conv_rate < rate_sample_ratio))
dkato 6:aa1fc6a5cc2a 2326 {
dkato 6:aa1fc6a5cc2a 2327 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2328 }
dkato 6:aa1fc6a5cc2a 2329 }
dkato 6:aa1fc6a5cc2a 2330 }
dkato 6:aa1fc6a5cc2a 2331
dkato 6:aa1fc6a5cc2a 2332 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2333 {
dkato 6:aa1fc6a5cc2a 2334 /* check wait time */
dkato 6:aa1fc6a5cc2a 2335 if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->src_cfg.wait_sample)
dkato 6:aa1fc6a5cc2a 2336 {
dkato 6:aa1fc6a5cc2a 2337 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2338 }
dkato 6:aa1fc6a5cc2a 2339 }
dkato 6:aa1fc6a5cc2a 2340
dkato 6:aa1fc6a5cc2a 2341 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2342 {
dkato 6:aa1fc6a5cc2a 2343 /* check min rate ratio */
dkato 6:aa1fc6a5cc2a 2344 if ((SCUX_MIN_RATE_MIN_PAERCENTAGE > (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) ||
dkato 6:aa1fc6a5cc2a 2345 (SCUX_MIN_RATE_MAX_PAERCENTAGE < (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage))
dkato 6:aa1fc6a5cc2a 2346 {
dkato 6:aa1fc6a5cc2a 2347 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2348 }
dkato 6:aa1fc6a5cc2a 2349 }
dkato 6:aa1fc6a5cc2a 2350
dkato 6:aa1fc6a5cc2a 2351 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2352 {
dkato 6:aa1fc6a5cc2a 2353 /* check input data position */
dkato 6:aa1fc6a5cc2a 2354 for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
dkato 6:aa1fc6a5cc2a 2355 {
dkato 6:aa1fc6a5cc2a 2356 if ((SCUX_AUDIO_CH_MIN >= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]) ||
dkato 6:aa1fc6a5cc2a 2357 (SCUX_AUDIO_CH_MAX <= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]))
dkato 6:aa1fc6a5cc2a 2358 {
dkato 6:aa1fc6a5cc2a 2359 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2360 }
dkato 6:aa1fc6a5cc2a 2361 }
dkato 6:aa1fc6a5cc2a 2362 }
dkato 6:aa1fc6a5cc2a 2363 }
dkato 6:aa1fc6a5cc2a 2364
dkato 6:aa1fc6a5cc2a 2365 return retval;
dkato 6:aa1fc6a5cc2a 2366 }
dkato 6:aa1fc6a5cc2a 2367
dkato 6:aa1fc6a5cc2a 2368 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2369 End of function SCUX_CheckSrcParam
dkato 6:aa1fc6a5cc2a 2370 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2371
dkato 6:aa1fc6a5cc2a 2372 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2373 * Function Name: SCUX_CheckDvuParam
dkato 6:aa1fc6a5cc2a 2374 * @brief Check DVU parameter.
dkato 6:aa1fc6a5cc2a 2375 *
dkato 6:aa1fc6a5cc2a 2376 * Description:<br>
dkato 6:aa1fc6a5cc2a 2377 *
dkato 6:aa1fc6a5cc2a 2378 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 2379 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2380 * EACCES : DVU setting isn't performed when DVU is used.
dkato 6:aa1fc6a5cc2a 2381 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 2382 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2383 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2384
dkato 6:aa1fc6a5cc2a 2385 static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2386 {
dkato 6:aa1fc6a5cc2a 2387 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2388 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 2389 uint32_t enable_ch_flag = false;
dkato 6:aa1fc6a5cc2a 2390
dkato 6:aa1fc6a5cc2a 2391 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2392 {
dkato 6:aa1fc6a5cc2a 2393 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2394 }
dkato 6:aa1fc6a5cc2a 2395 else
dkato 6:aa1fc6a5cc2a 2396 {
dkato 6:aa1fc6a5cc2a 2397 if (false == p_scux_info_ch->dvu_setup)
dkato 6:aa1fc6a5cc2a 2398 {
dkato 6:aa1fc6a5cc2a 2399 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2400 }
dkato 6:aa1fc6a5cc2a 2401 else
dkato 6:aa1fc6a5cc2a 2402 {
dkato 6:aa1fc6a5cc2a 2403 if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
dkato 6:aa1fc6a5cc2a 2404 {
dkato 6:aa1fc6a5cc2a 2405 /* check digital volume value */
dkato 6:aa1fc6a5cc2a 2406 if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
dkato 6:aa1fc6a5cc2a 2407 {
dkato 6:aa1fc6a5cc2a 2408 /* check digital volume value */
dkato 6:aa1fc6a5cc2a 2409 for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
dkato 6:aa1fc6a5cc2a 2410 {
dkato 6:aa1fc6a5cc2a 2411 if (SCUX_MAX_DIGITAL_VOLUME < p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
dkato 6:aa1fc6a5cc2a 2412 {
dkato 6:aa1fc6a5cc2a 2413 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2414 }
dkato 6:aa1fc6a5cc2a 2415 }
dkato 6:aa1fc6a5cc2a 2416 }
dkato 6:aa1fc6a5cc2a 2417
dkato 6:aa1fc6a5cc2a 2418 /* check ramp volume value */
dkato 6:aa1fc6a5cc2a 2419 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 2420 {
dkato 6:aa1fc6a5cc2a 2421 enable_ch_flag |= (uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch];
dkato 6:aa1fc6a5cc2a 2422 }
dkato 6:aa1fc6a5cc2a 2423
dkato 6:aa1fc6a5cc2a 2424 if ((ESUCCESS == retval) && (false != (bool_t)enable_ch_flag))
dkato 6:aa1fc6a5cc2a 2425 {
dkato 6:aa1fc6a5cc2a 2426 /* check ramp up period */
dkato 6:aa1fc6a5cc2a 2427 if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
dkato 6:aa1fc6a5cc2a 2428 (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
dkato 6:aa1fc6a5cc2a 2429 {
dkato 6:aa1fc6a5cc2a 2430 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2431 }
dkato 6:aa1fc6a5cc2a 2432
dkato 6:aa1fc6a5cc2a 2433 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2434 {
dkato 6:aa1fc6a5cc2a 2435 /* check ramp down period */
dkato 6:aa1fc6a5cc2a 2436 if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
dkato 6:aa1fc6a5cc2a 2437 (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
dkato 6:aa1fc6a5cc2a 2438 {
dkato 6:aa1fc6a5cc2a 2439 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2440 }
dkato 6:aa1fc6a5cc2a 2441 }
dkato 6:aa1fc6a5cc2a 2442
dkato 6:aa1fc6a5cc2a 2443 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2444 {
dkato 6:aa1fc6a5cc2a 2445 /* check ramp volume */
dkato 6:aa1fc6a5cc2a 2446 if (SCUX_MAX_RAMP_VOLUME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
dkato 6:aa1fc6a5cc2a 2447 {
dkato 6:aa1fc6a5cc2a 2448 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2449 }
dkato 6:aa1fc6a5cc2a 2450 }
dkato 6:aa1fc6a5cc2a 2451
dkato 6:aa1fc6a5cc2a 2452 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 2453 {
dkato 6:aa1fc6a5cc2a 2454 /* check wait time */
dkato 6:aa1fc6a5cc2a 2455 if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
dkato 6:aa1fc6a5cc2a 2456 {
dkato 6:aa1fc6a5cc2a 2457 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2458 }
dkato 6:aa1fc6a5cc2a 2459 }
dkato 6:aa1fc6a5cc2a 2460 }
dkato 6:aa1fc6a5cc2a 2461 }
dkato 6:aa1fc6a5cc2a 2462 }
dkato 6:aa1fc6a5cc2a 2463 }
dkato 6:aa1fc6a5cc2a 2464
dkato 6:aa1fc6a5cc2a 2465 return retval;
dkato 6:aa1fc6a5cc2a 2466 }
dkato 6:aa1fc6a5cc2a 2467
dkato 6:aa1fc6a5cc2a 2468 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2469 End of function SCUX_CheckDvuParam
dkato 6:aa1fc6a5cc2a 2470 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2471
dkato 6:aa1fc6a5cc2a 2472 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2473 * Function Name: SCUX_CheckSsifParam
dkato 6:aa1fc6a5cc2a 2474 * @brief Check SSIF parameter.
dkato 6:aa1fc6a5cc2a 2475 *
dkato 6:aa1fc6a5cc2a 2476 * Description:<br>
dkato 6:aa1fc6a5cc2a 2477 *
dkato 6:aa1fc6a5cc2a 2478 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2479 * @param[in] ssif_ch : Used ssif channel number.
dkato 6:aa1fc6a5cc2a 2480 * @param[in] use_mix_flag : Flag of Using MIX .
dkato 6:aa1fc6a5cc2a 2481 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2482 * EACCES : SSIF setting isn't performed when SSIF is used.
dkato 6:aa1fc6a5cc2a 2483 * EACCES : SSIF channel is already used.
dkato 6:aa1fc6a5cc2a 2484 * EACCES : When use MIX, it is a setup which does not agree in a route setup.
dkato 6:aa1fc6a5cc2a 2485 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 2486 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2487 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2488
dkato 6:aa1fc6a5cc2a 2489 static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag)
dkato 6:aa1fc6a5cc2a 2490 {
dkato 6:aa1fc6a5cc2a 2491 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2492 uint32_t ssif_arrange_num;
dkato 6:aa1fc6a5cc2a 2493 uint32_t mix_ssif_ch_bit = 0;
dkato 6:aa1fc6a5cc2a 2494 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2495
dkato 6:aa1fc6a5cc2a 2496 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch) || (NULL == ssif_ch))
dkato 6:aa1fc6a5cc2a 2497 {
dkato 6:aa1fc6a5cc2a 2498 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2499 }
dkato 6:aa1fc6a5cc2a 2500 else
dkato 6:aa1fc6a5cc2a 2501 {
dkato 6:aa1fc6a5cc2a 2502 if (false == use_mix_flag)
dkato 6:aa1fc6a5cc2a 2503 {
dkato 6:aa1fc6a5cc2a 2504 /* used SSIF channel check no used MIX route */
dkato 6:aa1fc6a5cc2a 2505 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2506 {
dkato 6:aa1fc6a5cc2a 2507 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 2508 {
dkato 6:aa1fc6a5cc2a 2509 /* check SSIF is already setup */
dkato 6:aa1fc6a5cc2a 2510 if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
dkato 6:aa1fc6a5cc2a 2511 {
dkato 6:aa1fc6a5cc2a 2512 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2513 }
dkato 6:aa1fc6a5cc2a 2514 else
dkato 6:aa1fc6a5cc2a 2515 {
dkato 6:aa1fc6a5cc2a 2516 /* used SSIF channel is checked by other SCUX channel */
dkato 6:aa1fc6a5cc2a 2517 if (0 != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel)
dkato 6:aa1fc6a5cc2a 2518 {
dkato 6:aa1fc6a5cc2a 2519 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2520 }
dkato 6:aa1fc6a5cc2a 2521 }
dkato 6:aa1fc6a5cc2a 2522 }
dkato 6:aa1fc6a5cc2a 2523 }
dkato 6:aa1fc6a5cc2a 2524 }
dkato 6:aa1fc6a5cc2a 2525 else
dkato 6:aa1fc6a5cc2a 2526 {
dkato 6:aa1fc6a5cc2a 2527 /* used SSIF channel check on MIX route */
dkato 6:aa1fc6a5cc2a 2528 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2529 {
dkato 6:aa1fc6a5cc2a 2530 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 2531 {
dkato 6:aa1fc6a5cc2a 2532 /* clear SCUX_SSIF_use_mix_flag and get SSIF channel number */
dkato 6:aa1fc6a5cc2a 2533 mix_ssif_ch_bit |= (1U << ssif_ch[ssif_arrange_num]);
dkato 6:aa1fc6a5cc2a 2534 /* check SSIF is already setup */
dkato 6:aa1fc6a5cc2a 2535 if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
dkato 6:aa1fc6a5cc2a 2536 {
dkato 6:aa1fc6a5cc2a 2537 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2538 }
dkato 6:aa1fc6a5cc2a 2539 }
dkato 6:aa1fc6a5cc2a 2540 }
dkato 6:aa1fc6a5cc2a 2541 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2542 {
dkato 6:aa1fc6a5cc2a 2543 /* used SSIF channel check, on MIX route check */
dkato 6:aa1fc6a5cc2a 2544 if (0U != p_info_drv->shared_info.mix_ssif_ch)
dkato 6:aa1fc6a5cc2a 2545 {
dkato 6:aa1fc6a5cc2a 2546 /* In the MIX setup for the and after 2times, it is checked that same SSIF ch on 1st setting is set up */
dkato 6:aa1fc6a5cc2a 2547 if (p_info_drv->shared_info.mix_ssif_ch != mix_ssif_ch_bit)
dkato 6:aa1fc6a5cc2a 2548 {
dkato 6:aa1fc6a5cc2a 2549 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2550 }
dkato 6:aa1fc6a5cc2a 2551 }
dkato 6:aa1fc6a5cc2a 2552 else
dkato 6:aa1fc6a5cc2a 2553 {
dkato 6:aa1fc6a5cc2a 2554 /*It checks that SSIF channel is not used once on first MIX setup */
dkato 6:aa1fc6a5cc2a 2555 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
dkato 6:aa1fc6a5cc2a 2556 {
dkato 6:aa1fc6a5cc2a 2557 if ((0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel) ||
dkato 6:aa1fc6a5cc2a 2558 (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]].scux_channel) ||
dkato 6:aa1fc6a5cc2a 2559 (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]].scux_channel))
dkato 6:aa1fc6a5cc2a 2560 {
dkato 6:aa1fc6a5cc2a 2561 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2562 }
dkato 6:aa1fc6a5cc2a 2563 }
dkato 6:aa1fc6a5cc2a 2564 else
dkato 6:aa1fc6a5cc2a 2565 {
dkato 6:aa1fc6a5cc2a 2566 if (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel)
dkato 6:aa1fc6a5cc2a 2567 {
dkato 6:aa1fc6a5cc2a 2568 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2569 }
dkato 6:aa1fc6a5cc2a 2570 }
dkato 6:aa1fc6a5cc2a 2571 }
dkato 6:aa1fc6a5cc2a 2572 }
dkato 6:aa1fc6a5cc2a 2573 }
dkato 6:aa1fc6a5cc2a 2574
dkato 6:aa1fc6a5cc2a 2575 /* each SSIF parameter check */
dkato 6:aa1fc6a5cc2a 2576 for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2577 {
dkato 6:aa1fc6a5cc2a 2578 /* used SSIF channel check, on SSIF direct route check */
dkato 6:aa1fc6a5cc2a 2579 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
dkato 6:aa1fc6a5cc2a 2580 {
dkato 6:aa1fc6a5cc2a 2581
dkato 6:aa1fc6a5cc2a 2582 /* check system word */
dkato 6:aa1fc6a5cc2a 2583 if ((gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word <= SCUX_SSIF_SYSTEM_LEN_MIN) ||
dkato 6:aa1fc6a5cc2a 2584 (gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word >= SCUX_SSIF_SYSTEM_LEN_MAX))
dkato 6:aa1fc6a5cc2a 2585 {
dkato 6:aa1fc6a5cc2a 2586 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2587 }
dkato 6:aa1fc6a5cc2a 2588 else
dkato 6:aa1fc6a5cc2a 2589 {
dkato 6:aa1fc6a5cc2a 2590 /* check system word >= data word */
dkato 6:aa1fc6a5cc2a 2591 /* The combination applicable to error only of data word of 24bit and system word of 16bit */
dkato 6:aa1fc6a5cc2a 2592 if ((SCUX_DATA_LEN_16 != p_scux_info_ch->src_cfg.word_len) &&
dkato 6:aa1fc6a5cc2a 2593 (SCUX_SSIF_SYSTEM_LEN_16 == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word))
dkato 6:aa1fc6a5cc2a 2594 {
dkato 6:aa1fc6a5cc2a 2595 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2596 }
dkato 6:aa1fc6a5cc2a 2597 }
dkato 6:aa1fc6a5cc2a 2598
dkato 6:aa1fc6a5cc2a 2599 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2600 {
dkato 6:aa1fc6a5cc2a 2601 /* if multiple channel is used, TDM is disable */
dkato 6:aa1fc6a5cc2a 2602 if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) &&
dkato 6:aa1fc6a5cc2a 2603 (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm))
dkato 6:aa1fc6a5cc2a 2604 {
dkato 6:aa1fc6a5cc2a 2605 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2606 }
dkato 6:aa1fc6a5cc2a 2607 }
dkato 6:aa1fc6a5cc2a 2608 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2609 {
dkato 6:aa1fc6a5cc2a 2610 retval = SCUX_CheckSsifClockDiv(p_scux_info_ch, ssif_ch[ssif_arrange_num]);
dkato 6:aa1fc6a5cc2a 2611 }
dkato 6:aa1fc6a5cc2a 2612
dkato 6:aa1fc6a5cc2a 2613 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2614 {
dkato 6:aa1fc6a5cc2a 2615 gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel
dkato 6:aa1fc6a5cc2a 2616 = (int_t)((uint32_t)gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel | (1U << p_scux_info_ch->channel));
dkato 6:aa1fc6a5cc2a 2617 }
dkato 6:aa1fc6a5cc2a 2618 }
dkato 6:aa1fc6a5cc2a 2619 }
dkato 6:aa1fc6a5cc2a 2620
dkato 6:aa1fc6a5cc2a 2621 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2622 {
dkato 6:aa1fc6a5cc2a 2623 /* set SSIF information structure pointer */
dkato 6:aa1fc6a5cc2a 2624 if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
dkato 6:aa1fc6a5cc2a 2625 {
dkato 6:aa1fc6a5cc2a 2626 p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
dkato 6:aa1fc6a5cc2a 2627 p_scux_info_ch->p_ssif_info2 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]];
dkato 6:aa1fc6a5cc2a 2628 p_scux_info_ch->p_ssif_info3 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]];
dkato 6:aa1fc6a5cc2a 2629 }
dkato 6:aa1fc6a5cc2a 2630 else
dkato 6:aa1fc6a5cc2a 2631 {
dkato 6:aa1fc6a5cc2a 2632 p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
dkato 6:aa1fc6a5cc2a 2633 p_scux_info_ch->p_ssif_info2 = NULL;
dkato 6:aa1fc6a5cc2a 2634 p_scux_info_ch->p_ssif_info3 = NULL;
dkato 6:aa1fc6a5cc2a 2635 }
dkato 6:aa1fc6a5cc2a 2636 }
dkato 6:aa1fc6a5cc2a 2637 }
dkato 6:aa1fc6a5cc2a 2638
dkato 6:aa1fc6a5cc2a 2639 return retval;
dkato 6:aa1fc6a5cc2a 2640 }
dkato 6:aa1fc6a5cc2a 2641
dkato 6:aa1fc6a5cc2a 2642 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2643 End of function SCUX_CheckSsifParam
dkato 6:aa1fc6a5cc2a 2644 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2645
dkato 6:aa1fc6a5cc2a 2646 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2647 * Function Name: SCUX_CheckMixParam
dkato 6:aa1fc6a5cc2a 2648 * @brief Check MIX parameter.
dkato 6:aa1fc6a5cc2a 2649 *
dkato 6:aa1fc6a5cc2a 2650 * Description:<br>
dkato 6:aa1fc6a5cc2a 2651 *
dkato 6:aa1fc6a5cc2a 2652 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 2653 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2654 * EACCES : MIX setting isn't performed when MIX is used.
dkato 6:aa1fc6a5cc2a 2655 * EPERM : Parameter is unexpected value.
dkato 6:aa1fc6a5cc2a 2656 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2657 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2658
dkato 6:aa1fc6a5cc2a 2659 static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2660 {
dkato 6:aa1fc6a5cc2a 2661 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2662 int_t scux_ch;
dkato 6:aa1fc6a5cc2a 2663 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 2664 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2665
dkato 6:aa1fc6a5cc2a 2666 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 2667 {
dkato 6:aa1fc6a5cc2a 2668 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2669 }
dkato 6:aa1fc6a5cc2a 2670 else
dkato 6:aa1fc6a5cc2a 2671 {
dkato 6:aa1fc6a5cc2a 2672 if (false == p_info_drv->shared_info.mix_setup)
dkato 6:aa1fc6a5cc2a 2673 {
dkato 6:aa1fc6a5cc2a 2674 retval = EACCES;
dkato 6:aa1fc6a5cc2a 2675 }
dkato 6:aa1fc6a5cc2a 2676 else
dkato 6:aa1fc6a5cc2a 2677 {
dkato 6:aa1fc6a5cc2a 2678 if (false != p_info_drv->shared_info.mixmode_ramp)
dkato 6:aa1fc6a5cc2a 2679 {
dkato 6:aa1fc6a5cc2a 2680 /* check ramp up time */
dkato 6:aa1fc6a5cc2a 2681 if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.up_period) ||
dkato 6:aa1fc6a5cc2a 2682 (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.up_period))
dkato 6:aa1fc6a5cc2a 2683 {
dkato 6:aa1fc6a5cc2a 2684 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2685 }
dkato 6:aa1fc6a5cc2a 2686
dkato 6:aa1fc6a5cc2a 2687 /* check ramp down time */
dkato 6:aa1fc6a5cc2a 2688 if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.down_period) ||
dkato 6:aa1fc6a5cc2a 2689 (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.down_period))
dkato 6:aa1fc6a5cc2a 2690 {
dkato 6:aa1fc6a5cc2a 2691 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2692 }
dkato 6:aa1fc6a5cc2a 2693 }
dkato 6:aa1fc6a5cc2a 2694
dkato 6:aa1fc6a5cc2a 2695 /* check MIX volume */
dkato 6:aa1fc6a5cc2a 2696 for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (SCUX_CH_NUM > scux_ch)); scux_ch++)
dkato 6:aa1fc6a5cc2a 2697 {
dkato 6:aa1fc6a5cc2a 2698 /* register set on the channel itself which sets up or channel which has already MIX operated */
dkato 6:aa1fc6a5cc2a 2699 if ((scux_ch == p_scux_info_ch->channel) ||
dkato 6:aa1fc6a5cc2a 2700 (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
dkato 6:aa1fc6a5cc2a 2701 {
dkato 6:aa1fc6a5cc2a 2702 if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
dkato 6:aa1fc6a5cc2a 2703 {
dkato 6:aa1fc6a5cc2a 2704 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2705 }
dkato 6:aa1fc6a5cc2a 2706 }
dkato 6:aa1fc6a5cc2a 2707 }
dkato 6:aa1fc6a5cc2a 2708
dkato 6:aa1fc6a5cc2a 2709 /* check output data position */
dkato 6:aa1fc6a5cc2a 2710 for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
dkato 6:aa1fc6a5cc2a 2711 {
dkato 6:aa1fc6a5cc2a 2712 /* check min rate ratio */
dkato 6:aa1fc6a5cc2a 2713 if ((SCUX_AUDIO_CH_MIN >= p_info_drv->shared_info.select_out_data_ch[audio_ch]) ||
dkato 6:aa1fc6a5cc2a 2714 (SCUX_AUDIO_CH_MAX <= p_info_drv->shared_info.select_out_data_ch[audio_ch]))
dkato 6:aa1fc6a5cc2a 2715 {
dkato 6:aa1fc6a5cc2a 2716 retval = EPERM;
dkato 6:aa1fc6a5cc2a 2717 }
dkato 6:aa1fc6a5cc2a 2718 }
dkato 6:aa1fc6a5cc2a 2719 }
dkato 6:aa1fc6a5cc2a 2720 }
dkato 6:aa1fc6a5cc2a 2721
dkato 6:aa1fc6a5cc2a 2722 return retval;
dkato 6:aa1fc6a5cc2a 2723 }
dkato 6:aa1fc6a5cc2a 2724
dkato 6:aa1fc6a5cc2a 2725 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2726 End of function SCUX_CheckMixParam
dkato 6:aa1fc6a5cc2a 2727 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2728
dkato 6:aa1fc6a5cc2a 2729 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2730 * Function Name: SCUX_StrNLen
dkato 6:aa1fc6a5cc2a 2731 * @brief computes the length of the string
dkato 6:aa1fc6a5cc2a 2732 *
dkato 6:aa1fc6a5cc2a 2733 * Description:<br>
dkato 6:aa1fc6a5cc2a 2734 * if string is longer than maxlen, this function return maxlen
dkato 6:aa1fc6a5cc2a 2735 * @param[in] p_str :pointer of string
dkato 6:aa1fc6a5cc2a 2736 * @param[in] maxlen :maximum length of inspection
dkato 6:aa1fc6a5cc2a 2737 * @retval 'number of characters in the string' or 'maxlen'
dkato 6:aa1fc6a5cc2a 2738 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2739 size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen)
dkato 6:aa1fc6a5cc2a 2740 {
dkato 6:aa1fc6a5cc2a 2741 size_t ret_len;
dkato 6:aa1fc6a5cc2a 2742
dkato 6:aa1fc6a5cc2a 2743 if (NULL == p_str)
dkato 6:aa1fc6a5cc2a 2744 {
dkato 6:aa1fc6a5cc2a 2745 /* character string does not exist */
dkato 6:aa1fc6a5cc2a 2746 ret_len = 0;
dkato 6:aa1fc6a5cc2a 2747 }
dkato 6:aa1fc6a5cc2a 2748 else
dkato 6:aa1fc6a5cc2a 2749 {
dkato 6:aa1fc6a5cc2a 2750 /* ->IPA P1.3.1 Even if a sign is positive, even a negative is no problem. */
dkato 6:aa1fc6a5cc2a 2751 for (ret_len = 0; (maxlen != 0U) && (*p_str != '\0'); ret_len++)
dkato 6:aa1fc6a5cc2a 2752 /* <-IPA P1.3.1 */
dkato 6:aa1fc6a5cc2a 2753 {
dkato 6:aa1fc6a5cc2a 2754 maxlen--;
dkato 6:aa1fc6a5cc2a 2755 p_str++;
dkato 6:aa1fc6a5cc2a 2756 }
dkato 6:aa1fc6a5cc2a 2757 }
dkato 6:aa1fc6a5cc2a 2758
dkato 6:aa1fc6a5cc2a 2759 return ret_len;
dkato 6:aa1fc6a5cc2a 2760 }
dkato 6:aa1fc6a5cc2a 2761
dkato 6:aa1fc6a5cc2a 2762 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2763 End of function SCUX_StrNLen
dkato 6:aa1fc6a5cc2a 2764 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2765 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 2766 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2767 * Function Name: SCUX_CmnUnInitialize
dkato 6:aa1fc6a5cc2a 2768 * @brief uninitialize driver infomation.
dkato 6:aa1fc6a5cc2a 2769 *
dkato 6:aa1fc6a5cc2a 2770 * Description:<br>
dkato 6:aa1fc6a5cc2a 2771 *
dkato 6:aa1fc6a5cc2a 2772 * @param[in] None.
dkato 6:aa1fc6a5cc2a 2773 * @retval ESUCCESS : Parameter is no problems.
dkato 6:aa1fc6a5cc2a 2774 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 2775 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2776 static int_t SCUX_CmnUnInitialize(void)
dkato 6:aa1fc6a5cc2a 2777 {
dkato 6:aa1fc6a5cc2a 2778 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2779 osStatus sem_ercd;
dkato 6:aa1fc6a5cc2a 2780 int_t ssif_ch_count;
dkato 6:aa1fc6a5cc2a 2781 uint32_t cpg_value;
dkato 6:aa1fc6a5cc2a 2782 uint32_t was_masked;
dkato 6:aa1fc6a5cc2a 2783 volatile uint8_t dummy_buf;
dkato 6:aa1fc6a5cc2a 2784
dkato 6:aa1fc6a5cc2a 2785 /* software reset */
dkato 6:aa1fc6a5cc2a 2786 SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
dkato 6:aa1fc6a5cc2a 2787
dkato 6:aa1fc6a5cc2a 2788 for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
dkato 6:aa1fc6a5cc2a 2789 {
dkato 6:aa1fc6a5cc2a 2790 if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
dkato 6:aa1fc6a5cc2a 2791 {
dkato 6:aa1fc6a5cc2a 2792 sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
dkato 6:aa1fc6a5cc2a 2793 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 2794 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 2795 {
dkato 6:aa1fc6a5cc2a 2796 /* set error return value */
dkato 6:aa1fc6a5cc2a 2797 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2798 }
dkato 6:aa1fc6a5cc2a 2799
dkato 6:aa1fc6a5cc2a 2800 gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
dkato 6:aa1fc6a5cc2a 2801 }
dkato 6:aa1fc6a5cc2a 2802 }
dkato 6:aa1fc6a5cc2a 2803
dkato 6:aa1fc6a5cc2a 2804 if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
dkato 6:aa1fc6a5cc2a 2805 {
dkato 6:aa1fc6a5cc2a 2806 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
dkato 6:aa1fc6a5cc2a 2807 /* semaphore error check */
dkato 6:aa1fc6a5cc2a 2808 if (osOK != sem_ercd)
dkato 6:aa1fc6a5cc2a 2809 {
dkato 6:aa1fc6a5cc2a 2810 /* set error return value */
dkato 6:aa1fc6a5cc2a 2811 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 2812 }
dkato 6:aa1fc6a5cc2a 2813
dkato 6:aa1fc6a5cc2a 2814 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
dkato 6:aa1fc6a5cc2a 2815 }
dkato 6:aa1fc6a5cc2a 2816
dkato 10:c5c630882b90 2817 #if defined (__ICCARM__)
dkato 10:c5c630882b90 2818 was_masked = __disable_irq_iar();
dkato 10:c5c630882b90 2819 #else
dkato 6:aa1fc6a5cc2a 2820 was_masked = __disable_irq();
dkato 10:c5c630882b90 2821 #endif
dkato 6:aa1fc6a5cc2a 2822
dkato 6:aa1fc6a5cc2a 2823 /* stop clock for SCUX */
dkato 6:aa1fc6a5cc2a 2824 cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
dkato 6:aa1fc6a5cc2a 2825 CPG.STBCR8 = (uint8_t)cpg_value;
dkato 6:aa1fc6a5cc2a 2826 dummy_buf = CPG.STBCR8;
dkato 6:aa1fc6a5cc2a 2827
dkato 6:aa1fc6a5cc2a 2828 if (0U == was_masked)
dkato 6:aa1fc6a5cc2a 2829 {
dkato 6:aa1fc6a5cc2a 2830 /* enable all irq */
dkato 6:aa1fc6a5cc2a 2831 __enable_irq();
dkato 6:aa1fc6a5cc2a 2832 }
dkato 6:aa1fc6a5cc2a 2833
dkato 6:aa1fc6a5cc2a 2834 return retval;
dkato 6:aa1fc6a5cc2a 2835 }
dkato 6:aa1fc6a5cc2a 2836
dkato 6:aa1fc6a5cc2a 2837 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2838 End of function SCUX_CmnUnInitialize
dkato 6:aa1fc6a5cc2a 2839 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2840 #endif /* end mbed */